A remapping method based on routability and integrated circuit

Abstract

The application discloses a remapping method based on routability and an integrated circuit, comprising the following steps: performing global layout on the whole netlist; performing global routing on the whole netlist; extracting a subnetlist with routing congestion; performing incremental remapping on the subnetlist; rewriting the subnetlist with the result of the incremental remapping; performing incremental global layout on the rewritten subnetlist; and performing incremental global routing on the rewritten subnetlist. Through the design, local congestion can be relieved, and routability can be improved. Through congestion minimization, time can also be improved. The congestion minimization is integrated into area and time delay indexes, the influence among area, time delay and congestion minimization is balanced, congestion is reduced without damaging the time delay constraint, and only a small part of area is increased.

Description

Technical Field

[0001] This application relates to the technical field of integrated circuits, and more specifically to a remapping method based on wiredability and an integrated circuit. Background Technology

[0002] For VLSI (Very Large Scale Integration) level digital circuit design processes, designers often employ computer-aided techniques. Standard languages ​​such as Hardware Description Languages ​​(HDLs) have been developed to describe digital circuits, aiding in the design and simulation of complex digital circuits. Various hardware description languages, such as VHDL and Verilog, have gradually become industry standards. VHDL and Verilog are general-purpose hardware description languages ​​that allow the use of abstract data types to define chip primitive-level, register-transfer-level (RTL), or behavioral-level hardware models. As device technology continues to advance, various product design tools have been developed to adapt HDLs for new devices and design styles.

[0003] When designing integrated circuits using HDL code, the code is first written and then compiled by an HDL compiler. The HDL source code describes circuit elements at a certain layer, and the compiler generates an RTL netlist. An RTL netlist consists of multiple RTL objects or components and multiple nets (which are the signal connections between the components). The RTL netlist is typically technology-independent because it is independent of the technology or architecture of a particular vendor's integrated circuit (e.g., a Field-Programmable Gate Array (FPGA) or Application-Specific Integrated Circuit (ASIC)). The RTL netlist corresponds to a schematic representation (as opposed to a behavioral representation) of the circuit elements. A mapping operation is then performed to convert the technology-independent RTL netlist into a technology-specific netlist that can be used to create circuits in a vendor's technology or architecture. This mapping operation includes placing instances and routing interconnects to ensure the circuit meets given timing, spacing, and power constraints.

[0004] Electronic design automation (EDA) software tools provide a wide range of functions related to the design, simulation, analysis, verification, and manufacturing of integrated circuits (ICs). Advances in computing speed and power, as well as memory capacity, have reduced the time required to complete these functions. At the same time, increasing design complexity (the number of devices and their interconnections) and faster design cycles have made IC designers increasingly reliant on EDA software tools to produce IC layouts that are correctly executed while meeting time-to-market targets.

[0005] Process mapping uses logic cells provided in the process library (standard cell library) to implement the internal representation of the design; that is, the design is mapped to the target process. During the mapping process, timing, area, and power constraints must be met, and some local optimizations must be performed. Process mapping is a crucial step connecting the EDA front-end and back-end; through process mapping, we can truly transform logic circuits into actual physical circuits. Traditional process mapping generally includes three steps: node cutting and cutting equation calculation, Boolean matching, and covering. Among these, the Boolean matching step, which generates the solution space, is of paramount importance.

[0006] Traditional process mapping only considers latency and area constraints when selecting the optimal Boolean match, neglecting router availability (congestion). Routing availability plays a crucial role in the subsequent placement and routing phases. How to prevent two distant cells from being connected together, thereby improving the utilization of routing resources, is a pressing technical problem that needs to be solved.

[0007] The background description is provided for the purpose of understanding the relevant technologies in this field and is not intended as an admission of prior art. Summary of the Invention

[0008] Therefore, the process mapping method provided by this invention can alleviate local congestion, improve cabling availability, and increase cabling resource utilization.

[0009] In a first aspect, embodiments of the present invention provide a remapping method based on roamability, characterized by comprising the following steps: performing global layout on the entire netlist; performing global routing on the entire netlist; extracting sub-netlists with routing congestion; performing incremental remapping on the sub-netlists; rewriting the sub-netlists using the result of the incremental remapping; performing incremental global layout on the rewritten sub-netlists; and performing incremental global routing on the rewritten sub-netlists.

[0010] Optionally, after the incremental global cabling step, it can be determined whether there is a subnet table with cabling congestion.

[0011] Optionally, the incremental remapping includes the following steps: inputting a congested subnet table;

[0012] The congested subnettable is decomposed into a NAND graph; the NAND graph is then mapped using a routing-driven process to form a new netlist; the new netlist is then returned.

[0013] Optionally, the congested subnet table is decomposed into a NAND graph, including the following steps: performing topological sorting on the nodes; performing a specified operation on each node in the topological sequence; determining whether the current node is the last node; determining whether the current node has only two inputs; taking out the two inputs of the current node and decomposing them to generate a new node; connecting the output of the new node to the current node; and calculating the position of the new node.

[0014] Optionally, repeating the steps of claim 4 until the current node has only two inputs.

[0015] Optionally, the wiring-driven process mapping includes the following steps: calculating node cuts from bottom to top; calculating the truth table of the cuts; traversing each node from bottom to top; determining whether the current node is the last node; traversing each cut of the current node; determining whether the current cut is the last cut; traversing each gate that matches the truth table of the current cut; determining whether the current matching gate is the last matching gate; calculating the coordinates of the current matching gate; calculating the area and arrival time of the current matching gate; updating the area and delay matching gates of the current node; and selecting matching gates for each node from top to bottom to cover the entire netlist.

[0016] Optionally, the coordinates of the matching door are obtained through the centroids of the fan-in connection object and the fan-out connection object of the matching door; the fan-in connection object is the matching door of the fan-in node; the fan-out connection object is the fan-out node. Optionally, the total area of ​​the matching door is the sum of the area of ​​the matching door and the area of ​​the line length multiplied by a coefficient; the area of ​​the matching door is the sum of the areas of the current matching door and the matching doors of its fan-in node divided by the number of fan-out nodes; the area of ​​the line length is the sum of the distance between the matching door of the fan-in node and the current matching door and the area of ​​the line length of the fan-in node, divided by the number of fan-out nodes.

[0017] Optionally, the arrival time of the matched gate includes: the arrival time of the input pin of the matched gate and the arrival time of the output pin of the matched gate; the arrival time of the input pin is obtained by the arrival time of the fan-in node connected to the input pin and the line delay; the arrival time of the output pin is obtained by the arrival time of the input pin and the delay from the input pin to the output pin.

[0018] In a second aspect of this invention, an integrated circuit is provided, wherein the integrated circuit is configured to use the method described in any one of claims 1-9 when performing a process mapping operation.

[0019] Other optional features and technical effects of the embodiments of the present invention are partly described below and partly apparent from reading this document. Attached Figure Description

[0020] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The elements shown are not limited to the scale shown in the drawings, and the same or similar reference numerals in the drawings denote the same or similar elements, wherein:

[0021] Figure 1 A schematic diagram of a prior art wiring method for designing integrated circuits is shown.

[0022] Figure 2 A flowchart illustrating a wiring method that can be implemented according to an embodiment of the present invention is shown;

[0023] Figure 3 A flowchart illustrating an incremental remapping method that can implement embodiments of the present invention is shown.

[0024] Figure 4 A flowchart illustrating a method for decomposing a netlist into a NAND graph, which can be implemented according to an embodiment of the present invention, is shown.

[0025] Figure 5 A schematic flowchart of a process mapping method for implementing the wiring capability of embodiments of the present invention is shown;

[0026] Figure 6a A schematic diagram is shown of a process mapping method based on minimum area that can be implemented according to embodiments of the present invention;

[0027] Figure 6b A schematic diagram is shown of a remapping-based method that can be implemented according to an embodiment of the present invention. Detailed Implementation

[0028] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to specific embodiments and accompanying drawings. Here, the illustrative embodiments and descriptions of this invention are used to explain the invention, but are not intended to limit the invention.

[0029] The term "comprising" and its variations as used herein signify open inclusion, i.e., "including but not limited to". Unless otherwise stated, the term "or" means "and / or". The term "based on" means "at least partially based on". The terms "one example embodiment" and "one embodiment" mean "at least one example embodiment". The term "another embodiment" means "at least one additional embodiment". The terms "first", "second", etc., may refer to different or the same objects. Other explicit and implicit definitions may also be included below.

[0030] In an embodiment of the present invention, a process mapping method is provided to alleviate local congestion, improve cabling availability, and increase cabling resource utilization.

[0031] In some embodiments, the present invention provides a remapping method based on wireability that can be combined with the features of the integrated circuit of any embodiment, and vice versa, which will not be elaborated here.

[0032] Figure 1 A schematic diagram of a prior art wiring method for designing integrated circuits is shown, such as... Figure 1 In the prior art, after the HDL code is prepared, it is synthesized to generate a netlist, which is typically optimized by performing logic optimization. Following this, a mapping process maps the netlist to a specific target technology / architecture. After step 101, synthesis is complete, and a netlist for the technology / architecture used in the vendor's IC is now available. This netlist is effectively located at the gate level and timing analysis is estimated using interconnect property statistical models based on pre-layout information (e.g., fan-out count, or the type and size of connected components). After synthesis, conventional placement operations are performed on the logic circuitry in step 102, and local modifications are made to the netlist in step 103 (only at the chip level, cell level, or gate level) to meet timing performance requirements. Then, conventional routing operations are performed in step 104 to create the circuit design in each IC. If any unmet constraints exist, the process is modified through loop iterations.

[0033] In floorplanning, the design is divided into multiple regions on the chip, and while statistical models are used to estimate interconnects within each region, layout-based interconnect estimation is applied to the interconnects between regions. Floorplanning can be used early in the RTL phase or after the initial synthesis run. Floorplanning can be extended to partition, copy, and cut RTL components into multiple regions, and combined with RTL-level timing and region models.

[0034] How to avoid connecting two areas that are far apart together, thereby improving the utilization rate of cabling resources, is a problem that existing technologies cannot solve.

[0035] Figure 2 A flowchart illustrating a wiring method that can be implemented according to embodiments of the present invention is shown, as follows: Figure 2As shown, to assess cabling congestion, a global layout is performed on the entire netlist in step 201; global routing is performed on the entire netlist in step 202 to determine the location of cells and extract congestion areas; in step 203, it is determined whether cabling congestion exists. If no congestion area exists, the incremental process ends and proceeds to step 208; in step 204, a sub-netlist is extracted; in step 205, incremental remapping is performed on the extracted sub-netlist, and the sub-netlist is rewritten with the remapped result and then placed back into the original sub-netlist; in step 206, incremental global layout is performed on the updated netlist; in step 207, incremental global routing is performed on the updated netlist; after step 207, the process returns to step 203 to determine whether there is a congestion area in the updated netlist. If no congestion area exists, the incremental process ends; otherwise, the steps in the above embodiment continue until no congestion area exists and the incremental process ends.

[0036] In the above embodiment, when the method flow is executed for the first time, step 203 does not need to make a judgment, and step 204 is executed directly.

[0037] Figure 3 A flowchart illustrating an incremental remapping method that can implement embodiments of the present invention is shown, as follows: Figure 3 As shown, in step 301, a congested netlist is input; in step 302, the netlist is decomposed into a NAND graph; in step 303, a routeability-driven process mapping is performed on the NAND graph to form a new netlist; in step 304, the mapped new netlist is returned. Congestion is then assessed on the new netlist according to the above embodiment. Figure 3 The embodiment is Figure 2 The detailed process of step 205 in the embodiment.

[0038] Figure 4 A flowchart illustrating a method for decomposing a netlist into a NAND graph, which can be implemented according to embodiments of the present invention, is shown. Figure 4 The diagram shows that in step 401, the nodes are arranged topologically; in step 402, a specified operation is performed on each node v in the topological sequence, and the specified operation is as follows: Figure 4 The subsequent processing steps in the illustrated embodiment are as follows: In step 403, determine whether node v is the last node; in step 404, determine whether node v has only two inputs; in step 405, extract the two inputs of node v and decompose them to generate a new node; in step 406, connect the output of the new node to node v; in step 407, calculate the position of the new node; and in step 408, end the process of decomposing the netlist into a NAND graph.

[0039] exist Figure 4In the illustrated embodiment, the decomposition process of the current node is a recursive operation. Each multi-input node is decomposed according to topological order, ensuring that the fan-in node of the current node has been decomposed. Each node sequentially combines its inputs pairwise to decompose into two new input nodes. The outputs of these two new input nodes are then connected to the original node, and the original node is decomposed again until only two inputs remain. In this process, the coordinates of the newly decomposed node are defined as the centroids of the nodes connected to its fan-in and fan-out nodes. The coordinates of the newly decomposed node are obtained using formula (1):

[0040]

[0041]

[0042] Where pos_x(v) is the x-coordinate of the node, pos_y(v) is the y-coordinate of the node, fanin is the fan-in node, and fanout is the fan-out node.

[0043] Figure 4 The embodiment shown is Figure 3 A detailed process for step 302 in the illustrated embodiment.

[0044] Figure 5 A schematic flowchart of a process mapping method for implementing the wiring capability embodiments of the present invention is shown; as follows: Figure 5 The process is as follows: Step 501: Calculate node cuts from bottom to top; Step 502: Calculate the truth table of cuts; Step 503: Traverse each node v from bottom to top; Step 504: Determine if node v is the last node; Step 505: Traverse each cut c of node v; Step 506: Determine if cut c is the last cut; Step 506: Traverse each gate g that matches the truth table of cut c; Step 508: Determine if matching gate g is the last gate that matches the truth table of cut c; Step 509: Calculate the coordinates of the matching gate; Step 510: Calculate the area and arrival time of the matching gate; Step 511: Update the optimal area and delay matching gate for the current node v; Step 512: Select the optimal matching gate for each node from top to bottom to cover the entire netlist; Step 510: End the process flow of the routerability mapping method.

[0045] Figure 5The fabrication mapping method for router capability shown mainly consists of three parts: slicing and truth table calculation, Boolean operation, and covering. Slicing calculation generates all possible slices of size no greater than 6 for each node from the bottom up, while simultaneously calculating the truth table for each slice. The covering step is a top-down process: first, the best matching gate is selected for all major output nodes, and then the best matching gate is selected for the fan-in nodes of these matching gates, until the major input nodes are reached. The truth table calculation and covering steps can be performed using existing techniques; this application does not impose specific limitations. Figure 5 The process shown contains three loops: the first loop iterates through each node from bottom to top, the second loop iterates through each cut generated by the node, and the third loop iterates through each matching gate whose truth table is the same as the cut truth table. These three loops will generate four best matching gates for each node, that is, each node will ultimately retain four possible solutions. In the third loop, for each matching gate, the coordinate position of the current matching gate is first calculated based on the centroid of the fan-in and fan-out connection objects of the matching gate. Since the best matching gate of each node is calculated from bottom to top, the best matching gate of the fan-out node of the current node has not yet been calculated. Therefore, when calculating the coordinates, the fan-in connection object is the best matching gate of the fan-in node, and the fan-out connection object is the fan-out node. The calculation of the matching gate is shown in formulas (3) and (4):

[0046]

[0047]

[0048] After calculating the coordinates of the current matching gate, the total area and arrival time of the matching gate, considering the line length, are calculated using the coordinates of the matching gate. The total area of ​​the matching gate is defined as the area of ​​the matching gate plus the line length area multiplied by a coefficient. The coefficient can be obtained empirically or theoretically, and this application does not impose specific restrictions. The area of ​​the matching gate is the sum of the areas of the current matching gate and the best matching gate of its fan-in node, divided by the number of fan-out nodes. The line length area is defined as the sum of the distances between the best matching of the fan-in node and the current matching gate, plus the sum of the line length areas of the fan-in nodes, divided by the number of fan-out nodes. area_cost(m, v) refers to the total area, which consists of the area of ​​the matching gate and the line length area. area(m, v) represents the area of ​​the current matching gate, m represents the current matching gate, fanin(m, v) represents the fan-in node of the current matching gate, and area(v) represents the line length area. i ) represents node v i The area of ​​the best-matching gate. wire(m, v) represents the area of ​​the wire length, match(v) represents the area of ​​the gate. i ) represents node v i The best matching gate, pos(m, v) represents the position of the matching gate for the current node v.

[0049] The formula for calculating the total area is shown in formula (5):

[0050] area_cost(m,v)=area(m,v)+k*wire(m,v) (5)

[0051] The formula for calculating the area of ​​the current matching gate is shown in formula (6):

[0052]

[0053] The formula for calculating the area of ​​a line is shown in formula (7):

[0054]

[0055] The formula for calculating the distance between the best matching gate and the current matching gate is shown in formula (8).

[0056] dist((x1, y1), (x2, y2))=|x1-x2|+|y1-y2| (8)

[0057] Where x1 and y1 are the coordinates of the current matching gate, and x2 and y2 are the coordinates of the best matching gate.

[0058] The delay of a matched gate is measured in terms of arrival time. Each matched gate requires calculating the arrival time of its input pin and the arrival time of its output pin. The arrival time of the matched gate is the arrival time of its output pin. The arrival time of an input pin is the arrival time of the best matched gate for the fan-in node corresponding to that pin, plus the line length delay multiplied by a coefficient. The arrival time of an output pin is the maximum value of the sum of the arrival times of each input pin of the matched gate and their delays to the output pin. The arrival time of an input pin is expressed as arrival time(fanin driver pin), where arrival time(fanin driver pin) represents the arrival time of the fan-in node connected to the input pin, and wrie_delay represents the line delay, estimated using Manhattan distance. The formula for calculating the arrival time of an input pin is shown in formula (9):

[0059]

[0060] The arrival time of the output pin is represented by arrival time(f), which indicates the arrival time of the i-th input pin.

[0061] Pin-to-pin delay represents the time delay from the i-th input pin to the output pin, which is determined by the properties of the matched gate itself. The formula for calculating the arrival time of the output pin is shown in formula (10).

[0062] arrival time out = max i∈input pin(arrival time(i)+pin to pin delay) (10)

[0063] After calculating the total area and delay of the gates, the matching gate is compared with the best matching gate of the current node. If the area is smaller, the smallest matching gate is updated; if the arrival time is earlier, the best matching gate with the delay is updated.

[0064] Figure 6a A schematic diagram is shown of a process mapping method based on minimum area that can be implemented according to embodiments of the present invention. For example... Figure 6a As shown, g5 is a four-input gate with four inputs: g1, g2, g3, and g4. Figure 6a As can be seen in the embodiment shown, in the result of the existing area-minimization-based mapping method, there are two "long lines" connecting the four inputs of g5: one pin from g3 to g5 and another pin from g4 to g5.

[0065] Figure 6b A schematic diagram is shown of a remapping-based method that can be implemented according to embodiments of the present invention. For example... Figure 6b As shown in the remapping process method provided in the above embodiments of this application, g5 is decomposed into three logic gates: g6, g7, and g8. Specifically, g6 is connected to the original logic gates g1 and g2; g7 is connected to the original logic gates g3 and g4. Figure 6b As can be seen from the embodiments shown, the remapping method provided in this application eliminates the existence of "long lines," reduces the connection length between logic gates, and improves congestion. The remapping method provided in this application allows a cell to be connected to adjacent cells as much as possible, avoiding the phenomenon of "long lines" in subsequent wiring.

[0066] As can be seen from the above embodiments, the incremental remapping method provided in this embodiment can alleviate local congestion and improve routing feasibility. It improves timeliness by minimizing congestion. The incremental remapping method provided in this application integrates congestion minimization into area and latency metrics, balancing the impact of area, latency, and congestion minimization. It reduces congestion without violating latency constraints, and only slightly increases the area. The initial input of the new incremental remapping proposed in the incremental remapping method provided in this application is based on the results after routing, thereby improving the accuracy of congestion assessment during the remapping process and making the remapping results more feasible.

[0067] While most embodiments of the present invention are intended for use in HDL design synthesis software programs, the invention is not necessarily limited to such applications. Other languages ​​and computer programs can be used (e.g., computer programs can be written to describe hardware so that they can be considered as expressions in HDL form and can be compiled, or in some embodiments, the invention can allocate and redistribute logical representations created without using HDL, such as netlists), but many embodiments of the invention are intended for use in HDL synthesis systems. It is known that the target architecture is typically determined by the programmable IC vendor. One example of a target architecture is a programmable lookup table for an integrated circuit and its associated logic. Other examples of target architectures / technologies include those known architectures in field-programmable gate arrays and complex programmable logic devices. For some embodiments, the invention can also be used with application-specific integrated circuits (ASICs).

[0068] Those skilled in the art will understand that the embodiments described in this specification can be provided as methods, systems, or computer program products. Therefore, those skilled in the art will realize that the functional modules / units or controllers and related method steps described in the above embodiments can be implemented in software, hardware, or a combination of both.

[0069] Unless explicitly stated otherwise, the actions or steps of the methods and procedures described in the embodiments of the present invention do not necessarily have to be performed in a specific order and can still achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0070] This document describes several embodiments of the present invention; however, for the sake of brevity, the descriptions of the embodiments are not exhaustive, and identical or similar features or parts between the embodiments may be omitted. In this document, "one embodiment," "some embodiments," "example," "specific example," or "some examples" refers to embodiments applicable to at least one, but not all, of the present invention. The above terms do not necessarily refer to the same embodiments or examples. Without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described herein, as well as the features of the different embodiments or examples.

[0071] The exemplary systems and methods of the present invention have been specifically shown and described with reference to the above embodiments, which are merely examples of the best mode for implementing the systems and methods. Those skilled in the art will understand that various changes can be made to the embodiments of the systems and methods described herein without departing from the spirit and scope of the invention as defined in the appended claims when implementing the systems and / or methods.

Claims

1. A remapping method based on wiredability, characterized in that, Includes the following steps: Perform a global layout for the entire netlist; Perform global routing on the entire netlist; Extract the subnet table of cabling congestion; Perform incremental remapping on the subnet table, and rewrite the subnet table using the result of the incremental remapping; The incremental remapping includes the following steps: Input a congested subnet table; The congested subnet table is decomposed into a NAND graph, including: combining the inputs of each node in pairs according to the topological order to decompose a new two-input node, connecting the output of the new node to the original node, recursively decomposing until the original node has only two inputs left, and calculating the position of the new node. Perform a wiring-driven process mapping on the NAND graph to form a new netlist; Return the new netlist; wherein the wiredability-driven process mapping includes: calculating the node cuts and the truth table of the cuts from bottom to top, traversing the matching gates that match the truth table of the current cut, calculating the coordinates, area and arrival time of the current matching gate, updating the area and delay matching gates of the current node, and selecting the matching gates of each node from top to bottom to cover the subnetlist. The coordinate position of the matching door is obtained by the centroid of the fan-in connection object and the fan-out connection object of the matching door. The fan-in connection object is the matching door of the fan-in node, and the fan-out connection object is the fan-out node. The total area of ​​the matching gate is the sum of the area of ​​the matching gate and the area of ​​the line length multiplied by a coefficient. The area of ​​the line length is the sum of the distance between the matching gate of the fan-in node and the current matching gate and the area of ​​the line length of the fan-in node, divided by the number of fan-out nodes. Perform incremental global layout on the rewritten subnet table; Incremental global routing is performed on the rewritten subnetlist.

2. The remapping method based on wiredability according to claim 1, characterized in that, After the incremental global cabling step, determine whether there is a subnet table with cabling congestion.

3. The remapping method based on wiredability according to claim 1, characterized in that, The congested subnet table is decomposed into a NAND graph, including the following steps: Perform topological sorting on the nodes; Perform the specified operation on each node in the topological sequence; The specified operations include: determining whether the current node is the last node; if it is the last node, then the process ends. If it is not the last node, determine whether the current node has only two inputs. If so, perform the specified operation on each node in the topology sequence. If not, take out the two inputs of the current node and decompose them to generate a new node. Connect the output of the new node to the current node. Calculate the position of the new node.

4. The remapping method based on wiredability according to claim 1, characterized in that, The wiring-driven process mapping includes the following steps: Calculate node cuts from bottom to top; Calculate the truth table for the cut; Traverse each node from bottom to top; Determine if the current node is the last node. If so, select the best matching gate for each node from top to bottom to cover the entire netlist. If not, then iterate through each cut of the current node; Determine if the current cut is the last cut; if so, traverse each node from bottom to top. If not, then iterate through each gate that matches the current cut truth table; Determine if the current matching gate is the last matching gate. If so, iterate through each cut of the current node. If not, calculate the coordinates of the current matching gate; Calculate the area and arrival time of the currently matched gate; Update the area and delay matching gate of the current node; Returns each gate that matches the current cut truth table.

5. The remapping method based on wiredability according to claim 4, characterized in that, The coordinates of the matching door are obtained through the centroids of the fan-in connection object and the fan-out connection object of the matching door; The fan-in connection object is the matching gate of the fan-in node; The fan-out connection object is a fan-out node.

6. The remapping method based on wiredability according to claim 4, characterized in that, The area of ​​the matching door is the sum of the areas of the current matching door and the matching doors of its fan-in nodes, divided by the number of fan-out nodes.

7. The remapping method based on wiredability according to claim 4, characterized in that, The arrival time of the matched gate includes the arrival time of the input pin of the matched gate and the arrival time of the output pin of the matched gate; The arrival time of the input pin is obtained by the arrival time of the fan-in node connected to the input pin and the line delay; The arrival time of the output pin is obtained by the arrival time of the input pin and the time delay from the input pin to the output pin.

8. An integrated circuit, characterized in that, The integrated circuit is configured to use the method described in any one of claims 1-7 when performing a process mapping operation.

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