Image generation using one or more neural networks

Abstract

This disclosure relates to image generation using one or more neural networks. Apparatuses, systems, and techniques for generating one or more images are described. In at least one embodiment, one or more neural networks are used to generate one or more images based at least in part on one or more noise values.

Description

Technical Field

[0001] At least one embodiment relates to processing resources for performing and facilitating artificial intelligence. For example, at least one embodiment relates to a processor or computing system for training neural networks according to various novel techniques described herein. Background Technology

[0002] Techniques such as machine learning are increasingly capable of generating realistic, high-quality images. However, training different types of models for image generation presents various challenges. For example, while the Denoising Diffusion Probabilistic Model (DDPM) may be more stable to train than models like Generative Adversarial Networks (GANs), the large number of training steps required makes DDPM training very slow and computationally expensive. Methods to reduce the training time of models such as DDPM have negatively impacted the quality of the generated images. Attached Figure Description

[0003] Various embodiments of this disclosure will be described with reference to the accompanying drawings, in which:

[0004] Figure 1A , Figure 1B and Figure 1C Aspects of a trained generative model according to at least one embodiment are shown;

[0005] Figure 2A and Figure 2B A method for using IMLE to assist in training DDPM according to at least one embodiment is shown;

[0006] Figure 3 An example process for training a generative model according to at least one embodiment is shown;

[0007] Figure 4 A process for generating an image according to at least one embodiment is shown;

[0008] Figure 5 The illustration shows components of a system for generating one or more images according to at least one embodiment;

[0009] Figure 6A The inference and / or training logic according to at least one embodiment is illustrated;

[0010] Figure 6B The inference and / or training logic according to at least one embodiment is illustrated;

[0011] Figure 7 An example data center system according to at least one embodiment is shown;

[0012] Figure 8 A block diagram of a computer system according to at least one embodiment is shown;

[0013] Figure 9 A block diagram of a computer system according to at least one embodiment is shown;

[0014] Figure 10 A computer system according to at least one embodiment is shown;

[0015] Figure 11 A computer system according to at least one embodiment is shown;

[0016] Figure 12A A computer system according to at least one embodiment is shown;

[0017] Figure 12B A computer system according to at least one embodiment is shown;

[0018] Figure 12C A computer system according to at least one embodiment is shown;

[0019] Figure 12D A computer system according to at least one embodiment is shown;

[0020] Figure 12E and Figure 12F A shared programming model according to at least one embodiment is shown;

[0021] Figure 13 An exemplary integrated circuit and an associated graphics processor according to at least one embodiment are shown;

[0022] Figures 14A to 14B An exemplary integrated circuit and an associated graphics processor according to at least one embodiment are shown;

[0023] Figures 15A to 15B Additional exemplary graphics processor logic according to at least one embodiment is shown;

[0024] Figure 16 A computer system according to at least one embodiment is shown;

[0025] Figure 17A A parallel processor according to at least one embodiment is shown;

[0026] Figure 17B A partitioning unit according to at least one embodiment is shown;

[0027] Figure 17C A processing cluster according to at least one embodiment is shown;

[0028] Figure 17D A graphics multiprocessor according to at least one embodiment is shown;

[0029] Figure 18 A multi-graphics processing unit (GPU) system according to at least one embodiment is illustrated;

[0030] Figure 19 A graphics processor according to at least one embodiment is shown;

[0031] Figure 20 The microarchitecture of a processor according to at least one embodiment is shown;

[0032] Figure 21 A deep learning application processor according to at least one embodiment is shown;

[0033] Figure 22 A block diagram of an example neuromorphic processor according to at least one embodiment is shown;

[0034] Figure 23 and Figure 24 At least a portion of a graphics processor according to one or more embodiments is shown;

[0035] Figure 25 At least a portion of a graphics processor core according to at least one embodiment is shown;

[0036] Figures 26A to 26B At least a portion of a graphics processor core according to at least one embodiment is shown.

[0037] Figure 27 A parallel processing unit (“PPU”) according to at least one embodiment is shown;

[0038] Figure 28 A general-purpose processing cluster (“GPC”) according to at least one embodiment is illustrated;

[0039] Figure 29 A memory partition unit of a parallel processing unit (“PPU”) according to at least one embodiment is shown;

[0040] Figure 30 A streaming multiprocessor according to at least one embodiment is illustrated;

[0041] Figure 31 This is an example data flow diagram of an advanced computing pipeline according to at least one embodiment;

[0042] Figure 32 This is a system schematic diagram of an example system for training, adapting, instantiating, and deploying machine learning models in an advanced computing pipeline, according to at least one embodiment.

[0043] Figure 33AA data flow diagram illustrating the process for training a machine learning model according to at least one embodiment is shown; and

[0044] Figure 33B This is an example illustration of a client-server architecture that utilizes a pre-trained annotation model to enhance an annotation tool, according to at least one embodiment. Detailed Implementation

[0045] In at least one embodiment, the generative model can generate an output image 104 or output image data. In at least one embodiment, the generative model can include a diffusion probability model, such as a denoising diffusion probability model (DDPM) 106. In at least one embodiment, the DDPM can take a noisy image 102 as input and can generate an output image 104 that is substantially free of noise or other such artifacts. In at least one embodiment, the input image 102 can be an image of one or more objects including a certain amount of noise, or it can be a randomly generated noise image, and other such options. In at least one embodiment, the DDPM-based model can generate images from different input distributions, such as those selected from a latent space. In at least one embodiment, the generation involves, for example,... Figure 1B The diffusion process shown in case 120, represented by the top arrow moving to the left in the figure, involves adding a certain amount of noise, such as Gaussian noise, to image 124 for each of the multiple steps. In at least one embodiment, given image 124, an additional amount of noise can be added to the image feature distribution at each of these steps. In at least one embodiment, after a sufficient number of steps, an image 122 is produced that consists essentially of pixel values ​​corresponding to the Gaussian noise. In at least one embodiment, the DDPM can then learn the reverse process, as represented by the bottom arrow moving to the right in the figure. In at least one embodiment, for each step from (T→0), an attempt is made to remove a certain amount of noise from the current image. In at least one embodiment, the corresponding image generated during the diffusion process can be used as ground truth for comparison. In at least one embodiment, the DDPM model can then learn to reverse these diffusion steps such that, given the Gaussian noise image 122 as input, the DDPM can output a high-quality image 124 that is essentially noise-free.

[0046] In at least one embodiment, such a model involves numerous steps to learn to generate a high-quality model that is substantially free of noise or artifacts given an input (e.g., image data based on Gaussian noise). In at least one embodiment, this could include thousands of steps for a basic DDPM. In at least one embodiment, even with improvements to DDPM, such a process still involves dozens of steps, each involving a forward pass of the neural network, which results in such a process consuming a significant amount of time for inference or image generation. In at least one embodiment, in addition to the high computational cost, the long time required for such a network to generate images also prevents its use in many time-sensitive applications. In at least one embodiment, there is also a limited number of diffusion operations, which may involve Gaussian noise or binomial noise. In at least one embodiment, many diffusion models also utilize a high-dimensional latent space, which is also equivalent to a large sample (e.g., image) space.

[0047] In at least one embodiment, various diffusion modeling methods require numerous relatively small sampling steps, partly because the result of the backdiffusion step can be multimodal. In at least one embodiment, such as Figure 1C As shown in case 140, it can be assumed that each reverse diffusion arrow (in) Figure 1B (From center to right) is a Gaussian distribution corresponding to the added Gaussian noise, as shown in the figure, which can transform the first data space 142 into a second data space 144 including the added noise. Thus, in at least one embodiment, the probability distribution of x1 conditioned on x2 is a Gaussian distribution, such that each backdiffusion step can be approximated by a Gaussian model as long as the step size is small, and the number of steps is large. In at least one embodiment, as shown in data space 144, there may be a point x located between two Gaussian distributions. In at least one embodiment, adding such Gaussian noise back to data space 142 may have multimodal challenges because it may be difficult to determine definitively whether point x should be included in the distribution c1 or c2.

[0048] In at least one embodiment, the multimodal problem can be solved at least partially at each denoising step used to train the diffusion model using a multimodal random decoder. In at least one embodiment, because such a model does not require reliance on a unimodal Gaussian decoder that cannot represent complex distributions, fewer steps may be needed to train the model. In at least one embodiment, such a process can allow for the introduction of a larger amount of noise per step, which may require fewer steps and result in faster sampling. In at least one embodiment, such a process can also allow any diffusion process to be used with a smaller latent space. In at least one embodiment, the Gaussian inverse step process can be replaced with a framework that can capture more complex distributions. In at least one embodiment, this may include using an implicit maximum likelihood estimation framework (IMLE) that can provide end-to-end learning of a model that combines distributions and differentiable neural components. In at least one embodiment, IMLE can be implemented (e.g., Figure 2A As shown in configuration 200, where the generative model G is trained in the reverse step, it attempts to remove noise from the image for each step in the set of steps. In at least one embodiment, in each step, G202 attempts to denoise the image given random noise and image data from the previous step. In at least one embodiment, this can result in G202 generating random fake images. In at least one embodiment, G can capture a very complex image distribution, not just a single Gaussian distribution. In at least one embodiment, the real image 206 is sampled, here represented by points in the sample (image) space. In at least one embodiment, it is possible to identify the noise from the random noise input (z1 to z2). n The generated fake image contains points in the sample space, and points 204 of the fake image that can be identified as the closest point 206 to the real image. In at least one embodiment, for each iteration, different z-noise values ​​can be sampled to obtain different output images, each output image having different points in the sample (image) space. In at least one embodiment, in each iteration, the distance between point 206 of the real image and point 204 of the closest generated image in the sample space is determined. In at least one embodiment, this can be used as a loss value, and the iteration can attempt to reduce or minimize this loss value such that the model generates an image that is sufficiently close to the real image in the sample space. In at least one embodiment, values ​​z1 to z... n It can be randomly sampled from a prior distribution such as a Gaussian distribution.

[0049] In at least one embodiment, the functionality of this IMLE-based method can be similar to that of... Figure 2BThe configuration 250 combines the functionality of the DDPM-based method. In at least one embodiment, IMLE here can be used as a denoising step during the DDPM training process. In at least one embodiment, the figure again illustrates the backdiffusion step of the generative model (here, generator G 252). In at least one embodiment, G 252 accepts the noisy image x t And a random value z sampled from a distribution such as a Gaussian distribution is used as input. In at least one embodiment, the generator G 252 can generate an output image, denoted here as In at least one embodiment, different z-values ​​can be sampled to obtain different output images, and it can be determined that the generated output image (in the sample or image space) is closest to the clean ground truth image. In at least one embodiment, the image or sample space can be an n-dimensional latent space, where the image can be analyzed to extract representative features that can be mapped to points in the latent space, and the distances between these points in the n-dimensional latent space can be calculated. In at least one embodiment, the shortest distance can then be used as a loss value to train the generative network, for example, by modifying the network parameters through backpropagation to attempt to minimize the loss. In at least one embodiment, this IMLE-based model approach can be used for each training step of the generative model. In at least one embodiment, once the model is trained, random noise can be sampled and the model can be repeatedly applied over a relatively small number of steps (e.g., ten steps) to generate realistic or high-quality output images that are substantially free of noise or other such artifacts. In at least one embodiment, a multimodal DDPM can be generated using IMLE and multiple generated samples of each real sample with DDPM. This multimodal DDPM avoids the multimodal problems previously proposed herein. It can handle a relatively large amount of noise at each step and requires far fewer steps than other DDPM-based methods, which can significantly reduce processing time and cost. Therefore, at least based on the lower requirements for resources and memory capacity, the performance of the computing system can be improved, which can then be dedicated to other tasks or allow for smaller capacity resources to perform at least some of these tasks.

[0050] In at least one embodiment, such as Figure 3As shown, a process 300 for training a generative network can be performed. In at least one embodiment, a generative model such as DDPM can be selected 302 to be trained using multiple training images. In at least one embodiment, for each training image among such multiple training images, a certain amount of noise can be introduced 304 at each step of multiple diffusion steps to produce a set of noisy images. In at least one embodiment, this can include introducing Gaussian noise, wherein the noise can be selected using a random sampling method or a specified sampling method about a Gaussian distribution (or other suitable distribution), for example, a specific amount of noise that does not follow a specified pattern can be introduced into the image at each step. In at least one embodiment, for the noisiest image that has not yet been processed in the reverse diffusion step, a reverse diffusion step 306 can be performed by providing the image and noise values ​​(e.g., which can be randomly sampled or sampled according to a sampling algorithm from a Gaussian or other distribution) to an estimator model (e.g., IMLE), which can generate a set of candidate images for this particular reverse diffusion step.

[0051] In at least one embodiment, the distance between each of these candidate images, reflected by points in the image space, and a point in the image space corresponding to the ground truth image or a version of the input image before the addition of additional noise in the corresponding step can be calculated. In at least one embodiment, the shortest distance (in the image space) between one of these candidate images and the corresponding ground truth image from the corresponding diffusion step can be determined 308. In at least one embodiment, if it is determined 312 that there are more reverse steps to be performed, the process can continue. Otherwise, if enough training images have been processed to meet the training termination criteria, such as the maximum number of training iterations, meeting the convergence criteria, or processing all training data, the trained model can be provided 314 for generating high-quality images from the noisy input images. In at least one embodiment, this may include images containing one or more noisy objects, or may include fully noisy images that can be generated based on sampling to a suitable distribution.

[0052] In at least one embodiment, a process 400 for generating one or more images can be performed, such as... Figure 4 As shown. In at least one embodiment, one or more noise values ​​can be selected. In at least one embodiment, this can include a set of noise values ​​sampled from a distribution such as a Gaussian distribution. In at least one embodiment, one or more neural networks can then be used to generate one or more images based at least in part on these noise values. In at least one embodiment, this can include using a model that has been trained by introducing these noise values ​​in each of a plurality of backdiffusion steps.

[0053] In at least one embodiment, various types of hardware can be used on various devices to process data and perform mathematical operations in various ways. In at least one embodiment, client device 502 can use components of application 504 on client device 502 to generate or process session data, wherein at least a portion of the data is stored locally on the client device, such as... Figure 5As shown. In at least one embodiment, application 524 executing on server 520 can initiate a session associated with at least client device 502, such as by utilizing a session manager and user data stored in user database 536, and can cause content 534 to be determined by content manager 526, or cause data to be received or otherwise accessed for the purpose of performing one or more operations. In at least one embodiment, the image content can be generated using one or more rendering engines 528 or applications as discussed herein, which can use a generative model trained with diffusion information from diffusion module 530 under the supervision of one or more training modules 532. In at least one embodiment, an account manager can be used to ensure that the content is accessible by a requesting user or target client device, at least in part based on data stored in user database 536 and permissions granted to that user data. In at least one embodiment, before or after any such processing, the data can be transmitted to client device 502 using a suitable transmission manager 522 for transmission via download, streaming, or another such transmission channel. In at least one embodiment, the client device 502 receiving the content or data can provide the content or data to a corresponding application 504, which may also or alternatively include a data manager 510, a rendering engine 512, or a diffusion module 514 for generating or processing at least a portion of the content or data, such as generating image or video content via the client device 502 for presentation, including image or interface content via a display 506 and audio (e.g., sound and music) via at least one audio playback device 508 (e.g., a speaker or headphones). In at least one embodiment, at least a portion of the content may already be stored on the client device 502, rendered on the client device 502, or already accessible to the client device 502, such that at least that portion of the content does not need to be transmitted over the network 540, for example, if the content has previously been downloaded or locally stored on a hard drive or optical disc. In at least one embodiment, a transmission mechanism such as data streaming can be used to transfer the content or data from the server 520 or content database 534 to the client device 502. In at least one embodiment, at least a portion of the content or data may be obtained from or processed by another source, which may also perform one or more operations on the data, such as another client device 560 or a third-party content service 550, which may also include an application 552 for generating, processing, handling, or providing content or data. In at least one embodiment, the result of the processing may be provided to at least one other client device 560.In at least one embodiment, a portion of the function may be performed using multiple computing devices or multiple processors within one or more computing devices (e.g., possibly including a combination of CPU and GPU).

[0054] Reasoning and training logic

[0055] Figure 6A Inference and / or training logic 615 is illustrated for performing inference and / or training operations associated with one or more embodiments. The following is in conjunction with... Figure 6A and / or Figure 6B Provide details about reasoning and / or training logic 615.

[0056] In at least one embodiment, inference and / or training logic 615 may include, but is not limited to, code and / or data storage 601 for storing forward and / or output weights and / or input / output data, and / or other parameters for configuring neurons or layers of a neural network trained and / or used for inference in one or more embodiments. In at least one embodiment, training logic 615 may include or be coupled to code and / or data storage 601 for storing graph code or other software to control timing and / or sequence, wherein weight and / or other parameter information is loaded to configure logic, which includes integer and / or floating-point units (collectively, arithmetic logic units (ALUs)). In at least one embodiment, code (such as graph code) loads weight or other parameter information into the processor ALU based on the architecture of the neural network to which the code corresponds. In at least one embodiment, code and / or data storage 601 stores weight parameters and / or input / output data of each layer of a neural network trained or used in one or more embodiments during forward propagation of input / output data and / or weight parameters using aspects of training and / or inference in one or more embodiments. In at least one embodiment, any portion of the code and / or data storage 601 may be included within other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory.

[0057] In at least one embodiment, any portion of the code and / or data storage 601 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, the code and / or data storage 601 may be a cache memory, dynamic random access memory (“DRAM”), static random access memory (“SRAM”), non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, the choice of whether the code and / or data storage 601 is internal or external to the processor, for example, or includes DRAM, SRAM, flash memory, or some other storage type, may depend on the available on-chip versus off-chip storage, the latency requirements of the training and / or inference functions being performed, the batch size of the data used in the inference and / or training of the neural network, or some combination of these factors.

[0058] In at least one embodiment, inference and / or training logic 615 may include, but is not limited to, code and / or data storage 605 for storing backpropagation and / or output weights and / or input / output data corresponding to neurons or layers of a neural network trained and / or used for inference in one or more embodiments. In at least one embodiment, during training and / or inference using one or more embodiments, code and / or data storage 605 stores weight parameters and / or input / output data of each layer of a neural network trained or used in one or more embodiments during backpropagation of input / output data and / or weight parameters. In at least one embodiment, training logic 615 may include or be coupled to code and / or data storage 605 for storing graph code or other software to control timing and / or sequence, wherein weight and / or other parameter information is loaded to configure logic including integer and / or floating-point units (collectively referred to as arithmetic logic units (ALUs)). In at least one embodiment, code (such as graph code) causes weight or other parameter information to be loaded into a processor ALU based on the architecture of the neural network corresponding to the code. In at least one embodiment, any portion of the code and / or data storage 605 may be included together with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory. In at least one embodiment, any portion of the code and / or data storage 605 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, the code and / or data storage 605 may be cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, the choice of whether the code and / or data storage 605 is internal or external to the processor, for example, including DRAM, SRAM, flash memory, or some other type of storage, may depend on the available on-chip versus off-chip storage, the latency requirements of the training and / or inference functions being performed, the batch size of the data used in the inference and / or training of the neural network, or some combination of these factors.

[0059] In at least one embodiment, code and / or data storage 601 and code and / or data storage 605 may be separate storage structures. In at least one embodiment, code and / or data storage 601 and code and / or data storage 605 may be the same storage structure. In at least one embodiment, code and / or data storage 601 and code and / or data storage 605 may be partially combined and partially separated. In at least one embodiment, any portion of code and / or data storage 601 and code and / or data storage 605 may be included together with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory.

[0060] In at least one embodiment, the inference and / or training logic 615 may include, but is not limited to, one or more arithmetic logic units (“ALUs”) 610 (including integer and / or floating-point units) for performing logical and / or mathematical operations at least in part based on or instructed by training and / or inference code (e.g., graph code), the results of which may produce activations (e.g., output values ​​from layers or neurons within a neural network) stored in activation storage 620, which are functions of input / output and / or weight parameter data stored in code and / or data storage 601 and / or code and / or data storage 605. In at least one embodiment, activations stored in activation storage 620 are generated based on linear algebra and / or matrix-based mathematics performed by ALU 610 in response to execution instructions or other code, wherein weight values ​​stored in code and / or data storage 605 and / or code and / or data storage 601 are used as operands, and other values, such as bias values, gradient information, momentum values, or other parameters or hyperparameters, may be stored in code and / or data storage 605 or code and / or data storage 601 or other on-chip or off-chip storage.

[0061] In at least one embodiment, one or more ALUs 610 are included in one or more processors or other hardware logic devices or circuits, while in another embodiment, one or more ALUs 610 may be external to the processor or other hardware logic device or the circuitry that uses them (e.g., a coprocessor). In at least one embodiment, ALUs 610 may be included within an execution unit of a processor, or otherwise included in an ALU bank accessible by the execution unit of the processor, which may be within the same processor or distributed among different processors of different types (e.g., a central processing unit, a graphics processing unit, a fixed-function unit, etc.). In at least one embodiment, code and / or data storage 601, code and / or data storage 605, and activation storage 620 may be on the same processor or other hardware logic device or circuitry, while in another embodiment, they may be on different processors or other hardware logic devices or circuitries, or in some combination of the same and different processors or other hardware logic devices or circuitries. In at least one embodiment, any portion of activation storage 620 may be included together with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory. Furthermore, inference and / or training code may be stored along with other code accessible to the processor or other hardware logic or circuitry, and may be retrieved and / or processed using the processor’s fetch, decode, schedule, execute, exit, and / or other logic circuitry.

[0062] In at least one embodiment, the active memory 620 may be a cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other memory. In at least one embodiment, the active memory 620 may be entirely or partially located within or outside one or more processors or other logic circuits. In at least one embodiment, the choice of whether the active memory 620 is internal to or external to the processor, for example, or including DRAM, SRAM, flash memory, or certain other memory types, may depend on the availability of on-chip versus off-chip memory, latency requirements for performing training and / or inference functions, batch size of data used in inference and / or training of the neural network, or some combination of these factors. In at least one embodiment, Figure 6A The inference and / or training logic 615 shown can be used in conjunction with an application-specific integrated circuit (“ASIC”), such as those from Google. Processing unit, from Graphcore TM The inference processing unit (IPU) or from Intel. (e.g., "Lake Crest") processor. In at least one embodiment, Figure 6AThe inference and / or training logic 615 shown can be used in conjunction with central processing unit (“CPU”) hardware, graphics processing unit (“GPU”) hardware or other hardware (such as field programmable gate array (“FPGA”)).

[0063] Figure 6B Inference and / or training logic 615 according to at least one or more embodiments is illustrated. In at least one or more embodiments, the inference and / or training logic 615 may include, but is not limited to, hardware logic, wherein computational resources, along with weight values ​​or other information corresponding to one or more layers of neurons within a neural network, are used dedicatedly or otherwise exclusively. In at least one embodiment, Figure 6B The inference and / or training logic 615 shown can be used in conjunction with an application-specific integrated circuit (ASIC), such as those from Google. Processing unit, from Graphcore TM The inference processing unit (IPU) or from Intel. (e.g., "Lake Crest") processor. In at least one embodiment, Figure 6B The inference and / or training logic 615 shown can be used in conjunction with central processing unit (CPU) hardware, graphics processing unit (GPU) hardware, or other hardware (e.g., field-programmable gate array (FPGA)). In at least one embodiment, the inference and / or training logic 615 includes, but is not limited to, code and / or data storage 601 and code and / or data storage 605, which can be used to store code (e.g., graph code), weight values, and / or other information, including bias values, gradient information, momentum values, and / or other parameter or hyperparameter information. Figure 6B In at least one embodiment shown, each of code and / or data storage 601 and code and / or data storage 605 is associated with dedicated computing resources (e.g., computing hardware 602 and computing hardware 606). In at least one embodiment, each of computing hardware 602 and computing hardware 606 includes one or more ALUs that perform mathematical functions (e.g., linear algebraic functions) on the information stored in code and / or data storage 601 and code and / or data storage 605, respectively, with the results stored in active storage 620.

[0064] In at least one embodiment, each of the code and / or data storage 601 and 605 and the corresponding computing hardware 602 and 606 corresponds to a different layer of the neural network, such that an activation obtained from a storage / computation pair 601 / 602 of the code and / or data storage 601 and computing hardware 602 is provided as input to the next storage / computation pair 605 / 606 of the code and / or data storage 605 and computing hardware 606, in order to reflect the conceptual organization of the neural network. In at least one embodiment, each storage / computation pair 601 / 602 and 605 / 606 may correspond to more than one neural network layer. In at least one embodiment, additional storage / computation pairs (not shown) may be included in the inference and / or training logic 615 after or in parallel with the storage / computation pairs 601 / 602 and 605 / 606.

[0065] Data Center

[0066] Figure 7 An example data center 700 that can be used with at least one embodiment is shown. In at least one embodiment, the data center 700 includes a data center infrastructure layer 710, a framework layer 720, a software layer 730, and an application layer 740.

[0067] In at least one embodiment, such as Figure 7 As shown, the data center infrastructure layer 710 may include a resource coordinator 712, grouped computing resources 714, and node computing resources (“nodes CR”) 716(1)-716(N), where “N” represents any positive integer. In at least one embodiment, nodes CR 716(1)-716(N) may include, but are not limited to, any number of central processing units (“CPUs”) or other processors (including accelerators, field-programmable gate arrays (FPGAs), graphics processors, etc.), memory devices (e.g., dynamic read-only memory), storage devices (e.g., solid-state or disk drives), network input / output (“NW I / O”) devices, network switches, virtual machines (“VMs”), power modules, and cooling modules, etc. In at least one embodiment, one or more nodes CR 716(1)-716(N) may be servers having one or more of the aforementioned computing resources.

[0068] In at least one embodiment, the grouped computing resources 714 may include individual groups of node CRs housed within one or more racks (not shown), or a plurality of racks housed within data centers (also not shown) in various geographical locations. Individual groups of node CRs within the grouped computing resources 714 may include computing, networking, memory, or storage resources that can be configured or allocated to support groups of one or more workloads. In at least one embodiment, several node CRs, including CPUs or processors, may be grouped within one or more racks to provide computing resources to support one or more workloads. In at least one embodiment, one or more racks may also include any number of power modules, cooling modules, and network switches in any combination.

[0069] In at least one embodiment, resource coordinator 712 may be configured or otherwise control one or more nodes CR716(1)-716(N) and / or grouped computing resources 714. In at least one embodiment, resource coordinator 712 may include a Software Design Infrastructure (“SDI”) management entity for data center 700. In at least one embodiment, resource coordinator may include hardware, software, or some combination thereof.

[0070] In at least one embodiment, such as Figure 7 As shown, framework layer 720 includes a job scheduler 722, a configuration manager 724, a resource manager 726, and a distributed file system 728. In at least one embodiment, framework layer 720 may include a framework of software 732 supporting software layer 730 and / or one or more applications 742 supporting application layer 740. In at least one embodiment, software 732 or application 742 may respectively include web-based service software or applications, such as service software or applications provided by Amazon Web Services, Google Cloud, and Microsoft Azure. In at least one embodiment, framework layer 720 may be, but is not limited to, a type of free and open-source software web application framework, such as Apache Spark, which can utilize distributed file system 728 for large-scale data processing (e.g., "big data"). TM(Hereinafter referred to as "Spark"). In at least one embodiment, the job scheduler 722 may include a Spark driver for facilitating the scheduling of workloads supported by various layers of the data center 700. In at least one embodiment, the configuration manager 724 may be able to configure different layers, such as the software layer 730 and the framework layer 720, which includes Spark and a distributed file system 728 for supporting large-scale data processing. In at least one embodiment, the resource manager 726 may be able to manage clustered or grouped computing resources mapped to or allocated to support the distributed file system 728 and the job scheduler 722. In at least one embodiment, the clustered or grouped computing resources may include grouped computing resources 714 at the data center infrastructure layer 710. In at least one embodiment, the resource manager 726 may coordinate with the resource coordinator 712 to manage these mapped or allocated computing resources.

[0071] In at least one embodiment, the software 732 included in the software layer 730 may include software used by at least portions of nodes CR716(1)-716(N), grouped computing resources 714, and / or the distributed file system 728 of the framework layer 720. One or more types of software may include, but are not limited to, Internet web page search software, email virus scanning software, database software, and streaming video content software.

[0072] In at least one embodiment, one or more applications 742 included in application layer 740 may include one or more types of applications used by at least portions of nodes CR716(1)-716(N), grouped computing resources 714, and / or the distributed file system 728 of framework layer 720. One or more types of applications may include, but are not limited to, any number of genomics applications, cognitive computing and machine learning applications, including training or inference software, machine learning framework software (e.g., PyTorch, TensorFlow, Caffe, etc.), or other machine learning applications used in conjunction with one or more embodiments.

[0073] In at least one embodiment, any of the configuration manager 724, resource manager 726, and resource coordinator 712 can implement any number and type of self-modification actions based on any amount and type of data acquired in any technically feasible manner. In at least one embodiment, self-modification actions can mitigate potentially poor configuration decisions by data center operators of data center 700 and can prevent underutilization and / or poor performance of the data center.

[0074] In at least one embodiment, data center 700 may include tools, services, software, or other resources for training one or more machine learning models or using one or more machine learning models to predict or infer information according to one or more embodiments described herein. For example, in at least one embodiment, a machine learning model can be trained by calculating weight parameters based on a neural network architecture using the software and computing resources described above with respect to data center 700. In at least one embodiment, information can be inferred or predicted using trained machine learning models corresponding to one or more neural networks using the resources described above with respect to data center 700 by using weight parameters calculated through one or more training techniques described herein.

[0075] In at least one embodiment, the data center may use a CPU, application-specific integrated circuit (ASIC), GPU, FPGA, or other hardware to utilize the aforementioned resources to perform training and / or inference. Furthermore, one or more of the aforementioned software and / or hardware resources may be configured as a service to allow a user to train or perform information inference, such as image recognition, speech recognition, or other artificial intelligence services.

[0076] Inference and / or training logic 615 is used to perform inference and / or training operations associated with one or more embodiments. The following is combined with... Figure 6A and / or Figure 6B Details are provided regarding the inference and / or training logic 615. In at least one embodiment, the inference and / or training logic 615 can be... Figure 7 It is used in systems for inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases as described herein.

[0077] Inference and / or training logic 615 is used to perform inference and / or training operations associated with one or more embodiments. In at least one embodiment, this logic may be used with components of these graphs to generate one or more images using one or more neural networks, at least in part, based on one or more noise values.

[0078] Computer System

[0079] Figure 8This is a block diagram illustrating an exemplary computer system according to at least one embodiment. The exemplary computer system may be a system of interconnected devices and components, a system-on-a-chip (SOC), or some combination thereof 800 formed with a processor, which may include an execution unit for executing instructions. In at least one embodiment, according to this disclosure, such as in the embodiments described herein, the computer system 800 may include, but is not limited to, components such as processor 802 for employing the execution unit (including logic) to execute algorithms for process data. In at least one embodiment, the computer system 800 may include a processor, such as those available from Intel Corporation of Santa Clara, California. Processor family, Xeon TM , XScale TM and / or StrongARM TM , Core TM or Nervana TM The microprocessor can be used, although other systems (including PCs, engineering workstations, set-top boxes, etc.) with other microprocessors can also be used. In at least one embodiment, the computer system 800 can execute a version of the Windows operating system available from Microsoft Corporation of Redmond, Washington, although other operating systems (such as UNIX and Linux), embedded software, and / or graphical user interfaces can also be used.

[0080] The embodiments can be used in other devices, such as handheld devices and embedded applications. Some examples of handheld devices include cellular phones, Internet Protocol (IP) devices, digital cameras, personal digital assistants (“PDAs”), and handheld PCs. In at least one embodiment, the embedded application may include a microcontroller, a digital signal processor (“DSP”), a system-on-a-chip (SoC), a network computer (“NetPC”), a set-top box, a network hub, a wide area network (“WAN”) switch, or any other system capable of executing one or more instructions according to at least one embodiment.

[0081] In at least one embodiment, the computer system 800 may include, but is not limited to, a processor 802, which may include, but is not limited to, one or more execution units 808 for performing machine learning model training and / or inference according to the techniques described herein. In at least one embodiment, the computer system 800 is a single-processor desktop or server system, but in another embodiment, the computer system 800 may be a multiprocessor system. In at least one embodiment, the processor 802 may include, but is not limited to, for example, a Complex Instruction Set Computer (“CISC”) microprocessor, a Reduced Instruction Set Computing (“RISC”) microprocessor, a Very Long Instruction Word (“VLIW”) microprocessor, a processor implementing instruction set combination, or any other processor device, such as a digital signal processor. In at least one embodiment, the processor 802 may be coupled to a processor bus 810, which allows data signaling between the processor 802 and other components in the computer system 800.

[0082] In at least one embodiment, processor 802 may include, but is not limited to, a Level 1 (“L1”) internal cache memory (“cache”) 804. In at least one embodiment, processor 802 may have a single internal cache or multiple levels of internal caches. In at least one embodiment, the cache memory may reside external to processor 802. Depending on specific implementation and requirements, other embodiments may also include a combination of internal and external caches. In at least one embodiment, register file 806 may store different types of data in various registers, including but not limited to integer registers, floating-point registers, status registers, and instruction pointer registers.

[0083] In at least one embodiment, an execution unit 808, including but not limited to logic for performing integer and floating-point operations, is also located in the processor 802. In at least one embodiment, the processor 802 may also include a microcode (“ucode”) read-only memory (“ROM”) storing microcode of certain macro instructions. In at least one embodiment, the execution unit 808 may include logic for processing a packaged instruction set 809. In at least one embodiment, by including the packaged instruction set 809 in the instruction set of the general-purpose processor 802 and the associated circuitry to be executed, packaged data in the general-purpose processor 802 can be used to perform operations used by numerous multimedia applications. In one or more embodiments, numerous multimedia applications can be accelerated and executed more efficiently by using the full width of the processor's data bus to perform operations on packaged data, eliminating the need to transfer smaller data units on the processor's data bus to perform one or more operations on one data element at a time.

[0084] In at least one embodiment, execution unit 808 may also be used in a microcontroller, embedded processor, graphics device, DSP, and other types of logic circuitry. In at least one embodiment, computer system 800 may include, but is not limited to, memory 820. In at least one embodiment, memory 820 may be implemented as a dynamic random access memory (“DRAM”) device, a static random access memory (“SRAM”) device, a flash memory device, or other memory device. In at least one embodiment, memory 820 may store one or more instructions 819 and / or data 821 represented by data signals executable by processor 802.

[0085] In at least one embodiment, the system logic chip may be coupled to a processor bus 810 and a memory 820. In at least one embodiment, the system logic chip may include, but is not limited to, a memory controller hub (“MCH”) 816, and the processor 802 may communicate with the MCH 816 via the processor bus 810. In at least one embodiment, the MCH 816 may provide a high-bandwidth memory path 818 to the memory 820 for storing instructions and data, as well as for storing graphics commands, data, and textures. In at least one embodiment, the MCH 816 may direct data signals between the processor 802, the memory 820, and other components in the computer system 800, and bridge data signals between the processor bus 810, the memory 820, and the system I / O 822. In at least one embodiment, the system logic chip may provide a graphics port for coupling to a graphics controller. In at least one embodiment, the MCH 816 may be coupled to the memory 820 via the high-bandwidth memory path 818, and the graphics / video card 812 may be coupled to the MCH 816 via an Accelerated Graphics Port (“AGP”) interconnect 814.

[0086] In at least one embodiment, the computer system 800 may use system I / O 822 as a proprietary hub interface bus to couple MCH 816 to I / O controller hub (“ICH”) 830. In at least one embodiment, ICH 830 may provide direct connectivity to certain I / O devices via a local I / O bus. In at least one embodiment, the local I / O bus may include, but is not limited to, a high-speed I / O bus for connecting peripheral devices to memory 820, chipset, and processor 802. Examples may include, but are not limited to, an audio controller 829, a firmware hub (“Flash BIOS”) 828, a wireless transceiver 826, a data storage 824, a conventional I / O controller 823 including a user input and keyboard interface 825, a serial expansion port 827 (such as Universal Serial Bus (“USB”)), and a network controller 834. Data storage 824 may include a hard disk drive, floppy disk drive, CD-ROM device, flash memory device, or other mass storage device.

[0087] In at least one embodiment, Figure 8 A system including interconnected hardware devices or "chips" is shown, while in other embodiments, Figure 8 An exemplary system-on-a-chip (“SoC”) may be illustrated. In at least one embodiment, Figure 8 The devices shown can be interconnected using proprietary interconnects, standardized interconnects (e.g., PCIe), or some combination thereof. In at least one embodiment, one or more components of the computer system 800 are interconnected using a Compute Fast Link (CXL) interconnect.

[0088] Inference and / or training logic 615 is used to perform inference and / or training operations associated with one or more embodiments. The following is combined with... Figure 6A and / or Figure 6B Details are provided regarding the inference and / or training logic 615. In at least one embodiment, the inference and / or training logic 615 can be... Figure 8 Used in systems for inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases as described herein.

[0089] Inference and / or training logic 615 is used to perform inference and / or training operations associated with one or more embodiments. In at least one embodiment, this logic may be used with components of these graphs to generate one or more images using one or more neural networks, at least in part, based on one or more noise values.

[0090] Figure 9This is a block diagram illustrating an electronic device 900 for utilizing a processor 910 according to at least one embodiment. In at least one embodiment, the electronic device 900 may be, for example, but not limited to, a laptop computer, tower server, rack server, blade server, laptop computer, desktop computer, tablet computer, mobile device, telephone, embedded computer, or any other suitable electronic device.

[0091] In at least one embodiment, the electronic device 900 may, but is not limited to, a processor 910 communicatively coupled to any suitable number or type of components, peripherals, modules, or devices. In at least one embodiment, the processor 910 is coupled using a bus or interface, such as I... 2 C-bus, System Management Bus (“SMBus”), Low Pin Count (LPC) bus, Serial Peripheral Interface (“SPI”), High Definition Audio (“HDA”) bus, Serial Advanced Technology Accessory (“SATA”) bus, Universal Serial Bus (“USB”) (version 1, version 2, version 3) or Universal Asynchronous Receiver / Transmitter (“UART”) bus. In at least one embodiment, Figure 9 The system shown includes interconnected hardware devices or "chips," while in other embodiments, Figure 9 An exemplary system-on-a-chip (“SoC”) may be illustrated. In at least one embodiment, Figure 9 The devices shown can be interconnected using proprietary interconnects, standardized interconnects (e.g., PCIe), or some combination thereof. In at least one embodiment, Figure 9 One or more components are interconnected using Computational Fast Link (CXL) interconnect.

[0092] In at least one embodiment, Figure 9 This may include a display 924, a touchscreen 925, a touchpad 930, a near-field communication unit (“NFC”) 945, a sensor hub 940, a thermal sensor 946, a fast chipset (“EC”) 935, a trusted platform module (“TPM”) 938, a BIOS / firmware / flash memory (“BIOS, FW Flash”) 922, a DSP 960, a drive 920 (such as a solid-state drive (“SSD”) or a hard disk drive (“HDD”)), a wireless local area network unit (“WLAN”) 950, a Bluetooth unit 952, a wireless wide area network unit (“WWAN”) 956, a global positioning system (GPS) 955, a camera (“USB 3.0 camera”) 954 (such as a USB 3.0 camera), and / or a low-power double data rate (“LPDDR”) memory unit (“LPDDR3”) 915 implemented in, for example, the LPDDR3 standard. These components may each be implemented in any suitable manner.

[0093] In at least one embodiment, other components may be communicatively coupled to processor 910 via the components discussed above. In at least one embodiment, accelerometer 941, ambient light sensor (“ALS”) 942, compass 943, and gyroscope 944 may be communicatively coupled to sensor hub 940. In at least one embodiment, thermal sensor 939, fan 937, keyboard 936, and touchpad 930 may be communicatively coupled to EC 935. In at least one embodiment, speaker 963, earphone 964, and microphone (“mic”) 965 may be communicatively coupled to audio unit (“audio codec and Class D amplifier”) 962, which in turn may be communicatively coupled to DSP 960. In at least one embodiment, audio unit 962 may include, for example, but not limited to, audio encoder / decoder (“codec”) and Class D amplifier. In at least one embodiment, SIM card (“SIM”) 957 may be communicatively coupled to WWAN unit 956. In at least one embodiment, components such as WLAN unit 950, Bluetooth unit 952, and WWAN unit 956 may be implemented as next-generation form factors (“NGFF”).

[0094] Inference and / or training logic 615 is used to perform inference and / or training operations associated with one or more embodiments. The following is combined with... Figure 6A and / or Figure 6B Details are provided regarding the inference and / or training logic 615. In at least one embodiment, the inference and / or training logic 615 can be... Figure 9 Used in systems for inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases as described herein.

[0095] Inference and / or training logic 615 is used to perform inference and / or training operations associated with one or more embodiments. In at least one embodiment, this logic may be used with components of these graphs to generate one or more images using one or more neural networks, at least in part, based on one or more noise values.

[0096] Figure 10 A computer system 1000 according to at least one embodiment is shown. In at least one embodiment, the computer system 1000 is configured to implement various processes and methods described throughout this disclosure.

[0097] In at least one embodiment, the computer system 1000 includes, but is not limited to, at least one central processing unit (“CPU”) 1002 connected to a communication bus 1010 implemented using any suitable protocol, such as PCI (“Peripheral Component Interconnect”), Peripheral Component Interconnect Fast (“PCI-Express”), AGP (“Accelerated Graphics Port”), HyperTransport, or any other bus or point-to-point communication protocol. In at least one embodiment, the computer system 1000 includes, but is not limited to, main memory 1004 and control logic (e.g., implemented in hardware, software, or a combination thereof), and data is stored in the main memory 1004, which may take the form of random access memory (“RAM”). In at least one embodiment, a network interface subsystem (“network interface”) 1022 provides an interface to other computing devices and networks for receiving data from and sending data to other systems using the computer system 1000.

[0098] In at least one embodiment, the computer system 1000 includes, but is not limited to, an input device 1008, a parallel processing system 1012, and a display device 1006, which may be implemented using conventional cathode ray tubes (“CRTs”), liquid crystal displays (“LCDs”), light-emitting diodes (“LEDs”), plasma displays, or other suitable display technologies. In at least one embodiment, user input is received from the input device 1008 (such as a keyboard, mouse, touchpad, microphone, etc.). In at least one embodiment, each of the foregoing modules may reside on a single semiconductor platform to form the processing system.

[0099] Inference and / or training logic 615 is used to perform inference and / or training operations associated with one or more embodiments. The following is combined with... Figure 6A and / or Figure 6B Details are provided regarding the inference and / or training logic 615. In at least one embodiment, the inference and / or training logic 615 can be... Figure 10 The system is used to perform inference or prediction operations based at least in part on weight parameters calculated using the neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0100] Inference and / or training logic 615 is used to perform inference and / or training operations associated with one or more embodiments. In at least one embodiment, this logic may be used with components of these graphs to generate one or more images using one or more neural networks, at least in part, based on one or more noise values.

[0101] Figure 11A computer system 1100 according to at least one embodiment is illustrated. In at least one embodiment, the computer system 1100 includes, but is not limited to, a computer 1110 and a USB flash drive 1120. In at least one embodiment, the computer 1110 may include, but is not limited to, any number and type of processors (not shown) and memory (not shown). In at least one embodiment, the computer 1110 includes, but is not limited to, a server, a cloud instance, a laptop computer, and a desktop computer.

[0102] In at least one embodiment, the USB flash drive 1120 includes, but is not limited to, a processing unit 1130, a USB interface 1140, and USB interface logic 1150. In at least one embodiment, the processing unit 1130 can be any instruction execution system, apparatus, or device capable of executing instructions. In at least one embodiment, the processing unit 1130 can include, but is not limited to, any number and type of processing cores (not shown). In at least one embodiment, the processing unit 1130 includes an application-specific integrated circuit (“ASIC”) optimized to perform any number and type of operations associated with machine learning. For example, in at least one embodiment, the processing unit 1130 is a tensor processing unit (“TPC”) optimized to perform machine learning inference operations. In at least one embodiment, the processing unit 1130 is a vision processing unit (“VPU”) optimized to perform machine vision and machine learning inference operations.

[0103] In at least one embodiment, the USB interface 1140 can be any type of USB connector or USB receptacle. For example, in at least one embodiment, the USB interface 1140 is a USB 3.0 Type-C receptacle for data and power. In at least one embodiment, the USB interface 1140 is a USB 3.0 Type-A connector. In at least one embodiment, the USB interface logic 1150 may include any amount and type of logic enabling the processing unit 1130 to interface with a device (e.g., computer 1110) via the USB connector 1140.

[0104] Inference and / or training logic 615 is used to perform inference and / or training operations associated with one or more embodiments. The following is combined with... Figure 6A and / or Figure 6B Details are provided regarding the inference and / or training logic 615. In at least one embodiment, the inference and / or training logic 615 can be... Figure 11 Used in systems for inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases as described herein.

[0105] Inference and / or training logic 615 is used to perform inference and / or training operations associated with one or more embodiments. In at least one embodiment, this logic may be used with components of these graphs to generate one or more images using one or more neural networks, at least in part, based on one or more noise values.

[0106] Figure 12A An exemplary architecture is illustrated, in which multiple GPUs 1210-1213 are communicatively coupled to multiple multi-core processors 1205-1206 via high-speed links 1240-1243 (e.g., bus, point-to-point interconnect, etc.). In one embodiment, the high-speed links 1240-1243 support communication throughput of 4GB / s, 30GB / s, 80GB / s, or higher. Various interconnect protocols can be used, including but not limited to PCIe 4.0 or 5.0 and NVLink 2.0.

[0107] Furthermore, in one embodiment, two or more GPUs 1210-1213 are interconnected via high-speed links 1229-1230, which may use the same or different protocols / links as those used for high-speed links 1240-1243. Similarly, two or more multi-core processors 1205-1206 may be connected via high-speed link 1228, which may be a symmetric multiprocessor (SMP) bus operating at speeds of 20GB / s, 30GB / s, 120GB / s, or higher. Alternatively, the same protocol / link (e.g., via a common interconnect structure) may be used. Figure 12A This shows all communication between the various system components.

[0108] In one embodiment, each multi-core processor 1205-1206 is communicatively coupled to processor memories 1201-1202 via memory interconnects 1226-1227, and each GPU 1210-1213 is communicatively coupled to GPU memories 1220-1223 via GPU memory interconnects 1250-1253. Memory interconnects 1226 and 1250 may utilize the same or different memory access technologies. By way of example and not limitation, processor memories 1201-1202 and GPU memories 1220-1223 may be volatile memories, such as dynamic random access memory (DRAM) (including stacked DRAM), graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or high-bandwidth memory (HBM), and / or may be non-volatile memories, such as 3D XPoint or Nano-RAM. In one embodiment, some portions of the processor memories 1201-1202 may be volatile memory, while other portions may be non-volatile memory (e.g., using a two-level memory (2LM) hierarchy).

[0109] As described below, although the individual multi-core processors 1205-1206 and GPUs 1210-1213 can be physically coupled to specific memories 1201-1202 and 1220-1223 respectively, a unified memory architecture can be implemented, in which the same virtual system address space (also known as the "effective address" space) is distributed among the various physical memories. For example, processor memories 1201-1202 can each include 64GB of system memory address space, and GPU memories 1220-1223 can each include 32GB of system memory address space (resulting in a total of 256GB of addressable memory in this example).

[0110] Figure 12B Additional details are shown regarding the interconnection between a multi-core processor 1207 and a graphics acceleration module 1246 according to an exemplary embodiment. The graphics acceleration module 1246 may include one or more GPU chips integrated on a line card coupled to the processor 1207 via a high-speed link 1240. Alternatively, the graphics acceleration module 1246 may be integrated on the same package or chip as the processor 1207.

[0111] In at least one embodiment, the processor 1207 shown includes a plurality of cores 1260A-1260D, each core having a translation back buffer 1261A-1261D and one or more caches 1262A-1262D. In at least one embodiment, cores 1260A-1260D may include various other components, not shown, for executing instructions and processing data. Caches 1262A-1262D may include Level 1 (L1) and Level 2 (L2) caches. Furthermore, one or more shared caches 1256 may be included in caches 1262A-1262D and shared by the respective groups of cores 1260A-1260D. For example, one embodiment of processor 1207 includes 24 cores, each core having its own L1 cache, 12 shared L2 caches, and 12 shared L3 caches. In this embodiment, two adjacent cores share one or more L2 and L3 caches. Processor 1207 and graphics acceleration module 1246 are connected to system memory 1214, which may include Figure 12A The processor memory 1201-1202 in the middle.

[0112] The consistency bus 1264 maintains consistency for data and instructions stored in the various caches 1262A-1262D, 1256 and system memory 1214 via inter-core communication. For example, each cache may have associated cache consistency logic / circuit to communicate via the consistency bus 1264 in response to the detection of a read or write to a specific cache line. In one implementation, a cache snooping protocol is implemented via the consistency bus 1264 to snoop on cache accesses.

[0113] In one embodiment, proxy circuitry 1225 communicatively couples graphics acceleration module 1246 to coherence bus 1264, thereby allowing graphics acceleration module 1246 to participate in cache coherence protocols as a peer of cores 1260A-1260D. Specifically, interface 1235 provides connectivity to proxy circuitry 1225 via high-speed link 1240 (e.g., PCIe bus, NVLink, etc.), and interface 1237 connects graphics acceleration module 1246 to high-speed link 1240.

[0114] In one implementation, the accelerator integrated circuit 1236 provides cache management, memory access, context management, and interrupt management services for multiple graphics processing engines 1231, 1232, and N of the graphics acceleration module 1246. The graphics processing engines 1231, 1232, and N may each include a separate graphics processing unit (GPU). Alternatively, the graphics processing engines 1231, 1232, and N may include different types of graphics processing engines within the GPU, such as graphics execution units, media processing engines (e.g., video encoders / decoders), samplers, and blit (block-moving) engines. In at least one embodiment, the graphics acceleration module 1246 may be a GPU with multiple graphics processing engines 1231, 1232, and N, or the graphics processing engines 1231, 1232, and N may be individual GPUs integrated on a general-purpose package, line card, or chip.

[0115] In one embodiment, the accelerator integrated circuit 1236 includes a memory management unit (MMU) 1239 for performing various memory management functions, such as virtual-to-physical memory translation (also known as effective-to-real memory translation), and a memory access protocol for accessing system memory 1214. The MMU 1239 may also include a translation back buffer (“TLB”) (not shown) for caching virtual / effective-to-physical / real address translations. In one implementation, cache 1238 stores commands and data for efficient access by graphics processing engines 1231-1232, N. In one embodiment, data stored in cache 1238 and graphics memories 1233-1234, M is kept consistent with core caches 1262A-1262D, 1256 and system memory 1214. As described above, this can mean that cache 1238 and memories 1233-1234, M are implemented via proxy circuitry 1225 (e.g., sending updates related to modifications / accesses to cache lines on processor caches 1262A-1262D, 1256 to cache 1238 and receiving updates from cache 1238).

[0116] A set of registers 1245 stores context data for threads executed by graphics processing engines 1231-1232, and context management circuitry 1248 manages the thread context. For example, context management circuitry 1248 can perform save and restore operations to save and restore the context of individual threads during context switching (e.g., saving the first thread and storing the second thread so that the second thread can be executed by the graphics processing engine). For example, during context switching, context management circuitry 1248 can store the current register value in a designated area of ​​memory (e.g., identified by a context pointer). The register value can then be restored upon returning to the context. In one embodiment, interrupt management circuitry 1247 receives and processes interrupts received from system devices.

[0117] In one implementation, MMU 1239 translates virtual / effective addresses from graphics processing engine 1231 into real / physical addresses in system memory 1214. One embodiment of accelerator integrated circuit 1236 supports multiple (e.g., 4, 8, 16) graphics accelerator modules 1246 and / or other accelerator devices. Graphics accelerator module 1246 may be dedicated to a single application executing on processor 1207, or may be shared among multiple applications. In one embodiment, a virtualized graphics execution environment is presented, where the resources of graphics processing engines 1231-1232, N are shared with multiple applications or virtual machines (VMs). In at least one embodiment, resources may be subdivided into “slices” based on processing requirements and priorities associated with VMs and / or applications, which are allocated to different VMs and / or applications.

[0118] In at least one embodiment, the accelerator integrated circuit 1236 acts as a bridge to the system of the graphics acceleration module 1246, providing address translation and system memory caching services. Additionally, the accelerator integrated circuit 1236 can provide virtualization facilities for the host processor to manage the virtualization, interrupt, and memory management of the graphics processing engines 1231-1232, N.

[0119] Because the hardware resources of graphics processing engines 1231-1232, N are explicitly mapped to the actual address space seen by the host processor 1207, any host processor can directly address these resources using valid address values. In one embodiment, one function of the accelerator integrated circuit 1236 is to physically separate the graphics processing engines 1231-1232, N, so that they appear as independent units to the system.

[0120] In at least one embodiment, one or more graphics memories 1233-1234, M are coupled to each graphics processing engine 1231-1232, N, respectively. Graphics memories 1233-1234, M store instructions and data being processed by each graphics processing engine 1231-1232, N. In at least one embodiment, graphics memories 1233-1234, M may be volatile memories, such as DRAM (including stacked DRAM), GDDR memory (e.g., GDDR5, GDDR6), or HBM, and / or may be non-volatile memories, such as 3D XPoint or Nano-RAM.

[0121] In one embodiment, to reduce data traffic on the high-speed link 1240, a biasing technique is used to ensure that the data stored in the graphics memories 1233-1234, M is the data most frequently used by the graphics processing engines 1231-1232, N, and preferably data that is not used (or at least infrequently used) by the cores 1260A-1260D. Similarly, the biasing mechanism attempts to keep data needed by the cores (and preferably not needed by the graphics processing engines 1231-1232, N) in the core caches 1262A-1262D, 1256 and system memory 1214.

[0122] Figure 12C Another exemplary embodiment is shown, in which the accelerator integrated circuit 1236 is integrated within the processor 1207. At least in this embodiment, the graphics processing engines 1231-1232, N communicate directly with the accelerator integrated circuit 1236 via a high-speed link 1240 through interfaces 1237 and 1235 (again, which can utilize any form of bus or interface protocol). The accelerator integrated circuit 1236 can perform operations related to… Figure 12B The operation described is the same, but due to its close proximity to the coherence bus 1264 and caches 1262A-1262D, 1256, it may have higher throughput. At least one embodiment supports different programming models, including a process-specific programming model (without graphics acceleration module virtualization) and a shared programming model (with virtualization). These programming models may include a programming model controlled by accelerator integrated circuit 1236 and a programming model controlled by graphics acceleration module 1246.

[0123] In at least one embodiment, graphics processing engines 1231-1232, N are dedicated to a single application or process under a single operating system. In at least one embodiment, a single application can funnel requests from other applications to graphics processing engines 1231-1232, N, thereby providing virtualization within a VM / partition.

[0124] In at least one embodiment, graphics processing engines 1231-1232, N can be shared by multiple VM / application partitions. In at least one embodiment, the shared model can use a hypervisor to virtualize graphics processing engines 1231-1232, N to allow each operating system to access them. For a single-partition system without a hypervisor, the operating system owns graphics processing engines 1231-1232, N. In at least one embodiment, the operating system can virtualize graphics processing engines 1231-1232, N to provide access to each process or application.

[0125] In at least one embodiment, the graphics acceleration module 1246 or the individual graphics processing engines 1231-1232, N uses a process handle to select a process element. In at least one embodiment, the process element is stored in system memory 1214 and can be addressed using the effective address to physical address translation techniques described herein. In at least one embodiment, the process handle may be an implementation-specific value that is provided to the host process when registering its context with the graphics processing engines 1231-1232, N (i.e., invoking system software to add the process element to the process element linked list). In at least one embodiment, the lower 16 bits of the process handle may be the offset of the process element in the process element linked list.

[0126] Figure 12D An exemplary accelerator integration slice 1290 is illustrated. As used herein, a “slice” includes a designated portion of the processing resources of the accelerator integrated circuit 1236. The application is an effective address space 1282 in system memory 1214, which stores process element 1283. In one embodiment, process element 1283 is stored in response to a GPU call 1281 from an application 1280 executing on processor 1207. Process element 1283 contains the process state of the corresponding application 1280. A job descriptor (WD) 1284 contained in process element 1283 may be a single job requested by the application, or it may contain a pointer to a job queue. In at least one embodiment, WD 1284 is a pointer to a job request queue in the application's address space 1282.

[0127] The graphics acceleration module 1246 and / or the various graphics processing engines 1231-1232, N can be shared by all processes or a subset of processes in the system. In at least one embodiment, infrastructure may be included for setting process states and sending WD 1284 to the graphics acceleration module 1246 to begin operations in a virtualized environment.

[0128] In at least one embodiment, the process-specific programming model is implementation-specific. In this model, a single process owns either the graphics acceleration module 1246 or an individual graphics processing engine 1231. Since the graphics acceleration module 1246 is owned by a single process, the hypervisor initializes the accelerator integrated circuit for the owned partition, and when the graphics acceleration module 1246 is assigned, the operating system initializes the accelerator integrated circuit 1236 for the owned process.

[0129] In operation, the WD fetch unit 1291 in the accelerator integrated slice 1290 fetches the next WD 1284, which includes instructions for the work to be performed by one or more graphics processing engines of the graphics acceleration module 1246. Data from the WD 1284 can be stored in register 1245 and used by the MMU 1239, interrupt management circuitry 1247, and / or context management circuitry 1248, as shown. For example, one embodiment of the MMU 1239 includes segment / page walk circuitry for accessing segment / page tables 1286 within the OS virtual address space 1285. The interrupt management circuitry 1247 can handle interrupt events 1292 received from the graphics acceleration module 1246. When performing graphics operations, the effective address 1293 generated by the graphics processing engines 1231-1232, N is translated into a real address by the MMU 1239.

[0130] In one embodiment, the same set of registers 1245 is copied for each graphics processing engine 1231-1232, N, and / or graphics acceleration module 1246, and these registers 1245 can be initialized by a hypervisor or the operating system. Each of these copied registers can be included in the accelerator integration slice 1290. Exemplary registers that can be initialized by a hypervisor are shown in Table 1.

[0131] Table 1 – Registers for Supervisor Initialization

[0132]

[0133]

[0134] Table 2 shows exemplary registers that can be initialized by the operating system.

[0135] Table 2 – Operating System Initialization Registers

[0136] 1 Process and thread identifiers 2 Valid Address (EA) Context Save / Restore Pointer 3 Virtual Address (VA) accelerator utilization record pointer 4 Virtual address (VA) memory segment table pointer 5 Access Control 6 Job descriptor

[0137] In one embodiment, each WD 1284 is dedicated to a specific graphics acceleration module 1246 and / or graphics processing engine 1231-1232, N. It contains all the information required for the graphics processing engine 1231-1232, N to complete its work, or it may be a pointer to a memory location where the application has set up a command queue for the work to be completed.

[0138] Figure 12E Additional details of an exemplary embodiment of the shared model are shown. This embodiment includes a hypervisor real address space 1298, in which a list of process elements 1299 is stored. The hypervisor real address space 1298 can be accessed via a hypervisor 1296, which virtualizes the graphics acceleration module engine for operating system 1295.

[0139] In at least one embodiment, the shared programming model allows all processes or subsets of processes from all partitions or subsets of partitions in the system to use the graphics acceleration module 1246. Two programming models exist where the graphics acceleration module 1246 is shared by multiple processes and partitions: time-slice sharing and graphics-oriented sharing.

[0140] In this model, the hypervisor 1296 owns the graphics acceleration module 1246 and makes its functionality available to all operating systems 1295. For the graphics acceleration module 1246 to support virtualization through the hypervisor 1296, the graphics acceleration module 1246 can comply with the following: 1) Application job requests must be autonomous (i.e., no state needs to be maintained between jobs), or the graphics acceleration module 1246 must provide context saving and restoration mechanisms. 2) The graphics acceleration module 1246 guarantees that application job requests are completed within a specified amount of time, including any translation errors, or the graphics acceleration module 1246 provides the ability to preempt job processing. 3) When operating in a directed shared programming model, fairness of the graphics acceleration module 1246 among processes must be ensured.

[0141] In at least one embodiment, application 1280 needs to make a system call to operating system 1295 using graphics acceleration module 1246 type, working descriptor (WD), authority mask register (AMR) value, and context save / restore region pointer (CSRP). In at least one embodiment, the graphics acceleration module 1246 type describes the target acceleration function for the system call. In at least one embodiment, the graphics acceleration module 1246 type can be a system-specific value. In at least one embodiment, the WD is specifically formatted for graphics acceleration module 1246 and can take the form of graphics acceleration module 1246 commands, valid address pointers to user-defined structures, valid address pointers to command queues, or any other data structure describing the work to be performed by graphics acceleration module 1246. In one embodiment, the AMR value is the AMR state for the current process. In at least one embodiment, the value passed to the operating system is similar to that of the application that sets the AMR. If the implementation of accelerator integrated circuit 1236 and graphics acceleration module 1246 does not support the User Authority Mask Overwrite Register (UAMOR), the operating system can apply the current UAMOR value to the AMR value before passing the AMR in the hypervisor call. Hypervisor 1296 may selectively apply the Current Privilege Mask Overwrite Register (AMOR) value before placing the AMR into process element 1283. In at least one embodiment, CSRP is one of registers 1245 containing the effective address of a region in the application's effective address space 1282 for the graphics acceleration module 1246 to save and restore context state. This pointer is optional if saving state between jobs is not required or when a job is preempted. In at least one embodiment, the context save / restore region may be fixed system memory.

[0142] Upon receiving a system call, the operating system 1295 can verify that the application 1280 has been registered and granted permission to use the graphics acceleration module 1246. Then, the operating system 1295 uses the information shown in Table 3 to invoke the hypervisor 1296.

[0143] Table 3 – Operating System to Hypervisor Call Parameters

[0144] 1 Working Descriptor (WD) 2 Access Control Register (AMR) value (may be masked) 3 Valid Address (EA) Context Save / Restore Region Pointer (CSRP) 4 Process ID (PID) and optional thread ID (TID) 5 Virtual Address (VA) Accelerator Utilization Log Pointer (AURP) 6 Virtual address of the segment table pointer (SSTP) 7 Logical Interrupt Service Number (LISN)

[0145] Upon receiving a hypervisor call, hypervisor 1296 verifies that operating system 1295 has been registered and granted permission to use graphics acceleration module 1246. Then, hypervisor 1296 adds process element 1283 to the linked list of process elements of the corresponding graphics acceleration module 1246 type. The process element may include the information shown in Table 4.

[0146] Table 4 – Process Element Information

[0147] 1 Working Descriptor (WD) 2 Access Control Register (AMR) value (may be masked) 3 Valid Address (EA) Context Save / Restore Region Pointer (CSRP) 4 Process ID (PID) and optional thread ID (TID) 5 Virtual Address (VA) Accelerator Utilization Log Pointer (AURP) 6 Virtual address of the segment table pointer (SSTP) 7 Logical Interrupt Service Number (LISN) 8 Interrupt vector table derived from parameters called by the management program 9 Status Register (SR) Value 10 Logical Partition ID (LPID) 11 Real Address (RA) Manager Accelerator Utilization Record Pointer 12 Storage Descriptor Register (SDR)

[0148] In at least one embodiment, the hypervisor initializes registers 1245 of multiple accelerator integration slices 1290.

[0149] like Figure 12F As shown, in at least one embodiment, a unified memory is used, which is addressable via a common virtual memory address space for accessing physical processor memories 1201-1202 and GPU memories 1220-1223. In this implementation, operations performed on GPUs 1210-1213 utilize the same virtual / effective memory address space to access processor memories 1201-1202 and vice versa, thereby simplifying programmability. In one embodiment, a first portion of the virtual / effective address space is allocated to processor memory 1201, a second portion to second processor memory 1202, a third portion to GPU memory 1220, and so on. In at least one embodiment, the entire virtual / effective memory space (sometimes referred to as the effective address space) is thus distributed across each of processor memories 1201-1202 and GPU memories 1220-1223, thereby allowing any processor or GPU to access that memory using a virtual address mapped to any physical memory.

[0150] In one embodiment, the bias / coherence management circuitry 1294A-1294E within one or more MMUs 1239A-1239E ensures cache coherence between the caches of one or more host processors (e.g., 1205) and the GPUs 1210-1213, and implements biasing techniques that indicate the physical memory in which certain types of data should be stored. While in Figure 12F Several instances of the bias / coherence management circuitry 1294A-1294E are shown, but the bias / coherence circuitry can be implemented within the MMU of one or more host processors 1205 and / or within the accelerator integrated circuit 1236.

[0151] One embodiment allows the attached GPU's memory 1220-1223 to be mapped as part of the system memory and accessed using shared virtual memory (SVM) technology without suffering the performance drawbacks associated with system-wide cache coherence. In at least one embodiment, the ability of the attached GPU's memory 1220-1223 to be accessed as system memory without the heavy overhead of cache coherence provides a favorable operating environment for GPU offloading. This arrangement allows the host processor 1205 to software-set operands and access computation results without the overhead of conventional I / O DMA data copying. Such conventional copying includes driver calls, interrupts, and memory-mapped I / O (MMIO) accesses, all of which are less efficient than simple memory accesses. In at least one embodiment, the ability to access the attached GPU's memory 1220-1223 without cache coherence overhead can be critical for the execution time of offloaded computations. For example, in cases with high volumes of streaming write memory traffic, cache coherence overhead can significantly reduce the effective write bandwidth seen by the GPUs 1210-1213. In at least one embodiment, the efficiency of operand setup, the efficiency of result access, and the efficiency of GPU computation may play a role in determining the effectiveness of GPU offloading.

[0152] In at least one embodiment, the selection of GPU bias and host processor bias is driven by a bias tracker data structure. For example, a bias table can be used, which may be a page-granular structure (e.g., controlled at the memory page level) comprising 1 or 2 bits per memory page of each attached GPU. In at least one embodiment, with or without a bias cache (e.g., for caching frequently / recently used entries in the bias table) in GPUs 1210-1213, the bias table can be implemented over the stolen memory range of one or more attached GPUs' memory 1220-1223. Alternatively, the entire bias table can be maintained within the GPU.

[0153] In at least one embodiment, prior to actual access to GPU memory, the bias table entry associated with each access to the attached GPU's memory 1220-1223 is accessed, causing the following operations: First, a local request from GPU 1210 to find its page in the GPU bias is directly forwarded to the corresponding GPU memory 1220-1223. A local request from the GPU to find its page in the host bias is forwarded to processor 1205 (e.g., via the high-speed link discussed above). In one embodiment, a request from processor 1205 to find the requested page in the host processor bias completes a request similar to a normal memory read. Alternatively, requests to GPU bias pages can be forwarded to GPUs 1210-1213. In at least one embodiment, if the GPU is not currently using the page, the GPU can migrate the page to the host processor bias. In at least one embodiment, the page bias state can be changed by a software-based mechanism, a hardware-assisted software mechanism, or, in a limited set of cases, by a purely hardware-based mechanism.

[0154] One mechanism for changing the bias state employs an API call (e.g., OpenCL), which in turn invokes the GPU's device driver, which in turn sends a message (or enqueues a command descriptor) to the GPU, instructing the GPU to change the bias state and, in some migrations, performs a cache refresh operation on the host. In at least one embodiment, the cache refresh operation is used for migrating from the host processor 1205 bias to the GPU bias, but not for the reverse migration.

[0155] In one embodiment, cache coherence is maintained by temporarily rendering GPU bias pages that the host processor 1205 cannot cache. To access these pages, the processor 1205 may request access from the GPU 1210, which may or may not grant access immediately. Therefore, to reduce communication between the processor 1205 and the GPU 1210, it is beneficial to ensure that the GPU bias pages are pages needed by the GPU, not those needed by the host processor 1205, and vice versa.

[0156] The inference and / or training logic 615 is used to execute one or more implementations. (In conjunction with...) Figure 6A and / or Figure 6B Provide details about reasoning and / or training logic 615.

[0157] Inference and / or training logic 615 is used to perform inference and / or training operations associated with one or more embodiments. In at least one embodiment, this logic may be used with components of these graphs to generate one or more images using one or more neural networks, at least in part, based on one or more noise values.

[0158] Figure 13 Exemplary integrated circuits and associated graphics processors according to various embodiments described herein are illustrated, which can be manufactured using one or more IP cores. In addition to those illustrated, at least one embodiment may also include other logic and circuitry, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0159] Figure 13 This is a block diagram illustrating an exemplary system on a chip integrated circuit 1300 that can be fabricated using one or more IP cores according to at least one embodiment. In at least one embodiment, the integrated circuit 1300 includes one or more application processors 1305 (e.g., CPU), at least one graphics processor 1310, and may additionally include an image processor 1315 and / or a video processor 1320, any of which may be a modular IP core. In at least one embodiment, the integrated circuit 1300 includes peripheral or bus logic, which includes a USB controller 1325, a UART controller 1330, an SPI / SDIO controller 1335, and an I... 2 S / I 2 C controller 1340. In at least one embodiment, integrated circuit 1300 may include a display device 1345 coupled to one or more of a High Definition Multimedia Interface (HDMI) controller 1350 and a Mobile Industrial Processor Interface (MIPI) display interface 1355. In at least one embodiment, storage may be provided by a flash memory subsystem 1360, which includes flash memory and a flash memory controller. In at least one embodiment, a memory interface may be provided via a memory controller 1365 for accessing an SDRAM or SRAM memory device. In at least one embodiment, some integrated circuits also include an embedded security engine 1370.

[0160] Inference and / or training logic 615 is used to perform inference and / or training operations associated with one or more embodiments. The following is combined with... Figure 6A and / or Figure 6BDetails are provided regarding the inference and / or training logic 615. In at least one embodiment, the inference and / or training logic 615 may be used in integrated circuit 1300 to infer or predict operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0161] Inference and / or training logic 615 is used to perform inference and / or training operations associated with one or more embodiments. In at least one embodiment, this logic may be used with components of these graphs to generate one or more images using one or more neural networks, at least in part, based on one or more noise values.

[0162] Figures 14A-14B Exemplary integrated circuits and associated graphics processors according to various embodiments described herein are illustrated, which may be fabricated using one or more IP cores. In addition to those illustrated, at least one embodiment may include other logic and circuitry, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0163] Figures 14A-14B This is a block diagram illustrating an exemplary graphics processor used within a SoC according to embodiments described herein. Figure 14A An exemplary graphics processor 1410 of a system-on-a-chip integrated circuit according to at least one embodiment is shown, which can be manufactured using one or more IP cores. Figure 14B An additional exemplary graphics processor 1440 of a system-on-a-chip integrated circuit according to at least one embodiment is shown, which can be manufactured using one or more IP cores. In at least one embodiment, Figure 14A The graphics processor 1410 is a low-power graphics processor core. In at least one embodiment, Figure 14B The graphics processor 1440 is a higher-performance graphics processor core. In at least one embodiment, each graphics processor 1410, 1440 may be... Figure 13 A variant of the 1310 graphics processor.

[0164] In at least one embodiment, the graphics processor 1410 includes a vertex processor 1405 and one or more fragment processors 1415A-1415N (e.g., 1415A, 1415B, 1415C, 1415D to 1415N-1 and 1415N). In at least one embodiment, the graphics processor 1410 may execute different shader programs via separate logic, such that the vertex processor 1405 is optimized to perform operations for vertex shader programs, while one or more fragment processors 1415A-1415N perform fragment (e.g., pixel) shading operations for fragment or pixel shader programs. In at least one embodiment, the vertex processor 1405 performs the vertex processing stage of the 3D graphics pipeline and generates primitive and vertex data. In at least one embodiment, one or more fragment processors 1415A-1415N use the primitive and vertex data generated by the vertex processor 1405 to generate framebuffers for display on a display device. In at least one embodiment, one or more fragment processors 1415A-1415N are optimized to execute fragment shader programs as provided in the OpenGL API, which can be used to perform operations similar to those of pixel shader programs provided in the Direct 3D API.

[0165] In at least one embodiment, the graphics processor 1410 additionally includes one or more memory management units (MMUs) 1420A-1420B, one or more caches 1425A-1425B, and one or more circuit interconnects 1430A-1430B. In at least one embodiment, the one or more MMUs 1420A-1420B provide virtual-to-physical address mapping for the graphics processor 1410 (including for the vertex processor 1405 and / or fragment processors 1415A-1415N), and may reference vertex or image / texture data stored in memory in addition to vertex or image / texture data stored in the one or more caches 1425A-1425B. In at least one embodiment, one or more MMUs 1420A-1420B can be synchronized with other MMUs within the system, including one or more MMUs associated with one or more application processors 1305, graphics processors 1315, and / or video processors 1320 of FIG. 13, such that each processor 1305-1320 can participate in a shared or unified virtual memory system. In at least one embodiment, one or more circuit interconnects 1430A-1430B enable the graphics processor 1410 to interface with other IP cores within the SoC via the SoC's internal bus or via a direct connection.

[0166] In at least one embodiment, the graphics processor 1440 includes Figure 14A The graphics processor 1410 includes one or more MMUs 1420A-1420B, one or more caches 1425A-1425B, and one or more circuit interconnects 1430A-1430B. In at least one embodiment, the graphics processor 1440 includes, as shown in the figure, Figure 14B The one or more shader cores 1455A-1455N (e.g., 1455A, 1455B, 1455C, 1455D, 1455E, 1455F to 1455N-1 and 1455N) shown provide a unified shader core architecture, wherein a single core or type or core can execute all types of programmable shader code, including shader program code for implementing vertex shaders, fragment shaders, and / or compute shaders. In at least one embodiment, the number of shader cores can vary. In at least one embodiment, the graphics processor 1440 includes an inter-core task manager 1445, which acts as a thread dispatcher for dispatching execution threads to one or more shader cores 1455A-1455N and a tile unit 1458 to accelerate tile-based rendering operations, where scene rendering operations are subdivided in image space, for example, to utilize local spatial consistency within the scene or optimize the use of internal caches.

[0167] Inference and / or training logic 615 is used to perform inference and / or training operations associated with one or more embodiments. The following is combined with... Figure 6A and / or Figure 6B Details are provided regarding the inference and / or training logic 615. In at least one embodiment, the inference and / or training logic 615 can be... Figure 14A and / or Figure 14B The integrated circuit uses inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases as described herein. Inference and / or training logic 615 is used to perform inference and / or training operations associated with one or more embodiments. In at least one embodiment, this logic can be used with components of these graphs to generate one or more images using one or more neural networks based at least in part on one or more noise values.

[0168] Figures 15A-15B Additional exemplary graphics processor logic according to embodiments described herein is illustrated. In at least one embodiment, Figure 15A It shows that it can be included in Figure 13 The graphics core 1500 within the graphics processor 1310, and in at least one embodiment, may be as follows: Figure 14B The Unified Shader Core 1455A-1455N shown is an example. Figure 15B A highly parallel general-purpose graphics processing unit 1530 suitable for deployment on a multi-chip module is shown in at least one embodiment.

[0169] In at least one embodiment, the graphics core 1500 includes a shared instruction cache 1502, texture units 1518, and cache / shared memory 1520, which are shared for execution resources within the graphics core 1500. In at least one embodiment, the graphics core 1500 may include multiple slices 1501A-1501N or partitions of each core, and the graphics processor may include multiple instances of the graphics core 1500. Slices 1501A-1501N may include supporting logic, including local instruction caches 1504A-1504N, thread schedulers 1506A-1506N, thread dispatchers 1508A-1508N, and a set of registers 1510A-1510N. In at least one embodiment, slices 1501A-1501N may include a set of additional functional units (AFU 1512A-1512N), floating-point units (FPU 1514A-1514N), integer arithmetic logic units (ALU 1516A-1516N), address calculation units (ACU 1513A-1513N), double-precision floating-point units (DPFPU 1515A-1515N), and matrix processing units (MPU 1517A-1517N).

[0170] In at least one embodiment, the FPU 1514A-1514N can perform single-precision (32-bit) and half-precision (16-bit) floating-point operations, while the DPFPU 1515A-1515N performs double-precision (64-bit) floating-point operations. In at least one embodiment, the ALU 1516A-1516N can perform variable-precision integer operations with 8-bit, 16-bit, and 32-bit precision, and can be configured for mixed-precision operations. In at least one embodiment, the MPU 1517A-1517N can also be configured for mixed-precision matrix operations, including half-precision floating-point operations and 8-bit integer operations. In at least one embodiment, the MPU 1517A-1517N can perform various matrix operations to accelerate machine learning application frameworks, including enabling support for accelerated generalized matrix-to-matrix multiplication (GEMM). In at least one embodiment, the AFU 1512A-1512N can perform additional logical operations not supported by the floating-point or integer units, including trigonometric function operations (e.g., sine, cosine, etc.).

[0171] Inference and / or training logic 615 is used to perform inference and / or training operations associated with one or more embodiments. The following is combined with... Figure 6A and / or Figure 6B Details regarding inference and / or training logic 615 are provided. In at least one embodiment, inference and / or training logic 615 may be used in graphics core 1500 for performing inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0172] Inference and / or training logic 615 is used to perform inference and / or training operations associated with one or more embodiments. In at least one embodiment, this logic may be used with components of these graphs to generate one or more images using one or more neural networks, at least in part, based on one or more noise values.

[0173] Figure 15B A general-purpose processing unit (GPGPU) 1530 is illustrated in at least one embodiment, which can be configured to enable highly parallel computational operations to be performed by an array of graphics processing units. In at least one embodiment, the GPGPU 1530 can be directly linked to other instances of the GPGPU 1530 to create a multi-GPU cluster to improve the training speed for deep neural networks. In at least one embodiment, the GPGPU 1530 includes a host interface 1532 for establishing a connection with a host processor. In at least one embodiment, the host interface 1532 is a PCI Express interface. In at least one embodiment, the host interface 1532 can be a vendor-specific communication interface or communication structure. In at least one embodiment, the GPGPU 1530 receives commands from the host processor and uses a global scheduler 1534 to allocate execution threads associated with those commands to a group of compute clusters 1536A-1536H. In at least one embodiment, compute clusters 1536A-1536H share a cache memory 1538. In at least one embodiment, cache memory 1538 can be used as a higher-level cache within the cache memory of computing clusters 1536A-1536H.

[0174] In at least one embodiment, the GPGPU 1530 includes memories 1544A-1544B coupled to the computing clusters 1536A-1536H via a set of memory controllers 1542A-1542B. In at least one embodiment, memories 1544A-1544B may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), which includes graphics double data rate (GDDR) memory.

[0175] In at least one embodiment, each of the computing clusters 1536A-1536H includes a set of graphics cores, such as Figure 15A The graphics core 1500 may include various types of integer and floating-point logic units that can perform computational operations over a range of precision suitable for machine learning computations. For example, in at least one embodiment, at least a subset of the floating-point units in each computing cluster 1536A-1536H may be configured to perform 16-bit or 32-bit floating-point operations, while different subsets of the floating-point units may be configured to perform 64-bit floating-point operations.

[0176] In at least one embodiment, multiple instances of GPGPU 1530 can be configured to operate as a compute cluster. In at least one embodiment, the communication used for synchronization and data exchange by compute clusters 1536A-1536H varies between embodiments. In at least one embodiment, multiple instances of GPGPU 1530 communicate via host interface 1532. In at least one embodiment, GPGPU 1530 includes an I / O hub 1539 that couples GPGPU 1530 to GPU link 1540, which provides direct connectivity to other instances of GPGPU 1530. In at least one embodiment, GPU link 1540 is coupled to a dedicated GPU-to-GPU bridge that enables communication and synchronization between multiple instances of GPGPU 1530. In at least one embodiment, GPU link 1540 is coupled to a high-speed interconnect for sending and receiving data to and from other GPGPUs or parallel processors. In at least one embodiment, multiple instances of GPGPU 1530 reside in a separate data processing system and communicate via a network device accessible via host interface 1532. In at least one embodiment, in addition to or as an alternative to host interface 1532, GPU link 1540 may also be configured to implement a connection to the host processor.

[0177] In at least one embodiment, the GPGPU 1530 can be configured to train a neural network. In at least one embodiment, the GPGPU 1530 can be used within an inference platform. In at least one embodiment, when using the GPGPU 1530 for inference, the GPGPU 1530 may include fewer compute clusters 1536A-1536H compared to when using the GPGPU 1530 to train a neural network. In at least one embodiment, the memory technology associated with memories 1544A-1544B can differ between inference and training configurations, with higher bandwidth memory technology dedicated to the training configuration. In at least one embodiment, the inference configuration of the GPGPU 1530 can support inference-specific instructions. For example, in at least one embodiment, the inference configuration can provide support for one or more 8-bit integer dot product instructions, which can be used during the inference operation of the deployed neural network.

[0178] Inference and / or training logic 615 is used to perform inference and / or training operations associated with one or more embodiments. The following is combined with... Figure 6A and / or Figure 6B Details are provided regarding inference and / or training logic 615. In at least one embodiment, inference and / or training logic 615 may be used in GPGPU 1530 for performing inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0179] Inference and / or training logic 615 is used to perform inference and / or training operations associated with one or more embodiments. In at least one embodiment, this logic may be used with components of these graphs to generate one or more images using one or more neural networks, at least in part, based on one or more noise values.

[0180] Figure 16This is a block diagram illustrating a computing system 1600 according to at least one embodiment. In at least one embodiment, the computing system 1600 includes a processing subsystem 1601 having one or more processors 1602 and system memory 1604 communicating via interconnect paths that may include a memory hub 1605. In at least one embodiment, the memory hub 1605 may be a separate component within a chipset assembly or may be integrated within one or more processors 1602. In at least one embodiment, the memory hub 1605 is coupled to an I / O subsystem 1611 via a communication link 1606. In at least one embodiment, the I / O subsystem 1611 includes an I / O hub 1607 that enables the computing system 1600 to receive input from one or more input devices 1608. In at least one embodiment, the I / O hub 1607 enables a display controller to provide output to one or more display devices 1610A, the display controller being included in one or more processors 1602. In at least one embodiment, one or more display devices 1610A coupled to the I / O hub 1607 may include local, internal, or embedded display devices.

[0181] In at least one embodiment, the processing subsystem 1601 includes one or more parallel processors 1612 coupled to a memory hub 1605 via a bus or other communication link 1613. In at least one embodiment, the communication link 1613 may use one of any number of standards based on a communication link technology or protocol (such as, but not limited to, PCI Express), or may be a vendor-specific communication interface or communication architecture. In at least one embodiment, one or more parallel processors 1612 form a compute-intensive parallel or vector processing system, which may include a large number of processing cores and / or processing clusters, such as integrated many-core (MIC) processors. In at least one embodiment, one or more parallel processors 1612 form a graphics processing subsystem that can output pixels to one or more display devices 1610A coupled via an I / O hub 1607. In at least one embodiment, one or more parallel processors 1612 may also include a display controller and a display interface (not shown) for implementing direct connection to one or more display devices 1610B.

[0182] In at least one embodiment, system storage unit 1614 may be connected to I / O hub 1607 to provide a storage mechanism for computing system 1600. In at least one embodiment, I / O switch 1616 may be used to provide an interface mechanism for enabling connectivity between I / O hub 1607 and other components, such as network adapter 1618 and / or wireless network adapter 1619 integrated into one or more platforms, and various other devices that can be added via one or more additional devices 1620. In at least one embodiment, network adapter 1618 may be an Ethernet adapter or another wired network adapter. In at least one embodiment, wireless network adapter 1619 may include one or more of Wi-Fi, Bluetooth, near field communication (NFC), or other network devices including one or more wireless devices.

[0183] In at least one embodiment, the computing system 1600 may include other components, not explicitly shown, that may also be connected to the I / O hub 1607, including USB or other port connections, optical storage drives, video capture devices, etc. In at least one embodiment, the interconnect can be implemented using any suitable protocol, such as a PCI (Peripheral Component Interconnect) based protocol (e.g., PCI-Express) or other bus or point-to-point communication interface and / or protocol (e.g., NV-Link high-speed interconnect or interconnect protocols). Figure 16 The communication paths of each component.

[0184] In at least one embodiment, one or more parallel processors 1612 include circuitry optimized for graphics and video processing, including, for example, video output circuitry, and constituting a graphics processing unit (GPU). In at least one embodiment, one or more parallel processors 1612 include circuitry optimized for general-purpose processing. In at least one embodiment, components of the computing system 1600 may be integrated with one or more other system elements on a single integrated circuit. For example, in at least one embodiment, one or more parallel processors 1612, a memory hub 1605, one or more processors 1602, and an I / O hub 1607 may be integrated into a system-on-a-chip (SoC) integrated circuit. In at least one embodiment, components of the computing system 1600 may be integrated into a single package to form a system-in-package (SIP) configuration. In at least one embodiment, at least a portion of the components of the computing system 1600 may be integrated into a multi-chip module (MCM), which may interconnect with other MCMs to a modular computing system.

[0185] Inference and / or training logic 615 is used to perform inference and / or training operations associated with one or more embodiments. The following is combined with... Figure 6A and / or Figure 6B Details are provided regarding the inference and / or training logic 615. In at least one embodiment, the inference and / or training logic 615 can be... Figure 16 The system 1600 is used for inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases as described herein.

[0186] Inference and / or training logic 615 is used to perform inference and / or training operations associated with one or more embodiments. In at least one embodiment, this logic may be used with components of these graphs to generate one or more images using one or more neural networks, at least in part, based on one or more noise values.

[0187] processor

[0188] Figure 17A A parallel processor 1700 according to at least one embodiment is illustrated. In at least one embodiment, the various components of the parallel processor 1700 may be implemented using one or more integrated circuit devices, such as a programmable processor, an application-specific integrated circuit (ASIC), or a field-programmable gate array (FPGA). In at least one embodiment, the illustrated parallel processor 1700 is according to an exemplary embodiment. Figure 16 The variant shown is a parallel processor 1612 with one or more parallel processors.

[0189] In at least one embodiment, the parallel processor 1700 includes a parallel processing unit 1702. In at least one embodiment, the parallel processing unit 1702 includes an I / O unit 1704 that enables communication with other devices, including other instances of the parallel processing unit 1702. In at least one embodiment, the I / O unit 1704 can be directly connected to other devices. In at least one embodiment, the I / O unit 1704 is connected to other devices via a hub or switch interface (e.g., a memory hub 1705). In at least one embodiment, the connection between the memory hub 1705 and the I / O unit 1704 forms a communication link 1713. In at least one embodiment, the I / O unit 1704 is connected to a host interface 1706 and a memory crossbar switch 1716, wherein the host interface 1706 receives commands for performing processing operations, and the memory crossbar switch 1716 receives commands for performing memory operations.

[0190] In at least one embodiment, when host interface 1706 receives a command buffer via I / O unit 1704, host interface 1706 can route work operations for executing those commands to front end 1708. In at least one embodiment, front end 1708 is coupled to scheduler 1710, which is configured to assign commands or other work items to processing cluster array 1712. In at least one embodiment, scheduler 1710 ensures that processing cluster array 1712 is correctly configured and in an active state before assigning tasks to clusters in processing cluster array 1712. In at least one embodiment, scheduler 1710 is implemented via firmware logic executed on a microcontroller. In at least one embodiment, the microcontroller-implemented scheduler 1710 can be configured to perform complex scheduling and work assignment operations at both coarse and fine granular levels, thereby enabling fast preemption and context switching of threads executing on processing cluster array 1712. In at least one embodiment, host software can demonstrate workloads for scheduling on processing cluster array 1712 via one of multiple graphics processing paths. In at least one embodiment, the workload can then be automatically distributed on the processing cluster array 1712 by the scheduler 1710 logic within the microcontroller, which includes the scheduler 1710.

[0191] In at least one embodiment, the processing cluster array 1712 may include up to "N" processing clusters (e.g., clusters 1714A, 1714B to 1714N). In at least one embodiment, each cluster 1714A-1714N of the processing cluster array 1712 may execute a large number of concurrent threads. In at least one embodiment, the scheduler 1710 may use various scheduling and / or work allocation algorithms to allocate work to clusters 1714A-1714N in the processing cluster array 1712, which may vary depending on the workload generated for each type of program or computation. In at least one embodiment, scheduling may be handled dynamically by the scheduler 1710, or may be partially assisted by compiler logic during the compilation of program logic configured to be executed by the processing cluster array 1712. In at least one embodiment, different clusters 1714A-1714N in the processing cluster array 1712 may be assigned to process different types of programs or to perform different types of computations.

[0192] In at least one embodiment, the processing cluster array 1712 can be configured to perform various types of parallel processing operations. In at least one embodiment, the processing cluster array 1712 is configured to perform general-purpose parallel computing operations. For example, in at least one embodiment, the processing cluster array 1712 may include logic for performing processing tasks, including filtering video and / or audio data, performing modeling operations, including physical operations, and performing data transformations.

[0193] In at least one embodiment, the processing cluster array 1712 is configured to perform parallel graphics processing operations. In at least one embodiment, the processing cluster array 1712 may include additional logic for supporting the execution of such graphics processing operations, including but not limited to texture sampling logic for performing texture operations, as well as tessellation logic and other vertex processing logic. In at least one embodiment, the processing cluster array 1712 may be configured to execute shader programs related to graphics processing, such as, but not limited to, vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. In at least one embodiment, the parallel processing unit 1702 may transfer data from system memory via I / O unit 1704 for processing. In at least one embodiment, during processing, the transferred data may be stored in on-chip memory (e.g., parallel processor memory 1722) and then written back to system memory.

[0194] In at least one embodiment, when the parallel processing unit 1702 is used to perform graphics processing, the scheduler 1710 can be configured to divide the processing workload into tasks of approximately equal size to better distribute graphics processing operations among multiple clusters 1714A-1714N in the processing cluster array 1712. In at least one embodiment, portions of the processing cluster array 1712 can be configured to perform different types of processing. For example, in at least one embodiment, a first portion can be configured to perform vertex shading and topology generation, a second portion can be configured to perform tessellation and geometry shading, and a third portion can be configured to perform pixel shading or other screen-space operations to produce a rendered image for display. In at least one embodiment, intermediate data generated by one or more of the clusters 1714A-1714N can be stored in a buffer to allow intermediate data to be transferred between the clusters 1714A-1714N for further processing.

[0195] In at least one embodiment, the processing cluster array 1712 may receive processing tasks to be executed via a scheduler 1710, which receives commands defining the processing tasks from a front end 1708. In at least one embodiment, the processing task may include an index of data to be processed, such as surface (patch) data, raw data, vertex data, and / or pixel data, as well as state parameters and commands defining how the data is processed (e.g., what program to execute). In at least one embodiment, the scheduler 1710 may be configured to acquire an index corresponding to a task, or may receive an index from the front end 1708. In at least one embodiment, the front end 1708 may be configured to ensure that the processing cluster array 1712 is configured to be active before initiating the workload specified by an incoming command buffer (e.g., a batch buffer, push buffer, etc.).

[0196] In at least one embodiment, each of one or more instances of the parallel processing unit 1702 may be coupled to the parallel processor memory 1722. In at least one embodiment, the parallel processor memory 1722 may be accessed via a memory crossbar switch 1716, which may receive memory requests from the processing cluster array 1712 and the I / O unit 1704. In at least one embodiment, the memory crossbar switch 1716 may be accessed via a memory interface 1718. In at least one embodiment, the memory interface 1718 may include a plurality of partition units (e.g., partition units 1720A, 1720B to 1720N), each of which may be coupled to a portion (e.g., a memory cell) of the parallel processor memory 1722. In at least one embodiment, the number of partition units 1720A-1720N is configured to be equal to the number of memory units, such that the first partition unit 1720A has a corresponding first memory unit 1724A, the second partition unit 1720B has a corresponding second memory unit 1724B, and the Nth partition unit 1720N has a corresponding Nth memory unit 1724N. In at least one embodiment, the number of partition units 1720A-1720N may not be equal to the number of memory devices.

[0197] In at least one embodiment, memory cells 1724A-1724N may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In at least one embodiment, memory cells 1724A-1724N may also include 3D stacked memory, including but not limited to high bandwidth memory (HBM). In at least one embodiment, rendering targets such as frame buffers or texture maps may be stored across memory cells 1724A-1724N, allowing partitioning cells 1720A-1720N to write portions of each rendering target in parallel to efficiently utilize the available bandwidth of the parallel processor memory 1722. In at least one embodiment, local instances of the parallel processor memory 1722 may be excluded to facilitate a unified memory design that utilizes system memory and local cache memory.

[0198] In at least one embodiment, any of clusters 1714A-1714N in the processing cluster array 1712 can process data to be written to any memory cell 1724A-1724N within the parallel processor memory 1722. In at least one embodiment, the memory crossbar switch 1716 can be configured to transfer the output of each cluster 1714A-1714N to any partition cell 1720A-1720N or another cluster 1714A-1714N, which can perform additional processing operations on the output. In at least one embodiment, each cluster 1714A-1714N can communicate with the memory interface 1718 via the memory crossbar switch 1716 to read from or write to various external memory devices. In at least one embodiment, the memory crossbar switch 1716 has a connection to a memory interface 1718 for communication with I / O unit 1704, and a connection to a local instance of parallel processor memory 1722, enabling processing units within different processing clusters 1714A-1714N to communicate with system memory or other memory not local to parallel processing unit 1702. In at least one embodiment, the memory crossbar switch 1716 can use virtual channels to separate traffic flows between clusters 1714A-1714N and partition units 1720A-1720N.

[0199] In at least one embodiment, multiple instances of the parallel processing unit 1702 may be provided on a single add-in card, or multiple add-in cards may be interconnected. In at least one embodiment, different instances of the parallel processing unit 1702 may be configured to interoperate, even if the different instances have different numbers of processing cores, different numbers of local parallel processor memories, and / or other configuration differences. For example, in at least one embodiment, some instances of the parallel processing unit 1702 may include higher-precision floating-point units relative to other instances. In at least one embodiment, a system including one or more instances of the parallel processing unit 1702 or the parallel processor 1700 may be implemented in various configurations and form factors, including but not limited to desktop computers, laptop or handheld personal computers, servers, workstations, game consoles, and / or embedded systems.

[0200] Figure 17B This is a block diagram of a partitioning unit 1720 according to at least one embodiment. In at least one embodiment, the partitioning unit 1720 is... Figure 17A This is an example of one of the partitioning units 1720A-1720N. In at least one embodiment, the partitioning unit 1720 includes an L2 cache 1721, a frame buffer interface 1725, and a raster operation unit (“ROP”) 1726. The L2 cache 1721 is a read / write cache configured to perform load and store operations received from the memory crossbar switch 1716 and the ROP 1726. In at least one embodiment, the L2 cache 1721 outputs read misses and urgent write-back requests to the frame buffer interface 1725 for processing. In at least one embodiment, updates can also be sent to the frame buffer for processing via the frame buffer interface 1725. In at least one embodiment, the frame buffer interface 1725 communicates with memory cells in the parallel processor memory (such as…) Figure 17A It is coupled to one of the memory cells 1724A-1724N (e.g., within the parallel processor memory 1722).

[0201] In at least one embodiment, ROP 1726 is a processing unit that performs raster operations such as stenciling, z-testing, blending, etc. In at least one embodiment, ROP 1726 then outputs processed graphics data stored in graphics memory. In at least one embodiment, ROP 1726 includes compression logic for compressing depth or color data written to memory and decompressing depth or color data read from memory. In at least one embodiment, the compression logic may be lossless compression logic utilizing one or more of a variety of compression algorithms. The compression logic performed by ROP 1726 may vary based on the statistical characteristics of the data to be compressed. For example, in at least one embodiment, incremental color compression is performed on depth and color data per tile.

[0202] In at least one embodiment, ROP 1726 is included within each processing cluster (e.g., clusters 1714A-1714N of FIG. 17A), rather than within partition unit 1720. In at least one embodiment, read and write requests for pixel data, rather than pixel fragment data, are transmitted via memory crossbar switch 1716. In at least one embodiment, the processed graphics data can be displayed on a display device (such as...) Figure 16 Displayed on one or more display devices 1610, routed by processor 1602 for further processing, or by... Figure 17A One of the processing entities within the parallel processor 1700 is routed for further processing.

[0203] Figure 17C This is a block diagram of a processing cluster 1714 within a parallel processing unit according to at least one embodiment. In at least one embodiment, the processing cluster is... Figure 17A An instance of one of the processing clusters 1714A-1714N. In at least one embodiment, one or more of the processing clusters 1714 can be configured to execute a number of threads in parallel, where a "thread" refers to an instance of a specific program executing on a particular set of input data. In at least one embodiment, a Single Instruction Multiple Data (SIMD) instruction issuing technique is used to support the parallel execution of a large number of threads without providing multiple independent instruction units. In at least one embodiment, a Single Instruction Multiple Threading (SIMT) technique is used to support the parallel execution of a large number of typically synchronized threads using a common instruction unit configured to issue instructions to a set of processing engines within each processing cluster.

[0204] In at least one embodiment, the operation of the processing cluster 1714 can be controlled via a pipeline manager 1732 that assigns processing tasks to the SIMT parallel processors. In at least one embodiment, the pipeline manager 1732 receives... Figure 17AThe scheduler 1710 receives instructions and manages the execution of these instructions via the graphics multiprocessor 1734 and / or texture unit 1736. In at least one embodiment, the graphics multiprocessor 1734 is an exemplary instance of a SIMT parallel processor. However, in at least one embodiment, the processing cluster 1714 may include various types of SIMT parallel processors with different architectures. In at least one embodiment, the processing cluster 1714 may include one or more instances of the graphics multiprocessor 1734. In at least one embodiment, the graphics multiprocessor 1734 can process data, and the data crossover switch 1740 can be used to allocate the processed data to one of a number of possible destinations, including other shader units. In at least one embodiment, the pipeline manager 1732 can facilitate the allocation of processed data by specifying the destination of the processed data to be allocated via the data crossover switch 1740.

[0205] In at least one embodiment, each graphics multiprocessor 1734 within the processing cluster 1714 may include the same set of functional execution logic (e.g., arithmetic logic units, load-memory units, etc.). In at least one embodiment, the functional execution logic may be configured in a pipelined manner, wherein new instructions may be issued before previous instructions complete. In at least one embodiment, the functional execution logic supports a variety of operations, including integer and floating-point arithmetic, comparison operations, Boolean operations, bit shifting, and computation of various algebraic functions. In at least one embodiment, the same functional unit hardware may be used to perform different operations, and any combination of functional units may exist.

[0206] In at least one embodiment, instructions sent to the processing cluster 1714 constitute threads. In at least one embodiment, a group of threads executed across a set of parallel processing engines is a thread group. In at least one embodiment, the thread group executes programs on different input data. In at least one embodiment, each thread within the thread group can be assigned to a different processing engine within the graphics multiprocessor 1734. In at least one embodiment, the thread group may include fewer threads than the number of processing engines within the graphics multiprocessor 1734. In at least one embodiment, when the number of threads included in the thread group is less than the number of processing engines, one or more processing engines may be idle during a loop that is processing the thread group. In at least one embodiment, the thread group may also include more threads than the number of processing engines within the graphics multiprocessor 1734. In at least one embodiment, when the thread group includes more threads than the number of processing engines within the graphics multiprocessor 1734, processing can be performed in consecutive clock cycles. In at least one embodiment, multiple thread groups can be executed concurrently on the graphics multiprocessor 1734.

[0207] In at least one embodiment, the graphics multiprocessor 1734 includes an internal cache memory for performing load and store operations. In at least one embodiment, the graphics multiprocessor 1734 may forgo the internal cache and use a cache memory within the processing cluster 1714 (e.g., L1 cache 1748). In at least one embodiment, each graphics multiprocessor 1734 may also access partition units (e.g., Figure 17A The L2 cache is located within partition units 1720A-1720N, which are shared among all processing clusters 1714 and can be used to transfer data between threads. In at least one embodiment, the graphics multiprocessor 1734 can also access off-chip global memory, which may include one or more of local parallel processor memory and / or system memory. In at least one embodiment, any memory outside of the parallel processing unit 1702 can be used as global memory. In at least one embodiment, the processing cluster 1714 includes multiple instances of the graphics multiprocessor 1734, which can share common instructions and data that can be stored in the L1 cache 1748.

[0208] In at least one embodiment, each processing cluster 1714 may include a memory management unit (“MMU”) 1745 configured to map virtual addresses to physical addresses. In at least one embodiment, one or more instances of the MMU 1745 may reside in Figure 17A The memory interface 1718 is located within the MMU 1745. In at least one embodiment, the MMU 1745 includes a set of page table entries (PTEs) for mapping virtual addresses to physical addresses of tiles and optionally to cache line indices. In at least one embodiment, the MMU 1745 may include an address translation back buffer (TLB) or a cache that may reside within the graphics multiprocessor 1734, the L1 cache 1748, or the processing cluster 1714. In at least one embodiment, physical addresses are processed to allocate surface data access locations to allow efficient request interleaving between partition units. In at least one embodiment, cache line indices may be used to determine whether a request for a cache line is a hit or a miss.

[0209] In at least one embodiment, the processing cluster 1714 may be configured such that each graphics multiprocessor 1734 is coupled to a texture unit 1736 to perform a texture mapping operation that determines texture sample locations, reads texture data, and filters texture data. In at least one embodiment, texture data may be read from an internal texture L1 cache (not shown) or from an L1 cache within the graphics multiprocessor 1734, and may also be retrieved from an L2 cache, local parallel processor memory, or system memory, as needed. In at least one embodiment, each graphics multiprocessor 1734 outputs one or more processed tasks to a data crossbar switch 1740 to provide one or more processed tasks to another processing cluster 1714 for further processing, or to store one or more processed tasks in an L2 cache, local parallel processor memory, or in system memory via a memory crossbar switch 1716. In at least one embodiment, preROP 1742 (pre-raster operation unit) is configured to receive data from graphics multiprocessor 1734 and direct the data to a ROP unit, which can be connected to the partitioning unit described herein (e.g., Figure 17A The PreROP 1742 unit is located together with the partitioning units 1720A-1720N. In at least one embodiment, the PreROP 1742 unit can perform optimizations for color mixing, organizing pixel color data, and performing address translation.

[0210] Inference and / or training logic 615 is used to perform inference and / or training operations associated with one or more embodiments. The following is combined with... Figure 6A and / or Figure 6B Details are provided regarding inference and / or training logic 615. In at least one embodiment, inference and / or training logic 615 may be used in graphics processing cluster 1714 for performing inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0211] Inference and / or training logic 615 is used to perform inference and / or training operations associated with one or more embodiments. In at least one embodiment, this logic may be used with components of these graphs to generate one or more images using one or more neural networks, at least in part, based on one or more noise values.

[0212] Figure 17DA graphics multiprocessor 1734 according to at least one embodiment is illustrated. In at least one embodiment, the graphics multiprocessor 1734 is coupled to a pipeline manager 1732 of a processing cluster 1714. In at least one embodiment, the graphics multiprocessor 1734 has an execution pipeline including, but not limited to, an instruction cache 1752, an instruction unit 1754, an address mapping unit 1756, a register file 1758, one or more general-purpose graphics processing unit (GPGPU) cores 1762, and one or more load / store units 1766. One or more GPGPU cores 1762 and one or more load / store units 1766 are coupled to a cache memory 1772 and a shared memory 1770 via a memory and cache interconnect 1768.

[0213] In at least one embodiment, instruction cache 1752 receives a stream of instructions to be executed from pipeline manager 1732. In at least one embodiment, instructions are cached in instruction cache 1752 and dispatched for execution by instruction unit 1754. In at least one embodiment, instruction unit 1754 may dispatch instructions as thread groups (e.g., thread bundles), where each thread group is assigned to a different execution unit within one or more GPGPU cores 1762. In at least one embodiment, instructions can access any local, shared, or global address space by specifying an address within a unified address space. In at least one embodiment, address mapping unit 1756 may be used to translate addresses in the unified address space into different memory addresses that can be accessed by one or more load / store units 1766.

[0214] In at least one embodiment, register file 1758 provides a set of registers for functional units of graphics multiprocessor 1734. In at least one embodiment, register file 1758 provides temporary storage for operands of data paths connected to functional units of graphics multiprocessor 1734 (e.g., GPGPU core 1762, load / store unit 1766). In at least one embodiment, register file 1758 is partitioned among each functional unit, such that a dedicated portion of register file 1758 is allocated to each functional unit. In at least one embodiment, register file 1758 is partitioned among different thread bundles being executed by graphics multiprocessor 1734.

[0215] In at least one embodiment, each GPGPU core 1762 may include a floating-point unit (FPU) and / or an integer arithmetic logic unit (ALU) for executing instructions of the graphics multiprocessor 1734. The architectures of the various GPGPU cores 1762 may be similar or different. In at least one embodiment, a first portion of the GPGPU core 1762 includes a single-precision FPU and an integer ALU, while a second portion of the GPGPU core includes a double-precision FPU. In at least one embodiment, the FPU may implement the IEEE 754-2008 standard for floating-point algorithms or enable variable-precision floating-point algorithms. In at least one embodiment, the graphics multiprocessor 1734 may additionally include one or more fixed-function or special-function units for performing specific functions, such as copying rectangles or pixel blending operations. In at least one embodiment, one or more GPGPU cores may also include fixed-function or special-function logic.

[0216] In at least one embodiment, the GPGPU core 1762 includes SIMD logic capable of executing a single instruction on multiple sets of data. In at least one embodiment, the GPGPU core 1762 can physically execute SIMD4, SIMD8, and SIMD16 instructions, and logically execute SIMD1, SIMD2, and SIMD32 instructions. In at least one embodiment, the SIMD instructions for the GPGPU core can be generated at compile time by a shader compiler, or automatically generated when executing a program written and compiled for a Single Program Multiple Data (SPMD) or SIMT architecture. In at least one embodiment, multiple threads of a program configured for a SIMT execution model can be executed via a single SIMD instruction. For example, in at least one embodiment, eight SIMT threads performing the same or similar operations can be executed in parallel via a single SIMD8 logic unit.

[0217] In at least one embodiment, the memory and cache interconnect 1768 is an interconnect network connecting each functional unit of the graphics multiprocessor 1734 to the register file 1758 and the shared memory 1770. In at least one embodiment, the memory and cache interconnect 1768 is a cross-switch interconnect that allows the load / store unit 1766 to perform load and store operations between the shared memory 1770 and the register file 1758. In at least one embodiment, the register file 1758 can operate at the same frequency as the GPGPU core 1762, resulting in very low latency for data transfer between the GPGPU core 1762 and the register file 1758. In at least one embodiment, the shared memory 1770 can be used to implement communication between threads executing on functional units within the graphics multiprocessor 1734. In at least one embodiment, the cache memory 1772 can be used, for example, as a data cache for caching texture data communicated between functional units and texture units 1736. In at least one embodiment, the shared memory 1770 can also be used as a program-managed cache. In at least one embodiment, in addition to the data automatically cached in cache memory 1772, the thread executing on GPGPU core 1762 can also programmatically store data in shared memory.

[0218] In at least one embodiment, a parallel processor or GPGPU, as described herein, is communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. In at least one embodiment, the GPU may be communicatively coupled to the host processor / core via a bus or other interconnect (e.g., a high-speed interconnect such as PCIe or NVLink). In at least one embodiment, the GPU may be integrated with the core on the same package or chip and communicatively coupled to the core via an internal processor bus / interconnect (e.g., within the package or chip). In at least one embodiment, regardless of how the GPU is connected, the processor core may assign work to the GPU in the form of a sequence of commands / instructions contained in a job descriptor. In at least one embodiment, the GPU then uses dedicated circuitry / logic to efficiently process these commands / instructions.

[0219] Inference and / or training logic 615 is used to perform inference and / or training operations associated with one or more embodiments. The following is combined with... Figure 6A and / or Figure 6BDetails are provided regarding inference and / or training logic 615. In at least one embodiment, inference and / or training logic 615 may be used in graphics multiprocessor 1734 for performing inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0220] Inference and / or training logic 615 is used to perform inference and / or training operations associated with one or more embodiments. In at least one embodiment, this logic may be used with components of these graphs to generate one or more images using one or more neural networks, at least in part, based on one or more noise values.

[0221] Figure 18 A multi-GPU computing system 1800 according to at least one embodiment is illustrated. In at least one embodiment, the multi-GPU computing system 1800 may include a processor 1802 coupled to a plurality of general-purpose graphics processing units (GPGPUs) 1806A-D via a host interface switch 1804. In at least one embodiment, the host interface switch 1804 is a PCI Express switch device that couples the processor 1802 to a PCI Express bus, through which the processor 1802 communicates with the GPGPUs 1806A-D. The GPGPUs 1806A-D may be interconnected via a set of high-speed P2P (peer-to-peer) GPU-to-GPU links 1816. In at least one embodiment, the GPU-to-GPU links 1816 are connected to each of the GPGPUs 1806A-D via dedicated GPU links. In at least one embodiment, the P2P GPU links 1816 enable direct communication between each GPGPU 1806A-D without communication via the host interface bus 1804 to which the processor 1802 is connected. In at least one embodiment, when GPU-to-GPU traffic is directed to the P2P GPU link 1816, the host interface bus 1804 remains available for system memory access or, for example, communication with other instances of the multi-GPU computing system 1800 via one or more network devices. While in at least one embodiment, the GPGPUs 1806A-D are connected to the processor 1802 via the host interface switch 1804, in at least one embodiment, the processor 1802 includes direct support for the P2P GPU link 1816 and can be directly connected to the GPGPUs 1806A-D.

[0222] Inference and / or training logic 615 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 6Aand / or Figure 6B Details are provided regarding inference and / or training logic 615. In at least one embodiment, inference and / or training logic 615 may be used in a multi-GPU computing system 1800 for performing inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0223] Inference and / or training logic 615 is used to perform inference and / or training operations associated with one or more embodiments. In at least one embodiment, this logic may be used with components of these graphs to generate one or more images using one or more neural networks, at least in part, based on one or more noise values.

[0224] Figure 19 This is a block diagram of a graphics processor 1900 according to at least one embodiment. In at least one embodiment, the graphics processor 1900 includes a ring interconnect 1902, a pipeline front end 1904, a media engine 1937, and graphics cores 1980A-1980N. In at least one embodiment, the ring interconnect 1902 couples the graphics processor 1900 to other processing units, said processing units including other graphics processors or one or more general-purpose processor cores. In at least one embodiment, the graphics processor 1900 is one of many processors integrated within a multi-core processing system.

[0225] In at least one embodiment, the graphics processor 1900 receives multiple batches of commands via a ring interconnect 1902. In at least one embodiment, the input commands are interpreted by a command streamer 1903 in a pipeline front-end 1904. In at least one embodiment, the graphics processor 1900 includes scalable execution logic for performing 3D geometry processing and media processing via graphics cores 1980A-1980N. In at least one embodiment, for 3D geometry processing commands, the command streamer 1903 provides the commands to the geometry pipeline 1936. In at least one embodiment, for at least some media processing commands, the command streamer 1903 provides the commands to a video front-end 1934, which is coupled to a media engine 1937. In at least one embodiment, the media engine 1937 includes a video quality engine (VQE) 1930 for video and image post-processing, and a multi-format encoding / decoding (MFX) engine 1933 for providing hardware-accelerated media data encoding and decoding. In at least one embodiment, the geometry pipeline 1936 and the media engine 1937 each generate an execution thread for thread execution resources provided by at least one graphics core 1980.

[0226] In at least one embodiment, the graphics processor 1900 includes scalable thread execution resources featuring modular cores 1980A-1980N (sometimes referred to as core slices), each graphics core having multiple sub-cores 1950A-1950N, 1960A-1960N (sometimes referred to as core sub-slices). In at least one embodiment, the graphics processor 1900 may have any number of graphics cores 1980A to 1980N. In at least one embodiment, the graphics processor 1900 includes a graphics core 1980A having at least a first sub-core 1950A and a second sub-core 1960A. In at least one embodiment, the graphics processor 1900 is a low-power processor with a single sub-core (e.g., 1950A). In at least one embodiment, the graphics processor 1900 includes multiple graphics cores 1980A-1980N, each graphics core including a set of first sub-cores 1950A-1950N and a set of second sub-cores 1960A-1960N. In at least one embodiment, each of the first sub-cores 1950A-1950N includes at least a first set of execution units 1952A-1952N and media / texture samplers 1954A-1954N. In at least one embodiment, each of the second sub-cores 1960A-1960N includes at least a second set of execution units 1962A-1962N and samplers 1964A-1964N. In at least one embodiment, each sub-core 1950A-1950N and 1960A-1960N shares a set of shared resources 1970A-1970N. In at least one embodiment, the shared resources include shared cache memory and pixel operation logic.

[0227] Inference and / or training logic 615 is used to perform inference and / or training operations associated with one or more embodiments. The following is combined with... Figure 6A and / or Figure 6B Details are provided regarding inference and / or training logic 615. In at least one embodiment, inference and / or training logic 615 may be used in graphics processor 1900 for performing inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0228] Inference and / or training logic 615 is used to perform inference and / or training operations associated with one or more embodiments. In at least one embodiment, this logic may be used with components of these graphs to generate one or more images using one or more neural networks, at least in part, based on one or more noise values.

[0229] Figure 20 This is a block diagram illustrating a microarchitecture for a processor 2000 according to at least one embodiment, the processor 2000 including logic circuitry for executing instructions. In at least one embodiment, the processor 2000 can execute instructions, including x86 instructions, ARM instructions, special-purpose instructions for application-specific integrated circuits (ASICs), etc. In at least one embodiment, the processor 2000 may include registers for storing packed data, such as 64-bit wide MMX data in a microprocessor implemented using Intel's MMX technology from Santa Clara, California. TM Registers. In at least one embodiment, an MMX register available in both integer and floating-point forms can operate with packed data elements accompanying Single Instruction Multiple Data (“SIMD”) and Streaming SIMD Extensions (“SSE”) instructions. In at least one embodiment, a 128-bit wide XMM register associated with SSE2, SSE3, SSE4, AVX, or later (beyond) (commonly referred to as “SSEx”) technology can hold such packed data operands. In at least one embodiment, the processor 2000 can execute instructions to accelerate machine learning or deep learning algorithms, training, or inference.

[0230] In at least one embodiment, processor 2000 includes an ordered front end (“front end”) 2001 for fetching instructions to be executed and preparing instructions for later use in the processor pipeline. In at least one embodiment, front end 2001 may include several units. In at least one embodiment, instruction prefetcher 2026 fetches instructions from memory and feeds the instructions to instruction decoder 2028, which in turn decodes or interprets the instructions. For example, in at least one embodiment, instruction decoder 2028 decodes the received instructions into one or more machine-executable so-called “micro-operations” or “micro-instructions” (also referred to as “micro ops” or “uops”). In at least one embodiment, instruction decoder 2028 parses the instructions into opcodes and corresponding data and control fields, which can be used by the microarchitecture to perform operations according to at least one embodiment. In at least one embodiment, trace cache 2030 may assemble the decoded micro-operations into an ordered sequence or trace of programs in micro-operation queue 2034 for execution. In at least one embodiment, when the trace cache 2030 encounters a complex instruction, the microcode ROM 2032 provides the micro-operations required to complete the operation.

[0231] In at least one embodiment, some instructions may be converted into a single micro-operation, while others require several micro-operations to complete the entire operation. In at least one embodiment, if more than four micro-operations are required to complete an instruction, the instruction decoder 2028 may access the microcode ROM 2032 to execute the instruction. In at least one embodiment, an instruction may be decoded into a small number of micro-operations for processing at the instruction decoder 2028. In at least one embodiment, if multiple micro-operations are required to complete the operation, the instruction may be stored in the microcode ROM 2032. In at least one embodiment, the tracking cache 2030 references an entry point programmable logic array (“PLA”) to determine the correct micro-instruction pointer for reading a microcode sequence from the microcode ROM 2032 to complete one or more instructions, according to at least one embodiment. In at least one embodiment, after the microcode ROM 2032 has completed the serialization of the micro-operations of the instruction, the machine front end 2001 may resume fetching micro-operations from the tracking cache 2030.

[0232] In at least one embodiment, the out-of-order execution engine (“out-of-order engine”) 2003 can prepare instructions for execution. In at least one embodiment, the out-of-order execution logic has multiple buffers to smooth and reorder the instruction stream to optimize performance as the instruction stream moves down the pipeline and is scheduled for execution. In at least one embodiment, the out-of-order execution engine 2003 includes, but is not limited to, an allocator / register renamer 2040, a memory micro-operation queue 2042, an integer / floating-point micro-operation queue 2044, a memory scheduler 2046, a fast scheduler 2002, a slow / general-purpose floating-point scheduler (“slow / general-purpose FP scheduler”) 2004, and a simple floating-point scheduler (“simple FP scheduler”) 2006. In at least one embodiment, the fast scheduler 2002, the slow / general-purpose floating-point scheduler 2004, and the simple floating-point scheduler 2006 are also collectively referred to herein as “micro-operation schedulers 2002, 2004, 2006”. In at least one embodiment, the allocator / register renamer 2040 allocates the machine buffers and resources required for each micro-operation to execute. In at least one embodiment, the allocator / register renamer 2040 renames logical registers to entries in a register file. In at least one embodiment, the allocator / register renamer 2040 also allocates entries for each micro-operation in one of two micro-operation queues, preceding the memory scheduler 2046 and the micro-operation schedulers 2002, 2004, 2006, with memory micro-operation queue 2042 for memory operations and integer / floating-point micro-operation queue 2044 for non-memory operations. In at least one embodiment, the micro-operation schedulers 2002, 2004, 2006 determine when a micro-operation is ready to be executed based on the readiness of their dependent input register operand sources and the availability of execution resources required for the micro-operation to complete its operation. In at least one embodiment, the fast scheduler 2002 may schedule on each half of the master clock cycle, while the slow / general-purpose floating-point scheduler 2004 and the simple floating-point scheduler 2006 may schedule once per master processor clock cycle. In at least one embodiment, micro-operation schedulers 2002, 2004, and 2006 arbitrate dispatch ports to schedule micro-operations for execution.

[0233] In at least one embodiment, execution block 2011 includes, but is not limited to, integer register file / bypass network 2008, floating-point register file / bypass network (“FP register file / bypass network”) 2010, address generation units (“AGU”) 2012 and 2014, fast arithmetic logic units (“fast ALU”) 2016 and 2018, slow arithmetic logic unit (“slow ALU”) 2020, floating-point ALU (“FP”) 2022, and floating-point movement unit (“FP movement”) 2024. In at least one embodiment, integer register file / bypass network 2008 and floating-point register file / bypass network 2010 are also referred to herein as “register files 2008, 2010”. In at least one embodiment, AGU 2012 and 2014, fast ALU 2016 and 2018, slow ALU 2020, floating-point ALU 2022, and floating-point movement unit 2024 are also referred to herein as "execution units 2012, 2014, 2016, 2018, 2020, 2022, and 2024". In at least one embodiment, execution block 2011 may include, but is not limited to, any number (including zero) and type of register files, bypass networks, address generation units, and execution units in any combination.

[0234] In at least one embodiment, register files 2008 and 2010 may be arranged between micro-operation schedulers 2002, 2004, and 2006 and execution units 2012, 2014, 2016, 2018, 2020, 2022, and 2024. In at least one embodiment, integer register file / bypass network 2008 performs integer operations. In at least one embodiment, floating-point register file / bypass network 2010 performs floating-point operations. In at least one embodiment, each of register files 2008 and 2010 may include, but is not limited to, a bypass network that can bypass a recently completed result that has not yet been written to the register file or forward it to a new relevant micro-operation. In at least one embodiment, register files 2008 and 2010 can communicate data with each other. In at least one embodiment, integer register file / bypass network 2008 may include, but is not limited to, two separate register files, one for low-order 32-bit data and the other for high-order 32-bit data. In at least one embodiment, the floating-point register file / bypass network 2010 may include, but is not limited to, 128-bit wide entries, since floating-point instructions typically have operands with widths ranging from 64 to 128 bits.

[0235] In at least one embodiment, execution units 2012, 2014, 2016, 2018, 2020, 2022, and 2024 can execute instructions. In at least one embodiment, register files 2008 and 2010 store integer and floating-point data operation values ​​that the microinstructions need to execute. In at least one embodiment, processor 2000 may include, but is not limited to, any number of execution units 2012, 2014, 2016, 2018, 2020, 2022, and 2024, and combinations thereof. In at least one embodiment, floating-point ALU 2022 and floating-point move unit 2024 can perform floating-point, MMX, SIMD, AVX, and SSE or other operations, including specialized machine learning instructions. In at least one embodiment, floating-point ALU 2022 may include, but is not limited to, a 64-bit multiplication-64-bit floating-point divider for performing division, square root, and remainder micro-operations. In at least one embodiment, floating-point hardware can be used to process instructions involving floating-point values. In at least one embodiment, ALU operations can be passed to the fast ALU 2016, 2018. In at least one embodiment, the fast ALU 2016, 2018 can perform fast operations with an effective delay of half a clock cycle. In at least one embodiment, most complex integer operations are routed to the slow ALU 2020, because the slow ALU 2020 can include, but is not limited to, integer execution hardware for long-delay type operations, such as multipliers, shifters, flag logic, and branching. In at least one embodiment, memory load / store operations can be performed by AGU 2012, 2014. In at least one embodiment, the fast ALU 2016, fast ALU 2018, and slow ALU 2020 can perform integer operations on 64-bit data operands. In at least one embodiment, the fast ALU 2016, fast ALU 2018, and slow ALU 2020 can be implemented to support various data bit sizes, including sixteen, thirty-two, 128, 256, etc. In at least one embodiment, the floating-point ALU 2022 and the floating-point movement unit 2024 can be implemented to support a range of operands with various bit widths. In at least one embodiment, the floating-point ALU 2022 and the floating-point movement unit 2024 can operate on 128-bit wide packed data operands that combine SIMD and multimedia instructions.

[0236] In at least one embodiment, micro-operation schedulers 2002, 2004, and 2006 dispatch dependent operations before the parent load has been completed. In at least one embodiment, since micro-operations can be speculatively scheduled and executed within processor 2000, processor 2000 may also include logic for handling memory misses. In at least one embodiment, if a data load miss occurs in the data cache, there may be a dependent operation running in the pipeline that temporarily prevents the scheduler from accessing the correct data. In at least one embodiment, a replay mechanism tracks and re-executes instructions that use incorrect data. In at least one embodiment, it may be necessary to replay dependent operations and may allow independent operations to complete. In at least one embodiment, the scheduler and replay mechanism of at least one embodiment of the processor may also be designed to capture instruction sequences used for text string comparison operations.

[0237] In at least one embodiment, the term "register" may refer to an onboard processor storage location that can be used as part of an instruction that identifies an operand. In at least one embodiment, a register may be one that can be used from outside the processor (from a programmer's perspective). In at least one embodiment, a register may not be limited to a particular type of circuitry. Rather, in at least one embodiment, a register may store data, provide data, and perform the functions described herein. In at least one embodiment, the registers described herein may be implemented by circuitry within the processor using any number of different techniques, such as dedicated physical registers, dynamically allocated physical registers renamed using register renaming, combinations of dedicated and dynamically allocated physical registers, etc. In at least one embodiment, an integer register stores 32-bit integer data. The register file of at least one embodiment also includes eight multimedia SIMD registers for packing data.

[0238] Inference and / or training logic 615 is used to perform inference and / or training operations associated with one or more embodiments. The following is combined with... Figure 6A and / or Figure 6B Details regarding inference and / or training logic 615 are provided. In at least one embodiment, some or all of the inference and / or training logic 615 may be incorporated into execution block 2011 along with other memory or registers shown or not shown. For example, in at least one embodiment, the training and / or inference techniques described herein may utilize one or more ALUs shown in execution block 2011. Furthermore, weight parameters may be stored in on-chip or off-chip memory and / or registers (shown or not shown) that configure the ALUs of execution block 2011 to execute one or more machine learning algorithms, neural network architectures, use cases, or training techniques described herein.

[0239] Inference and / or training logic 615 is used to perform inference and / or training operations associated with one or more embodiments. In at least one embodiment, this logic may be used with components of these graphs to generate one or more images using one or more neural networks, at least in part, based on one or more noise values.

[0240] Figure 21 A deep learning application processor 2100 according to at least one embodiment is illustrated. In at least one embodiment, the deep learning application processor 2100 uses instructions that, if executed by the deep learning application processor 2100, cause the deep learning application processor 2100 to perform some or all of the processes and techniques described herein. In at least one embodiment, the deep learning application processor 2100 is an application-specific integrated circuit (ASIC). In at least one embodiment, as a result of executing one or more instructions or both, the application processor 2100 performs matrix multiplication operations or is "hardwired" into hardware. In at least one embodiment, the deep learning application processor 2100 includes, but is not limited to, processing clusters 2110(1)-2110(12), inter-chip link (“ICL”) 2120(1)-2120(12), inter-chip controller (“ICC”) 2130(1)-2130(2), memory controller (“Mem Ctrlr”) 2142(1)-2142(4), high-bandwidth memory physical layer (“HBM PHY”) 2144(1)-2144(4), management controller central processing unit (“management controller CPU”) 2150, peripheral component interconnect fast controller and direct memory access block (“PCIe controller and DMA”) 2170, and sixteen-channel peripheral component interconnect fast port (“PCI Express x 16”) 2180.

[0241] In at least one embodiment, processing cluster 2110 can perform deep learning operations, including inference or prediction operations based on weight parameters computed using one or more training techniques (including those described herein). In at least one embodiment, each processing cluster 2110 can include, but is not limited to, any number and type of processors. In at least one embodiment, deep learning application processor 2100 can include any number and type of processing cluster 2100. In at least one embodiment, the inter-chip link 2120 is bidirectional. In at least one embodiment, the inter-chip link 2120 and the inter-chip controller 2130 enable multiple deep learning application processors 2100 to exchange information, including activation information generated from executing one or more machine learning algorithms embodied in one or more neural networks. In at least one embodiment, deep learning application processor 2100 can include any number (including zero) and type of ICL 2120 and ICC 2130.

[0242] In at least one embodiment, the HBM2 2140 provides a total of 32GB of memory. The HBM2 2140(i) is associated with both the memory controller 2142(i) and the HBM PHY 2144(i). In at least one embodiment, any number of HBM2 2140s can provide any type and total amount of high-bandwidth memory and can be associated with any number (including zero) and type of memory controller 2142 and HBM PHY 2144. In at least one embodiment, any number and type of blocks implementing any number and type of communication standards can replace SPI, I... 2 C. GPIO2160, PCIe controller and DMA 2170 and / or PCIe 2180.

[0243] Inference and / or training logic 615 is used to perform inference and / or training operations associated with one or more embodiments. The following is combined with... Figure 6A and / or Figure 6B Details regarding the inference and / or training logic 615 are provided. In at least one embodiment, the deep learning application processor is used to train a machine learning model (such as a neural network) to predict or infer information provided to the deep learning application processor 2100. In at least one embodiment, the deep learning application processor 2100 is used to infer or predict information based on a trained machine learning model (e.g., a neural network) that has been trained by another processor or system or by the deep learning application processor 2100. In at least one embodiment, the processor 2100 may be used to perform one or more neural network use cases described herein.

[0244] Inference and / or training logic 615 is used to perform inference and / or training operations associated with one or more embodiments. In at least one embodiment, this logic may be used with components of these graphs to generate one or more images using one or more neural networks, at least in part, based on one or more noise values.

[0245] Figure 22 This is a block diagram of a neuromorphic processor 2200 according to at least one embodiment. In at least one embodiment, the neuromorphic processor 2200 may receive one or more inputs from a source external to the neuromorphic processor 2200. In at least one embodiment, these inputs may be transmitted to one or more neurons 2202 within the neuromorphic processor 2200. In at least one embodiment, the neurons 2202 and their components may be implemented using circuitry or logic including one or more arithmetic logic units (ALUs). In at least one embodiment, the neuromorphic processor 2200 may include, but is not limited to, thousands or millions of instances of neurons 2202, but any suitable number of neurons 2202 may be used. In at least one embodiment, each instance of a neuron 2202 may include a neuron input 2204 and a neuron output 2206. In at least one embodiment, a neuron 2202 may generate an output that can be transmitted to the inputs of other instances of the neuron 2202. For example, in at least one embodiment, the neuron input 2204 and the neuron output 2206 may be interconnected via synapses 2208.

[0246] In at least one embodiment, neuron 2202 and synapse 2208 may be interconnected, causing neuromorphic processor 2200 to operate to process or analyze information received by neuromorphic processor 2200. In at least one embodiment, neuron 2202 may send an output pulse (or "fire" or "spike") when the input received through neuron input 2204 exceeds a threshold. In at least one embodiment, neuron 2202 may sum or integrate the signal received at neuron input 2204. For example, in at least one embodiment, neuron 2202 may be implemented as a leaky integrate-and-fire neuron, wherein if the summation (referred to as "membrane potential") exceeds a threshold, neuron 2202 may use a transfer function such as a sigmoid or threshold function to generate an output (or "fire"). In at least one embodiment, the leaky integrate-and-fire neuron may sum the signal received at neuron input 2204 to a membrane potential and may also apply an attenuation factor (or leakage) to reduce the membrane potential. In at least one embodiment, a leaky, integrated firing neuron may fire if multiple input signals are received at neuron input 2204 quickly enough to exceed a threshold (i.e., before the membrane potential decays too low to fire). In at least one embodiment, neuron 2202 may be implemented using circuitry or logic that receives input, integrates the input into a membrane potential, and decays the membrane potential. In at least one embodiment, the input may be averaged, or any other suitable transfer function may be used. Furthermore, in at least one embodiment, neuron 2202 may include, but is not limited to, comparator circuitry or logic that generates an output spike at neuron output 2206 when the result of applying the transfer function to neuron input 2204 exceeds a threshold. In at least one embodiment, once neuron 2202 fires, it can ignore previously received input information by, for example, resetting the membrane potential to 0 or another suitable default value. In at least one embodiment, once the membrane potential is reset to 0, neuron 2202 may resume normal operation after a suitable time period (or refractory period).

[0247] In at least one embodiment, neurons 2202 can be interconnected via synapses 2208. In at least one embodiment, synapses 2208 are operable to transmit signals from the output of a first neuron 2202 to the input of a second neuron 2202. In at least one embodiment, neurons 2202 can transmit information on more than one instance of synapses 2208. In at least one embodiment, one or more instances of neuron outputs 2206 can be connected via instances of synapses 2208 to instances of neuron inputs 2204 in the same neuron 2202. In at least one embodiment, an instance of neuron 2202 that generates an output to be transmitted on that instance of synapse 2208 may be referred to as a "presynaptic neuron" relative to an instance of synapse 2208. In at least one embodiment, an instance of neuron 2202 that receives input transmitted via that instance of synapse 2208 may be referred to as a "postsynaptic neuron" relative to an instance of synapse 2208. In at least one embodiment, relative to each instance of synapse 2208, because an instance of neuron 2202 can receive input from one or more instances of synapse 2208 and can also transmit output through one or more instances of synapse 2208, a single instance of neuron 2202 can be both a "presynaptic neuron" and a "postsynaptic neuron".

[0248] In at least one embodiment, neurons 2202 may be organized into one or more layers. Each instance of neuron 2202 may have a neuron output 2206 that can fan out to one or more neuron inputs 2204 via one or more synapses 2208. In at least one embodiment, the neuron output 2206 of neuron 2202 in the first layer 2210 may be connected to the neuron input 2204 of neuron 2202 in the second layer 2212. In at least one embodiment, layer 2210 may be referred to as a “feedforward layer.” In at least one embodiment, each instance of neuron 2202 in an instance of the first layer 2210 may fan out to each instance of neuron 2202 in the second layer 2212. In at least one embodiment, the first layer 2210 may be referred to as a “fully connected feedforward layer.” In at least one embodiment, each instance of neuron 2202 in an instance of the second layer 2212 may fan out to fewer than all instances of neuron 2202 in the third layer 2214. In at least one embodiment, the second layer 2212 may be referred to as a “sparsely connected feedforward layer.” In at least one embodiment, neurons 2202 in the second layer 2212 may fan out to neurons 2202 in multiple other layers, including to neurons 2202 in the (same) second layer 2212. In at least one embodiment, the second layer 2212 may be referred to as a “recurrent layer.” In at least one embodiment, the neuromorphic processor 2200 may be any suitable combination of recurrent layers and feedforward layers, including but not limited to sparsely connected feedforward layers and fully connected feedforward layers.

[0249] In at least one embodiment, the neuromorphic processor 2200 may include, but is not limited to, a reconfigurable interconnect architecture or dedicated hardwired interconnect for connecting synapses 2208 to neurons 2202. In at least one embodiment, the neuromorphic processor 2200 may include, but is not limited to, circuitry or logic that allows synapses to be assigned to different neurons 2202 as needed based on the neural network topology and neuron fan-in / fan-out. For example, in at least one embodiment, interconnect structures (such as on-chip networks) or dedicated connections may be used to connect synapses 2208 to neurons 2202. In at least one embodiment, circuitry or logic may be used to implement synaptic interconnects and their components.

[0250] Inference and / or training logic 615 is used to perform inference and / or training operations associated with one or more embodiments. In at least one embodiment, this logic may be used with components of these graphs to generate one or more images using one or more neural networks, at least in part, based on one or more noise values.

[0251] Figure 23 This is a processing system according to at least one embodiment. In at least one embodiment, system 2300 includes one or more processors 2302 and one or more graphics processors 2308, and may be a single-processor desktop system, a multi-processor workstation system, or a server system having a large number of processors 2302 or processor cores 2307. In at least one embodiment, system 2300 is a processing platform included within a system-on-a-chip (SoC) integrated circuit for use in mobile, handheld, or embedded devices.

[0252] In at least one embodiment, system 2300 may include or be integrated into a server-based gaming platform, a game console including a game and media console, a mobile game console, a handheld game console, or an online game console. In at least one embodiment, system 2300 is a mobile phone, smartphone, tablet computing device, or mobile internet device. In at least one embodiment, processing system 2300 may also include components coupled to or integrated into a wearable device, such as a smartwatch wearable device, smart glasses device, augmented reality device, or virtual reality device. In at least one embodiment, processing system 2300 is a television or set-top box device having one or more processors 2302 and a graphical interface generated by one or more graphics processors 2308.

[0253] In at least one embodiment, each of the one or more processors 2302 includes one or more processor cores 2307 for processing instructions that, when executed, perform operations against the system and user software. In at least one embodiment, each of the one or more processor cores 2307 is configured to process a particular instruction set 2309. In at least one embodiment, the instruction set 2309 may facilitate Complex Instruction Set Computing (CISC), Reduced Instruction Set Computing (RISC), or computation via Very Long Instruction Word (VLIW). In at least one embodiment, the processor cores 2307 may each process a different instruction set 2309, which may include instructions that facilitate the emulation of other instruction sets. In at least one embodiment, the processor cores 2307 may also include other processing devices, such as digital signal processors (DSPs).

[0254] In at least one embodiment, processor 2302 includes cache memory 2304. In at least one embodiment, processor 2302 may have a single internal cache or more levels of internal caches. In at least one embodiment, the cache memory is shared among various components of processor 2302. In at least one embodiment, processor 2302 also uses an external cache (e.g., a Level 3 (L3) cache or a last-level cache (LLC)) (not shown), which can be shared among processor cores 2307 using known cache coherence techniques. In at least one embodiment, processor 2302 additionally includes a register file 2306, which may include different types of registers (e.g., integer registers, floating-point registers, status registers, and instruction pointer registers) for storing different types of data. In at least one embodiment, register file 2306 may include general-purpose registers or other registers.

[0255] In at least one embodiment, one or more processors 2302 are coupled to one or more interface buses 2310 to transmit communication signals, such as address, data, or control signals, between the processors 2302 and other components in the system 2300. In at least one embodiment, the interface bus 2310 may be a processor bus, such as a version of the Direct Media Interface (DMI) bus. In at least one embodiment, the interface bus 2310 is not limited to the DMI bus and may include one or more peripheral component interconnect buses (e.g., PCI, PCI Express), memory buses, or other types of interface buses. In at least one embodiment, one or more processors 2302 include an integrated memory controller 2316 and a platform controller hub 2330. In at least one embodiment, the memory controller 2316 facilitates communication between memory devices and other components of the system 2300, while the platform controller hub (PCH) 2330 provides connectivity to I / O devices via a local I / O bus.

[0256] In at least one embodiment, memory device 2320 may be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, a phase-change memory device, or some other memory device with suitable performance for use as processor memory. In at least one embodiment, memory device 2320 may operate as system memory of system 2300 for storing data 2322 and instructions 2321 for use when one or more processors 2302 execute an application or process. In at least one embodiment, memory controller 2316 is also coupled to an optional external graphics processor 2312, which may communicate with one or more graphics processors 2308 of processor 2302 to perform graphics and media operations. In at least one embodiment, display device 2311 may be connected to one or more processors 2302. In at least one embodiment, display device 2311 may include one or more internal display devices, such as in mobile electronic devices or laptop devices, or external display devices attached via a display interface (e.g., DisplayPort). In at least one embodiment, the display device 2311 may include a head-mounted display (HMD), such as a stereoscopic display device for virtual reality (VR) or augmented reality (AR) applications.

[0257] In at least one embodiment, the platform controller hub 2330 enables peripheral devices to connect to the memory device 2320 and the processor 2302 via a high-speed I / O bus. In at least one embodiment, the I / O peripheral devices include, but are not limited to, an audio controller 2346, a network controller 2334, a firmware interface 2328, a wireless transceiver 2326, a touch sensor 2325, and a data storage device 2324 (e.g., a hard disk drive, flash memory, etc.). In at least one embodiment, the data storage device 2324 may be connected via a storage interface (e.g., SATA) or via a peripheral bus, such as a peripheral component interconnect bus (e.g., PCI, PCIe). In at least one embodiment, the touch sensor 2325 may include a touchscreen sensor, a pressure sensor, or a fingerprint sensor. In at least one embodiment, the wireless transceiver 2326 may be a Wi-Fi transceiver, a Bluetooth transceiver, or a mobile network transceiver, such as a 3G, 4G, or LTE transceiver. In at least one embodiment, the firmware interface 2328 enables communication with the system firmware and may be, for example, a Unified Extensible Firmware Interface (UEFI). In at least one embodiment, network controller 2334 can implement network connectivity to a wired network. In at least one embodiment, a high-performance network controller (not shown) is coupled to interface bus 2310. In at least one embodiment, audio controller 2346 is a multi-channel high-definition audio controller. In at least one embodiment, system 2300 includes an optional legacy I / O controller 2340 for coupling legacy (e.g., Personal System 2 (PS / 2)) devices to system 2300. In at least one embodiment, platform controller hub 2330 can also be connected to one or more Universal Serial Bus (USB) controllers 2342, which connect input devices such as keyboard and mouse 2343 combinations, camera 2344, or other USB input devices.

[0258] In at least one embodiment, instances of the memory controller 2316 and platform controller hub 2330 may be integrated into a discrete external graphics processor, such as external graphics processor 2312. In at least one embodiment, the platform controller hub 2330 and / or the memory controller 2316 may be external to one or more processors 2302. For example, in at least one embodiment, system 2300 may include external memory controller 2316 and platform controller hub 2330, which may be configured as a memory controller hub and peripheral controller hub in a system chipset communicating with one or more processors 2302.

[0259] Inference and / or training logic 615 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 6A and / or Figure 6B Details regarding the inference and / or training logic 615 are provided. In at least one embodiment, some or all of the inference and / or training logic 615 may be incorporated into the graphics processor 2300. For example, in at least one embodiment, the training and / or inference techniques described herein may use one or more ALUs embodied in the graphics processor 2312. Furthermore, in at least one embodiment, the inference and / or training operations described herein may use, in addition to Figure 6A or Figure 6B The logic is performed using logic other than that shown. In at least one embodiment, the weight parameters may be stored in on-chip or off-chip memory and / or registers (shown or not shown), which configure the ALU of the graphics processor 2308 to execute one or more machine learning algorithms, neural network architectures, use cases, or training techniques described herein.

[0260] Inference and / or training logic 615 is used to perform inference and / or training operations associated with one or more embodiments. In at least one embodiment, this logic may be used with components of these graphs to generate one or more images using one or more neural networks, at least in part, based on one or more noise values.

[0261] Figure 24 This is a block diagram of a processor 2400 having one or more processor cores 2402A-2402N, an integrated memory controller 2414, and an integrated graphics processor 2408, according to at least one embodiment. In at least one embodiment, the processor 2400 may include additional cores, up to and including additional cores 2402N, indicated by dashed boxes. In at least one embodiment, each processor core 2402A-2402N includes one or more internal cache units 2404A-2404N. In at least one embodiment, each processor core may also access one or more shared cache units 2406.

[0262] In at least one embodiment, internal cache units 2404A-2404N and shared cache unit 2406 represent a cache memory hierarchy within processor 2400. In at least one embodiment, cache memory units 2404A-2404N may include at least one level of instruction and data cache within each processor core and one or more levels of shared intermediate cache, such as Level 2 (L2), Level 3 (L3), Level 4 (L4), or other levels of cache, wherein the highest level of cache preceding external memory is classified as LLC. In at least one embodiment, cache coherence logic maintains coherence between the individual cache units 2406 and 2404A-2404N.

[0263] In at least one embodiment, the processor 2400 may further include a group of one or more bus controller units 2416 and a system agent core 2410. In at least one embodiment, one or more bus controller units 2416 manage a group of peripheral buses, such as one or more PCI or PCIe buses. In at least one embodiment, the system agent core 2410 provides management functions for various processor components. In at least one embodiment, the system agent core 2410 includes one or more integrated memory controllers 2414 for managing access to various external memory devices (not shown).

[0264] In at least one embodiment, one or more processor cores 2402A-2402N include support for simultaneous multithreaded processing. In at least one embodiment, system agent core 2410 includes components for coordinating and operating cores 2402A-2402N during multithreaded processing. In at least one embodiment, system agent core 2410 may additionally include a power control unit (PCU) including logic and components for regulating one or more power states of processor cores 2402A-2402N and graphics processor 2408.

[0265] In at least one embodiment, processor 2400 further includes a graphics processor 2408 for performing graphics processing operations. In at least one embodiment, graphics processor 2408 is coupled to a shared cache unit 2406 and a system proxy core 2410 including one or more integrated memory controllers 2414. In at least one embodiment, system proxy core 2410 further includes a display controller 2411 for driving graphics processor outputs to one or more coupled displays. In at least one embodiment, display controller 2411 may also be a separate module coupled to graphics processor 2408 via at least one interconnect, or it may be integrated within graphics processor 2408.

[0266] In at least one embodiment, the ring-based interconnect unit 2412 is used to couple internal components of the processor 2400. In at least one embodiment, alternative interconnect units, such as point-to-point interconnects, switched interconnects, or other technologies, may be used. In at least one embodiment, the graphics processor 2408 is coupled to the ring interconnect 2412 via I / O link 2413.

[0267] In at least one embodiment, I / O link 2413 represents at least one of a variety of I / O interconnects, including packaged I / O interconnects that facilitate communication between various processor components and high-performance embedded memory modules 2418 (such as eDRAM modules). In at least one embodiment, each of the processor cores 2402A-2402N and the graphics processor 2408 uses the embedded memory module 2418 as a shared last-level cache.

[0268] In at least one embodiment, processor cores 2402A-2402N are homogeneous cores executing a common instruction set architecture. In at least one embodiment, processor cores 2402A-2402N are heterogeneous in terms of instruction set architecture (ISA), with one or more processor cores 2402A-2402N executing a common instruction set, while one or more other cores of processor cores 2402A-2402N execute a subset of the common instruction set or a different instruction set. In at least one embodiment, processor cores 2402A-2402N are heterogeneous in terms of microarchitecture, with one or more cores having relatively high power consumption coupled to one or more power cores having lower power consumption. In at least one embodiment, processor 2400 may be implemented on one or more chips or implemented as a SoC integrated circuit.

[0269] Inference and / or training logic 615 is used to perform inference and / or training operations associated with one or more embodiments. The following is combined with... Figure 6A and / or Figure 6B Details regarding the inference and / or training logic 615 are provided. In at least one embodiment, some or all of the inference and / or training logic 615 may be incorporated into the processor 2400. For example, in at least one embodiment, the training and / or inference techniques described herein may use one or more ALUs embodied in... Figure 24 The graphics processor 2312, graphics core 2402A-2402N, or other components are used. Furthermore, in at least one embodiment, the inference and / or training operations described herein can use, except... Figure 6A or Figure 6BThe logic is performed using logic other than that shown. In at least one embodiment, the weight parameters may be stored in on-chip or off-chip memory and / or registers (shown or not shown), which configure the ALU of the graphics processor 2400 to execute one or more machine learning algorithms, neural network architectures, use cases, or training techniques described herein.

[0270] Inference and / or training logic 615 is used to perform inference and / or training operations associated with one or more embodiments. In at least one embodiment, this logic may be used with components of these graphs to generate one or more images using one or more neural networks, at least in part, based on one or more noise values.

[0271] Figure 25 This is a block diagram of the hardware logic of a graphics processor core 2500 according to at least one embodiment described herein. In at least one embodiment, the graphics processor core 2500 is included within a graphics core array. In at least one embodiment, the graphics processor core 2500 (sometimes referred to as a core slice) may be one or more graphics cores within a modular graphics processor. In at least one embodiment, the graphics processor core 2500 is an example of a graphics core slice, and the graphics processor described herein may include multiple graphics core slices based on target power and performance envelopes. In at least one embodiment, each graphics core 2500 may include a fixed-function block 2530 coupled to a plurality of sub-cores 2501A-2501F (also referred to as sub-slices), which includes modular blocks of general-purpose and fixed-function logic.

[0272] In at least one embodiment, the fixed-function block 2530 includes a geometry / fixed-function pipeline 2536, which, for example, may be shared by all sub-cores of the graphics processor 2500 in a lower-performance and / or lower-power graphics processor implementation. In at least one embodiment, the geometry / fixed-function pipeline 2536 includes a 3D fixed-function pipeline, a video front-end unit, a thread generator and a thread dispatcher, and a unified return buffer manager that manages a unified return buffer.

[0273] In at least one embodiment, the fixed functional block 2530 further includes a graphics SoC interface 2537, a graphics microcontroller 2538, and a media pipeline 2539. In at least one embodiment, the fixed graphics SoC interface 2537 provides an interface between the graphics core 2500 and other processor cores in the system-on-a-chip integrated circuit. In at least one embodiment, the graphics microcontroller 2538 is a programmable subprocessor configurable to manage various functions of the graphics processor 2500, including thread dispatch, scheduling, and preemption. In at least one embodiment, the media pipeline 2539 includes logic facilitating the decoding, encoding, preprocessing, and / or post-processing of multimedia data, including image and video data. In at least one embodiment, the media pipeline 2539 implements media operations via requests for computation or sampling logic within subcores 2501A-2501F.

[0274] In at least one embodiment, the SoC interface 2537 enables the graphics core 2500 to communicate with a general-purpose application processor core (e.g., a CPU) and / or other components within the SoC, including memory hierarchy elements such as shared last-level cache memory, system RAM, and / or embedded on-chip or packaged DRAM. In at least one embodiment, the SoC interface 2537 also enables communication with fixed-function devices within the SoC (e.g., a camera imaging pipeline) and enables the use and / or implementation of global memory atoms that can be shared between the graphics core 2500 and the CPU within the SoC. In at least one embodiment, the SoC interface 2537 also implements power management controls for the graphics core 2500 and enables interfacing between the clock domain of the graphics core 2500 and other clock domains within the SoC. In at least one embodiment, the SoC interface 2537 enables the receipt of command buffers from a command stream converter and a global thread dispatcher configured to provide commands and instructions to each of one or more graphics cores within the graphics processor. In at least one embodiment, when a media operation is to be performed, commands and instructions can be dispatched to the media pipeline 2539, or when a graphics processing operation is to be performed, commands and instructions can be dispatched to the geometry and fixed function pipelines (e.g., geometry and fixed function pipelines 2536 and 2514).

[0275] In at least one embodiment, the graphics microcontroller 2538 can be configured to perform various scheduling and management tasks on the graphics core 2500. In at least one embodiment, the graphics microcontroller 2538 can perform graphics and / or compute workload scheduling on various graphics parallel engines within the execution unit (EU) arrays 2502A-2502F, 2504A-2504F in sub-cores 2501A-2501F. In at least one embodiment, host software executing on the CPU core of the SoC including the graphics core 2500 can submit workloads to one of a plurality of graphics processor doorbells, which invoke scheduling operations on the appropriate graphics engine. In at least one embodiment, the scheduling operations include determining which workload should be run next, submitting the workload to a command stream converter, preempting existing workloads running on the engine, monitoring the progress of the workload, and notifying the host software when the workload is completed. In at least one embodiment, the graphics microcontroller 2538 may also facilitate a low-power or idle state of the graphics core 2500, thereby providing the graphics core 2500 with the ability to save and restore registers across low-power state transitions within the graphics core 2500, independent of the operating system and / or the graphics driver software on the system.

[0276] In at least one embodiment, the graphics core 2500 may have up to N more or fewer modular sub-cores than the illustrated sub-cores 2501A-2501F. For each group of N sub-cores, in at least one embodiment, the graphics core 2500 may further include shared functional logic 2510, shared and / or cache memory 2512, geometry / fixed-function pipeline 2514, and additional fixed-function logic 2516 for accelerating various graphics and computational processing operations. In at least one embodiment, the shared functional logic 2510 may include logic units (e.g., samplers, mathematical and / or inter-thread communication logic) that can be shared by each of the N sub-cores within the graphics core 2500. In at least one fixed-function embodiment, the shared and / or cache memory 2512 may be the last-level cache of the N sub-cores 2501A-2501F within the graphics core 2500, and may also be used as shared memory accessible by multiple sub-cores. In at least one embodiment, a geometry / fixed function pipeline 2514 may be included to replace the geometry / fixed function pipeline 2536 within the fixed function block 2530, and may include the same or similar logic units.

[0277] In at least one embodiment, the graphics core 2500 includes additional fixed-function logic 2516, which may include various fixed-function acceleration logics for use by the graphics core 2500. In at least one embodiment, the additional fixed-function logic 2516 includes additional geometry pipelines for use in position-only shading. In position-only shading, there are at least two geometry pipelines, namely a full geometry pipeline and a culling pipeline within the geometry and fixed-function pipelines 2514, 2536, which are additional geometry pipelines that may be included in the additional fixed-function logic 2516. In at least one embodiment, the culling pipeline is a trimmed version of the full geometry pipeline. In at least one embodiment, the full pipeline and the culling pipeline can execute different instances of the application, each with a separate context. In at least one embodiment, position-only shading can hide long culling runs of discarded triangles, thereby enabling earlier completion of shading in some cases. For example, in at least one embodiment, the culling pipeline logic in the additional fixed-function logic 2516 can execute the position shader in parallel with the main application and typically generates critical results faster than the full pipeline because the culling pipeline acquires the positional attributes of vertices and shades them without performing rasterization and rendering pixels to the framebuffer. In at least one embodiment, the culling pipeline can use the generated critical results to compute visibility information for all triangles, regardless of whether those triangles were culled. In at least one embodiment, the full pipeline (which in this case might be called the replay pipeline) can consume visibility information to skip culled triangles and shade only the visible triangles that are ultimately passed to the rasterization stage.

[0278] In at least one embodiment, the additional fixed-function logic 2516 may also include machine learning acceleration logic, such as fixed-function matrix multiplication logic, for including optimized implementations for machine learning training or inference.

[0279] In at least one embodiment, each graphics subcore 2501A-2501F includes a set of execution resources that can be used to perform graphics, media, and compute operations in response to requests from the graphics pipeline, media pipeline, or shader program. In at least one embodiment, the graphics subcore 2501A-2501F includes multiple EU arrays 2502A-2502F, 2504A-2504F, thread dispatch and inter-thread communication (TD / IC) logic 2503A-2503F, 3D (e.g., texture) samplers 2505A-2505F, media samplers 2506A-2506F, shader processors 2507A-2507F, and shared local memory (SLM) 2508A-2508F. In at least one embodiment, each of the EU arrays 2502A-2502F and 2504A-2504F includes multiple execution units, which are general-purpose graphics processing units capable of performing floating-point and integer / fixed-point logic operations to serve graphics, media, or computational operations (including graphics, media, or computational shader programs). In at least one embodiment, the TD / IC logic 2503A-2503F performs local thread dispatch and thread control operations for the execution units within the subcore and facilitates communication between threads executing on the execution units of the subcore. In at least one embodiment, the 3D samplers 2505A-2505F can read data associated with textures or other 3D graphics into memory. In at least one embodiment, the 3D samplers can read texture data differently based on the configured sample state and the texture format associated with a given texture. In at least one embodiment, the media samplers 2506A-2506F can perform similar read operations based on the type and format associated with the media data. In at least one embodiment, each graphics subcore 2501A-2501F may alternatively include a unified 3D and media sampler. In at least one embodiment, threads executing on execution units within each subcore 2501A-2501F may utilize shared local memory 2508A-2508F within each subcore, enabling threads executing within a thread group to utilize a common pool of on-chip memory for execution.

[0280] Inference and / or training logic 615 is used to perform inference and / or training operations associated with one or more embodiments. The following is combined with... Figure 6A and / or Figure 6B Details regarding the inference and / or training logic 615 are provided. In at least one embodiment, some or all of the inference and / or training logic 615 may be incorporated into the graphics processor 2510. For example, in at least one embodiment, the training and / or inference techniques described herein may be used in… Figure 25The graphics processor 2312, graphics microcontroller 2538, geometry and fixed-function pipelines 2514 and 2536, or other logic embodied in one or more ALUs. Furthermore, in at least one embodiment, the inference and / or training operations described herein can use, except... Figure 6A or Figure 6B The logic other than that shown is used to perform the task. In at least one embodiment, the weight parameters may be stored in on-chip or off-chip memory and / or registers (shown or not shown), which configure the ALU of the graphics processor 2500 to execute one or more machine learning algorithms, neural network architectures, use cases or training techniques described herein.

[0281] Inference and / or training logic 615 is used to perform inference and / or training operations associated with one or more embodiments. In at least one embodiment, this logic may be used with components of these graphs to generate one or more images using one or more neural networks, at least in part, based on one or more noise values.

[0282] Figures 26A-26B The diagram illustrates thread execution logic 2600 of an array of processing elements including a graphics processor core, according to at least one embodiment. Figure 26A At least one embodiment is shown in which thread execution logic 2600 is used. Figure 26B Exemplary internal details of an execution unit according to at least one embodiment are shown.

[0283] like Figure 26AAs shown, in at least one embodiment, thread execution logic 2600 includes a shader processor 2602, a thread dispatcher 2604, an instruction cache 2606, a scalable execution unit array including multiple execution units 2608A-2608N, one or more samplers 2610, a data cache 2612, and a data port 2614. In at least one embodiment, the scalable execution unit array can be dynamically expanded, for example, based on the computational requirements of the workload, by enabling or disabling one or more execution units (e.g., any one of execution units 2608A, 2608B, 2608C, 2608D, 2608N-1 to 2608N). In at least one embodiment, the scalable execution units are interconnected via an interconnect structure linking to each execution unit. In at least one embodiment, the thread execution logic 2600 includes one or more connections to memory (such as system memory or cache memory) via one or more of the instruction cache 2606, data port 2614, sampler 2610, and execution units 2608A-2608N. In at least one embodiment, each execution unit (e.g., 2608A) is an independent programmable general-purpose computing unit capable of executing multiple concurrent hardware threads, processing multiple data elements in parallel for each thread. In at least one embodiment, the array of execution units 2608A-2608N can be expanded to include any number of individual execution units.

[0284] In at least one embodiment, execution units 2608A-2608N are primarily used to execute shader programs. In at least one embodiment, shader processor 2602 can process various shader programs and dispatch execution threads associated with the shader programs via thread dispatcher 2604. In at least one embodiment, thread dispatcher 2604 includes logic for arbitrating thread initialization requests from the graphics and media pipeline and instantiating the requested thread on one or more execution units 2608A-2608N. For example, in at least one embodiment, the geometry pipeline can dispatch vertex, tessellation, or geometry shaders to thread execution logic for processing. In at least one embodiment, thread dispatcher 2604 can also handle runtime thread generation requests from executing shader programs.

[0285] In at least one embodiment, execution units 2608A-2608N support an instruction set that includes native support for many standard 3D graphics shader instructions, enabling shader programs from graphics libraries (e.g., Direct3D and OpenGL) to be executed with minimal conversion. In at least one embodiment, the execution units support vertex and geometry processing (e.g., vertex programs, geometry programs, vertex shaders), pixel processing (e.g., pixel shaders, fragment shaders), and general processing (e.g., computation and media shaders). In at least one embodiment, each execution unit 2608A-2608N (which includes one or more arithmetic logic units (ALUs)) is capable of executing multiple issue single instruction multiple data (SIMD), and multithreaded operation enables an efficient execution environment, despite higher memory access latency. In at least one embodiment, each hardware thread within each execution unit has a dedicated high-bandwidth register file and associated independent thread states. In at least one embodiment, execution is multi-clockwise issued to the pipeline, which is capable of integer, single-precision, and double-precision floating-point operations, SIMD branching functions, logical operations, transcendental operations, and other miscellaneous operations. In at least one embodiment, while waiting for data from one of the memory or shared functions, dependency logic within the execution units 2608A-2608N causes the waiting thread to sleep until the requested data is returned. In at least one embodiment, while the waiting thread is sleeping, hardware resources can be dedicated to processing other threads. For example, in at least one embodiment, during the latency associated with vertex shader operations, the execution unit can perform operations on the pixel shader, fragment shader, or another type of shader program (including different vertex shaders).

[0286] In at least one embodiment, each execution unit in the execution units 2608A-2608N operates on an array of data elements. In at least one embodiment, the number of data elements is an "execution size" or the number of instruction channels. In at least one embodiment, an execution channel is a logical execution unit used for data element access, masking, and flow control within an instruction. In at least one embodiment, the number of channels may be independent of the number of physical arithmetic logic units (ALUs) or floating-point units (FPUs) of a particular graphics processor. In at least one embodiment, the execution units 2608A-2608N support both integer and floating-point data types.

[0287] In at least one embodiment, the execution unit instruction set includes SIMD instructions. In at least one embodiment, individual data elements may be stored in registers as packed data types, and the execution unit will process each element based on the data size of those elements. For example, in at least one embodiment, when operating on a 256-bit wide vector, the 256-bit vector is stored in registers, and the execution unit operates on vectors that are four separate 64-bit packed data elements (four-word (QW) size data elements), eight separate 26-bit packed data elements (double-word (DW) size data elements), sixteen separate 16-bit packed data elements (word (W) size data elements), or thirty-two separate 8-bit data elements (byte (B) size data elements). However, in at least one embodiment, different vector widths and register sizes are possible.

[0288] In at least one embodiment, one or more execution units can be combined into fused execution units 2609A-2609N having thread control logic (2607A-2607N) shared by fused EUs. In at least one embodiment, multiple EUs can be fused into an EU group. In at least one embodiment, each EU in the fused EU group can be configured to execute a separate SIMD hardware thread. The number of EUs in the fused EU group can vary depending on the embodiments. In at least one embodiment, each EU can execute various SIMD widths, including but not limited to SIMD8, SIMD16, and SIMD26. In at least one embodiment, each fused graphics execution unit 2609A-2609N includes at least two execution units. For example, in at least one embodiment, the fused execution unit 2609A includes a first EU 2607A, a second EU 2608A, and thread control logic 2607A shared by the first EU 2607A and the second EU 2608A. In at least one embodiment, thread control logic 2607A controls the threads executing on the fused graphics execution unit 2609A, thereby allowing each EU within the fused execution units 2609A-2609N to execute using a common instruction pointer register.

[0289] In at least one embodiment, one or more internal instruction caches (e.g., 2606) are included in the thread execution logic 2600 to cache thread instructions for the execution unit. In at least one embodiment, one or more data caches (e.g., 2612) are included to cache thread data during thread execution. In at least one embodiment, a sampler 2610 is included to provide texture sampling for 3D operations and media sampling for media operations. In at least one embodiment, the sampler 2610 includes dedicated texture or media sampling functions to process texture or media data during the sampling process before providing sampled data to the execution unit.

[0290] During execution, in at least one embodiment, the graphics and media pipeline sends thread initiation requests to thread execution logic 2600 via thread creation and dispatch logic. In at least one embodiment, once a set of geometric objects has been processed and rasterized into pixel data, pixel processor logic (e.g., pixel shader logic, fragment shader logic, etc.) within shader processor 2602 is invoked to further compute output information and cause the results to be written to output surfaces (e.g., color buffer, depth buffer, stencil buffer, etc.). In at least one embodiment, the pixel shader or fragment shader computes values ​​of individual vertex attributes to be interpolated on the rasterized objects. In at least one embodiment, the pixel processor logic within shader processor 2602 then executes a pixel or fragment shader program provided by an application programming interface (API). In at least one embodiment, to execute the shader program, shader processor 2602 dispatches threads to execution units (e.g., 2608A) via thread dispatcher 2604. In at least one embodiment, shader processor 2602 uses texture sampling logic in sampler 2610 to access texture data in a texture map stored in memory. In at least one embodiment, arithmetic operations on the texture data and the input geometry data are performed to calculate pixel color data for each geometric segment, or one or more pixels are discarded without further processing.

[0291] In at least one embodiment, data port 2614 provides a memory access mechanism for thread execution logic 2600 to output processed data to memory for further processing on the graphics processor output pipeline. In at least one embodiment, data port 2614 includes or is coupled to one or more cache memories (e.g., data cache 2612) for caching data for memory access via the data port.

[0292] like Figure 26BAs shown, in at least one embodiment, the graphics execution unit 2608 may include an instruction fetch unit 2637, a general-purpose register file array (GRF) 2624, an architecture register file array (ARF) 2626, a thread arbiter 2622, a send unit 2630, a branch unit 2632, a set of SIMD floating-point units (FPUs) 2634, and, in at least one embodiment, a set of dedicated integer SIMD ALUs 2635. In at least one embodiment, the GRF 2624 and ARF 2626 include a set of general-purpose register files and architecture register files associated with each concurrent hardware thread that may be active in the graphics execution unit 2608. In at least one embodiment, the per-thread architecture state is maintained in the ARF 2626, while data used during thread execution is stored in the GRF 2624. In at least one embodiment, the execution state of each thread, including the instruction pointer of each thread, may be stored in thread-specific registers in the ARF 2626.

[0293] In at least one embodiment, the graphics execution unit 2608 has an architecture that is a combination of simultaneous multithreading (SMT) and fine-grained interleaved multithreading (IMT). In at least one embodiment, the architecture has a modular configuration that can be fine-tuned at design time based on a target number of simultaneous threads and the number of registers per execution unit, wherein execution unit resources are logically partitioned for executing multiple simultaneous threads.

[0294] In at least one embodiment, the graphics execution unit 2608 can jointly issue multiple instructions, each of which can be a different instruction. In at least one embodiment, the thread arbiter 2622 of the graphics execution unit thread 2608 can dispatch instructions to one of the sending unit 2630, the branching unit 2632, or the SIMD FPU 2634 for execution. In at least one embodiment, each execution thread can access 128 general-purpose registers in the GRF 2624, where each register can store 32 bytes and can be accessed as a SIMD 8-element vector of 32-bit data elements. In at least one embodiment, each execution unit thread can access 4KB of the GRF 2624, but the embodiments are not limited thereto, and more or fewer register resources may be provided in other embodiments. In at least one embodiment, although the number of threads per execution unit may also vary depending on the embodiment, up to seven threads can be executed simultaneously. In at least one embodiment, where the seven threads can access 4KB, the GRF 2624 can store a total of 28KB. In at least one embodiment, the flexible addressing mode can allow registers to be addressed together to efficiently build wider registers or rectangular block data structures representing strides.

[0295] In at least one embodiment, memory operations, sampler operations, and other longer-delay system communications are dispatched via a "transmit" instruction executed by a message passed to the transmitting unit 2630. In at least one embodiment, branch instructions are dispatched to a dedicated branching unit 2632 to facilitate SIMD divergence and eventual convergence.

[0296] In at least one embodiment, the graphics execution unit 2608 includes one or more SIMD floating-point units (FPUs) 2634 for performing floating-point operations. In at least one embodiment, one or more FPUs 2634 also support integer computation. In at least one embodiment, one or more FPUs 2634 can perform up to M 32-bit floating-point (or integer) operations in SIMD, or perform up to 2M 16-bit integer or 16-bit floating-point operations in SIMD. In at least one embodiment, at least one of the FPUs provides extended mathematical capabilities to support high-throughput transcendental mathematical functions and double-precision 64-bit floating-point operations. In at least one embodiment, a set of 8-bit integer SIMD ALUs 2635 are also present, and these can be specifically optimized to perform operations associated with machine learning computations.

[0297] In at least one embodiment, an array of multiple instances of the graphics execution unit 2608 may be instantiated in a graphics sub-core group (e.g., a sub-slice). In at least one embodiment, the execution unit 2608 may execute instructions across multiple execution channels. In at least one embodiment, each thread executing on the graphics execution unit 2608 executes on a different channel.

[0298] Inference and / or training logic 615 is used to perform inference and / or training operations associated with one or more embodiments. The following is combined with... Figure 6A and / or Figure 6B Details are provided regarding the inference and / or training logic 615. In at least one embodiment, some or all of the inference and / or training logic 615 may be incorporated into the execution logic 2600. Furthermore, in at least one embodiment, additional... Figure 6A or Figure 6B The logic other than that shown herein is used to perform the inference and / or training operations described herein. In at least one embodiment, weight parameters may be stored in on-chip or off-chip memory and / or registers (shown or not shown), which configure the ALU of execution logic 2600 to execute one or more machine learning algorithms, neural network architectures, use cases, or training techniques described herein.

[0299] Inference and / or training logic 615 is used to perform inference and / or training operations associated with one or more embodiments. In at least one embodiment, this logic may be used with components of these graphs to generate one or more images using one or more neural networks, at least in part, based on one or more noise values.

[0300] Figure 27 A parallel processing unit (“PPU”) 2700 according to at least one embodiment is illustrated. In at least one embodiment, the PPU 2700 is configured with machine-readable code that, if executed by the PPU 2700, causes the PPU 2700 to perform some or all of the processes and techniques described herein. In at least one embodiment, the PPU 2700 is a multi-threaded processor implemented on one or more integrated circuit devices and utilizing multithreading as a latency-hiding technique designed to process computer-readable instructions (also referred to as machine-readable instructions or simply instructions) in parallel on multiple threads. In at least one embodiment, a thread refers to an execution thread and is an instantiation of a set of instructions configured to be executed by the PPU 2700. In at least one embodiment, the PPU 2700 is a graphics processing unit (“GPU”) configured to implement a graphics rendering pipeline for processing three-dimensional (“3D”) graphics data to generate two-dimensional (“2D”) image data for display on a display device, such as a liquid crystal display (“LCD”) device. In at least one embodiment, the PPU 2700 is used to perform computations, such as linear algebra operations and machine learning operations. Figure 27 An example parallel processor is shown for illustrative purposes only and should be interpreted as a non-limiting example of a processor architecture contemplated within the scope of this disclosure, which may be supplemented and / or replaced by any suitable processor.

[0301] In at least one embodiment, one or more PPU 2700s are configured to accelerate high-performance computing (“HPC”), data center, and machine learning applications. In at least one embodiment, the PPU 2700 is configured to accelerate deep learning systems and applications, including, but not limited to, the following non-limiting examples: autonomous vehicle platforms, deep learning, high-precision speech, image, and text recognition systems, intelligent video analytics, molecular simulation, drug discovery, disease diagnosis, weather forecasting, big data analytics, astronomy, molecular dynamics simulation, financial modeling, robotics, factory automation, real-time language translation, online search optimization, and personalized user recommendations, etc.

[0302] In at least one embodiment, the PPU 2700 includes, but is not limited to, an input / output (“I / O”) unit 2706, a front-end unit 2710, a scheduler unit 2712, a job allocation unit 2714, a hub 2716, a crossbar (“Xbar”) 2720, one or more general-purpose processing clusters (“GPCs”) 2718, and one or more partitioning units (“memory partitioning units”) 2722. In at least one embodiment, the PPU 2700 is connected to a host processor or other PPU 2700 via one or more high-speed GPU interconnects (“GPU interconnects”) 2708. In at least one embodiment, the PPU 2700 is connected to a host processor or other peripheral device via interconnect 2702. In at least one embodiment, the PPU 2700 is connected to local memory including one or more memory devices (“memory”) 2704. In at least one embodiment, the memory device 2704 includes, but is not limited to, one or more dynamic random access memory (“DRAM”) devices. In at least one embodiment, one or more DRAM devices are configured and / or configurable as high-bandwidth memory (“HBM”) subsystems, and multiple DRAM dies are stacked within each device.

[0303] In at least one embodiment, the high-speed GPU interconnect 2708 may refer to a wire-based multi-channel communication link used by the system for expansion and includes one or more PPUs 2700 coupled with one or more central processing units (“CPUs”), supporting cache coherency between the PPUs 2700 and the CPU, as well as CPU master control. In at least one embodiment, the high-speed GPU interconnect 2708 transmits data and / or commands to or from other units of the PPU 2700 via a hub 2716, said other units such as one or more copy engines, video encoders, video decoders, power management units, and / or other components. Figure 27 Other components that may not be explicitly shown.

[0304] In at least one embodiment, the I / O unit 2706 is configured to access the host processor via the system bus 2702. Figure 27(Not shown) Sending and receiving communications (e.g., commands, data). In at least one embodiment, I / O unit 2706 communicates directly with the host processor via system bus 2702 or through one or more intermediate devices (such as memory bridges). In at least one embodiment, I / O unit 2706 may communicate with one or more other processors (such as one or more PPUs 2700) via system bus 2702. In at least one embodiment, I / O unit 2706 implements a Peripheral Component Interconnect Fast (“PCIe”) interface for communication via the PCIe bus. In at least one embodiment, I / O unit 2706 implements an interface for communication with external devices.

[0305] In at least one embodiment, I / O unit 2706 decodes packets received via system bus 2702. In at least one embodiment, at least some packets represent commands configured to cause PPU 2700 to perform various operations. In at least one embodiment, I / O unit 2706 transmits the decoded commands to various other units of PPU 2700 as specified by the commands. In at least one embodiment, the commands are transmitted to front-end unit 2710 and / or to hub 2716 or other units of PPU 2700, such as one or more copy engines, video encoders, video decoders, power management units, etc. Figure 27 (Not explicitly shown). In at least one embodiment, I / O unit 2706 is configured to route communication between and within the various logical units of PPU 2700.

[0306] In at least one embodiment, a program executed by the host processor encodes a command stream in a buffer that provides a workload to the PPU 2700 for processing. In at least one embodiment, the workload includes instructions and data to be processed by those instructions. In at least one embodiment, the buffer is an area in memory accessible (e.g., read / write) by both the host processor and the PPU 2700—the host interface unit can be configured to access the buffer in system memory connected to the system bus 2702 via a memory request, which is transmitted by the I / O unit 2706 via the system bus 2702. In at least one embodiment, the host processor writes a command stream to the buffer and then sends a pointer to the start of the command stream to the PPU 2700, causing the front-end unit 2710 to receive pointers to one or more command streams and manage one or more command streams, read commands from the command streams, and forward the commands to the respective units of the PPU 2700.

[0307] In at least one embodiment, front-end unit 2710 is coupled to scheduler unit 2712, which configures various GPCs 2718 to process tasks defined by one or more command streams. In at least one embodiment, scheduler unit 2712 is configured to track status information related to various tasks managed by scheduler unit 2712, wherein the status information may indicate which GPC 2718 a task is assigned to, whether the task is active or inactive, the priority associated with the task, etc. In at least one embodiment, scheduler unit 2712 manages the execution of multiple tasks on one or more GPCs 2718.

[0308] In at least one embodiment, scheduler unit 2712 is coupled to job allocation unit 2714, which is configured to dispatch tasks for execution on GPC 2718. In at least one embodiment, job allocation unit 2714 tracks multiple scheduled tasks received from scheduler unit 2712 and manages a pending task pool and an active task pool for each GPC 2718. In at least one embodiment, the pending task pool includes multiple time slots (e.g., 32 time slots) containing tasks assigned to be processed by a particular GPC 2718; the active task pool may include multiple time slots (e.g., 4 time slots) for tasks actively processed by GPC 2718, such that as one of GPCs 2718 completes the execution of a task, that task is evicted from the active task pool of the GPC 2718, and another task is selected from the pending task pool and scheduled for execution on GPC 2718. In at least one embodiment, if an active task is idle on GPC 2718, such as while waiting for a data dependency to be resolved, the active task is evicted from GPC 2718 and returned to the pool of pending tasks, while another task in the pool of pending tasks is selected and scheduled to be executed on GPC 2718.

[0309] In at least one embodiment, the work allocation unit 2714 communicates with one or more GPCs 2718 via XBar 2720. In at least one embodiment, XBar 2720 is an interconnect network that couples a plurality of units of PPU 2700 to other units of PPU 2700, and can be configured to couple the work allocation unit 2714 to a specific GPC 2718. In at least one embodiment, one or more other units of PPU 2700 may also be connected to XBar 2720 via hub 2716.

[0310] In at least one embodiment, tasks are managed by scheduler unit 2712 and dispatched to one of GPCs 2718 by work allocation unit 2714. GPCs 2718 are configured to process tasks and generate results. In at least one embodiment, results may be consumed by other tasks in GPCs 2718, routed to different GPCs 2718 via XBar 2720, or stored in memory 2704. In at least one embodiment, results may be written to memory 2704 via partitioning unit 2722, which implements a memory interface for writing data to or reading data from memory 2704. In at least one embodiment, results may be transferred to another PPU or CPU via high-speed GPU interconnect 2708. In at least one embodiment, PPU 2700 includes, but is not limited to, U partitioning units 2722, which is equal to the number of separate and different memory devices 2704 coupled to PPU 2700. In at least one embodiment, as described below... Figure 29 The partition unit 2722 is described in more detail.

[0311] In at least one embodiment, the host processor executes a driver kernel that implements an application programming interface (API) that enables one or more applications executing on the host processor to schedule operations for execution on the PPU 2700. In at least one embodiment, multiple computing applications are executed concurrently by the PPU 2700, and the PPU 2700 provides isolation, Quality of Service (“QoS”), and independent address spaces for the multiple computing applications. In at least one embodiment, an application generates instructions (e.g., in the form of API calls) that cause the driver kernel to generate one or more tasks to be executed by the PPU 2700, and the driver kernel outputs the tasks to one or more streams being processed by the PPU 2700. In at least one embodiment, each task includes one or more associated thread groups, which may be referred to as a warp. In at least one embodiment, a warp includes multiple associated threads (e.g., 32 threads) that can be executed in parallel. In at least one embodiment, a cooperating thread may refer to multiple threads, including instructions for performing tasks and exchanging data via shared memory. In at least one embodiment, combined with... Figure 29 Threads and cooperative threads are described in more detail according to at least one embodiment.

[0312] Inference and / or training logic 615 is used to perform inference and / or training operations associated with one or more embodiments. The following is combined with... Figure 6A and / or Figure 6BDetails regarding the inference and / or training logic 615 are provided. In at least one embodiment, the deep learning application processor is used to train a machine learning model (such as a neural network) to predict or infer information provided to the PPU 2700. In at least one embodiment, the PPU 2700 is used to infer or predict information based on a trained machine learning model (e.g., a neural network) that has been trained by another processor or system or by the PPU 2700. In at least one embodiment, the PPU 2700 can be used to perform one or more neural network use cases described herein.

[0313] Inference and / or training logic 615 is used to perform inference and / or training operations associated with one or more embodiments. In at least one embodiment, this logic may be used with components of these graphs to generate one or more images using one or more neural networks, at least in part, based on one or more noise values.

[0314] Figure 28 A general-purpose processing cluster (“GPC”) 2800 according to at least one embodiment is illustrated. In at least one embodiment, the GPC 2800 is Figure 27 The GPC 2718. In at least one embodiment, each GPC 2800 includes, but is not limited to, multiple hardware units for processing tasks, and each GPC 2800 includes, but is not limited to, a pipeline manager 2802, a pre-raster operation unit (“PROP”) 2804, a raster engine 2808, a work assignment crossbar switch (“WDX”) 2816, a memory management unit (“MMU”) 2818, one or more data processing clusters (“DPC”) 2806, and any suitable combination of components.

[0315] In at least one embodiment, the operation of GPC 2800 is controlled by pipeline manager 2802. In at least one embodiment, pipeline manager 2802 manages the configuration of one or more DPCs 2806 to handle tasks assigned to GPC 2800. In at least one embodiment, pipeline manager 2802 configures at least one of one or more DPCs 2806 to implement at least a portion of the graphics rendering pipeline. In at least one embodiment, DPC 2806 is configured to execute vertex shader programs on programmable streaming multiprocessor (“SM”) 2814. In at least one embodiment, pipeline manager 2802 is configured to route packets received from the work allocation unit to appropriate logic units within GPC 2800, and in at least one embodiment, some packets may be routed to fixed-function hardware units in PROP 2804 and / or raster engine 2808, while other packets may be routed to DPC 2806 for processing by primitive engine 2812 or SM 2814. In at least one embodiment, pipeline manager 2802 configures at least one of DPC 2806 to implement a neural network model and / or computation pipeline.

[0316] In at least one embodiment, the PROP unit 2804 is configured to route data generated by the raster engine 2808 and DPC 2806 to the above-connected... Figure 27A more detailed description of the raster operation (“ROP”) unit in partition unit 2722. In at least one embodiment, PROP unit 2804 is configured to perform optimizations for color blending, organize pixel data, perform address translation, etc. In at least one embodiment, raster engine 2808 includes, but is not limited to, multiple fixed-function hardware units configured to perform various raster operations, and in at least one embodiment, raster engine 2808 includes, but is not limited to, a setup engine, a coarse raster engine, a culling engine, a clipping engine, a fine raster engine, a tile aggregation engine, and any suitable combination thereof. In at least one embodiment, the setup engine receives the transformed vertices and generates plane equations associated with the geometric primitives defined by the vertices; the plane equations are passed to the coarse raster engine to generate coverage information for primitives (e.g., x, y overlay masks for tiles); the output of the coarse raster engine is passed to the culling engine, in which fragments associated with primitives that failed the z-test are culled, and is passed to the clipping engine, in which fragments located outside the view frustum are clipped. In at least one embodiment, the remaining fragments after cropping and culling are passed to a fine raster engine to generate properties of the pixel fragments based on the plane equations generated by the setting engine. In at least one embodiment, the output of the raster engine 2808 includes fragments that will be processed by any suitable entity (e.g., by a fragment shader implemented within the DPC 2806).

[0317] In at least one embodiment, each DPC 2806 included in the GPC 2800 includes, but is not limited to, an M-pipeline controller (“MPC”) 2810; a primitive engine 2812; one or more SMs 2814; and any suitable combination thereof. In at least one embodiment, the MPC 2810 controls the operation of the DPC 2806, routing packets received from the pipeline manager 2802 to the appropriate units within the DPC 2806. In at least one embodiment, packets associated with vertices are routed to the primitive engine 2812, which is configured to retrieve vertex attributes associated with vertices from memory; conversely, packets associated with shader programs may be passed to the SM 2814.

[0318] In at least one embodiment, the SM 2814 includes, but is not limited to, a programmable streaming processor configured to process tasks represented by multiple threads. In at least one embodiment, the SM 2814 is multithreaded and configured to concurrently execute multiple threads (e.g., 32 threads) from a specific thread group, and implements a Single Instruction, Multiple Data (“SIMD”) architecture, wherein each thread in a group of threads (e.g., a thread bundle) is configured to process a different dataset based on the same instruction set. In at least one embodiment, all threads in the thread group execute the same instructions. In at least one embodiment, the SM 2814 implements a Single Instruction, Multiple Thread (“SIMT”) architecture, wherein each thread in the thread group is configured to process a different dataset based on the same instruction set, but wherein individual threads in the thread group are allowed to diverge during execution. In at least one embodiment, a program counter, call stack, and execution state are maintained for each thread bundle, thereby achieving concurrency between the thread bundle and serial execution within the thread bundle when threads in the thread bundle diverge. In another embodiment, a program counter, call stack, and execution state are maintained for each individual thread, thereby achieving equal concurrency among all threads within and between thread bundles. In at least one embodiment, an execution state is maintained for each individual thread, and threads executing the same instructions can be converged and executed in parallel to improve efficiency. At least one embodiment of the SM 2814 is described in more detail below.

[0319] In at least one embodiment, the MMU 2818 is integrated with the GPC 2800 and memory partitioning unit (e.g., Figure 27 The MMU 2818 provides an interface between partition units 2722 and provides virtual address to physical address translation, memory protection, and arbitration of memory requests. In at least one embodiment, the MMU 2818 provides one or more translation back buffers (“TLBs”) for performing virtual address to physical address translation in memory.

[0320] Inference and / or training logic 615 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 6A and / or Figure 6BDetails regarding the inference and / or training logic 615 are provided. In at least one embodiment, the deep learning application processor is used to train a machine learning model (such as a neural network) to predict or infer information provided to the GPC 2800. In at least one embodiment, the GPC 2800 is used to infer or predict information based on a trained machine learning model (e.g., a neural network) that has been trained by another processor or system or the GPC 2800. In at least one embodiment, the GPC 2800 can be used to perform one or more neural network use cases described herein.

[0321] Inference and / or training logic 615 is used to perform inference and / or training operations associated with one or more embodiments. In at least one embodiment, this logic may be used with components of these graphs to generate one or more images using one or more neural networks, at least in part, based on one or more noise values.

[0322] Figure 29 A memory partitioning unit 2900 of a parallel processing unit (“PPU”) according to at least one embodiment is illustrated. In at least one embodiment, the memory partitioning unit 2900 includes, but is not limited to, a raster operation (“ROP”) unit 2902; a secondary (“L2”) cache 2904; a memory interface 2906; and any suitable combination thereof. In at least one embodiment, the memory interface 2906 is coupled to memory. In at least one embodiment, the memory interface 2906 may implement a 32, 64, 128, 1024-bit data bus or a similar implementation for high-speed data transfer. In at least one embodiment, the PPU includes U memory interfaces 2906, one memory interface 2906 per pair of partitioning units 2900, wherein each pair of partitioning units 2900 is connected to a corresponding memory device. For example, in at least one embodiment, the PPU may be connected to up to Y memory devices, such as high-bandwidth memory stacks or Graphics Double Data Rate version 5 Synchronous Dynamic Random Access Memory (“GDDR5 SDRAM”).

[0323] In at least one embodiment, the memory interface 2906 implements a second-generation high-bandwidth memory (“HBM2”) memory interface, and Y is equal to half of U. In at least one embodiment, the HBM2 memory stack resides on the same physical package as the PPU, providing significant power and area savings compared to conventional GDDR5 SDRAM systems. In at least one embodiment, each HBM2 stack includes, but is not limited to, four memory dies, and Y equals 4, wherein each HBM2 stack includes two 128-bit channels per die, for a total of eight channels and a 1024-bit data bus width. In at least one embodiment, the memory supports single error correction dual error detection (“SECDED”) error correction codes (“ECC”) for data protection. In at least one embodiment, ECC provides higher reliability for data corruption-sensitive computing applications.

[0324] In at least one embodiment, the PPU implements a multi-level memory hierarchy. In at least one embodiment, the memory partitioning unit 2900 supports unified memory for providing a single unified virtual address space for the central processing unit (“CPU”) and PPU memory, thereby enabling data sharing between virtual memory systems. In at least one embodiment, the frequency of PPU accesses to memory located on other processors is tracked to ensure that memory pages are moved to the physical memory of PPUs that access pages more frequently. In at least one embodiment, the high-speed GPU interconnect 2708 supports address translation services, which allow the PPU to directly access the CPU's page tables and provide the PPU with full access to the CPU's memory.

[0325] In at least one embodiment, the replication engine transfers data between multiple PPUs or between a PPU and a CPU. In at least one embodiment, the replication engine can generate page faults for addresses not mapped to page tables, and then the memory partitioning unit 2900 servicees the page faults, mapping the addresses to page tables, after which the replication engine performs the transfer. In at least one embodiment, multiple replication engines operating on fixed (i.e., non-pageable) memory across multiple processors significantly reduce available memory. In at least one embodiment, in the event of a hardware page fault, an address can be passed to the replication engine regardless of whether a memory page resides, and the replication process is transparent.

[0326] According to at least one embodiment, from Figure 27Data from memory 2704 or other system memory is retrieved by memory partitioning unit 2900 and stored in L2 cache 2904, which is located on-chip and shared among various GPCs. In at least one embodiment, each memory partitioning unit 2900 includes, but is not limited to, at least a portion of the L2 cache associated with the corresponding memory device. In at least one embodiment, lower-level caches are implemented in various units within a GPC. In at least one embodiment, each SM 2814 may implement a Level 1 (“L1”) cache, wherein the L1 cache is a private memory dedicated to a specific SM 2814, and data is retrieved from L2 cache 2904 and stored in each of the L1 caches for processing within the functional units of the SM 2814. In at least one embodiment, L2 cache 2904 is coupled to memory interface 2906 and XBar 2720.

[0327] In at least one embodiment, ROP unit 2902 performs graphic raster operations related to pixel color, such as color compression, pixel blending, etc. In at least one embodiment, ROP unit 2902, in conjunction with raster engine 2808, performs depth testing, receiving depth from the culling engine of raster engine 2808 for sample locations associated with pixel fragments. In at least one embodiment, the depth is tested relative to the corresponding depth in the depth buffer used for the sample locations associated with the fragments. In at least one embodiment, if the fragment passes the depth test for the sample location, ROP unit 2902 updates the depth buffer and transmits the result of the depth test to raster engine 2808. It will be understood that the number of partition units 2900 may differ from the number of GPCs; therefore, in at least one embodiment, each ROP unit 2902 may be coupled to each GPC. In at least one embodiment, ROP unit 2902 tracks packets received from different GPCs and determines the results routed to the ROP unit 2902 via XBar 2720.

[0328] Figure 30 A streaming multiprocessor (“SM”) 3000 according to at least one embodiment is illustrated. In at least one embodiment, the SM 3000 is Figure 28SM 2814. In at least one embodiment, SM 3000 includes, but is not limited to, instruction cache 3002; one or more scheduler units 3004; register file 3008; one or more processing cores (“cores”) 3010; one or more special function units (“SFUs”) 3012; one or more load / store units (“LSUs”) 3014; interconnect network 3016; shared memory / Level 1 (“L1”) cache 3018; and / or any suitable combination thereof. In at least one embodiment, the work allocation unit assigns tasks to execute on a general-purpose processing cluster (“GPC”) of parallel processing units (“PPUs”), and each task is assigned to a specific data processing cluster (“DPC”) within the GPC, and if the task is associated with a shader program, the task is assigned to one of the SMs 3000. In at least one embodiment, scheduler unit 3004 receives tasks from the work allocation unit and manages instruction scheduling for one or more thread blocks assigned to SM 3000. In at least one embodiment, scheduler unit 3004 schedules thread blocks to be executed as thread bundles of parallel threads, wherein each thread block is assigned at least one thread bundle. In at least one embodiment, each thread bundle executes a thread. In at least one embodiment, scheduler unit 3004 manages multiple different thread blocks, assigns thread bundles to different thread blocks, and then dispatches instructions from multiple different cooperative groups to various functional units (e.g., processing core 3010, SFU 3012, and LSU 3014) in each clock cycle.

[0329] In at least one embodiment, a cooperative group can refer to a programming model for organizing groups of communicating threads, allowing developers to express the granularity at which threads are communicating, thereby enabling richer expression and more efficient parallel decomposition. In at least one embodiment, a cooperative startup API supports synchronization between thread blocks to execute parallel algorithms. In at least one embodiment, the application of a conventional programming model provides a single, simple construct for synchronizing cooperative threads: a barrier (e.g., the `syncthreads()` function) across all threads in a thread block. However, in at least one embodiment, programmers can define thread groups at a granularity smaller than that of thread blocks and synchronize within the defined groups to achieve higher performance, design flexibility, and software reuse in the form of a set of group-wide functional interfaces. In at least one embodiment, cooperative groups enable programmers to explicitly define thread groups at the sub-block (i.e., as small as a single thread) and multi-block granularity and perform set operations, such as synchronizing threads within the cooperative group. In at least one embodiment, this programming model supports clean composition across software boundaries, so that libraries and utility functions can be safely synchronized in their local context without having to make assumptions about convergence. In at least one embodiment, the collaborative group primitives implement novel modes of collaborative parallelism, including but not limited to producer-consumer parallelism, opportunistic parallelism, and global synchronization across the entire thread block mesh.

[0330] In at least one embodiment, dispatch unit 3006 is configured to transmit instructions to one or more functional units, and scheduler unit 3004 includes, but is not limited to, two dispatch units 3006 that enable two different instructions from the same thread bundle to be dispatched in each clock cycle. In at least one embodiment, each scheduler unit 3004 includes a single dispatch unit 3006 or additional dispatch units 3006.

[0331] In at least one embodiment, each SM 3000 includes, but is not limited to, a register file 3008 that provides a set of registers for functional units of the SM 3000. In at least one embodiment, the register file 3008 is partitioned between each functional unit, thereby allocating a dedicated portion of the register file 3008 for each functional unit. In at least one embodiment, the register file 3008 is partitioned between different thread bundles being executed by the SM 3000, and the register file 3008 provides temporary storage for operands in data paths connected to functional units. In at least one embodiment, each SM 3000 includes, but is not limited to, a plurality of L processing cores 3010. In at least one embodiment, the SM 3000 includes, but is not limited to, a large number (e.g., 128 or more) of different processing cores 3010. In at least one embodiment, each processing core 3010 includes, but is not limited to, a fully pipelined, single-precision, double-precision, and / or mixed-precision processing unit, which includes, but is not limited to, a floating-point arithmetic logic unit and an integer arithmetic logic unit. In at least one embodiment, the floating-point arithmetic logic unit implements the IEEE 754-2008 standard for floating-point arithmetic. In at least one embodiment, the processing core 3010 includes, but is not limited to, 64 single-precision (32-bit) floating-point cores, 64 integer cores, 32 double-precision (64-bit) floating-point cores and 8 tensor cores.

[0332] According to at least one embodiment, a tensor core is configured to perform matrix operations. In at least one embodiment, one or more tensor cores are included in the processing core 3010. In at least one embodiment, the tensor core is configured to perform deep learning matrix arithmetic, such as convolution operations for neural network training and inference. In at least one embodiment, each tensor core operates on a 4×4 matrix and performs matrix multiplication and accumulation operations D = A×B + C, where A, B, C, and D are 4×4 matrices.

[0333] In at least one embodiment, matrix multiplication inputs A and B are 16-bit floating-point matrices, and accumulation matrices C and D are either 16-bit or 32-bit floating-point matrices. In at least one embodiment, the Tensor Core performs 32-bit floating-point accumulation on the 16-bit floating-point input data. In at least one embodiment, the 16-bit floating-point multiplication uses 64 operations to obtain a full-precision product, which is then accumulated with other intermediate multiplications using 32-bit floating-point addition to perform a 4x4x4 matrix multiplication. In at least one embodiment, the Tensor Core is used to perform matrix operations on larger two-dimensional or higher-dimensional matrices composed of these smaller elements. In at least one embodiment, APIs (such as the CUDA 9 C++ API) expose specialized matrix loading, matrix multiplication and accumulation, and matrix storage operations for efficient use of the Tensor Core from CUDA-C++ programs. In at least one embodiment, at the CUDA level, the thread bundle-level interface assumes a 16×16 matrix spanning all 32 threads of the thread bundle.

[0334] In at least one embodiment, each SM 3000 includes, but is not limited to, M SFUs 3012 that perform special functions (e.g., attribute evaluation, inverse square root, etc.). In at least one embodiment, an SFU 3012 includes, but is not limited to, a tree traversal unit configured to traverse a hierarchical tree data structure. In at least one embodiment, an SFU 3012 includes, but is not limited to, a texture unit configured to perform texture map filtering operations. In at least one embodiment, a texture unit is configured to load a texture map (e.g., a 2D array of texture pixels) from memory and sample the texture map to produce sampled texture values ​​for use in a shader program executed by the SM 3000. In at least one embodiment, the texture map is stored in shared memory / L1 cache 3018. In at least one embodiment, according to at least one embodiment, the texture unit uses mip-maps (e.g., texture maps at different levels of detail) to implement texture operations (such as filtering operations). In at least one embodiment, each SM 3000 includes, but is not limited to, two texture units.

[0335] In at least one embodiment, each SM 3000 includes, but is not limited to, N LSUs 3014 that implement load and store operations between the shared memory / L1 cache 3018 and the register file 3008. In at least one embodiment, each SM 3000 includes, but is not limited to, an interconnect network 3016 that connects each functional unit to the register file 3008 and connects the LSUs 3014 to both the register file 3008 and the shared memory / L1 cache 3018. In at least one embodiment, the interconnect network 3016 is a crossbar switch that can be configured to connect any functional unit to any register in the register file 3008 and connect the LSUs 3014 to memory locations in both the register file 3008 and the shared memory / L1 cache 3018.

[0336] In at least one embodiment, the shared memory / L1 cache 3018 is an array of on-chip memory that, in at least one embodiment, allows data storage and communication between the SM 3000 and the primitive engine, as well as between threads within the SM 3000. In at least one embodiment, the shared memory / L1 cache 3018 includes, but is not limited to, a storage capacity of 128KB and is located on the path from the SM 3000 to the partition unit. In at least one embodiment, the shared memory / L1 cache 3018 is used for cache reads and writes. In at least one embodiment, one or more of the shared memory / L1 cache 3018, the L2 cache, and memory are spare storage.

[0337] In at least one embodiment, combining data caching and shared memory functionality into a single memory block provides improved performance for both types of memory access. In at least one embodiment, the capacity is used by programs that do not use shared memory or is used as a cache, such as if shared memory is configured to use half its capacity, while texture and load / store operations can use the remaining capacity. According to at least one embodiment, integration within the shared memory / L1 cache 3018 enables the shared memory / L1 cache 3018 to be used as a high-throughput pipeline for streaming data, while providing high-bandwidth and low-latency access to frequently reused data. In at least one embodiment, a simpler configuration can be used compared to graphics processing when configured for general-purpose parallel computing. In at least one embodiment, a simpler programming model is created by bypassing a fixed-function graphics processing unit. In at least one embodiment, in a general-purpose parallel computing configuration, the work allocation unit directly assigns and allocates individual blocks of threads to the DPC. In at least one embodiment, threads within a block execute the same program, using unique thread IDs in computation to ensure each thread produces unique results, using an SM 3000 to execute the program and perform computations, using a shared memory / L1 cache 3018 for communication between threads, and using an LSU 3014 to read and write global memory via the shared memory / L1 cache 3018 and memory partitioning units. In at least one embodiment, when configured for general-purpose parallel computing, the SM 3000 can write commands to the scheduler unit 3004 to initiate new work on the DPC.

[0338] In at least one embodiment, the PPU is included in or coupled to a desktop computer, laptop computer, tablet computer, server, supercomputer, smartphone (e.g., wireless, handheld device), personal digital assistant (“PDA”), digital camera, vehicle, head-mounted display, handheld electronic device, etc. In at least one embodiment, the PPU is implemented on a single semiconductor substrate. In at least one embodiment, the PPU is included in a system-on-a-chip (“SoC”) along with one or more other devices (e.g., additional PPUs, memory, reduced instruction set computer (“RISC”) CPU, memory management unit (“MMU”), digital-to-analog converter (“DAC”), etc.).

[0339] In at least one embodiment, the PPU may be included on a graphics card that includes one or more memory devices. The graphics card may be configured to engage with a PCIe slot on a desktop computer motherboard. In at least one embodiment, the PPU may be an integrated graphics processing unit (“iGPU”) included in the chipset of the motherboard.

[0340] Inference and / or training logic 615 is used to perform inference and / or training operations associated with one or more embodiments. The following is combined with... Figure 6A and / or Figure 6B Details regarding the inference and / or training logic 615 are provided. In at least one embodiment, the deep learning application processor is used to train a machine learning model (such as a neural network) to predict or infer information provided to the SM 3000. In at least one embodiment, the SM 3000 is used to infer or predict information based on a trained machine learning model (e.g., a neural network) that has been trained by another processor or system or by the SM 3000. In at least one embodiment, the SM 3000 can be used to perform one or more neural network use cases described herein.

[0341] Inference and / or training logic 615 is used to perform inference and / or training operations associated with one or more embodiments. In at least one embodiment, this logic may be used with components of these graphs to generate one or more images using one or more neural networks, at least in part, based on one or more noise values.

[0342] In at least one embodiment, a single semiconductor platform may refer to a single semiconductor-based integrated circuit or chip. In at least one embodiment, a multi-chip module may be used with increased connectivity, simulating on-chip operations and representing a substantial improvement over implementations using a conventional central processing unit (“CPU”) and bus. In at least one embodiment, various modules may also be configured individually or in combinations of different semiconductor platforms, depending on user needs.

[0343] In at least one embodiment, a computer program in the form of machine-readable executable code or computer control logic algorithms is stored in main memory 1004 and / or secondary memory. According to at least one embodiment, if the computer program is executed by one or more processors, it enables system 1000 to perform various functions. In at least one embodiment, memory 1004, memory, and / or any other memory are possible examples of computer-readable media. In at least one embodiment, secondary storage can refer to any suitable storage device or system, such as hard disk drives and / or removable storage drives, representing floppy disk drives, magnetic tape drives, optical disk drives, digital versatile disc (“DVD”) drives, recording devices, Universal Serial Bus (“USB”) flash memory, etc. Parallel processing system 1012; integrated circuit having at least a portion of the functionality of CPU 1002; parallel processing system 1012; chipset (e.g., a set of integrated circuits designed to operate and be marketed as units performing related functions, etc.); and any suitable combination of integrated circuits.

[0344] In at least one embodiment, the architecture and / or functionality of the various preceding figures are implemented within the context of a general-purpose computer system, a circuit board system, a game console system dedicated to entertainment purposes, a special-purpose system, etc. In at least one embodiment, the computer system 1000 may take the form of a desktop computer, laptop computer, tablet computer, server, supercomputer, smartphone (e.g., wireless handheld device), personal digital assistant (“PDA”), digital camera, vehicle, head-mounted display, handheld electronic device, mobile phone device, television, workstation, game console, embedded system, and / or any other type of logic.

[0345] In at least one embodiment, the parallel processing system 1012 includes, but is not limited to, multiple parallel processing units (“PPUs”) 1014 and associated memory 1016. In at least one embodiment, the PPUs 1014 are connected to a host processor or other peripheral device via interconnects 1018 and switches 1020 or more multiplexers. In at least one embodiment, the parallel processing system 1012 distributes computational tasks across the PPUs 1014, which may be parallelizable—for example, as part of distributing computational tasks across multiple graphics processing units (“GPUs”) thread blocks. In at least one embodiment, memory is shared and accessible (e.g., for read and / or write access) among some or all of the PPUs 1014, although such shared memory may result in performance penalties 1014 associated with the use of local memory and registers residing in the PPUs. In at least one embodiment, the operation of the PPUs 1014 is synchronized using commands such as __syncthreads(), where all threads in a block (e.g., executed across multiple PPUs 1014) reach a certain point in code execution before proceeding.

[0346] Virtualization computing platform

[0347] Embodiments are disclosed that relate to virtualized computing platforms for advanced computing, such as image inference and image processing in medical applications. (Reference) Figure 31 , Figure 31This is an example data flow diagram of process 3100 for generating and deploying an image processing and inference pipeline according to at least one embodiment. In at least one embodiment, process 3100 may be deployed for imaging devices, processing devices, genomics devices, gene sequencing devices, radiological devices, and / or other device types at one or more facilities 3102, such as medical facilities, hospitals, medical institutions, clinics, research or diagnostic laboratories, etc. In at least one embodiment, process 3100 may be deployed to perform genomic analysis and inference on sequencing data. Examples of genomic analyses that can be performed using the systems and processes described herein include, but are not limited to, variant identification, mutation detection, and gene expression quantification. Process 3100 may be executed within training system 3104 and / or deployment system 3106. In at least one embodiment, training system 3104 may be used to train, deploy, and implement machine learning models (e.g., neural networks, object detection algorithms, computer vision algorithms, etc.) for use in deployment system 3106. In at least one embodiment, deployment system 3106 may be configured to offload processing and computing resources in a distributed computing environment to reduce infrastructure requirements at facility 3102. In at least one embodiment, deployment system 3106 may provide a streamlined platform for selecting, customizing, and implementing virtual instruments for use at facility 3102 with imaging equipment (e.g., MRI, CT scan, X-ray, ultrasound, etc.) or sequencing equipment. In at least one embodiment, the virtual instrument may include a software-defined application for performing one or more processing operations on imaging data generated by imaging equipment, sequencing equipment, radiology equipment, and / or other equipment types. In at least one embodiment, one or more applications in the pipeline may use or invoke services of deployment system 3106 (e.g., inference, visualization, computation, AI, etc.) during application execution.

[0348] In at least one embodiment, some applications used in the advanced processing and inference pipeline may use machine learning models or other AI to perform one or more processing steps. In at least one embodiment, machine learning models may be trained at facility 3102 using data 3108 (e.g., imaging data) generated at facility 3102 (and stored on one or more Picture Archiving and Communication System (PACS) servers at facility 3102), imaging or sequencing data 3108 from another facility (e.g., different hospitals, laboratories, clinics, etc.), or a combination thereof. In at least one embodiment, training system 3104 may be used to provide applications, services, and / or other resources to generate a deployable machine learning model for deployment of system 3106.

[0349] In at least one embodiment, the model registry 3124 may be supported by an object storage system that supports version control and object metadata. In at least one embodiment, it may be available from within a cloud platform via, for example, cloud storage (e.g., Figure 32 The system uses a cloud-compatible application programming interface (API) to access object storage. In at least one embodiment, machine learning models within the model registry 3124 can be uploaded, listed, modified, or deleted by the developer or partner of the system interacting with the API. In at least one embodiment, the API can provide access to methods that allow users with appropriate credentials to associate models with applications, enabling the models to be executed as part of the execution of a containerized instantiation of the application.

[0350] In at least one embodiment, training pipeline 3204 ( Figure 32 The following scenarios may be included: where facility 3102 is training its own machine learning model, or has an existing machine learning model that needs optimization or updating. In at least one embodiment, imaging data 3108 generated by one or more imaging devices, sequencing devices, and / or other types of devices may be received. In at least one embodiment, once the imaging data 3108 is received, AI-assisted annotation 3110 can be used to assist in generating annotations corresponding to the imaging data 3108 for use as ground truth data for the machine learning model. In at least one embodiment, AI-assisted annotation 3110 may include one or more machine learning models (e.g., convolutional neural networks (CNNs)) that can be trained to generate annotations corresponding to certain types of imaging data 3108 (e.g., from certain devices) and / or certain types of anomalies in the imaging data 3108. In at least one embodiment, the AI-assisted annotation 3110 can then be used directly, or it can be adjusted or fine-tuned using annotation tools (e.g., by researchers, clinicians, doctors, scientists, etc.) to generate ground truth data. In at least one embodiment, in some examples, labeled clinical data 3112 (e.g., annotations provided by clinicians, doctors, scientists, technicians, etc.) can be used as ground truth data for training a machine learning model. In at least one embodiment, AI-assisted annotations 3110, labeled clinical data 3112, or a combination thereof can be used as ground truth data for training a machine learning model. In at least one embodiment, the trained machine learning model can be referred to as output model 3116 and can be used by deployment system 3106 as described herein.

[0351] In at least one embodiment, training pipeline 3204 ( Figure 32This can include situations where facility 3102 requires a machine learning model to perform one or more processing tasks for deploying one or more applications in system 3106, but facility 3102 may not currently have such a machine learning model (or may not have an efficient or effective model optimized for this purpose). In at least one embodiment, an existing machine learning model can be selected from model registry 3124. In at least one embodiment, model registry 3124 can include machine learning models trained to perform various inference tasks on imaging data. In at least one embodiment, the machine learning model in model registry 3124 may have already been trained on imaging data from a facility different from facility 3102 (e.g., a facility located at a distance). In at least one embodiment, the machine learning model may have already been trained on imaging data from one location, two locations, or any number of locations. In at least one embodiment, when training on imaging data from a particular location, training can be performed at that location, or at least in a manner that protects the confidentiality of the imaging data or restricts the off-site transfer of the imaging data (e.g., to comply with HIPAA regulations, privacy regulations, etc.). In at least one embodiment, once a model has been trained or partially trained at one location, a machine learning model can be added to model registry 3124. In at least one embodiment, the machine learning model can then be retrained or updated at any number of other facilities, and the retrained or updated model can be obtained from model registry 3124. In at least one embodiment, a machine learning model (referred to as output model 3116) can then be selected from model registry 3124 and used in deployment system 3106 to perform one or more processing tasks for one or more applications of the deployment system.

[0352] In at least one embodiment, training pipeline 3204 ( Figure 32This may include a scenario where facility 3102 requires a machine learning model to perform one or more processing tasks for deploying one or more applications in system 3106, but facility 3102 may not currently have such a machine learning model (or may not have an optimized, efficient, or effective model). In at least one embodiment, the machine learning model selected from model registry 3124 may not be fine-tuned or optimized for the imaging data 3108 generated at facility 3102 due to population differences, genetic variations, robustness, anomalous diversity of training data, and / or other problems with the training data used to train the machine learning model. In at least one embodiment, AI-assisted annotation 3110 may be used to assist in generating annotations corresponding to the imaging data 3108 for use as ground truth data for retraining or updating the machine learning model. In at least one embodiment, labeled clinical data 3112 (e.g., annotations provided by clinicians, doctors, scientists, etc.) may be used as ground truth data for training the machine learning model. In at least one embodiment, retraining or updating the machine learning model may be referred to as model training 3114. In at least one embodiment, model training 3114 (e.g., AI-assisted annotation 3110, labeled clinical data 3112, or a combination thereof) can be used as ground truth data to retrain or update the machine learning model. In at least one embodiment, the trained machine learning model can refer to output model 3116 and can be used by deployment system 3106 as described herein. In at least one embodiment, deployment system 3106 may include software 3118, service 3120, hardware 3122, and / or other components, features, and functionalities. In at least one embodiment, deployment system 3106 may include a software "stack" such that software 3118 can be built on top of service 3120 and can be used to perform some or all of the processing tasks, and service 3120 and software 3118 can be built on top of hardware 3122 and the hardware 3122 can be used to perform the processing, storage, and / or other computational tasks of deployment system 3106.

[0353] In at least one embodiment, software 3118 may include any number of different containers, each of which can instantiate an application. In at least one embodiment, each application can perform one or more processing tasks (e.g., inference, object detection, feature detection, segmentation, image enhancement, registration, etc.) in an advanced processing and inference pipeline. In at least one embodiment, for each type of imaging device (e.g., CT, MRI, X-ray, ultrasound, ultrasound examination, echocardiography, etc.), sequencing device, radiology device, genomics device, etc., there may be any number of containers that can perform data processing tasks on the imaging data 3108 (or other data types, such as those described herein) generated by the device. In at least one embodiment, in addition to receiving and configuring imaging data for use by each container and / or for use by facility 3102 after processing through the pipeline, an advanced processing and inference pipeline can be defined based on the selection of different containers desired or required for processing imaging data 3108 (e.g., to convert output back to available data types, such as Medical Digital Imaging and Communications (DICOM) data, Radiological Information System (RIS) data, Clinical Information System (CIS) data, Remote Procedure Call (RPC) data, data substantially conforming to a Representational State Transfer (REST) ​​interface, data substantially conforming to a file-based interface, and / or raw data, for storage and display at facility 3102). In at least one embodiment, a combination of containers within software 3118 (e.g., constituting a pipeline) can be referred to as a virtual instrument (as described in more detail herein), and the virtual instrument can utilize service 3120 and hardware 3122 to perform some or all of the processing tasks of an application instantiated within the container.

[0354] In at least one embodiment, the data processing pipeline may receive input data (e.g., imaging data 3108) in DICOM, RIS, CIS, REST-compliant, RPC, raw, and / or other formats in response to an inference request (e.g., a request from a user (e.g., a clinician, physician, radiologist, etc.) of deployment system 3106). In at least one embodiment, the input data may represent one or more images, videos, and / or other data representations generated by one or more imaging devices, sequencing devices, radiology devices, genomics devices, and / or other device types. In at least one embodiment, the data may be preprocessed as part of the data processing pipeline to prepare the data for processing by one or more applications. In at least one embodiment, post-processing may be performed on the output of one or more inference tasks or other processing tasks of the pipeline to prepare output data for the next application, and / or to prepare the output data for user transmission and / or use (e.g., in response to an inference request). In at least one embodiment, the inference task may be performed by one or more machine learning models (such as trained or deployed neural networks), which may include the output model 3116 of the training system 3104.

[0355] In at least one embodiment, the tasks of the data processing pipeline can be encapsulated in one or more containers, each container representing a separate, fully functional instantiation of an application capable of referencing a machine learning model and a virtualized computing environment. In at least one embodiment, a container or application can be published to a private (e.g., restricted access) area of ​​a container registry (described in more detail herein), and a trained or deployed model can be stored in a model registry 3124 and associated with one or more applications. In at least one embodiment, an image of the application (e.g., a container image) can be obtained from the container registry, and once a user selects an image from the container registry for deployment in the pipeline, that image can be used to generate containers for instantiation of the application for use by the user's system.

[0356] In at least one embodiment, a developer (e.g., a software developer, clinician, physician, etc.) can develop, publish, and store an application (e.g., store it as a container) for performing image processing and / or inference on provided data. In at least one embodiment, a software development kit (SDK) associated with the system can be used to perform development, publication, and / or storage (e.g., to ensure that the developed application and / or container conforms to or is compatible with the system). In at least one embodiment, the developed application can be tested locally using the SDK (e.g., at a first facility, testing data from a first facility), the SDK serving as a system (e.g., Figure 32 System 3200 may support at least some services 3120. In at least one embodiment, since DICOM objects may contain one to hundreds of images or other data types, and due to variations in the data, the developer may be responsible for managing (e.g., setting up constructs for preprocessing built into the application, etc.) the extraction and preparation of incoming DICOM data. In at least one embodiment, once verified by system 3200 (e.g., for accuracy, security, patient privacy, etc.), the application may be available in the container registry for users (e.g., hospitals, clinics, laboratories, healthcare providers, etc.) to select and / or implement to perform one or more processing tasks on data at the user's facility (e.g., a second facility).

[0357] In at least one embodiment, the developer can then share the application or container over a network for the system (e.g., Figure 32The system 3200 allows for user access and use. In at least one embodiment, completed and validated applications or containers may be stored in a container registry, and associated machine learning models may be stored in a model registry 3124. In at least one embodiment, a requesting entity (e.g., a user of a healthcare institution) (which provides inference or image processing requests) may browse the container registry and / or model registry 3124 to obtain applications, containers, datasets, machine learning models, etc., select desired combinations of elements to include in the data processing pipeline, and submit image processing requests. In at least one embodiment, the request may include input data necessary to perform the request (in some examples, and associated patient data), and / or may include a selection of one or more applications and / or machine learning models to be performed when the request is processed. In at least one embodiment, the request may then be passed to one or more components of the deployment system 3106 (e.g., the cloud) to perform processing in the data processing pipeline. In at least one embodiment, processing performed by the deployment system 3106 may include referencing elements (e.g., applications, containers, models, etc.) selected from the container registry and / or model registry 3124. In at least one embodiment, once the pipeline generates results, the results can be returned to the user for reference (e.g., for viewing in a suite of viewing applications executed on a locally deployed workstation or terminal). In at least one embodiment, a radiologist can receive results from a data processing pipeline comprising any number of applications and / or containers, wherein the results can include the detection of abnormalities in X-rays, CT scans, MRIs, etc.

[0358] In at least one embodiment, service 3120 may be utilized to assist in processing or executing applications or containers in the pipeline. In at least one embodiment, service 3120 may include computing services, artificial intelligence (AI) services, visualization services, and / or other service types. In at least one embodiment, service 3120 may provide functionality common to one or more applications in software 3118, thus abstracting functionality into services that can be invoked or utilized by applications. In at least one embodiment, the functionality provided by service 3120 can operate dynamically and more efficiently, while also allowing applications to process data in parallel (e.g., using...). Figure 32The parallel computing platform 3230 in the system can be well scaled. In at least one embodiment, it is not required that each application providing the same functionality as the shared service 3120 must have a corresponding instance of the service 3120, but the service 3120 can be shared between and among the various applications. In at least one embodiment, as a non-limiting example, the service may include an inference server or engine that can be used to perform detection or segmentation tasks. In at least one embodiment, a model training service may be included, which can provide the ability to train and / or retrain machine learning models. In at least one embodiment, a data augmentation service may be further included, which can provide GPU-accelerated data (e.g., DICOM, RIS, CIS, conforming to REST, RPC, raw, etc.) extraction, resizing, scaling, and / or other enhancements. In at least one embodiment, a visualization service may be used, which can add image rendering effects (such as ray tracing, rasterization, denoising, sharpening, etc.) to add realism to two-dimensional (2D) and / or three-dimensional (3D) models. In at least one embodiment, a virtual instrument service may be included, which provides beamforming, segmentation, inference, imaging, and / or support for other applications within the virtual instrument pipeline.

[0359] In at least one embodiment, where service 3120 includes an AI service (e.g., an inference service), as part of application execution, one or more machine learning models associated with an application for anomaly detection (e.g., tumors, growth abnormalities, scarring, etc.) can be executed by invoking (e.g., as an API call) the inference service (e.g., an inference server) to execute one or more machine learning models or their processing. In at least one embodiment, where another application includes one or more machine learning models for a segmentation task, the application can invoke the inference service to execute the machine learning models for performing one or more processing operations associated with the segmentation task. In at least one embodiment, the software 3118 implementing the advanced processing and inference pipeline (which includes a segmentation application and an anomaly detection application) can be streamlined because each application can invoke the same inference service to execute one or more inference tasks.

[0360] In at least one embodiment, hardware 3122 may include a GPU, CPU, graphics card, AI / deep learning system (e.g., an AI supercomputer such as NVIDIA's DGX), cloud platform, or a combination thereof. In at least one embodiment, different types of hardware 3122 may be used to provide efficient, specially designed support for software 3118 and services 3120 in deployment system 3106. In at least one embodiment, GPU processing may be used to perform local processing (e.g., at facility 3102) within the AI / deep learning system, in the cloud system, and / or in other processing components of deployment system 3106 to improve the efficiency, accuracy, and performance of image processing, image reconstruction, segmentation, MRI examination, stroke or heart attack detection (e.g., in real-time), rendered image quality, etc. In at least one embodiment, the facility may include imaging equipment, genomics equipment, sequencing equipment, and / or other locally deployed equipment types that can utilize GPUs to generate imaging data representing the anatomical structures of a subject. In at least one embodiment, as a non-limiting example, software 3118 and / or services 3120 may be optimized for GPU processing in relation to deep learning, machine learning, and / or high-performance computing. In at least one embodiment, at least some of the computing environments of deployment system 3106 and / or training system 3104 can be executed in a data center, one or more supercomputers, or high-performance computing systems with GPU-optimized software (e.g., a hardware and software combination of NVIDIA DGX systems). In at least one embodiment, the data center can comply with HIPAA regulations, enabling the secure handling of the reception, processing, and transmission of imaging data and / or other patient data with respect to patient privacy. In at least one embodiment, as described herein, hardware 3122 can include any number of GPUs that can be invoked to perform data processing in parallel. In at least one embodiment, the cloud platform can also include GPU-optimized execution for deep learning tasks, GPU processing for machine learning tasks, or other computing tasks. In at least one embodiment, an AI / deep learning supercomputer and / or GPU-optimized software (e.g., as provided on NVIDIA's DGX systems) can be used as a hardware abstraction and extension platform to execute the cloud platform (e.g., NVIDIA's NGC). In at least one embodiment, the cloud platform can integrate application container clustering systems or coordination systems (e.g., KUBERNETES) across multiple GPUs to achieve seamless scaling and load balancing.

[0361] Figure 32 This is a system diagram of an example system 3200 for generating and deploying an imaging deployment pipeline according to at least one embodiment. In at least one embodiment, system 3200 can be used to implement... Figure 31The process 3100 and / or other processes include advanced processing and inference pipelines. In at least one embodiment, system 3200 may include training system 3104 and deployment system 3106. In at least one embodiment, training system 3104 and deployment system 3106 may be implemented using software 3118, service 3120 and / or hardware 3122, as described herein.

[0362] In at least one embodiment, system 3200 (e.g., training system 3104 and / or deployment system 3106) may be implemented in a cloud computing environment (e.g., using cloud 3226). In at least one embodiment, system 3200 may be implemented locally (in relation to a healthcare facility) or as a combination of cloud computing resources and local computing resources. In at least one embodiment, in the cloud-based implementation, patient data may be decoupled from one or more components of system 3200, or not processed by one or more components of system 3200, which would result in processing that does not comply with HIPAA and / or other data processing and privacy regulations or laws. In at least one embodiment, access to APIs in cloud 3226 may be restricted to authorized users by establishing security measures or protocols. In at least one embodiment, the security protocol may include a network token, which may be signed by an authentication service (e.g., AuthN, AuthZ, Gluecon, etc.) and may carry appropriate authorization. In at least one embodiment, the API of the virtual instrument (described herein) or other instances of system 3200 may be restricted to a set of public IPs that have been audited or authorized for interaction.

[0363] In at least one embodiment, the various components of system 3200 may communicate with and among each other using any of a variety of different network types, including but not limited to local area networks (LANs) and / or wide area networks (WANs) via wired and / or wireless communication protocols. In at least one embodiment, communication between facilities and components of system 3200 (e.g., for sending inference requests, for receiving the results of inference requests, etc.) may be transmitted via one or more data buses, wireless data protocols (Wi-Fi), wired data protocols (e.g., Ethernet), etc.

[0364] In at least one embodiment, similar to the description herein. Figure 31As described, the training system 3104 can execute a training pipeline 3204. In at least one embodiment, where the deployment system 3106 uses one or more machine learning models in the deployment pipeline 3210, the training pipeline 3204 can be used to train or retrain one or more (e.g., pre-trained) models, and / or implement one or more pre-trained models 3206 (e.g., without retraining or updating). In at least one embodiment, as a result of the training pipeline 3204, one or more output models 3116 can be generated. In at least one embodiment, the training pipeline 3204 may include any number of processing steps, such as, but not limited to, conversion or adaptation of imaging data (or other input data) (e.g., converting DICOM images to another format suitable for processing by the corresponding machine learning model, such as the Neuroimaging Information Technology Initiative (NIfTI) format using a DICOM adapter 3202A), AI-assisted annotation 3110, labeling or annotating imaging data 3108 (for generating labeled clinical data 3112), selecting a model from a model registry, model training 3114, training, retraining, or updating the model, and / or other processing steps. In at least one embodiment, different training pipelines 3204 may be used for different machine learning models used by the deployment system 3106. In at least one embodiment, similar to the approach regarding... Figure 31 The training pipeline 3204 described in the first example can be used for the first machine learning model, similar to the one described above. Figure 31 The training pipeline 3204 described in the second example can be used for a second machine learning model, similar to the one described above. Figure 31 The training pipeline 3204 of the third example described can be used for a third machine learning model. In at least one embodiment, any combination of tasks within the training system 3104 can be used according to the requirements of each respective machine learning model. In at least one embodiment, one or more machine learning models may have been trained and are ready for deployment, so the machine learning models may not undergo any processing by the training system 3104, and the machine learning models may be implemented by the deployment system 3106.

[0365] In at least one embodiment, depending on the implementation or embodiment, one or more output models 3116 and / or pre-trained models 3206 may include any type of machine learning model. In at least one embodiment, and not limited thereto, the machine learning models used by system 3200 may include one or more machine learning models using linear regression, logistic regression, decision trees, support vector machines (SVM), Naive Bayes, k-nearest neighbors (Knn), k-means clustering, random forests, dimensionality reduction algorithms, gradient boosting algorithms, neural networks (e.g., autoencoders, convolutions, recurrent structures, perceptrons, long / short-term memory (LSTM), Hopfield, Boltzmann, deep belief, deconvolution, generative adversarial, liquid state machines, etc.), and / or other types of machine learning models.

[0366] In at least one embodiment, training pipeline 3204 may include AI-assisted annotations, as described herein regarding at least Figure 33BMore specifically. In at least one embodiment, labeled clinical data 3112 can be generated using any number of techniques (e.g., conventional annotation). In at least one embodiment, in some examples, labels or other annotations can be generated in a drawing program (e.g., annotating program), a computer-aided design (CAD) program, a tagging program, another type of program suitable for generating ground truth annotations or labels, and / or can be hand-drawn. In at least one embodiment, ground truth data can be generated synthetically (e.g., from a computer model or rendering), realistically (e.g., designed and generated from real-world data), automatically by machine (e.g., extracting features from data using feature analysis and learning, and then generating labels), manually annotated (e.g., by a tagger or annotation expert, defining label locations), and / or a combination thereof. In at least one embodiment, for each instance of imaging data 3108 (or other data types used by the machine learning model), corresponding ground truth data generated by the training system 3104 may exist. In at least one embodiment, AI-assisted annotation can also be performed as part of the deployment pipeline 3210, in addition to including AI-assisted annotation in the training pipeline 3204, or instead of including AI-assisted annotation in the training pipeline 3204. In at least one embodiment, system 3200 may include a multi-layer platform, which may include a software layer (e.g., software 3118) of a diagnostic application (or other application type) that can perform one or more medical imaging and diagnostic functions. In at least one embodiment, system 3200 may be communicatively coupled (e.g., via an encrypted link) to a network of PACS servers in one or more facilities. In at least one embodiment, system 3200 may be configured to access and reference data (e.g., DICOM data, RIS data, raw data, CIS data, REST-compliant data, RPC, raw data, etc.) from a PACS server (e.g., via DICOM adapter 3202 or another data type adapter such as RIS, CIS, REST-compliant data, RPC, raw data, etc.) to perform operations such as training machine learning models, deploying machine learning models, image processing, inference, and / or other operations.

[0367] In at least one embodiment, the software layer may be implemented as a secure, encrypted, and / or authenticated API through which an application or container can be invoked (e.g., called) from one or more external environments (e.g., facility 3102). In at least one embodiment, the application may then invoke or execute one or more services 3120 to perform computational, AI, or visualization tasks associated with the respective application, and the software 3118 and / or service 3120 may utilize the hardware 3122 to perform processing tasks in an efficient and effective manner.

[0368] In at least one embodiment, deployment system 3106 can execute deployment pipeline 3210. In at least one embodiment, deployment pipeline 3210 can include any number of applications, which can be sequential, non-sequential, or otherwise applied to imaging data (and / or other data types) – including AI-assisted annotation, the imaging data being generated by imaging devices, sequencing devices, genomics devices, etc., as described above. In at least one embodiment, as described herein, deployment pipeline 3210 for an individual device can be referred to as a virtual instrument for the device (e.g., a virtual ultrasound machine, a virtual CT scanner, a virtual sequencer, etc.). In at least one embodiment, for a single device, more than one deployment pipeline 3210 may exist, depending on the desired information from the data generated by the device. In at least one embodiment, a first deployment pipeline 3210 may exist if it is desired to detect an anomaly from an MRI machine, and a second deployment pipeline 3210 may exist if it is desired to perform image enhancement from the output of the MRI machine.

[0369] In at least one embodiment, the applications available for deployment pipeline 3210 may include any application that can perform processing tasks on imaging data or other data from the device. In at least one embodiment, different applications may be responsible for image enhancement, segmentation, reconstruction, anomaly detection, object detection, feature detection, treatment planning, dosimetry, beamplanning (or other radiation therapy procedures), and / or other analysis, image processing, or inference tasks. In at least one embodiment, deployment system 3106 may define a construct for each application such that users of deployment system 3106 (e.g., a medical facility, laboratory, clinic, etc.) can understand the construct and adapt the application to be implemented within their respective facility. In at least one embodiment, an application for image reconstruction may be selected to be included in deployment pipeline 3210, but the data type generated by the imaging device may differ from the data type used within the application. In at least one embodiment, a DICOM adapter 3202B (and / or a DICOM reader) or an adapter or reader of another data type (e.g., RIS, CIS, REST compliant, RPC, raw, etc.) may be used within deployment pipeline 3210 to convert data into a form usable by applications within deployment system 3106. In at least one embodiment, access to DICOM, RIS, CIS, REST-compliant, RPC, raw, and / or other data type libraries can be accumulated and preprocessed, including decoding data, extracting data, and / or performing any convolution, color correction, sharpening, gamma, and / or other enhancements on the data. In at least one embodiment, DICOM, RIS, CIS, REST-compliant, RPC, and / or raw data can be unordered, and pre-passing can be performed to organize or sort the collected data. In at least one embodiment, since various applications can share common image operations, in some embodiments, data augmentation libraries (e.g., as one of services 3120) can be used to accelerate these operations. In at least one embodiment, to avoid bottlenecks in conventional processing methods that rely on CPU processing, a parallel computing platform 3230 can be used for GPU acceleration of these processing tasks.

[0370] In at least one embodiment, the image reconstruction application may include processing tasks that include using a machine learning model. In at least one embodiment, a user may wish to use their own machine learning model or select a machine learning model from a model registry 3124. In at least one embodiment, a user may implement their own machine learning model or select a machine learning model to include in the application performing the processing task. In at least one embodiment, the application may be optional and customizable, and by defining the application's construction, the deployment and implementation of the application for a particular user is presented as a more s...

Claims

1. A processor, comprising: One or more circuits are used for: The two or more first images are compared with the one or more second images by determining the distance between the positions of two or more first images generated by one or more neural networks and at least one of one or more second images in a multidimensional image space, wherein the two or more first images are generated using the one or more neural networks based at least in part on one or more noise values ​​input to the one or more neural networks; as well as The neural networks in one or more neural networks are updated at least in part based on the shortest distance among the determined distances.

2. The processor of claim 1, wherein the one or more neural networks comprise a denoising diffusion probability model (DDPM) for generating the two or more first images.

3. The processor of claim 2, wherein the one or more circuits are further configured to: train the DDPM at least in part by performing a sequence of diffusion steps to add a corresponding amount of noise to the one or more second images, and performing a sequence of reverse diffusion steps to attempt to remove the corresponding amount of noise.

4. The processor of claim 3, wherein the one or more circuits are further configured to utilize the one or more noise values ​​as input to generate the two or more first images for each corresponding backdiffusion step, wherein the one or more noise values ​​are sampled from a probability distribution.

5. The processor of claim 1, wherein the shortest distance among the determined distances is used as a loss value for adjusting the network parameters of the denoising diffusion probability model DDPM of the neural network.

6. A system comprising: One or more processors are used for: One or more neural networks are used to compare the two or more first images with the one or more second images by determining the distance between the positions of two or more first images generated by the one or more neural networks and at least one of one or more second images in a multidimensional image space, wherein the two or more first images are generated using the one or more neural networks based at least in part on one or more noise values ​​input to the one or more neural networks; The neural networks in one or more neural networks are updated at least in part based on the shortest distance among the determined distances.

7. The system of claim 6, wherein the one or more neural networks comprise a denoising diffusion probability model (DDPM) for generating the two or more first images.

8. The system of claim 7, wherein the one or more processors are further configured to: train the DDPM at least in part by performing a sequence of diffusion steps to add a corresponding amount of noise to the one or more second images, and performing a sequence of reverse diffusion steps to attempt to remove the corresponding amount of noise.

9. The system of claim 8, wherein the one or more processors are further configured to use the one or more noise values ​​as input to generate the two or more first images for each corresponding backdiffusion step, wherein the one or more noise values ​​are sampled from a probability distribution.

10. The system of claim 6, wherein the shortest distance among the determined distances is used as a loss value for adjusting the network parameters of the denoising diffusion probability model DDPM of the neural network.

11. A method comprising: One or more neural networks are used to compare the two or more first images with the one or more second images by determining the distance between the positions of two or more first images generated by the one or more neural networks and at least one of one or more second images in a multidimensional image space, wherein the two or more first images are generated using the one or more neural networks based at least in part on one or more noise values ​​input to the one or more neural networks; as well as The neural networks in one or more neural networks are updated at least in part based on the shortest distance among the determined distances.

12. The method of claim 11, wherein the one or more neural networks comprise a denoising diffusion probability model (DDPM) for generating the two or more first images.

13. The method of claim 12, further comprising: The DDPM is trained at least in part by performing a sequence of diffusion steps to add a corresponding amount of noise to one or more second images, and a sequence of reverse diffusion steps to attempt to remove that corresponding amount of noise.

14. The method of claim 13, further comprising: The one or more noise values ​​are used as input to generate the two or more first images for each corresponding backdiffusion step, wherein the one or more noise values ​​are sampled from a probability distribution.

15. The method of claim 11, further comprising: The shortest distance among the determined distances is selected as the loss value used to adjust the network parameters of the denoising diffusion probability model DDPM of the neural network.

16. A non-transitory machine-readable medium having a set of instructions stored thereon, the set of instructions, if executed by one or more processors, causes the one or more processors to at least: One or more neural networks are used to compare the two or more first images with the one or more second images by determining the distance between the positions of two or more first images generated by the one or more neural networks and at least one of one or more second images in a multidimensional image space, wherein the two or more first images are generated using the one or more neural networks based at least in part on one or more noise values ​​input to the one or more neural networks; The neural networks in one or more neural networks are updated at least in part based on the shortest distance among the determined distances.

17. The non-transitory machine-readable medium of claim 16, wherein the one or more neural networks comprise a denoising diffusion probability model (DDPM) for generating the two or more first images.

18. The non-transitory machine-readable medium of claim 17, wherein if the instructions are executed, they further cause the one or more processors to: The DDPM is trained at least in part by performing a sequence of diffusion steps to add a corresponding amount of noise to one or more second images, and a sequence of reverse diffusion steps to attempt to remove that corresponding amount of noise.

19. The non-transitory machine-readable medium of claim 18, wherein if the instructions are executed, they further cause the one or more processors to: The one or more noise values ​​are used as input to generate the two or more first images for each corresponding backdiffusion step, wherein the one or more noise values ​​are sampled from a probability distribution.

20. The non-transitory machine-readable medium of claim 16, wherein if the instructions are executed, they further cause the one or more processors to: The shortest distance among the determined distances is selected as the loss value used to adjust the network parameters of the denoising diffusion probability model DDPM of the neural network.

21. A system comprising: One or more processors are used for: One or more neural networks are used to compare the two or more first images with the one or more second images by determining the distance between the positions of two or more first images generated by the one or more neural networks and at least one of one or more second images in a multidimensional image space, wherein the two or more first images are generated using the one or more neural networks based at least in part on one or more noise values ​​input to the one or more neural networks; The neural networks in one or more neural networks are updated at least in part based on the shortest distance among the determined distances; as well as A memory for storing network parameters of the one or more neural networks.

22. The system of claim 21, wherein the one or more neural networks comprise a denoising diffusion probability model (DDPM) for generating the two or more first images.

23. The system of claim 22, wherein the one or more processors are further configured to: train the DDPM at least in part by performing a sequence of diffusion steps to add a corresponding amount of noise to the images of the one or more second images, and a sequence of reverse diffusion steps to attempt to remove the corresponding amount of noise.

24. The system of claim 23, wherein the one or more processors are further configured to use the one or more noise values ​​as input to generate the two or more first images for each corresponding backdiffusion step, wherein the one or more noise values ​​are sampled from a probability distribution.

25. The system of claim 21, wherein the shortest distance among the determined distances is used as a loss value for adjusting the network parameters of the denoising diffusion probability model DDPM of the neural network.

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