Memory devices and their manufacturing methods

Abstract

Embodiments of this application provide a memory device and a method of manufacturing the same. The memory device includes a memory array formed on the front side of a substrate. The memory array is accessible via a plurality of bit lines. The memory device includes a switching transistor formed on the front side of the substrate. The switching transistor is operatively coupled to the plurality of bit lines. The memory device includes a first capacitor formed on the back side of the substrate. The first capacitor is configured to reduce a voltage level present on at least one of the plurality of bit lines in response to the switching transistor being turned off.

Description

Technical Field

[0001] Embodiments of this application relate to memory devices and methods of manufacturing the same. Background Technology

[0002] Static random access memory (SRAM) is a type of semiconductor memory used in computing applications that require high-speed data access. For example, cache memory applications use SRAM to store frequently accessed data, such as data accessed by the central processing unit.

[0003] The cell structure and architecture of SRAM enable high-speed data access. An SRAM cell includes a bistable flip-flop structure, which comprises, for example, four to eight transistors. The SRAM architecture may include one or more memory cell arrays and supporting circuitry. Each SRAM array is arranged in rows and columns, respectively called "word lines" and "bit lines." The supporting circuitry includes address and driver circuitry to access each SRAM cell via word lines and bit lines for various SRAM operations. Summary of the Invention

[0004] According to one aspect of an embodiment of this application, a memory device is provided, comprising: a memory cell; a bit line coupled to the memory cell; and a voltage generator coupled to the bit line and configured to provide a negative voltage to the bit line; wherein the voltage generator comprises: a transistor; and a first capacitor having a first terminal and a second terminal respectively electrically coupled to the drain and gate of the transistor; and wherein the drain and gate of the transistor are formed on a first side of a substrate, and the first terminal and the second terminal of the first capacitor are formed on a second side of the substrate opposite to the first side.

[0005] According to another aspect of an embodiment of this application, a memory device is provided, comprising: a memory array formed on the front side of a substrate, wherein the memory array is accessible via a plurality of bit lines; a switching transistor formed on the front side of the substrate, wherein the switching transistor is operatively coupled to the plurality of bit lines; and a first capacitor formed on the back side of the substrate, wherein the first capacitor is configured to reduce a voltage level present on at least one of the plurality of bit lines in response to the switching transistor being turned off.

[0006] According to another aspect of the embodiments of this application, a method of manufacturing a memory device is provided, comprising: forming a plurality of memory transistors configured as a memory array on a front side of a substrate; forming a switching transistor on a front side of the substrate; forming a plurality of bit lines operatively coupled to the memory array on a front side of the substrate, wherein the switching transistor is operatively coupled to the plurality of bit lines; and forming a first capacitor on a back side of the substrate, the first capacitor being configured to reduce a voltage level present on at least one of the plurality of bit lines to a negative value. Attached Figure Description

[0007] The various aspects of the invention can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard industrial practice, the various components are not drawn to scale and are for illustrative purposes only. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0008] Figure 1 A schematic diagram of a memory device including write auxiliary circuitry according to some embodiments is shown.

[0009] Figure 2 Illustrations are shown according to some embodiments Figure 1 A schematic diagram of a memory cell in a memory device.

[0010] Figure 3 Illustrations are shown according to some embodiments Figure 1 A schematic diagram of the write auxiliary circuit for the memory device.

[0011] Figure 4 Illustrations are shown according to some embodiments Figure 3 A schematic diagram of the boost capacitor in the write auxiliary circuit.

[0012] Figure 5 It is shown that, according to some embodiments, it may be possible Figure 4 A cross-sectional view of an example semiconductor device representing a portion of an implementation of a memory device.

[0013] Figure 6 The method for forming according to some embodiments is shown. Figure 4 Example layout of boost capacitor.

[0014] Figure 7 It is according to some embodiments for manufacturing semiconductor devices (e.g., Figure 1 Example flowchart of the method for (memory device).

[0015] Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13A , Figure 13B , Figure 14A , Figure 14B , Figure 15A , Figure 15B , Figure 16A , Figure 16B , Figure 17A , Figure 17B , Figure 18A and Figure 18B The following are illustrations based on some embodiments of the passage. Figure 7 Cross-sectional views of example semiconductor devices at various manufacturing stages produced using the method described. Detailed Implementation

[0016] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific embodiments or examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and not intended to be limiting. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0017] Furthermore, for ease of description, this document may use spacing terms such as “below,” “under,” “lower,” “above,” “upper,” etc., to describe the relationship between one element or component and another, as shown in the figures. In addition to the orientations shown in the figures, spacing terms are intended to include different orientations of the device during use or operation. The device may be positioned in other ways (rotated 90 degrees or in other orientations), and the spacing descriptors used herein may be interpreted accordingly.

[0018] The following disclosure describes various aspects of memory devices, such as static random access memory (SRAM) devices. Specifically, this disclosure describes different embodiments relating to SRAM memory write operations. For ease of explanation, certain SRAM circuit elements and control logic are disclosed to facilitate the description of the different embodiments. It should be understood that SRAM devices also include other circuit elements and control logic. These other circuit elements and control logic are within the spirit and scope of this disclosure.

[0019] A typical SRAM device consists of an array of individual SRAM cells. Each SRAM cell is capable of storing a binary voltage value that represents a logic data bit (e.g., "0" or "1"). An existing configuration of an SRAM cell includes cross-coupled pairs of devices, such as inverters. Utilizing CMOS (Complementary Metal-Oxide-Semiconductor) technology, the inverter also includes a pull-up PFET (p-channel) transistor connected to a complementary pull-down NFET (n-channel) transistor. Inverters connected in a cross-coupled configuration act as latches, storing data bits in the latches whenever the memory array is powered. In a conventional six-transistor (6T) cell, access transistors or transmit gate pairs (when activated by word lines) selectively couple the inverter to the complementary bit line pairs. Other SRAM cell designs may include different numbers of transistors, such as 4T, 8T (4 transistors, 8 transistors), etc.

[0020] The design of SRAM cells traditionally involves trade-offs between read and write operations to maintain cell stability, read performance, and write performance. The transistors constituting a cross-coupled latch must be weak enough to be overdriven during write operations, while also being strong enough to hold their data values ​​while driving the bit lines during read operations. Connecting the cross-coupled cell node to the access transistors on the true bit line and complementary bit line affects cell stability and performance. In a single-port SRAM cell, typically a single pair of access transistors is used for both read and write access to the cell. The gate is driven to a digital value to switch the transistor between on and off states. Optimization of write operations will drive the on-resistance (R0) of the device. on The reduction in R is a concern. On the other hand, optimization of the access transistors used for read operations, aimed at isolating cells from bit line capacitance and preventing cell interference, has driven the reduction in R. on Increase.

[0021] A recently proposed method to improve the write performance of SRAM devices is to use a so-called "negative boost" to discharge the bit line to a voltage level below the nominal low supply rail value (e.g., ground). In other words, when written to, the corresponding bit line of the SRAM cell may present a negative voltage. This bit line is typically discharged to a negative voltage through a capacitor (or sometimes called a boost capacitor). In this way, the transfer gate of the SRAM cell coupled to the discharged bit line sees an increase in both the gate-to-source voltage and the drain-to-source voltage. This negative boost can allow for an increase of 3σ or more margin (in terms of anticipated device failures) compared to more conventional write techniques where the bit line simply discharges to the nominal low voltage rail value (e.g., ground).

[0022] However, despite the benefits of negative boost, existing SRAM devices with negative boost may still be less than satisfactory in many aspects. For example, boost capacitors are typically formed as metal-insulator-metal (MIM) or metal-oxide-metal (MOM) structures. This capacitor structure is usually disposed in one or more metallization layers on the front side of a substrate, where multiple active devices (e.g., corresponding transistors for SRAM cells) are formed. As transistor sizes continue to shrink in advanced technology nodes, the size of the boost capacitor may be forced to shrink accordingly, which could adversely reduce the capacitance value. On the other hand, maintaining the size of the boost capacitor significantly consumes valuable space in the front metallization layer, which could be used to form other routing signals.

[0023] This disclosure provides various embodiments of an SRAM device having a negative voltage generator comprising one or more components formed on the back side of a substrate, opposite to the front side of the substrate forming the respective SRAM cell. In various embodiments, as disclosed herein, the negative voltage generator can generate a negative voltage to a plurality of bit lines coupled to the SRAM cell during writing to those SRAM cells. The negative voltage generator may include at least one boost capacitor having at least a majority portion formed on the back side of the substrate. For example, the boost capacitor may be composed of a plurality of sub-capacitors connected in parallel. The respective (positive and negative) terminals of one or more sub-capacitors are formed as conductors on the back side of the substrate. Forming at least a portion of the boost capacitor on the back side can provide various advantages for the entire SRAM device. For example, using the back-side conductors as the boost capacitor can save significant front-side space that would otherwise be used for other purposes or applications (e.g., wires). In another example, the back-side conductors may be formed to have a greater thickness than the front-side conductors, which substantially increases the surface area of ​​the conductor plate of the boost capacitor. Therefore, within the same layout area, the boost capacitor disclosed herein can have a higher capacitance value (e.g., about 16 to 25%) compared to a conventional boost capacitor formed only on the front side.

[0024] Figure 1 A schematic diagram of an example static random access memory (SRAM) device / circuit 100 with write assist circuitry 110, including a boost capacitor, is shown according to various embodiments of the present disclosure. The SRAM device 100 includes a row decoder 120, a word line driver 130, a column decoder 140, a column multiplexer (MUX) 150, write driver circuitry 160, and an SRAM array 180.

[0025] SRAM array 180 includes a plurality of memory cells 190. The memory cells 190 may be arranged in one or more arrays within SRAM device 100. Figure 1In the example, a single SRAM array 180 is shown to simplify the description of the disclosed embodiments. The SRAM array 180 has an "M+1" number of rows and an "N+1" number of columns. For example, the memory cells 190 of the SRAM array 180 are arranged in rows, from row 0 to row 190. M And column 1700 to 170 N Therefore, the symbol "190" 00 "Refers to a memory cell 190 located in row 0 and column 1700. Similarly, the symbol "190" MN "Refers to the row" M and column 170 N Another memory unit 190 in the memory.

[0026] Each SRAM cell in the SRAM array 180 is accessed using a memory address (e.g., for memory read and memory write operations). Based on the memory address portion, access is made via word line drivers 130 (e.g., multiple word line drivers 1300…130). M The row decoder 120 selects the row of the memory cell (e.g., row 0 to row 120). M One of them) is used for access. Furthermore, according to some embodiments of this disclosure, based on the memory address, the column decoder 140 selects the column 1700-170 of the memory cell to be accessed via the write auxiliary circuit 110 and the column MUX 150. N Based on another part of the memory address, column decoder 140 outputs the corresponding YSEL signal to activate the corresponding pair of y-select transistors 152 and 154 in MUX 150 to access the corresponding column. Each column includes a bit line pair BL and BLB. The symbol “BL” refers to a bit line, and the symbol “BLB” refers to the complement of “BL”. For example, to access a memory cell in column 1700, column decoder 140 outputs the YSEL[0] signal to activate the transistor pair 152[0] and 154[0] corresponding to column 1700, thereby allowing access to the corresponding BL[0] and BLB[0] pair. In another example, to access column 170 N In the memory cell, column decoder 140 outputs the YSEL[N] signal to activate the corresponding column 170. N The transistor pairs 152[N] and 154[N] allow access to the corresponding BL[N] and BLB[N] pairs. In some embodiments, the write driver circuit 160 generates columns 1700 to 170 for access. N The voltage of the bit lines BL and BLB in one of them. Thus, the intersection of the accessed row and accessed column of the memory cell results in access to a single memory cell 190.

[0027] The memory cell 190 can have any of various circuit topologies. For example, the memory cell 190 can have a "6T (6 transistors)" circuit topology. Figure 2 An exemplary 6T circuit topology for memory cell 190 is shown. The 6T circuit topology includes n-channel metal-oxide-semiconductor (NMOS) transmission devices 220 and 230, NMOS pull-down devices 240 and 250, and p-channel metal-oxide-semiconductor (PMOS) pull-up devices 260 and 270. Voltage from word line driver 130 controls NMOS devices 220 and 230 to deliver voltages from the BL and BLB bit line pairs to a bistable flip-flop structure formed by NMOS devices 240 and 250 and PMOS devices 260 and 270. The bit line pair voltages of BL and BLB can be used during memory write operations. For example, if BL is "1" or a logic high value (e.g., the power supply voltage VDD, such as 0.4V, 0.6V, 0.7V, 1.0V, 1.2V, 1.8V, 2.4V, 3.3V, 5V, or any combination thereof) and BLB is "0" or a logic low value (e.g., ground or 0V), the voltage applied to the gate terminals of the NMOS transmission devices 220 and 230 via word line driver 130 can be at a sufficient voltage level to transmit the logic high value of BL and the logic low value of BLB to the bistable flip-flop structure. As a result, these logic values ​​are written (or programmed) into the bistable flip-flop structure.

[0028] Figure 3 A schematic diagram of an example of a write assist circuit 110 according to various embodiments of the present disclosure is shown. The write assist circuit 110 is configured to provide a reference voltage 118 to the write driver 160 as a reference voltage. According to some embodiments of the present disclosure, the reference voltage 118 may be ground (e.g., 0V), a negative voltage (e.g., -100mV, -200mV, or -300mV), or a combination thereof. The write assist circuit 110 includes one or more boost capacitors configured to provide such a negative reference voltage 118, which will be discussed below.

[0029] In some embodiments, the write driver circuit 160 includes level shifter devices 162 and 164, each receiving a reference voltage 118. When level shifter device 162 or 164 receives a logic low input, the corresponding level shifter device outputs a logic high value (e.g., the power supply voltage VDD of an inverter logic device such as 0.4V, 0.6V, 0.7V, 1.0V, 1.2V, 1.8V, 2.4V, 3.3V, 5V, or any combination thereof). Conversely, when level shifter device 162 or 164 receives a logic high input, the corresponding level shifter device outputs the reference voltage 118. Figure 3In this process, level shifter device 162 receives a logic high value and level shifter device 164 receives a logic low value. Therefore, level shifter device 162 outputs reference voltage 118 to the BL of the accessed column (e.g., asserted by the YSEL signal), and level shifter device 164 outputs a logic high value to the BLB of the same accessed column.

[0030] Write assist circuitry 110 is coupled to write driver circuitry 160 at node X. Write assist circuitry 110 includes an NMOS switching transistor 306 coupled between ground and node X and a boost capacitor 304 directly coupled between the drain (node ​​X) and gate (node ​​Y) terminals of transistor 306. In some embodiments, switching transistor 306 and boost capacitor 304 may provide a negative voltage to the coupled bit line. Switching transistor 306 and boost capacitor 304 are sometimes collectively referred to as a (negative) voltage generator. A bit line boost enable control signal 307 is provided at node Y by logic circuitry 302, which is responsive to write enable signal 309. Logic circuitry 302 may include a plurality of delay elements connected in series with one or more inverters, providing a delay to write enable signal 309. Write enable signal 309 can therefore be delayed and inverted to provide boost signal 307 at node Y. Before the write enable signal 309 goes high (at the start of a write operation / cycle), the boost signal 307 is high, which turns on transistor 306 and charges the boost capacitor 304. While the boost signal 307 is high, node X is also grounded through transistor 306. After a delay, the boost signal 307 goes low, which turns off transistor 306 and simultaneously causes the boost capacitor 304 to discharge, driving node X (i.e., reference voltage 118) from ground (low) to a negative value. This negative reference voltage 118 is then provided to the bit line (BL / BLB) (as described above) through the write driver circuit 160, which provides a boost for the write operation performed by SRAM cell 190, which is coupled to the bit line (BL / BLB).

[0031] Figure 4 A schematic diagram of a boost capacitor 304 connected between nodes X and Y according to various embodiments is shown. Specifically, the boost capacitor 304 has a first terminal connected to node X and a second terminal connected to node Y. According to various embodiments, the boost capacitor 304 has a plurality of sub-capacitors (or capacitors) connected in parallel. Each sub-capacitor has its own terminal pair sandwiched between dielectric material. In some embodiments, the capacitance value of the boost capacitor may be proportional to the number of sub-capacitors connected in parallel.

[0032] For example in Figure 4In this embodiment, the boost capacitor 304 has sub-capacitors C1, C2, C3, and C4 connected in parallel, which are at least partially implemented as a plurality of first metal lines 402 and 404 and a plurality of second metal lines 406, 408, and 410. The first metal lines 402-404 are connected to node X, which serves as a first terminal of the boost capacitor 304, and the second metal lines 406-410 are connected to node Y, which serves as a second terminal of the boost capacitor 304. Specifically, sub-capacitor C1 has a first metal line 402 and a second metal line 406 as its corresponding terminal (or sub-terminal). Sub-capacitor C2 has a first metal line 402 and a second metal line 408 as its corresponding terminal (or sub-terminal); sub-capacitor C3 has a first metal line 404 and a second metal line 408 as its corresponding terminal (or sub-terminal); and sub-capacitor C4 has a first metal line 404 and a second metal line 410 as its corresponding terminal (or sub-terminal). Although the boost capacitor 304 is formed by two first metal lines and three second metal lines (e.g., as four parallel sub-capacitors), it should be understood that the boost capacitor 304 can be formed by any number of first metal lines and any number of second metal lines (as any number of parallel sub-capacitors) while remaining within the scope of this disclosure.

[0033] Figure 5 A cross-sectional view of a semiconductor device 500 that can be implemented as at least a portion of an SRAM device 100 (e.g., write auxiliary circuitry 110) is shown. Figure 5 The transistors are cut along the longitudinal direction of the channels of the plurality of transistors in the semiconductor device 500, and each transistor is implemented as a gate-all-around field-effect transistor (GAA FET) device. However, it should be understood that the transistors of the semiconductor device 500 can be implemented as any of a variety of other transistor structures (e.g., FinFET, planar FET, or other nanostructure transistors, etc.) within the scope of this disclosure. Furthermore, Figure 5 The above-described components (e.g., boost capacitor 304, switching transistor 306) have been simplified to show their relative spatial arrangement; therefore, it should be understood that one or more components / structures of the completed GAA FET device may not be as shown. Figure 5 As shown.

[0034] On the front side of the substrate (surrounded by dashed lines, as it was removed when the back-side interconnect structure was formed), the semiconductor device 500 includes an active region 502 having portions formed as channels 504 and portions formed as source / drain structures 506. In various embodiments, each channel 504 includes one or more nanostructures (e.g., nanosheets, nanowires) perpendicularly spaced from each other. The semiconductor device 500 includes a plurality of (e.g., metal) gate structures 508, each gate structure 508 surrounding the nanostructures corresponding to the channel 504.

[0035] Above the source / drain structure 506, the semiconductor device 500 includes a plurality of source / drain interconnect structures (sometimes referred to as MDs) 510, some of which are coupled to gate via structures (sometimes referred to as VDs) 512 formed thereon. Above the gate structure 508, the semiconductor device 500 includes a plurality of gate via structures (sometimes referred to as VGs) 514.

[0036] VD 512 can couple MD 510 to a first metal line (sometimes referred to as M0 track) 516 in a first (e.g., bottommost) front metallization layer. VG 514 can couple gate structure 508 to a second M0 track 518. Above M0 tracks 516 and 518 (and various other metal lines in the bottommost front metallization layer), semiconductor device 500 includes a plurality of via structures (sometimes referred to as V0) 520 and 522 to couple M0 tracks 516 and 518 to corresponding metal lines (sometimes referred to as M1 tracks) 524 and 526 in the next front metallization layer further away from the substrate. Furthermore, above M1 tracks 524 and 526 (and various other metal lines in the same front-side metallization layer), semiconductor device 500 includes a plurality of via structures (sometimes referred to as V1) 528 and 530 to couple M1 tracks 524 and 526 to corresponding metal lines (sometimes referred to as M2 tracks) 532 and 534 in the next front-side metallization layer further away from the substrate. Although three front-side metallization layers are shown, it should be understood that semiconductor device 500 may include any number of front-side metallization layers. According to various embodiments, the metal tracks formed across such front-side metallization layers can be configured to electrically couple different components of SRAM device 100 (in order to route signals and / or deliver power).

[0037] On the back side of the substrate, the semiconductor device 500 includes a plurality of back-side via structures (sometimes referred to as BV) 542 and 544, which can couple the source / drain structure 506 and the gate structure 508 to a plurality of metal lines (sometimes referred to as BMO tracks) 546 and 548 in a first (e.g., the bottommost) back-side metallization layer, respectively. Furthermore, above the BMO tracks 546 and 548, the semiconductor device 500 includes a plurality of via structures (sometimes referred to as BVO) 550 and 552, which can couple the BMO tracks 546 and 548 to a plurality of metal lines (sometimes referred to as BMO tracks) 554 and 556 in a next back-side metallization layer further away from the substrate, respectively. Furthermore, above the BM1 orbitals 554 and 556, the semiconductor device 500 includes multiple via structures (sometimes referred to as BV1) 558 and 560, which can couple the BM1 orbitals 554 and 556 to multiple metal lines (sometimes referred to as BM2 orbitals) 562 and 564 of the next back-side metallization layer further away from the substrate.

[0038] According to various embodiments of this disclosure, at least one of the channels 504, together with a corresponding one of the gate structures 508 surrounding the channel and a corresponding source / drain structure pair 506, can form a switching transistor 306 of the write auxiliary circuit 110. Furthermore, at least one pair of back-side metal lines can form at least a portion of the boost capacitor 304 of the write auxiliary circuit 110. For example, in Figure 5 In this configuration, a BMO rail 546 coupled to one of the source / drain structures 506 of the switching transistor 306 can be used as the first terminal of a sub-capacitor (or capacitor) C1 of the boost capacitor 304, and a BMO rail 548 coupled to the other source / drain structure 506 of the switching transistor 306 can be used as the second terminal of a sub-capacitor (or capacitor) C1 of the boost capacitor 304. (See again...) Figure 4 A schematic diagram, Figure 5 BM0 orbitals 546 and 548 can respectively correspond to Figure 4 Metal wires 402 and 406.

[0039] It should be understood that the other sub-capacitors of the boost capacitor 304 can be formed from other BMO tracks (i.e., other metal lines in the bottommost back metallization layer). For example, Figure 6 A portion of a layout 600 is shown, comprising multiple patterns 602, 604, 606, 608, and 610 configured to form corresponding BMO tracks constituting a boost capacitor. As shown, metal lines (e.g., embodied as BMO tracks) 402 and 404 are configured to form, respectively. Figure 4 Patterns 604 and 608 can align their ends with each other. Hereinafter, patterns 604 and 608 are referred to as BMO tracks 604 and 608, respectively. Metal wires (e.g., embodied as BMO tracks) 406, 408, and 410 are configured to form metal wires (e.g., embodied as BMO tracks), respectively. Figure 4 Patterns 602, 606, and 610 can align their ends with each other. In the following text, patterns 602, 606, and 610 are referred to as BM0 tracks 602, 606, and 610, respectively. Therefore, the sub-capacitors C1, C2, C3, and C4 of the boost capacitor 304 can be formed by combinations of BM0 tracks 602 and 604, BM0 tracks 604 and 606, BM0 tracks 606 and 608, and BM0 tracks 608 and 610, respectively.

[0040] Furthermore, patterns 604 and 608 are laterally offset from patterns 602, 606, and 610 by a certain offset amount, allowing BM0 rails 604 and 608 to be electrically coupled to each other through one or more interconnect structures (e.g., pattern 620 configured to form MD / M1 rail 620), and BM0 rails 602, 606, and 610 to be electrically coupled to each other through one or more interconnect structures (e.g., pattern 630 configured to form MD / M1 rail 630). MD / M1 rail 620 is operatively connected to node X (e.g., the drain of switching transistor 306), and MD / M1 rail 630 is operatively connected to node Y (e.g., the gate of switching transistor 306).

[0041] It should also be understood that the pattern of layout 600 is not limited to forming the BM0 rails constituting the boost capacitor 304. Patterns 602 to 610 can also be used to form many other metal lines on the front and / or back sides. For example, patterns 602 to 610 can be used to form at least a portion of a plurality of BM2 rails constituting the boost capacitor 304 (e.g., Figure 5 (562, 564). In another example, in addition to the BM0 and / or BM2 tracks constituting the boost capacitor 304, patterns 602 to 610 may be used to form a plurality of M0 tracks constituting at least a portion of the boost capacitor 304 (e.g., ). Figure 5 516, 518) and / or M2 orbitals (e.g., Figure 5 (532, 534).

[0042] Refer again Figure 5 M0 tracks 516 and 518 can form one of a plurality of parallel-connected sub-capacitors, C1', to further increase the capacitance value of boost capacitor 304. M0 tracks 516 and 518, formed based on patterns 602 and 604 of layout 600 respectively, can be used as terminals of sub-capacitor C1'. Furthermore, other M0 tracks formed based on patterns 604 and 606 of layout 600 respectively can be used as terminals of another sub-capacitor C2'; other M0 tracks formed based on patterns 606 and 608 of layout 600 respectively can be used as terminals of yet another sub-capacitor C3'; and other M0 tracks formed based on patterns 608 and 610 of layout 600 respectively can be used as terminals of yet another sub-capacitor C4'.

[0043] Similarly, M2 tracks 532 and 534 can form one of a plurality of parallel-connected sub-capacitors, C1', to further increase the capacitance value of boost capacitor 304. M2 tracks 532 and 534, formed based on patterns 602 and 604 of layout 600 respectively, can be used as terminals of sub-capacitor C1'. Furthermore, other M2 tracks formed based on patterns 604 and 606 of layout 600 respectively can be used as terminals of another sub-capacitor C2'; other M2 tracks formed based on patterns 606 and 608 of layout 600 respectively can be used as terminals of yet another sub-capacitor C3'; and other M2 tracks formed based on patterns 608 and 610 of layout 600 respectively can be used as terminals of yet another sub-capacitor C4'.

[0044] According to various embodiments of this disclosure, the thickness of the back-side metal lines (e.g., BM0 track, BM2 track) is significantly greater than the thickness of the front-side metal lines (e.g., M0 track, M2 track). For example, utilizing a certain technology node, the back-side metal lines can have a thickness range of approximately 40 nanometers (nm) to approximately 400 nm, which is typically greater than the thickness range of the front-side metal lines. With such a greater thickness, the contact area of ​​each sub-capacitor of the boost capacitor 304 can be increased proportionally. The capacitance value of each sub-capacitor can be increased accordingly (e.g., approximately 16% to approximately 25%), which can advantageously reduce the discharge time of the boost capacitor 304. Therefore, the reference voltage 118 can be pulled to a negative voltage more quickly, allowing for faster and more efficient read operations of the SRAM device 100.

[0045] Figure 7 A flowchart depicts an example method 700 for forming or manufacturing a semiconductor device (e.g., at least a portion of an SRAM device 100) according to some embodiments. It should be understood that... Figure 7 Additional operations are performed before, during, and / or after the method described in section 700. For example... Figure 7 As shown, the operation of method 700 can be compared with... Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13A , Figure 13B , Figure 14A , Figure 14B , Figure 15A , Figure 15B , Figure 16A , Figure 16B , Figure 17A , Figure 17B , Figure 18A and Figure 18B(This will be discussed in further detail below) Cross-sectional views of the example semiconductor device 800 at each of the various manufacturing stages are shown. In some embodiments, method 700 can be used to form a semiconductor device according to various layout designs disclosed herein.

[0046] In summary, method 700 begins with operation 702, which involves providing a substrate. Next, method 700 may proceed to operation 704, which involves forming a buried oxide layer. Optionally, the buried oxide layer may be formed later (see operation 714). Then, method 700 proceeds to operation 706, which involves forming a channel layer and a sacrificial layer, the channel layer and the sacrificial layer being stacked alternately on top of each other. Method 700 proceeds to operation 708, which involves defining a semiconductor fin. Method 700 proceeds to operation 710, which involves forming a dummy gate structure over the semiconductor fin. Method 700 proceeds to operation 712, which involves forming source and / or drain trenches. If the buried oxide layer has not yet been formed in operation 704, method 700 may proceed to operation 714, which involves forming the buried oxide layer. Method 700 proceeds to operation 718, which involves replacing the dummy gate structure with a corresponding active structure. Method 700 proceeds to operation 720, which involves forming a front-side interconnect structure. Method 700 continues to operation 722, which involves thinning the substrate until the bottom oxide layer is exposed. Method 700 proceeds to operation 724, which forms the back-side interconnect structure.

[0047] As mentioned above, Figures 8-18B Cross-sectional views are shown during various manufacturing stages of an example semiconductor device 800 manufactured by method 700 according to some embodiments. The semiconductor device 800 may be an implementation of an SRAM device 100 including a plurality of transistors (e.g., 306) and a plurality of boost capacitors (e.g., 304). In various embodiments, some of the transistors may be implemented as a GAA FET structure. For example, Figures 8-11 It is a cross-sectional view of a semiconductor device 800 taken along the longitudinal (or vertical) direction of one or more pseudo-gate structures / active gate structures of the transistor at various manufacturing stages. Figures 12-18B This is a cross-sectional view of a semiconductor device 800 taken along the longitudinal (or vertical) direction of one or more channels of the transistor at various manufacturing stages. Although Figures 8-18B A semiconductor device 800 including a GAA FET structure is shown; however, it should be understood that the semiconductor device 800 may include any of a variety of other transistor structures and many other devices such as inductors, fuses, capacitors, coils, etc., for clarity of illustration. Figures 8-18B Not displayed.

[0048] For the sake of brevity, Figures 8-12 and from Figures 13A to 18AThe numbers ending with "A" indicate the various manufacturing stages of semiconductor device 800 during operation 704 of method 700. If operation 704 is not performed, operation 714 is performed to form a semiconductor device 800 as described in the previous section. Figure 13B The buried oxide layer is shown. Therefore, from Figures 13B to 18B The accompanying diagrams, ending in "B", illustrate the semiconductor device 800 at various manufacturing stages when operation 714 is performed.

[0049] Corresponding to operation 702, Figure 8 This is a cross-sectional view of a semiconductor device 800, including a semiconductor substrate 802, at one of the various manufacturing stages. Figure 8 It is cut along the longitudinal direction of one or more active gate structures / pseudo gate structures of the semiconductor device 800.

[0050] Substrate 802 may be a semiconductor substrate (such as a bulk semiconductor), which may be doped (e.g., with p-type or n-type dopants) or undoped. Substrate 802 may be a wafer, such as a silicon wafer. Other substrates may also be used, such as multilayer substrates or gradient substrates. In some embodiments, the semiconductor material of substrate 802 may include: silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and / or GaInAsP; or combinations thereof.

[0051] Corresponding to operation 704, Figure 9 This is a cross-sectional view of a semiconductor device 800 including a buried oxide layer 902 at one of the various manufacturing stages. Figure 9 It is cut along the longitudinal direction of one or more active gate structures / dummy gate structures of the semiconductor device 800. The semiconductor device 800 may also include a semiconductor material layer 904 formed on the buried oxide layer 902. This combination of substrate 802, buried oxide layer 902 and semiconductor material 904 is sometimes collectively referred to as a semiconductor-on-insulator (SOI) substrate.

[0052] Corresponding to operation 706, Figure 10 This is a cross-sectional view of a semiconductor device 800 comprising multiple sacrificial layers 1002 and multiple channel layers 1004 at one of the various manufacturing stages. Figure 10 It is cut along the longitudinal direction of one or more active gate structures / pseudo gate structures of the semiconductor device 800.

[0053] Multiple sacrificial layers 1002 and multiple channel layers 1004 are alternately disposed on top of each other to form a stack. For example, one of the channel layers 1004 is disposed above one of the sacrificial layers 1002, then another of the sacrificial layers 1002 is disposed above the channel layer 1004, and so on. The stack can include any number of alternately disposed sacrificial layers and channel layers 1002 and 1004. For example in Figure 10 In the embodiment shown (and the accompanying figures), the stack may include four sacrificial layers 1002, wherein four channel layers 1004 are alternately disposed therebetween, and one of the channel layers 1004 is the topmost semiconductor layer. It should be understood that the semiconductor device 800 may include any number of sacrificial layers and any number of channel layers, any one of which is the topmost layer, while remaining within the scope of this disclosure.

[0054] Layers 1002 and 1004 can each have different thicknesses. Furthermore, sacrificial layers 1002 can have different thicknesses from one layer to another. Channel layers 1004 can have different thicknesses from one layer to another. The thickness of each of layers 1002 and 1004 can range from a few nanometers to tens of nanometers. The first layer of the stack can be thicker than the other semiconductor layers 1002 and 1004. In one embodiment, each sacrificial layer 1002 has a thickness ranging from about 5 nanometers (nm) to about 20 nm, and each channel layer 1004 has a thickness of about 5 nm to about 20 nm.

[0055] The two layers 1002 and 1004 can have different compositions. In various embodiments, the two layers 1002 and 1004 have compositions that provide different oxidation rates and / or different etch selectivity between the layers. In an embodiment, the sacrificial layer 1002 may each comprise silicon germanium (Si... 1-x Ge x The channel layers may each comprise silicon (Si). In an embodiment, each of the channel layers 1004 may be undoped or substantially dopant-free (i.e., having a diameter from about 0 cm⁻¹). -3 Up to approximately 1×10 17 cm -3 The silicon has an external dopant concentration, wherein, for example, no intentional doping is performed when the channel layer 1004 (e.g., silicon) is formed.

[0056] In various embodiments, the semiconductor layers 1004 may be intentionally doped. For example, when the semiconductor device 800 is configured as an n-type transistor (and operates in enhancement mode), each of the channel layers 1004 may be silicon doped with p-type dopants such as boron (B), aluminum (Al), indium (In), and gallium (Ga); and when the semiconductor device 800 is configured as a p-type transistor (and operates in enhancement mode), each of the channel layers 1004 may be silicon doped with n-type dopants such as phosphorus (P), arsenic (As), and antimony (Sb). In another example, when the semiconductor device 800 is configured as an n-type transistor (and operates in depletion mode), each of the channel layers 1004 may be silicon doped with n-type dopants. And when the semiconductor device 800 is configured as a p-type transistor (and operates in depletion mode), each of the channel layers 1004 may be silicon doped with p-type dopants.

[0057] In some embodiments, each sacrificial layer 1002 is Si 1-x Ge x This includes Ge with a molar ratio of less than 50% (x < 0.5). For example, Ge can account for a significant portion of Si. 1-x Ge x The sacrificial layer 1002 has a molar ratio of approximately 15% to 35%. Furthermore, the sacrificial layers 1002 may include different compositions, and the channel layers 1004 may include different compositions. Either layer 1002 or 1004 may include other materials, such as compound semiconductors like silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide, alloy semiconductors like GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, and / or GaInAsP, or combinations thereof. The materials of layers 1002 and 1004 may be selected based on providing different oxidation rates and / or etch selectivity.

[0058] Layers 1002 and 1004 can be epitaxially grown from semiconductor substrate 802. For example, each of layers 1002 and 1004 can be grown using molecular beam epitaxy (MBE), chemical vapor deposition (CVD) processes (such as metal-organic CVD (MOCVD)), and / or other suitable epitaxial growth processes. During epitaxial growth, the crystal structure of semiconductor substrate 802 extends upward, resulting in layers 1002 and 1004 having the same crystal orientation as semiconductor substrate 802.

[0059] Corresponding to operation 708, Figure 11 This is a cross-sectional view of a semiconductor device 800 comprising multiple semiconductor fins 1102 and 1104 at one of the various manufacturing stages. Figure 11 It is cut along the longitudinal direction of one or more active gate structures / pseudo gate structures of the semiconductor device 800.

[0060] After growing layers 1002 and 1004 (as a stack) on the semiconductor substrate 802, the stack can be patterned to form fin structures 1102 and 1104, such as Figure 11 As shown. Each of the fin structures extends laterally and includes a stack of patterned sacrificial layers 1002 and channel layers 1004 that are interleaved with each other. The fin structures 1102 and 1104 are formed by patterning the stack of layers 1002 and 1004 and the semiconductor material 904 using techniques such as photolithography and etching.

[0061] For example, in the topmost semiconductor layer of the stack (e.g. Figure 10 A mask layer (which may include multiple layers, such as a pad oxide layer and an overlying hard mask layer) is formed over the topmost channel layer 1004. The pad oxide layer may be a thin film comprising, for example, silicon oxide formed using a thermal oxidation process. The pad oxide layer may act as an adhesion layer between the topmost channel layer 1004 and the hard mask layer. In some embodiments, the hard mask layer may include silicon nitride, silicon oxynitride, silicon carbonitride, or combinations thereof. In some other embodiments, the hard mask layer may include a material similar to the material of layers 1002 / 1004, such as Si. 1-y Ge y The molar ratio (y) can be different from or similar to the molar ratio (x) of the sacrificial layer 1002. A hard mask layer can be formed on top of the stack (i.e., in front of the patterned stack) using, for example, low-pressure chemical vapor deposition (LPCVD) or plasma-enhanced chemical vapor deposition (PECVD).

[0062] Photolithography can be used to pattern mask layers. Typically, photolithography uses deposited, irradiated (exposed), and developed photoresist material (not shown) to remove portions of the photoresist. The remaining photoresist material protects the underlying material (such as the mask layer in this example) from subsequent processing steps (such as etching). For example, photoresist material is used to pattern pad oxide layers and pad nitride layers to form a patterned mask.

[0063] A patterned mask can then be used to pattern the exposed portions of layers 1002 and 1004 and the semiconductor material 904 to form fin structures 1102 and 1104, thereby defining trenches (or openings) between adjacent fin structures. When multiple fin structures are formed, each such trench can be disposed between any adjacent fin structures. In some embodiments, fin structures 1102 and 1104 are formed by etching layers 1002-1004 and the semiconductor material 904 in the trenches using, for example, reactive ion etching (RIE), neutral beam etching (NBE), or combinations thereof. The etching can be anisotropic. In some embodiments, the trenches can be strips that are parallel to each other and closely spaced from each other (when viewed from above). In some embodiments, the trenches can be continuous and surround the respective fin structure.

[0064] Corresponding to operation 710, Figure 12 This is a cross-sectional view of a semiconductor device 800 comprising multiple pseudo-gate structures 1202 and 1204 at one of the various manufacturing stages. Figure 12 The semiconductor device 800 shown is cut along the longitudinal direction of one or more channels (formed by fin structures) of the semiconductor device 800.

[0065] Dummy gate structures 1202 and 1204 are formed above each fin structure 1102 and 1104. The dummy gate structures 1201 and 1204 extend parallel to each other in a transverse direction perpendicular to the longitudinal direction of the fin structures 1102 and 1104. Thus, each of the dummy gate structures 1202 and 1204 can span a corresponding (e.g., central) portion of the fin structures 1102 and 1104. That is, the top surface and sidewalls of each of the fin structures 1102 and 1104 are at least partially in contact with the dummy gate structures 1202 and 1204.

[0066] The dummy gate structures 1202 and 1204 may each include a dummy gate dielectric and a dummy gate, which are not shown separately for clarity. To form the dummy gate structure, a dielectric layer may be formed over the fin structure 1102 or 1104. The dielectric layer may be, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxycarbide, or multiple layers thereof, and may be deposited or thermally grown.

[0067] A gate layer is formed above a dielectric layer, and a mask layer is formed above the gate layer. The gate layer can be deposited above the dielectric layer and then planarized, for example, by CMP. The mask layer can be deposited above the gate layer. The gate layer can be formed of, for example, polysilicon, but other materials can also be used. The mask layer can be formed of, for example, silicon nitride. After forming the layers (e.g., dielectric layer, gate layer, and mask layer), the mask layer can be patterned using suitable photolithography and etching techniques. Next, the pattern of the mask layer can be transferred to the gate layer and dielectric layer using suitable etching techniques to form the pseudo-gate structure 1202 / 1204.

[0068] After forming the dummy gate structures 1202 and 1204, gate spacers (e.g., 1212, 1214) can be formed on the opposite sidewalls of corresponding ones of the dummy gate structures 1202 and 1204, such as... Figure 12 As shown. The gate spacers 1212 / 1214 can be low-k spacers and can be formed from suitable dielectric materials, such as silicon oxide, silicon carbonitride, etc. Any suitable deposition method can be used to form the gate spacers, such as thermal oxidation, chemical vapor deposition (CVD), etc. Figure 12 The shape and forming method of the gate spacers 1212 / 1214 shown are merely non-limiting examples, and other shapes and forming methods are also possible. These and other variations are intended to be included within the scope of this disclosure.

[0069] Corresponding to operation 712, Figure 13A This is a cross-sectional view of a semiconductor device 800 comprising multiple source / drain (S / D) recesses 1302 at one of the various manufacturing stages. Figure 13A It is cut along the longitudinal direction of one or more channels (formed by fin structures) of the semiconductor device 800.

[0070] The dummy gate structures 1202 and 1204 (along with their corresponding gate spacers) can be used as masks to recess (e.g., etch) the non-overlapping portions of each of the fin structures 1102 and 1104, resulting in the sacrificial layer 1002 and channel layer 1004 of the respective remaining portions of the remaining fin structures 1102 / 1104 being alternately stacked on top of each other. As a result, an S / D recess 1302 can be formed on the opposite sides of the remaining fin structures 1102 / 1104.

[0071] The recessing step for forming the S / D groove 1302 can be configured to have at least some anisotropic etching characteristics. For example, the recessing step may include a plasma etching process, which may have a certain amount of anisotropic characteristics. In such plasma etching processes (including radical plasma etching, remote plasma etching, and other suitable plasma etching processes), gas sources such as chlorine (Cl2), hydrogen bromide (HBr), carbon tetrafluoride (CF4), fluoroform (CHF3), difluoromethane (CH2F2), fluoromethane (CH3F), hexafluoro-1,3-butadiene (C4F6), boron trichloride (BCl3), sulfur hexafluoride (SF6), hydrogen (H2), nitrogen trifluoride (NF3), and other suitable gas sources and combinations thereof can be used with passivating gases such as nitrogen (N2), oxygen (O2), carbon dioxide (CO2), sulfur dioxide (SO2), carbon monoxide (CO), methane (CH4), silicon tetrachloride (SiCl4), and other suitable passivating gases and combinations thereof. Furthermore, for the recessing step, gases such as argon (Ar), helium (He), neon (Ne), and other suitable diluting gases and combinations thereof can be used to dilute the gas source and / or passivation gas in order to control the etching rate described above.

[0072] This corresponds to operation 714 (which can be executed without executing operation 704). Figure 13B This is a cross-sectional view of a semiconductor device 800, wherein a buried oxide layer (or bottom oxide layer) 1310 is formed when the S / D groove 1302 is formed. Figure 13B It is cut along the longitudinal direction of one or more channels (formed by fin structures) of the semiconductor device 800. For example, after forming the S / D groove 1302 by etching the fin structures 1102 and 1104, which does not have the semiconductor material 904 and the buried oxide layer 902 formed thereunder, a portion of the substrate 802 (exposed by the S / D groove 1302) can also be removed (e.g., etched). These removed portions of the substrate 802 can be refilled with a dielectric material to form the buried oxide layer 1310.

[0073] Corresponding to operation 716, Figure 14A This is a cross-sectional view of a semiconductor device 800 (with a buried oxide layer 902) including a source / drain (S / D) structure 1402 and an interlayer dielectric (ILD) 1406 at one of the various manufacturing stages. Figure 14B This is a cross-sectional view of a semiconductor device 800 (with a buried oxide layer 1310) that includes an S / D structure 1402 and an ILD 1406 at one of the various manufacturing stages. Figures 14A-14B The cross-sectional views are each cut along the longitudinal direction of one or more channels (formed by fin structures) of the semiconductor device 800.

[0074] S / D structure 1402 is disposed in S / D groove 1302 ( Figures 13A-13B Therefore, the S / D structure 1402 (at least the lower part) can inherit the dimensions and contours of the groove 1302. The S / D structure 1402 is formed by epitaxially growing semiconductor material (e.g., from the channel layer of the fin structures 1102 / 1104) in the groove 1302 using suitable methods such as metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), vapor phase epitaxy (VPE), selective epitaxial growth (SEG), or combinations thereof.

[0075] Before forming the S / D structure 1402, the ends of the sacrificial layer 1002 can be removed (e.g., etched) using a pull-back process with a pull-back distance. In an example where the channel layer 1004 comprises Si and the sacrificial layer 1002 comprises SiGe, the pull-back process can include an isotropic etching process using hydrogen chloride (HCl) gas, which etches SiGe without eroding Si. In this way, the Si layer (nanostructure) 1004 can remain substantially intact during the pull-back process. Therefore, a pair of grooves can be formed on the ends of each sacrificial layer 1002 relative to the adjacent channel layer 1004. Next, such grooves on the ends of each sacrificial layer 1002 can be filled with a dielectric material to form internal spacers 1410, such as... Figure 14A and Figure 14B As shown. The dielectric material used for the internal spacers may include silicon nitride, silicon boron carbonitride, silicon carbonitride, silicon carbonitride, or any other type of dielectric material suitable for forming insulating gate sidewall spacers of transistors (e.g., a dielectric material having a dielectric constant k of less than about 5).

[0076] like Figure 14A and Figure 14B As further shown, the S / D structure 1402 is disposed on opposite sides of the fin structures 1102 / 1104 to couple to the channel layer 1004 therein, and is separated from the sacrificial layer 1002 of the fin structures 1102 / 1104 by an internal spacer 1410 disposed therebetween. According to various embodiments of this disclosure, the channel layer 1004 in each of the fin structures 1102 and 1104 can collectively serve as the conductive channel of the completed transistor. The sacrificial layer 1002 in each of the fin structures 1102 and 1104 can later be configured to partially replace the active gate structure surrounding the corresponding channel layer.

[0077] In some embodiments, ILD 1406 may be formed simultaneously to cover at least S / D structure 1402. ILD 1406 is formed of a dielectric material such as silicon oxide, silicon phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped silicon phosphosilicate glass (BPSG), undoped silicate glass (USG), etc., and can be deposited by any suitable method, such as CVD, PECVD, or FCVD. After ILD formation, an optional dielectric layer (not shown) is formed over ILD. The dielectric layer can serve as a protective layer to prevent or reduce ILD loss in subsequent etching processes. The dielectric layer can be formed from a suitable material such as silicon nitride, silicon carbonitride, etc., using a suitable method such as CVD, PECVD, or FCVD. After dielectric layer formation, a planarization process, such as CMP, can be performed to achieve a flat top surface of the dielectric layer. In some embodiments, after the planarization process, the top surface of the dielectric layer is flush with the top surfaces of the dummy gate structures 1202 and 1204.

[0078] Corresponding to operation 718, Figure 15A This is a cross-sectional view of a semiconductor device 800 (with a buried oxide layer 902) including active metal gates 1502 and 1504 at one of the various manufacturing stages.

[0079] Figure 15B This is a cross-sectional view of a semiconductor device 800 (with a buried oxide layer 1310) including active metal gates 1502 and 1504 at one of the various manufacturing stages. Figures 15A-15B Each is cut along the longitudinal direction of one or more channels (formed by fin structures) of the semiconductor device 800.

[0080] After forming ILD 1406, the dummy gate structures 1202-1204 and the (remaining) sacrificial layer 1002 can be removed simultaneously. In various embodiments, the dummy gate structures 1202-1204 and the sacrificial layer 1002 can be removed by applying selective etching (e.g., hydrochloric acid (HCl)), while leaving the channel layer 1004 substantially intact. After removing the dummy gate structures, gate trenches can be formed to expose the corresponding sidewalls of each channel layer 1004. After removing the sacrificial layer 1002 (which may further extend the gate trenches), the corresponding bottom and / or top surfaces of each channel layer 1004 can be exposed. Thus, the entire periphery of each channel layer 1004 can be exposed. Active gate structures 1502 and 1504 are then formed to surround each channel layer 1004.

[0081] In some embodiments, active gate structures 1502-1504 each include a gate dielectric and a gate metal (not shown separately for clarity). The gate dielectric may encapsulate surrounding each channel layer 1004, such as the top and bottom surfaces and sidewalls. The gate dielectric may be formed of different high-k dielectric materials or similar high-k dielectric materials. Exemplary high-k dielectric materials include metal oxides or silicates of Hf, Al, Zr, La, Mg, Ba, Ti, Pb, and combinations thereof. The gate dielectric may include a stack of various high-k dielectric materials. Any suitable method may be used to deposit the gate dielectric, including molecular beam deposition (MBD), atomic layer deposition (ALD), PECVD, etc. In some embodiments, the gate dielectric may optionally include a substantially thin oxide (e.g., SiO2). x The layer can be an intrinsic oxide layer formed on the surface of each channel layer 1004.

[0082] The gate metal can comprise a stack of various metallic materials. For example, the gate metal can be a p-type work function layer, an n-type work function layer, multiple layers thereof, or a combination thereof. The work function layer can also be referred to as the work function metal. Exemplary p-type work function metals can include TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, WN, other suitable p-type work function materials, or combinations thereof. Exemplary n-type work function metals can include Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, other suitable n-type work function materials, or combinations thereof. The work function value is associated with the material composition of the work function layer; therefore, the material of the work function layer is selected to adjust its work function value, thereby achieving the target threshold voltage V in the device to be implemented. t The work function layer can be formed by CVD, physical vapor deposition (PVD), ALD and / or other suitable processes.

[0083] After forming the active gate structures 1502-1504, multiple GAA FETs can be defined (or otherwise formed). For example, in Figures 15A-15BIn this process, a first GAA FET 1510 and a second GAA FET 1520 are formed. The GAA FET 1510 has an active gate structure 1502 surrounding a corresponding channel layer 1004 and an S / D structure 1402 disposed on the opposite side of the active gate structure 1502, which are operably used as its gate (terminal) and source / drain (terminal), respectively. Similarly, the GAA FET 1520 has an active gate structure 1504 surrounding a corresponding channel layer 1004 and an S / D structure 1402 disposed on the opposite side of the active gate structure 1504, which are operably used as its gate (terminal) and source / drain (terminal), respectively. According to various embodiments, such GAA FETs can be used individually or collectively as one or more various components of the SRAM device 100, such as the switching transistor 306, transistors 220-270 of each memory cell 190, etc.

[0084] Corresponding to operation 720, Figure 16A This is a cross-sectional view of a semiconductor device 800 (with a buried oxide layer 902) including multiple front-side interconnect structures 1602, 1604, 1606, and 1608. Figure 16B This is a cross-sectional view of a semiconductor device (with a buried oxide layer 1310) including front-side interconnect structures 1602 to 1608 at one of the various manufacturing stages. Figures 16A-16B The cross-sectional views are cut along the longitudinal direction of one or more channels (formed by fin structures) of the semiconductor device 800.

[0085] Front-side interconnect structures 1602 to 1608 (formed from one or more metallic materials, such as copper) can be formed based on single-damascene processes, dual-damascene processes, reactive ion etching processes, and other suitable processes. For example, in a damascene process, one or more trenches / openings are formed in the ILD, and then the trenches / openings are refilled using one or more metallic materials to form the front-side interconnect structures 1602 to 1608. Such ILDs are formed from dielectric materials such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicon glass (USG), etc., and can be deposited by any suitable method such as CVD, PECVD, or FCVD.

[0086] It should be understood that the front interconnect structures 1602 to 1608 are provided for illustrative purposes, and therefore, the semiconductor device 800 may have any number of each of the front interconnect structures 1602 to 1608 while remaining within the scope of this disclosure. For example, the semiconductor device 800 may have any number of front interconnect structures 1602 (which may be VG connecting an active gate structure to one or more front metal tracks), any number of front interconnect structures 1604 (which may be MD coupling an S / D structure to one or more front metal tracks via VD), any number of front interconnect structures 1606 (which may be VD coupling an S / D structure to one or more front metal tracks via MD), and any number of front interconnect structures 1608 (which may be M0 track). Furthermore, the semiconductor device 800 may have any number of metal tracks (e.g., M1 track, M2 track, etc.) disposed above the front interconnect structures 1608.

[0087] In various embodiments, front-side interconnect structures 1602 to 1608 can electrically connect corresponding GAA FETs to one or more other GAA FETs for use as desired circuit components of the SRAM device 100 (e.g., memory cells, logic gates, etc.). Thus, these front-side interconnect structures 1602 to 1608 can each be configured to transmit or receive (or otherwise route) signals.

[0088] In some other embodiments, some of these front-side interconnect structures (e.g., M0 track 1608) can be used as portions of boost capacitor 304 (e.g., C1', C2', C3', C4', etc.), as described above regarding Figure 5 The subject of discussion. For example, two adjacent metal orbitals in a front metallization layer (e.g., Figures 16A-16B The M0 track 1608 shown can be operatively used as the first and second terminals of a sub-capacitor of the boost capacitor 304, which causes an internal electric field (extending from one terminal to the other). The portion of the ILD inserted between these metal tracks can reduce the electric field and increase the corresponding capacitance value.

[0089] Corresponding to operation 722, Figure 17A and Figure 17B These are cross-sectional views of a semiconductor device 800 having buried oxide layers 902 and 1310 at one of the various manufacturing stages in which the substrate 802 is thinned from its back side. Figures 17A-17B The cross-sectional views are each cut along the longitudinal direction of one or more channels (formed by fin structures) of the semiconductor device 800.

[0090] exist Figure 17AIn the example, substrate 802 (surrounded by dashed lines) is thinned from its back side by a polishing process (e.g., chemical mechanical polishing (CMP) process). The CMP process stops only when the buried oxide layer 902 is exposed. Figure 17B In the example, substrate 802 (surrounded by dashed lines) is thinned from its back side by a polishing process (e.g., chemical mechanical polishing (CMP) process). The CMP process stops only when the buried oxide layer 1310 is exposed.

[0091] Corresponding to operation 724, Figure 18A This is a cross-sectional view of a semiconductor device 800 (with a buried oxide layer 902) including multiple back-side interconnect structures 1802 and 1804 at one of the various manufacturing stages. Figure 18A This is a cross-sectional view of a semiconductor device 800 (with a buried oxide layer 902) including back-side interconnect structures 1802 to 1804 at one of the various manufacturing stages. Figures 18A-18B The cross-sectional views are each cut along the longitudinal direction of one or more channels (formed by fin structures) of the semiconductor device 800.

[0092] Back-side interconnect structures 1802 to 1804 (formed from one or more metallic materials, such as copper) can be formed based on single-damascene processes, dual-damascene processes, reactive ion etching processes, and other suitable processes. For example, in a damascene process, one or more trenches / openings are formed in the ILD, and then the trenches / openings are refilled using one or more metallic materials to form the back-side interconnect structures 1802 to 1804. Such ILDs are formed from dielectric materials such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicon glass (USG), etc., and can be deposited by any suitable method such as CVD, PECVD, or FCVD.

[0093] It should be understood that the back-side interconnect structures 1802 to 1804 are provided for illustrative purposes, and therefore, the semiconductor device 800 may have any number of each of the back-side interconnect structures 1802 to 1804 while remaining within the scope of this disclosure. For example, the semiconductor device 800 may have any number of back-side interconnect structures 1802 (which may be BVs connecting an active gate structure or an S / D structure to one or more back-side metal tracks) and any number of back-side interconnect structures 1804 (which may be BM0 tracks). Furthermore, the semiconductor device 800 may have any number of metal tracks (e.g., BM1 tracks, BM2 tracks, etc.) disposed above the back-side interconnect structures 1804.

[0094] In various embodiments, some of these back-side interconnect structures (e.g., BMO track 1804) can be used as portions of boost capacitor 304 (e.g., C1, C2, C3, C4, etc.), as described above regarding Figure 5 This is under discussion. For example, two adjacent metal orbitals in a back-side metallization layer (e.g., Figures 18A-18B The BM0 track 1804 shown is operably used as the first and second terminals of a sub-capacitor of the boost capacitor 304, which causes an internal electric field (extending from one terminal to the other). The portion of the ILD inserted between these metal tracks can reduce the electric field and increase the corresponding capacitance value.

[0095] In one aspect of this disclosure, a memory device is disclosed. The memory device includes: a memory cell; a bit line coupled to the memory cell; and a voltage generator coupled to the bit line and configured to provide a negative voltage to the bit line. The voltage generator includes: a transistor; and a first capacitor having a first terminal and a second terminal electrically coupled to the drain and gate of the transistor, respectively. The drain and gate of the transistor are formed on a first side of a substrate, and the first terminal and the second terminal of the first capacitor are formed on a second side of the substrate opposite to the first side.

[0096] In the above-described memory device, the memory cell includes a plurality of memory transistors and the bit line includes a first metal line, wherein the plurality of memory transistors and the first metal line are formed on a first side of the substrate.

[0097] In the aforementioned memory device, the first terminal and the second terminal of the first capacitor respectively include a first metal line and a second metal line, wherein the first metal line and the second metal line are arranged parallel to each other.

[0098] In the aforementioned memory device, the first metal line and the second metal line each have a thickness in the range of about 40 nanometers (nm) to about 400 nm.

[0099] In the memory device described above, the first metal line and the second metal line are disposed in a common metallization layer among a plurality of metallization layers formed on the second side of the substrate.

[0100] In the aforementioned memory devices, the common metallization layer is closer to the substrate than any other metallization layer.

[0101] In the aforementioned memory device, the common metallization layer is spaced apart from the substrate by two of the multiple metallization layers.

[0102] In the aforementioned memory device, the voltage generator includes: a second capacitor having a first terminal and a second terminal electrically coupled to the drain and gate of a transistor, respectively, wherein the first terminal and the second terminal of the second capacitor are formed on a second side of a substrate; a third capacitor having a first terminal and a second terminal electrically coupled to the drain and gate of a transistor, respectively, wherein the first terminal and the second terminal of the third capacitor are formed on a second side of a substrate; and a fourth capacitor having a first terminal and a second terminal electrically coupled to the drain and gate of a transistor, respectively, wherein the first terminal and the second terminal of the fourth capacitor are formed on a second side of a substrate.

[0103] In the aforementioned memory device, the second terminal of the first capacitor and the first terminal of the second capacitor share a first common metal line, the second terminal of the second capacitor and the second terminal of the third capacitor share a second common metal line, and the first terminal of the third capacitor and the first terminal of the fourth capacitor share a third common metal line.

[0104] In the aforementioned memory device, a negative voltage exists at the drain of the transistor in response to the transistor being turned off.

[0105] In the aforementioned memory device, the voltage generator includes a second capacitor having a first terminal and a second terminal electrically coupled to the drain and gate of a transistor, respectively, wherein the first and second terminals of the second capacitor are formed on a first side of a substrate.

[0106] In the aforementioned memory device, the first terminal and the second terminal of the first capacitor respectively include a first metal line and a second metal line, and the first terminal and the second terminal of the second capacitor respectively include a third metal line and a fourth metal line, wherein the first metal line and the second metal line each have a first thickness, and the third metal line and the fourth metal line each have a second thickness that is substantially thinner than the first thickness.

[0107] In another aspect of this disclosure, a memory device is disclosed. The memory device includes a memory array formed on the front side of a substrate. The memory array is accessible via a plurality of bit lines. The memory device includes a switching transistor formed on the front side of the substrate. The switching transistor is operatively coupled to the plurality of bit lines. The memory device includes a first capacitor formed on the back side of the substrate. The first capacitor is configured to reduce a voltage level present on at least one of the plurality of bit lines in response to the switching transistor being turned off.

[0108] The memory device described above also includes a second capacitor formed on the front side of the substrate, wherein the second capacitor is electrically coupled in parallel with the first capacitor.

[0109] In the aforementioned memory device, the first terminal and the second terminal of the first capacitor respectively include a first metal line and a second metal line, wherein the first metal line and the second metal line are arranged parallel to each other.

[0110] In the aforementioned memory device, the first metal line and the second metal line each have a thickness equal to or greater than about 40 nanometers (nm).

[0111] In the aforementioned memory device, the first terminal and the second terminal of the first capacitor are respectively coupled to the drain and gate of the switching transistor.

[0112] In the aforementioned memory device, the voltage level is configured to be reduced to below 0 volts.

[0113] In another aspect of this disclosure, a method for manufacturing a memory device is disclosed. The method includes forming a plurality of memory transistors configured as a memory array on the front side of a substrate. The method includes forming a plurality of bit lines operatively coupled to the memory array on the front side of the substrate. The method includes forming switching transistors operatively coupled to the plurality of bit lines on the front side of the substrate. The method includes forming a first capacitor on the back side of the substrate, the first capacitor being configured to reduce a voltage level present on at least one of the plurality of bit lines to a negative value.

[0114] In the above method, the step of forming the first capacitor further includes forming a first metal wire and a second metal wire arranged in parallel with each other.

[0115] The above method also includes forming a second capacitor on the front side of the substrate, which is electrically coupled to the first capacitor in parallel.

[0116] As used herein, the terms “about” and “approximately” generally refer to plus or minus 10% of the stated value. For example, about 0.5 would include 0.45 and 0.55, about 10 would include 9 to 11, and about 1000 would include 900 to 1100.

[0117] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages of the embodiments described herein. Those skilled in the art will also recognize that such equivalent structures do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made within the invention without departing from its spirit and scope.

Claims

1. A memory device, comprising: Memory unit; Bit lines are coupled to the memory cells; as well as A voltage generator is coupled to the bit line and configured to provide a negative voltage to the bit line; The voltage generator includes: transistor; and The first capacitor has a first terminal and a second terminal respectively electrically coupled to the drain and gate of the transistor; and The drain and gate of the transistor are formed on a first side of the substrate, and the first terminal and the second terminal of the first capacitor are formed on a second side of the substrate opposite to the first side. The voltage generator includes a second capacitor having a first terminal and a second terminal electrically coupled to the drain and the gate of the transistor, respectively. The first terminal and the second terminal of the second capacitor are formed on the first side of the substrate, and the capacitance of the first capacitor on the second side of the substrate is greater than the capacitance of the second capacitor on the first side of the substrate.

2. The memory device according to claim 1, wherein, The memory cell includes a plurality of memory transistors and the bit line includes a first metal line, wherein the plurality of memory transistors and the first metal line are formed on the first side of the substrate.

3. The memory device according to claim 1, wherein, The first terminal and the second terminal of the first capacitor respectively include a first metal wire and a second metal wire, wherein the first metal wire and the second metal wire are arranged parallel to each other.

4. The memory device according to claim 3, wherein, The first metal wire and the second metal wire each have a thickness in the range of 40 nanometers to 400 nanometers.

5. The memory device according to claim 3, wherein, The first metal line and the second metal line are disposed in a common metallization layer among a plurality of metallization layers formed on the second side of the substrate.

6. The memory device according to claim 5, wherein, The common metallization layer is closer to the substrate than any other metallization layer.

7. The memory device according to claim 5, wherein, The common metallization layer is spaced apart from the substrate by two of the plurality of metallization layers.

8. The memory device according to claim 1, wherein, The voltage generator includes: The second capacitor has a first terminal and a second terminal that are electrically coupled to the drain and the gate of the transistor, respectively, wherein the first terminal and the second terminal of the second capacitor are formed on the second side of the substrate; A third capacitor has a first terminal and a second terminal electrically coupled to the drain and gate of the transistor, respectively, wherein the first and second terminals of the third capacitor are formed on the second side of the substrate; and A fourth capacitor has a first terminal and a second terminal electrically coupled to the drain and the gate of the transistor, respectively, wherein the first terminal and the second terminal of the fourth capacitor are formed on the second side of the substrate.

9. The memory device according to claim 8, wherein, The second terminal of the first capacitor and the first terminal of the second capacitor share a first common metal line, the second terminal of the second capacitor and the second terminal of the third capacitor share a second common metal line, and the first terminal of the third capacitor and the first terminal of the fourth capacitor share a third common metal line.

10. The memory device according to claim 1, wherein, In response to the transistor being turned off, the negative voltage exists at the drain of the transistor.

11. The memory device according to claim 1, wherein, The first terminal and the second terminal of the first capacitor each have a thickness in the range of 40 nanometers to 400 nanometers.

12. The memory device according to claim 1, wherein, The first terminal and the second terminal of the first capacitor respectively include a first metal wire and a second metal wire, and the first terminal and the second terminal of the second capacitor respectively include a third metal wire and a fourth metal wire, wherein the first metal wire and the second metal wire each have a first thickness, and the third metal wire and the fourth metal wire each have a second thickness that is substantially thinner than the first thickness.

13. A memory device, comprising: A memory array is formed on the front side of a substrate, wherein the memory array is accessible via multiple bit lines; A switching transistor is formed on the front side of the substrate, wherein the switching transistor is operatively coupled to the plurality of bit lines; and A first capacitor is formed on the back side of the substrate, wherein the first capacitor is configured to reduce the voltage level present on at least one of the plurality of bit lines in response to the switching transistor being turned off, wherein a first terminal and a second terminal of the first capacitor are electrically coupled to the drain and gate of the switching transistor, respectively. A second capacitor is formed on the front side of the substrate, wherein the second capacitor is electrically coupled in parallel with the first capacitor, and the capacitance of the first capacitor on the back side of the substrate is greater than the capacitance of the second capacitor on the front side of the substrate.

14. The memory device according to claim 13, wherein, Both the first terminal and the second terminal have a thickness in the range of 40 nanometers to 400 nanometers.

15. The memory device according to claim 13, wherein, The first terminal and the second terminal of the first capacitor respectively include a first metal wire and a second metal wire, wherein the first metal wire and the second metal wire are arranged parallel to each other.

16. The memory device according to claim 15, wherein, The first metal wire and the second metal wire each have a thickness equal to or greater than 40 nanometers.

17. The memory device according to claim 15, wherein, The first metal line and the second metal line are disposed in a common metallization layer among a plurality of metallization layers formed on the second side of the substrate.

18. The memory device according to claim 13, wherein, The voltage level is configured to be reduced to below 0 volts.

19. A method for manufacturing a memory device, comprising: Multiple memory transistors configured as a memory array are formed on the front side of the substrate; A switching transistor is formed on the front side of the substrate; A plurality of bit lines operatively coupled to the memory array are formed on the front side of the substrate, wherein the switching transistors are operatively coupled to the plurality of bit lines; and A first capacitor is formed on the back side of the substrate, the first capacitor being configured to reduce the voltage level present on at least one of the plurality of bit lines to a negative value, wherein a first terminal and a second terminal of the first capacitor are electrically coupled to the drain and gate of the switching transistor, respectively. A second capacitor is formed on the front side of the substrate and electrically coupled to the first capacitor in parallel, wherein the capacitance of the first capacitor on the back side of the substrate is greater than the capacitance of the second capacitor on the front side of the substrate.

20. The method according to claim 19, wherein, The step of forming the first capacitor further includes forming a first metal wire and a second metal wire arranged parallel to each other.

21. The method according to claim 19, wherein, Both the first terminal and the second terminal have a thickness in the range of 40 nanometers to 400 nanometers.

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