Semiconductor memory device

Abstract

A semiconductor storage device which suppresses an increase in circuit area and generates an appropriate voltage is provided. The semiconductor storage device of an embodiment has a connection transistor which electrically connects a first wiring and a word line, a block decoder which supplies a signal to a gate of the connection transistor, and a voltage generation circuit which has a first node to which a first voltage used to generate the signal is supplied from the block decoder, a second node to which a second voltage is supplied to the first wiring, and a voltage difference generation circuit which is connected between the first node and the second node, and the voltage difference generation circuit has a first and a second diode-connected transistors which connect a current path between the first node and the second node, and a third transistor which has a first terminal connected to the first node, a gate connected to the gate of the second transistor, and a second terminal connected to the second node.

Description

[0001] Related applications

[0002] This application claims priority to Japanese Patent Application No. 2021-211390 (filed on December 24, 2021). This application incorporates the entire contents of the said basic application by reference. Technical Field

[0003] Embodiments of the present invention relate to a semiconductor memory device. Background Technology

[0004] In recent years, semiconductor memory devices such as NAND (Non-AND) type non-volatile memory have sought miniaturization and increased capacity through 3D construction. These semiconductor memory devices sometimes employ a configuration of multiple physically independent planes within the memory chip.

[0005] When writing to multiple planes simultaneously, the current supplied from the voltage generation circuit to each plane increases, resulting in a need to increase the size of the transistors in the voltage generation circuit. Summary of the Invention

[0006] This embodiment provides a semiconductor memory device that can suppress the increase of circuit area and generate an appropriate voltage.

[0007] The semiconductor memory device of the embodiment includes: a block having a plurality of memory cells; word lines connected to the gates of the plurality of memory cells; a plurality of bit lines, each connected to one end of the plurality of memory cells; a first wiring; a connecting transistor electrically connecting the first wiring to the word lines based on a signal supplied to the gate; a block decoder supplying the signal to the gate of the connecting transistor; and a voltage generating circuit having: a first node supplying a first voltage to the block decoder for generating the signal; a second node supplying a second voltage to the first wiring; and a voltage difference generating circuit connected to the first node and... Between the second nodes; and the voltage difference generating circuit has a first transistor, a second transistor and a third transistor, the first transistor having: a first terminal connected to the first node, a gate connected to the first node, and a second terminal; the second transistor having: a first terminal connected to the second terminal of the first transistor, a gate connected to the second terminal of the first transistor, and a second terminal connected to the second node; the third transistor having: a first terminal connected to the first node, a gate connected to the gate of the second transistor, and a second terminal connected to the second node. Attached Figure Description

[0008] Figure 1This is a block diagram illustrating an example of the configuration of a memory system related to an implementation method.

[0009] Figure 2 This is a block diagram illustrating an example of the configuration of the non-volatile memory in this embodiment.

[0010] Figure 3 It means Figure 2 A block diagram illustrating a specific example of the multiple planes within the structure.

[0011] Figure 4 This is a diagram showing the equivalent circuit of the block BLK of the 3D structured NAND memory cell array 3 in the non-volatile memory 2 of this embodiment.

[0012] Figure 5 This diagram illustrates an example of the configuration of a block BLK of a 3D NAND memory cell array 23 in the non-volatile memory 2 of this embodiment.

[0013] Figure 6 It is a graph showing the potential changes of each wire in the write operation (programming operation).

[0014] Figure 7 It is a circuit diagram that represents the state of the string during programming actions.

[0015] Figure 8 It is a graph that shows the threshold voltage on the horizontal axis and the number of transistors (cells) in the memory cell array on the vertical axis.

[0016] Figure 9 This is an example of encoding, illustrating the 2-3-2 encoding.

[0017] Figure 10 This is a diagram used to illustrate an example of the standard write order.

[0018] Figure 11 This is an explanatory diagram showing the standard write order in a write operation.

[0019] Figure 12 This is a block diagram representing a portion of the voltage generation circuit 28 and the MUX switch 29.

[0020] Figure 13 It means Figure 2 A block diagram illustrating an example of the configuration of the row decoder 25.

[0021] Figure 14 It indicates composition Figure 12 A block diagram illustrating an example of the specific configuration of the VPGM generation circuit 40 in the voltage generation circuit 28.

[0022] Figure 15 It means Figure 14The circuit diagram shows an example of the specific configuration of the charge pump circuit 41 in the circuit.

[0023] Figure 16 This is a circuit diagram representing a comparative example of the voltage difference generating circuit 45, namely the voltage difference generating circuit 45A.

[0024] Figure 17 This is a circuit diagram illustrating an example of the specific configuration of the voltage difference generating circuit 45.

[0025] Figure 18 This is a circuit diagram showing the voltage difference generating circuit 50 used in the second embodiment of the present invention.

[0026] Figure 19 This is a circuit diagram showing the voltage difference generating circuit 51 used in the third embodiment of the present invention.

[0027] Figure 20 This is a circuit diagram showing the voltage difference generating circuit 51 used in the third embodiment of the present invention. Detailed Implementation

[0028] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0029] (First Embodiment)

[0030] In addition to the voltage difference generating current path, which is formed by a transistor connected to a diode and generates two voltages with a voltage difference at its two ends, the voltage generating circuit of this embodiment also includes a bypass current path. A bypass current source is arranged in the bypass current path, thereby allowing a current of approximately a specific ratio to flow through the voltage difference generating current path and the bypass current path. This suppresses the increase in the transistor's circuit area and prevents the voltage difference from becoming too large.

[0031] (The structure of a memory system)

[0032] Figure 1 This is a block diagram illustrating an example configuration of a memory system related to an implementation embodiment. The memory system of this embodiment includes a memory controller 1 and non-volatile memory 2. The memory system can be connected to a host computer. The host computer is, for example, an electronic device such as a personal computer or a portable terminal.

[0033] Non-volatile memory 2 is a semiconductor storage device that stores data non-volatilely, such as a NAND flash memory. In this embodiment, non-volatile memory 2 is described as a NAND flash memory with each storage cell transistor capable of storing 3 bits, that is, a 3-bit / cell (TLC: Triple Level Cell) NAND flash memory, but it is not limited to this. Non-volatile memory 2 is 3-dimensional.

[0034] The memory controller 1 controls the writing of data to the non-volatile memory 2 according to write requests from the host. Furthermore, the memory controller 1 controls the reading of data from the non-volatile memory 2 according to read requests from the host. The memory controller 1 includes RAM (Random Access Memory) 11, a processor 12, a host interface 13, an ECC (Error Check and Correction) circuit 14, and a memory interface 15. The RAM 11, processor 12, host interface 13, ECC circuit 14, and memory interface 15 are interconnected via an internal bus 16.

[0035] The host interface 13 outputs requests received from the host, user data (i.e., write data), etc., to the internal bus 16. In addition, the host interface 13 sends user data read from the non-volatile memory 2, responses from the processor 12, etc., to the host.

[0036] The memory interface 15 controls, based on instructions from the processor 12, the processes of writing user data to the non-volatile memory 2 and reading user data from the non-volatile memory 2.

[0037] Processor 12 provides overall control over memory controller 1. Processor 12 may be, for example, a CPU (Central Processing Unit) or an MPU (Micro Processing Unit). When processor 12 receives a request from the host via host interface 13, it performs control according to the request. For example, processor 12, upon receiving a request from the host, instructs memory interface 15 to write user data and parity data to non-volatile memory 2. Furthermore, processor 12, upon receiving a request from the host, instructs memory interface 15 to read user data and parity data from non-volatile memory 2.

[0038] Processor 12 determines the storage area (hereinafter referred to as memory area) on non-volatile memory 2 based on the user data accumulated in RAM 11. User data is stored in RAM 11 via internal bus 16. Processor 12 determines the memory area for data written in units of pages, i.e., page data. In this specification, user data stored in one page of non-volatile memory 2 is defined as cell data. Cell data is, for example, encoded and stored as codewords in non-volatile memory 2.

[0039] Furthermore, encoding is not mandatory. Memory controller 1 can also store cell data in non-volatile memory 2 without encoding, but... Figure 1The following is an example of the encoding configuration. When the memory controller 1 does not perform encoding, the page data is identical to the cell data. Furthermore, a codeword can be generated based on one cell data, or it can be generated based on segmented data that divides the cell data. Alternatively, a codeword can be generated using multiple cell data.

[0040] Processor 12 determines the memory region of the non-volatile memory 2 to be written to based on the data in each unit. It allocates physical addresses to the memory regions of the non-volatile memory 2. Processor 12 uses the physical addresses to manage the memory regions to be written to the unit data. Processor 12 specifies the physical address of the determined memory region, instructing memory interface 15 to write user data to non-volatile memory 2. Processor 12 manages the mapping between the logical addresses (logical addresses managed by the host) and physical addresses of user data. When processor 12 receives a read request containing a logical address from the host, it specifies the physical address corresponding to the logical address, instructs memory interface 15 to read the user data.

[0041] ECC circuit 14 encodes the user data stored in RAM 11 to generate codewords. Furthermore, ECC circuit 14 decodes the codewords read from non-volatile memory 2.

[0042] RAM 11 temporarily stores user data received from the host until it is stored in non-volatile memory 2, or temporarily stores data read from non-volatile memory 2 until it is sent to the host. RAM 11 is, for example, general-purpose memory such as SRAM (Static Random Access Memory) or DRAM (Dynamic Random Access Memory).

[0043] Figure 1 The diagram shows an example configuration where the memory controller 1 includes both the ECC circuit 14 and the memory interface 15. However, the ECC circuit 14 can also be integrated into the memory interface 15. Alternatively, the ECC circuit 14 can be integrated into the non-volatile memory 2.

[0044] Upon receiving a write request from the host, the memory controller 1 operates as follows: The processor 12 temporarily stores the write data in RAM 11. The processor 12 reads the data stored in RAM 11 and inputs it to the ECC circuit 14. The ECC circuit 14 encodes the input data and provides the codeword to the memory interface 15. The memory interface 15 writes the input codeword to the non-volatile memory 2.

[0045] Upon receiving a read request from the host, the memory controller 1 operates as follows: The memory interface 15 provides the codeword read from the non-volatile memory 2 to the ECC circuit 14. The ECC circuit 14 decodes the input codeword and stores the decoded data in the RAM 11. The processor 12 then sends the data stored in the RAM 11 to the host via the host interface 13.

[0046] (A rough outline of non-volatile memory)

[0047] Figure 2 This is a block diagram illustrating an example of the configuration of the non-volatile memory in this embodiment. Furthermore, Figure 3 It means Figure 2 A block diagram illustrating a specific example of the multiple planes within the structure.

[0048] The non-volatile memory 2 includes a logic control circuit 21, an input / output circuit 22, a register 26, a sequence generator 27, a voltage generation circuit 28, a MUX switch 29, input / output pad groups 32, logic control pad groups 34, power input terminal groups 35, and multiple planes PB0, PB1, ... (hereinafter, without distinguishing between these planes PB0, PB1, ..., they are referred to as planes PB). Furthermore... Figure 2 The example shown is that the number of planes in plane PB is 4, but the number of planes in non-volatile memory 2 is not limited to this. For example, the number of planes in non-volatile memory 2 can also be 2, 3, 8, 16, etc.

[0049] In order to transmit and receive signals containing data with the memory controller 1, the input / output pad group 32 has multiple terminals (pads) corresponding to the signal DQ<7:0> and the data strobe signals DQS and / DQS.

[0050] In order to transmit and receive various signals with the memory controller 1, the logic control pad group 34 has multiple terminals (pads) corresponding to the chip start signal / CE, instruction latch start signal CLE, address latch start signal ALE, write start signal / WE, read start signal RE, / RE, write protection signal / WP, and ready / busy signal R / B.

[0051] Signals beginning with the symbol " / " indicate active low or negative logic. In other words, signals without the " / " symbol are active at "H" level, while signals with the " / " symbol are active at "L" level.

[0052] The / CE signal selects non-volatile memory 2. The CLE signal latches the instruction sent as the DQ signal into the instruction register. The ALE signal latches the address sent as the DQ signal into the address register. The / WE signal enables writing. The RE and / RE signals enable reading. The / WP signal disables writing and erasing. The R / B signal indicates whether non-volatile memory 2 is in a ready state (able to accept commands from external sources) or a busy state (unable to accept commands from external sources). Memory controller 1 can know the status of non-volatile memory 2 by receiving the R / B signal.

[0053] To supply various operating power sources to the non-volatile memory 2 from an external source, the power input terminal group 35 has multiple terminals for input power supply voltages Vcc, VccQ, Vpp, and ground voltage Vss. The power supply voltage Vcc is the circuit power supply voltage typically supplied externally as the operating power source, for example, a voltage of approximately 3.3V. The power supply voltage VccQ is, for example, a voltage of 1.2V. The power supply voltage VccQ is used when transmitting and receiving signals between the memory controller 1 and the non-volatile memory 2. The power supply voltage Vpp is a higher voltage than the power supply voltage Vcc, for example, a voltage of 12V.

[0054] The logic control circuit 21 and the input / output circuit 22 are connected to the memory controller 1 via a NAND bus. The input / output circuit 22 transmits and receives signals DQ (e.g., DQ0 to DQ7) with the memory controller 1 via the NAND bus.

[0055] The logic control circuit 21 receives external control signals (e.g., latch start signal / CE, instruction latch start signal CLE, address latch start signal ALE, write start signal / WE, read start signal RE, / RE, and write protection signal / WP) from the memory controller 1 via the NAND bus. Furthermore, the logic control circuit 21 sends a ready / busy signal R / B to the memory controller 1 via the NAND bus.

[0056] Register 26 includes an instruction register, an address register, and a status register. The instruction register temporarily stores instructions. The address register temporarily stores addresses. The status register temporarily stores data needed for the operation of the non-volatile memory 2. Register 26 is constructed, for example, from SRAM.

[0057] The sequence generator 27, which serves as the control circuit, receives instructions from the register 26 and controls the non-volatile memory 2 in sequence based on the instructions.

[0058] The voltage generation circuit 28 receives a power supply voltage from the external source of the non-volatile memory 2 and uses the power supply voltage to generate multiple voltages required for write, read, and erase operations. The voltage generation circuit 28 supplies the generated voltages to the memory cell array 23, sense amplifier 24, and row decoder 25 within the planar PB via the MUX switch 29.

[0059] Each plane PB has a memory cell array 23. The memory cell array 23 has multiple blocks. Each block BLK has multiple memory cell transistors (memory cells). In order to control the voltage applied to the memory cell transistors, the memory cell array 23 is provided with multiple bit lines, multiple word lines, and source lines.

[0060] Figure 3 The planes PB0 to PB3 shown have the same configuration, and each plane PB has a memory cell array 23, a sense amplifier 24 and a row decoder 25.

[0061] The row decoder 25 receives the row address from the register 26 and decodes the row address. Based on the decoded row address, the row decoder 25 performs word line selection. Furthermore, the row decoder 25 transmits multiple voltages required for write, read, and erase operations to the selected block.

[0062] The sense amplifier 24 receives the column address from the register 26 and decodes the column address. The sense amplifier 24 has a group of sense amplifier units 24A connected to each bit line, which selects any bit line based on the decoded column address. Furthermore, when reading data, the group of sense amplifier units 24A detects the data read from the memory cell transistor to the bit line and amplifies it. Additionally, when writing data, the group of sense amplifier units 24A writes data to the bit line.

[0063] The sensing amplifier 24 has a data register 24B. When reading data, the data register 24B temporarily stores the data detected by the sensing amplifier unit group 24A and serially transmits it to the input / output circuit 22. Furthermore, when writing data, the data register 24B temporarily stores the data serially transmitted from the input / output circuit 22 and transmits it to the sensing amplifier unit group 24A. The data register 24B is constructed using SRAM or the like.

[0064] The voltages used by the memory cell array 23, sense amplifier 24, and row decoder 25 during writing and reading are generated in the voltage generation circuit 28. That is, the voltage generation circuit 28 generates various voltages required for writing, reading, and erasing, and outputs them to the MUX switch 29. The MUX switch 29 switches which wiring is supplied with the various voltages generated by the voltage generation circuit 28 according to the order of writing and reading.

[0065] (Block structure of a memory cell array)

[0066] Figure 4 This is a diagram showing the equivalent circuit of the block BLK of the NAND memory cell array 23, which is a 3D structure of the non-volatile memory 2 in this embodiment. Figure 4 This represents one block BLK among the multiple blocks that make up the memory cell array 23. The other blocks in the memory cell array also have the same characteristics. Figure 4 The same structure. Furthermore, this embodiment can also be applied to 2D memory cell arrays.

[0067] As shown in the figure, block BLK contains, for example, four string cells SU0 to SU3 (hereinafter, these are referred to as string cells SU). Furthermore, each string cell SU has a NAND string NS, which contains multiple memory cell transistors MT (MT0 to MT7) and select gate transistors ST1 and ST2. Additionally, the number of memory cell transistors MT included in the NAND string NS is... Figure 4 There are typically eight gate transistors, but more can be used. The select-gate transistors ST1 and ST2 are represented as a single transistor in the circuit, but their construction can be identical to that of the memory cell transistors. Alternatively, multiple select-gate transistors can be used separately as select-gate transistors ST1 and ST2. Furthermore, a dummy cell transistor can be placed between the memory cell transistor MT and the select-gate transistors ST1 and ST2.

[0068] The memory cell transistor MT is configured in series between the select gate transistors ST1 and ST2. The memory cell transistor MT7 on one end (bit line side) is connected to the select gate transistor ST1, and the memory cell transistor MT0 on the other end (source line side) is connected to the select gate transistor ST2.

[0069] The gates of the select gate transistors ST1 in each of the series units SU0 to SU3 are connected to select gate lines SGD0 to SGD3 (hereinafter, these are referred to as select gate lines SGD). Furthermore, the gates of the select gate transistors ST2 in each of the series units SU0 to SU3 are connected to select gate lines SGS0 to SGS3 (hereinafter, these are referred to as select gate lines SGS). Additionally, the gates of the multiple select gate transistors 2 within each BLK block can also be connected to a common select gate line SGS.

[0070] Within the same BLK, the gates of memory cell transistors MT0 to MT7 are all connected to word lines WL0 to WL7. That is, word lines WL0 to WL7 are shared among multiple string cells SU0 to SU3 within the same BLK. Correspondingly, the select gate line SGD is also independent for each string cell SU0 to SU3 within the same BLK. Within the BLK, the gates of memory cell transistors MTi in the same row are connected to the same word line WLi.

[0071] Each NAND string NS is connected to its corresponding bit line. Therefore, each memory cell transistor MT is connected to the bit line via the select gate transistor ST1, ST2, or other memory cell transistor MT contained in the NAND string NS. Generally, the data of the memory cell transistors MT within the same BLK is erased together. On the other hand, typically, multiple memory cell transistors MT that share a word line WL disposed on a single string cell SU are read and written together. This group of memory cell transistors MT that share a word line WL within a single string cell SU is called a memory cell group MG.

[0072] Write and read operations on the memory cell group MG are performed on a page-by-page basis. For example, if each cell is a TLC (Triple Level Cell) capable of storing 3 bits (8 values) of data, one memory cell group MG can store 3 pages of data. The 3 bits that can be stored by the transistor MT of each memory cell correspond to the 3 pages respectively.

[0073] Figure 5 This diagram illustrates an example of the configuration of a block BLK of a 3D NAND memory cell array 23 in the non-volatile memory 2 of this embodiment. Figure 5 This represents one block BLK among the multiple blocks that make up the memory cell array 23. The other blocks in the memory cell array also have the same characteristics. Figure 5 Same composition.

[0074] More specifically, Figure 5 This is a partial cross-sectional view of the block BLK of the NAND memory cell array 23 in the non-volatile memory 2 of this embodiment. (See attached image.) Figure 5 As shown, transistors, such as a sense amplifier 24 or a row decoder 25, which are included in peripheral circuits, are formed on the semiconductor substrate 601, and memory cell transistors included in the memory cell array 23 are formed on the upper layer thereon. In the following description, the two directions orthogonal to the surface of the semiconductor substrate 601 are designated as the x-direction and the y-direction, and the direction perpendicular to the surface of the semiconductor substrate 601 is designated as the z-direction.

[0075] Figure 5The p-type or n-type well regions formed on the upper surface of the semiconductor substrate 601, the impurity diffusion regions formed in each well region, and the element separation regions that insulate between the well regions are not shown in the diagram. A conductor GC is disposed on the semiconductor substrate 601 as a gate insulating film (not shown). Furthermore, multiple contacts 661 are provided in multiple impurity diffusion regions (not shown) of the semiconductor substrate 601, sandwiching the conductor GC. Multiple conductors 641, which are wiring patterns, are connected to the multiple contacts 661. For example, the conductor GC functions as the gate electrode of a transistor, and the conductors 641 function as the source electrode or drain electrode of a transistor.

[0076] For example, a contact 662 is provided on conductor 641, and conductor 642, which serves as a wiring pattern, is connected to contact 662. A contact 663 is provided on conductor 642, and conductor 643, which serves as a wiring pattern, is connected to contact 663. The wiring layers on which conductors 641, 642, and 643 are provided are referred to as wiring layers D0, D1, and D2, respectively. Wiring layers D0, D1, and D2 are provided in the lower layer of the non-volatile memory 2. Furthermore, the wiring layers provided in the lower layer of the non-volatile memory 2 are not limited to three layers. They may consist of two or fewer wiring layers, or they may consist of four or more wiring layers.

[0077] Above conductor 643, conductor 644 is disposed with a dielectric, such as an interlayer insulating film (not shown). Conductor 644 is formed into a plate shape, for example, parallel to the xy plane, and functions as a source line SL. Above conductor 644, conductors 645 to 654 are sequentially deposited in the z direction, for example with an interlayer insulating film (not shown).

[0078] Conductors 645 to 654 are each formed as, for example, a plate parallel to the xy plane. For example, conductor 645 functions as the select gate line SGS, conductors 646 to 653 function as word lines WL0 to WL7 respectively, and conductor 654 functions as the select gate line SGD.

[0079] A columnar memory pillar 634 is provided in such a way that it contacts each conductor 645-654. The memory pillar 634 includes, for example: a semiconductor layer 638 on the center side; a tunnel insulating film 637 formed on the outside of the semiconductor layer 638; a charge accumulation film 636 formed on the outside of the tunnel insulating film 637; and a barrier insulating film 635 formed on the outside of the charge accumulation film 636. The portions of the memory pillar 634 that intersect with each conductor 646-654 function as memory cell transistors (MT). Furthermore, the portions of the memory pillar 634 that intersect with each conductor 645, 654 function as select transistors (ST).

[0080] Above the upper surface of the memory pillar 634, a conductor 655 is disposed on an interlayer insulating film (not shown). The conductor 655 is formed as a line extending in the x-direction and functions as a bit line BL. A plurality of conductors 655 are arranged at open intervals in the y-direction. The conductors 655 are electrically connected to the semiconductor layer 638 within one memory pillar 634 corresponding to each string cell SU via contact plugs CP.

[0081] Specifically, in each string cell SU, for example, a contact plug CP is provided on the semiconductor layer 638 within each memory hole 634, and a conductor 645 is provided on the contact plug CP. Alternatively, the configuration is not limited to this; for example, the semiconductor layer 638 and the conductor 645 may be further connected via multiple contacts or wiring.

[0082] Above the layer where the conductor 655 is disposed, an interlayer insulating film (not shown) is provided with a conductor 656. Above the layer where the conductor 656 is disposed, an interlayer insulating film (not shown) is provided with a conductor 657.

[0083] Conductors 656 and 657 function as wiring, for example, to connect the wiring disposed in the memory cell array 23 to the wiring of the peripheral circuitry disposed in the lower layer of the memory cell array 23. The layers on which conductors 655, 656, and 657 are disposed are referred to as wiring layers M0, M1, and M2, respectively.

[0084] (Write action)

[0085] The process of writing data to a memory cell MT generally includes programming and verification. Programming involves injecting electrons into the charge accumulation film to raise the threshold voltage of the memory cell MT (or maintaining the threshold voltage by disabling electron injection).

[0086] Figure 6 This is a diagram showing the potential changes of each wire during the write operation (programming operation). Voltage generation circuit 28 generates... Figure 6 The various voltages shown are controlled by the MUX switch 29, which is controlled by the sequence generator 27. Figure 6 The various voltages shown are assigned to each wiring.

[0087] Programming operations are performed based on the programming voltages and bit line voltages applied to the word lines and bit lines. For example... Figure 6 As shown, the character line is not aligned ( Figure 6 The block BLK for which the programming voltage VPGM is applied (selected WL, non-selected WL) is the non-selected BLK that is not the object to be written. Figure 6(Next paragraph). Furthermore, since the bit line voltage is applied to the memory cell transistor MT by turning on the select gate transistor ST1 connected to the bit line BL, the string cells SU in the block BLK (select block BLK) for which the voltage to turn on the select gate transistor ST1 is not applied to the select gate line SGD; these are non-select SUs not for which the write target is located. Figure 6 (Middle section). Also, regarding the non-selection of SU when choosing BLK ( Figure 6 Alternatively, before applying the programming voltage VPGM, the select gate line SGD can be set to, for example, 5V, to turn on the select gate transistor ST1.

[0088] Regarding the block BLK (select BLK) of the written object, the string unit SU (select SU) of the written object (select SU) Figure 6 (Upper section), before applying the programming voltage VPGM, such as Figure 6 As shown on the left side of the upper section, the select gate line SGD is set to, for example, 5V, turning on the select gate transistor ST1. Furthermore, during programming, the select gate line SGS is, for example, 0V. Therefore, the select gate transistor ST2 is in the off state. On the other hand, applying... Figure 6 When the programming voltage VPGM is shown on the right side of the upper section, the select gate line SGD is set to, for example, 2.5V. Therefore, the on / off state of the select gate transistor ST1 is determined by the bit line voltage connected to the bit line BL of the select gate transistor ST1.

[0089] As described above, the sense amplifier 24 transmits data to each bit line BL. For the bit line BL provided with "0" data, a ground voltage Vss of, for example, 0V is applied as the bit line voltage Vbl_L. For the bit line BL provided with "1" data, a write-inhibit voltage Vinhibit (e.g., 2.5V) is applied as the bit line voltage Vbl_H. Therefore, when the programming voltage VPGM is applied, the select gate transistor ST1 connected to the bit line BL provided with "0" data is turned on, and the select gate transistor ST1 connected to the bit line BL provided with "1" data is turned off. The memory cell transistor MT connected to the turned-off select gate transistor ST1 is disabled from writing.

[0090] The memory cell transistor MT connected to the select gate transistor ST1, which is in the ON state, injects electrons into the charge accumulation film according to the voltage applied to the word line WL. The memory cell transistor MT connected to the word line WL (non-select WL) where the word line voltage VPASS is applied, is in the ON state regardless of the threshold voltage, but does not inject electrons into the charge accumulation film. On the other hand, the memory cell transistor MT connected to the word line WL (select WL) where the word line voltage VPGM is applied, injects electrons into the charge accumulation film according to the programming voltage VPGM. In other words, the row decoder 25 selects any word line WL in the select block BLK, applies the programming voltage VPGM to the selected word line (select WL), and applies the voltage VPASS to the other word lines (non-select WL). The programming voltage VPGM is a high voltage used to inject electrons into the charge accumulation film through tunneling; VPGM > VPASS. The row decoder 25 controls the voltage of the word line WL, while the sense amplifier 24 supplies data to each word line BL, thereby performing the writing operation (programming operation) of each memory cell transistor MT in the memory cell array 23. In addition, for the select block BLK, the block select signal BLKSEL with voltage VPGMH is supplied to the row decoder 25.

[0091] Figure 7 It is a circuit diagram that represents the state of the string during programming actions. Figure 7 The diagram shows the two NAND strings corresponding to bit line BL for writing "0" and bit line BL for writing "1". Additionally, it shows the state when word line WL3 is selected.

[0092] As shown in the figure, a voltage VPGM is applied to the select word line WL3, and a voltage VPASS is applied to the non-select word lines WL0-WL2 and WL4-WL7. Furthermore, in the NAND string corresponding to the bit line BL where "0" is written, the select transistor ST1 is turned on. Therefore, the channel potential Vch of the memory cell transistor MT3 connected to the select word line WL3 becomes 0V. That is, the potential difference between the control gate and the channel increases, resulting in electron injection into the charge accumulation layer, and the threshold voltage of the memory cell transistor MT3 rises.

[0093] In the NAND string corresponding to the bit line BL of the "1" write target, the select transistor ST1 becomes off. Therefore, the channel electrical diffusion of the memory cell transistor MT3 connected to the select word line WL3 causes the channel potential Vch to rise to near the voltage VPGM due to capacitive coupling with word lines WL, etc. In other words, the potential difference between the control gate and the channel decreases, resulting in no electron injection into the charge accumulation layer, maintaining the threshold voltage of the memory cell transistor MT3 (the threshold voltage does not change to the point where the threshold voltage distribution level becomes higher).

[0094] (Threshold voltage distribution)

[0095] When writing multi-valued data to a memory cell transistor MT, the threshold voltage of the memory cell transistor MT is set to the value corresponding to the data value. If a programming voltage VPGM and a bit line voltage Vbl are applied to the memory cell transistor MT, electrons are injected into the charge accumulation film of the memory cell transistor MT, and the threshold voltage rises. By increasing the programming voltage VPGM, the amount of electron injection can be increased, thus raising the threshold voltage of the memory cell transistor MT. However, due to variations in the memory cell transistor MT, even when the same programming voltage VPGM is applied, the amount of electron injection varies from memory cell transistor MT to memory cell transistor MT. The temporarily injected electrons are retained until an erase operation is performed. Therefore, as described later, the programming voltage VPGM is gradually increased in a manner that falls within the allowable threshold voltage range set for each memory cell transistor MT, and multiple programming and verification operations (loops) are performed. The verification operation is a read operation performed as part of the write operation.

[0096] Figure 8 It is a graph that shows the threshold voltage on the horizontal axis and the number of transistors (cells) in the memory cell array on the vertical axis. Figure 8 The diagram illustrates an example of the threshold distribution for a 3-bit / cell non-volatile memory 2. In the non-volatile memory 2, the threshold voltage of the storage cell transistor MT is set based on the data values ​​of the multi-valued data stored in the storage cell transistor MT. Since the amount of charge injected into the charge accumulation film (charge storage region) is probabilistic, as shown... Figure 8 As shown, the threshold voltages of the transistors MT in each memory cell also exhibit a statistical distribution.

[0097] Figure 8 The threshold distribution is represented by dividing it into eight mountain-shaped regions: Er level, A level, B level, C level, ..., G level. The width of the threshold voltage in each region corresponds to the width of each target region. Figure 8 In the example, by setting the threshold voltage of the memory cell transistor MT in any of the eight target regions, the memory cell transistor MT can store 8 values ​​of data (3 bits of data).

[0098] In this embodiment, the threshold voltage Vth is... Figure 8 The target region with a threshold voltage below VrA is called the Er level; the target region with a threshold voltage greater than VrA but less than VrB is called the A level; the target region with a threshold voltage greater than VrB but less than VrC is called the B level; and the target region with a threshold voltage greater than VrC but less than VrD is called the C level. The same applies below. Figure 8As shown, the D level is set to the G level according to each voltage.

[0099] In other words, the level indicates which target region corresponds to the data value stored in the transistor MT of each memory cell. In the case of 3 bits and 8 values, the target region is divided into 8 levels: Er, A to G. Voltages VrA to VrG are reference voltages that form the boundaries of each target region. In addition, during the verification operation, voltages VrA to VrG can be used as verification levels (voltages), applied to the word line WL and read out. By disconnecting the target memory cell transistor MT, it is determined that the threshold voltage corresponding to the level has been reached.

[0100] Various methods can be used as encoding methods to correspond data values ​​to the levels (i.e., threshold distributions) of the storage cell transistors. Figure 9 This is an example of encoding, illustrating the 2-3-2 encoding. Figure 9 This indicates the values ​​of the UPPER, MIDDLE, and LOWER bits relative to the data at each threshold distribution.

[0101] Figure 9 In the example, it is shown that the Er level memory cell transistor stores data (1, 1, 1), the A level memory cell transistor stores data (1, 1, 0), the B level memory cell transistor stores data (1, 0, 0), the C level memory cell transistor stores data (0, 0, 0), the D level memory cell transistor stores data (0, 1, 0), the E level memory cell transistor stores data (0, 1, 1), the F level memory cell transistor stores data (0, 0, 1), and the G level memory cell transistor stores data (1, 0, 1).

[0102] The data groups of the upper, middle, and lower levels of each memory cell transistor are respectively referred to as UPPER pages, MIDDLE pages, or LOWER pages. Generally, reads are performed in units of these pages.

[0103] Assuming the read operation involves determining which of the three bits of data stored in each memory cell transistor is being read, rather than a page-level read, the read voltage applied to the select word line WL needs to be varied from voltage VrA to voltage VrG a maximum of seven times. In contrast, for a page-level read, the voltage can be varied only two or three times.

[0104] For example, when reading the UPPER page value of each memory cell transistor, the readout voltage only needs to be changed from voltage VrC to voltage VrG a maximum of two times. For example, when the readout voltage VrC is applied to the readout of the select word line WL, and the sense amplifier 24 determines that the memory cell transistor to be read is in the on state, the UPPER page of the memory cell transistor to be read can be determined to be "1".

[0105] Furthermore, for example, if the readout voltage VrC is applied to the readout of the select word line WL, and the sense amplifier 24 determines that the memory cell transistor to be read is in a non-conducting state, then the readout voltage VrG is read out. As a result, if the sense amplifier 24 determines that the memory cell transistor to be read is in a conducting state, the UPPER page of the memory cell transistor to be read can be determined to be "0", and if it is determined to be in a non-conducting state, the UPPER page of the memory cell transistor to be read can be determined to be "1".

[0106] in this way, Figure 9 In the 2-3-2 encoding, the read voltage changes a maximum of 2 times on the UPPER page, a maximum of 3 times on the MIDDLE page, and a maximum of 2 times on the LOWER page, thus enabling reading. Additionally, Figure 10 The encoding shown is Gray code, which is a code where only one bit of data changes between any two adjacent regions.

[0107] Figure 10 This is a diagram used to illustrate an example of the standard write order. Figure 10 The example described uses a case where data is written by repeating a combination of programming and verification (programming verification) actions 19 times. This repeated action is referred to as a "loop". The programming voltage VPGM is set to the lowest value in the first loop, and gradually increased to a higher value in the second, third, and subsequent loops. Figure 10 The circular markers indicate loops where programming verification actions can be performed. Furthermore, in each A-G level, the programming action proceeds at most up to the loop containing the circular marker, starting from the first loop. Hereinafter, the nth loop from the 1st to the 19th loop will be referred to as the nth loop.

[0108] For example, for a memory cell MT set to level B, programming may be performed by gradually increasing the programming voltage VPGM from cycle 1 to cycle 8. Programming verification is only performed in the cycles marked with circles. For memory cells MT that pass the programming verification and are determined to have reached the set target voltage, subsequent writing is prohibited.

[0109] Figure 11This is an explanatory diagram showing the standard write action sequence in a write operation. Figure 11 The horizontal axis represents time, and the vertical axis represents voltage. This indicates the change in the programming voltage VPGM during write operations based on the standard write sequence, and the timing of both the programming and verification operations. In other words, Figure 11 This example illustrates a write sequence for 19 cycles that involve changing the programming voltage VPGM 19 times. The write sequence for each plane PB is implemented synchronously.

[0110] like Figure 11 As shown, in the standard write sequence, the programming voltage VPGM applied to the select word line WL is increased sequentially in each cycle. Furthermore, in each cycle, a verification operation is performed on at least one state to determine whether the threshold voltage Vth of each memory cell MT in the write result has reached a value higher than the verification voltage. Figure 11 In the example, the program ultimately performs a maximum of 19 loops, with 19 programming actions (VPGM1 to VPGM19) and 42 verification actions (VrA to VrG).

[0111] (MUX switch)

[0112] Figure 12 It means Figure 2 A block diagram consisting of a voltage generation circuit 28 and a portion of a MUX switch 29. Figure 12 Only the VPGM generation circuit 40 and VPASS generation circuit 46, which constitute the voltage generation circuit 28, are shown, as well as the circuits that constitute the MUX switch 29. Figure 12 The circuit portion corresponding to the voltage generation circuit 28 shown.

[0113] The VPGM generation circuit 40 of the voltage generation circuit 28 generates voltage VPGM from output node N, and the VPASS generation circuit 46 generates voltage VPASS. The MUX switch 29 has multiple switches T01-T02, T11-T12, ..., T71-T72, and switch T00, all composed of transistors. The programming voltage VPGM from the VPGM generation circuit 40 is supplied to switches T01, T11, ..., T71, and the voltage VPASS from the VPASS generation circuit 46 is supplied to switches T02, T12, ..., T72. Switches T01-T02, T11-T12, ..., and T71-T72 are respectively connected to signal lines CG0, CG1, ..., CG7 (described later). Switches T01-T02 correspond to the switching switch 29B that supplies voltage to signal line CG0. Switches T11-T12 correspond to the switching switch 29B that supplies voltage to signal line CG1. Switches T71 to T72 correspond to switch 29B, which supplies voltage to signal line CG7.

[0114] The VPGM generation circuit 40 generates a voltage VPGMH from the output node P and supplies the voltage VPGMH to the block decoder 25B (described later) via switch T00.

[0115] Switches T01~T02, switches T11~T12, ... and switches T71~T72 are controlled by sequence generator 27, which supplies programming voltages VPGM and VPASS to signal lines CG0~CG7.

[0116] (Line decoder)

[0117] Figure 13 It means Figure 2 A block diagram illustrating an example of the configuration of the row decoder 25.

[0118] Figure 13 In the MUX switch 29, there are three switching switches 29A, 29B, and 29C. Switch 29A supplies voltages from voltage generation circuit 28 to signal lines SG0 to SG4 respectively. Furthermore, multiple switching switches 29B are equivalent to... Figure 12 Switches T01-T71 and T02-T72 supply voltage from voltage generation circuit 28 to signal lines CG0-CG7 respectively. Furthermore, switch 29C is equivalent to... Figure 12 The switch T00 supplies the voltage VGMH from the voltage generation circuit 28 to the block decoder 25B.

[0119] Signal lines SG0-SG4 and CG0-CG7 branch through row decoder 25 and connect to the wiring of each BLK block. That is, signal lines SG0-SG3 function as global drain-side select gate lines, connected via row decoder 25 to the select gate lines SGD0-SGD3 in each BLK block as local select gate lines. Signal lines CG0-CG7 function as global word lines, connected via row decoder 25 to the word lines WL0-WL7 in each BLK block as local word lines. Signal line SG4 functions as a global source-side select gate line, connected via row decoder 25 to the select gate line SGS in each BLK block as a local select gate line.

[0120] The voltage generation circuit 28, controlled by the sequence generator 27, generates various voltages. Switches 29A and 29B supply the generated voltages to the corresponding signal lines SG0-SG4 and CG0-CG7, respectively. For example, each switch 29B selects and supplies voltages such as VCGRV, VREAD, and VCG_RE to the corresponding word line WL based on the action object (row address) in the read operation.

[0121] The row decoder 25 has multiple switch circuit groups 25A corresponding to each block, and multiple block decoders 25B corresponding to the multiple switch circuit groups 25A. Each switch circuit group 25A includes: multiple transistors TR_SG0 to TR_SG3 connected to signal lines SG0 to SG3 and select gate lines SGD0 to SGD3 respectively; multiple transistors TR_CG0 to TR_CG7 connected to signal lines CG0 to CG7 and word lines WL0 to WL7 respectively; and transistor TR_SG4 connected to signal line SG4 and select gate line SGS. Transistors TR_SG0 to TR_SG4 and transistors TR_CG0 to TR_CG7 are each high-voltage resistant transistors.

[0122] When each block decoder 25B is specified by the row address, it supplies the block selection signal BLKSEL to the gates of transistors TR_SG0 to TR_SG4 and transistors TR_CG0 to TR_CG7. As a result, in the switching circuit group 25A that supplies the block selection signal BLKSEL from the block decoder 25B specified by the row decoder, transistors TR_SG0 to TR_SG4 and transistors TR_CG0 to TR_CG7 are turned on and conducted. Therefore, the voltage supplied from the power generation circuit 28 to the signal lines SG0 to SG4 and signal lines CG0 to CG7 is supplied to the selection gate lines SGD0 to SGD3, SGS and word lines WL0 to WL7 contained in the block BLK that is to be operated.

[0123] In other words, the voltage generation circuit 28, the MUX switch 29, and the row decoder 25 supply various voltages required for operation to each word line WL. Furthermore, for example, voltage VSGD is supplied to the select gate line SGD (SGDsel) connected to the select gate transistor ST1 belonging to the serial unit SU that is to be operated; voltage Vss is supplied to the select gate line SGD (SGDusel) connected to the select gate transistor ST1 that is not to be operated; and voltage VSGS is supplied to the select gate line SGS that is uniformly connected to the select gate transistor ST2 by each BLK block.

[0124] However, in order to turn on the transistors of the switching circuit group 25A, the block decoder 25B needs to generate a block selection signal BLKSEL with a voltage higher than the voltage VPGM. The block decoder 25B uses the voltage VGMMH supplied from the MUX switch 29 to generate this high-voltage block selection signal BLKSEL. The voltages VGMMH and VPGM are generated by the VPGM generation circuit 40 in the voltage generation circuit 28.

[0125] (Voltage generation circuit)

[0126] Figure 14 It indicates composition Figure 12A block diagram illustrating an example of the specific configuration of the VPGM generation circuit 40 within the voltage generation circuit 28. Figure 15 It means Figure 14 The circuit diagram shows an example of the specific configuration of the charge pump circuit 41 in the circuit.

[0127] The block control circuit 42 generates a clock signal CLK and its inverted signal, / CLK. The clock control circuit 42 supplies the complementary clock signals CLK and / CLK to the charge pump circuit 41. The charge pump circuit 41 uses the clock signals CLK and / CLK supplied from the clock control circuit 42 to generate a specific voltage VOUT.

[0128] like Figure 15 As shown, the charge pump circuit 41 includes n+1 NMOS transistors NT1, NT2, ..., NTn, NTn+1 and n capacitors C1 to Cn. Furthermore, the number n of the NMOS transistors and capacitors in the charge pump circuit 41 can be appropriately set.

[0129] NMOS transistors NT1 to NTn+1 are connected as diodes, functioning as diodes. The current paths of NMOS transistors NT1 to NTn+1 are connected in series sequentially. One end of capacitors C1 to Cn is electrically connected to one end of the current path output side of NMOS transistors NT1 to NTn. The other end of capacitors C1, C3, C5, ... is supplied with the clock signal CLK, and the other end of capacitors C2, C4, C6, ... is supplied with the clock signal / CLK.

[0130] A voltage VSUP (e.g., power supply voltage VDD) is supplied to one end of the current path input side of NMOS transistor NT1. Furthermore, capacitors C1 to Cn are repeatedly charged and discharged using clock signals CLK and / CLK, for example, with an amplitude equal to the power supply voltage VDD, thereby boosting the input voltage VSUP and sequentially transmitting it to the next stage. As a result, an output voltage VOUT greater than VSUP is generated on the current path output side of transistor NTn+1.

[0131] The charge pump circuit 41 can generate different voltage levels at each stage of the diode-connected NMOS transistor. The voltage generation circuit 28 generates the various voltages required for writing and reading from the output of the charge pump circuit 41.

[0132] Figure 14The diagram shows the VPGM generation circuit 40, which generates the programming voltage VPGM using the output of the charge pump circuit 41, within the voltage generation circuit 28. The output VOUT of the charge pump circuit 41 is supplied as the voltage VGMMH to the output circuit 43. A voltage difference generation circuit 45 is connected to the output circuit 43 along a current path for generating the voltage difference between the power supply line to which the supplied voltage VGMMH is located and the output node N. The voltage difference generation circuit 45 generates a voltage difference ΔV between the output terminal of the charge pump circuit 41 and the output node N. Alternatively, the circuit for generating the voltage difference can, for example, use two NMOS transistors connected in series with diodes connected in a current path.

[0133] Between the output node N and the reference potential point, the current path of NMOS transistor NM13, resistor R1, variable resistor R2, and the current path of NMOS transistor NM14 are connected in series. The connection point of resistors R1 and R2 is connected to one input terminal of comparator 44. A reference voltage VREF is applied to the other input terminal of comparator 44. During the period when the voltage at the connection point of resistors R1 and R2 is higher than the reference voltage VREF, comparator 44 outputs a stop signal to clock control circuit 42. During the period when clock control circuit 42 outputs the stop signal from comparator 44, it stops generating clock signals CLK and / CLK. The limiting circuit is composed of transistors NM13 and NM14, resistors R1 and R2, and comparator 44.

[0134] Transistors NM13 and NM14 are turned on when they are supplied with control signals (not shown) from sequence generator 27 and function as limiting circuits. During the period when transistors NM13 and NM14 are on, the voltage appearing at output node N is divided by resistors R1 and R2. The voltage at the junction of resistors R1 and R2 is compared with a reference voltage VREF in comparator 44. The reference voltage VREF is set to the voltage at the junction of resistors R1 and R2 when the voltage at output node N is the specified programming voltage VPGM.

[0135] Therefore, if the voltage at output node N exceeds the specified programming voltage VPGM, the voltage at the connection point of resistors R1 and R2 will be higher than the reference voltage VREF, and a stop signal will be generated from comparator 44. Based on this stop signal, clock control circuit 42 will stop generating clock signals CLK and / CLK. As a result, the output voltage of charge pump circuit 41 will decrease, suppressing the voltage rise at output node N, and maintaining the voltage at output node N at the specified programming voltage VPGM. Furthermore, if the voltage at output node N is lower than the specified programming voltage VPGM, the same action will cause the voltage at output node N to rise, maintaining the voltage at the specified programming voltage VPGM.

[0136] In other words, the feedback loop, consisting of charge pump circuit 41, voltage difference generation circuit 45, transistors NM13 and NM14, resistors R1 and R2, comparator 44, and clock control circuit 42, can determine the voltage VPGM through the voltage divider control of resistors R1 and R2. To obtain the voltage VPGM, the output voltage of charge pump circuit 41 changes, resulting in a voltage VGMMH that is ΔV higher than VPGM.

[0137] The voltage VGMH generated from the output terminal of the charge pump circuit 41 (hereinafter referred to as node P) is supplied to the block decoder 25B. The higher the voltage VGMH is than the voltage VPGM, that is, the larger the differential voltage ΔV generated by the voltage difference generation circuit 45, the lower the on-resistance of the transistors in the switching circuit group 25A. On the other hand, considering the voltage withstand capability of the transistors in the switching circuit group 25A, the differential voltage ΔV generated by the voltage difference generation circuit 45 has an upper limit.

[0138] Figure 16 This is a circuit diagram representing a comparative example of the voltage difference generating circuit 45, namely the voltage difference generating circuit 45A.

[0139] Figure 16 The voltage difference generation circuit 45A shown consists of two layers of diode-connected transistors. The current paths of NMOS transistors NM11 and NMOS transistor NM12 are connected in series between node P, where voltage VGMH occurs, and the output node N. The drain and gate of transistor NM11 are connected to node P. The drain and gate of transistor NM12 are connected to the source of transistor NM11, and the source is connected to the output node N. In other words, transistors NM11 and NM12 are diode-connected, generating a voltage difference ΔV between node P and the output node N based on the forward voltages of transistors NM11 and NM12. Furthermore, to sufficiently reduce the on-resistance of each transistor in the switching circuit group 25A, the voltage difference ΔV needs to be set to a sufficiently large value; for example, by connecting two layers of diode-connected transistors to obtain the voltage difference ΔV.

[0140] However, the differential voltage ΔV is determined by the Vgs (gate-source voltage) - Id (drain current) characteristics of the diode-connected transistors NM11 and NM12, and the current flowing through the diode-connected transistors NM11 and NM12. The larger the drain voltage Id, the larger the differential voltage ΔV. When the load on the memory cell array 23 side is large, the current supplied from the charge pump circuit 41 also increases, resulting in a temporary increase in ΔV. For example, when multiple planes are driven by the voltage difference generation circuit 45A, the current supplied from the charge pump circuit 41 also increases, resulting in a temporary increase in ΔV. As a result, the voltage VGMH at node P becomes larger than required relative to the voltage VGMH at node N, raising concerns about applying a relatively large voltage exceeding the withstand voltage to the gates of the transistors in the switching circuit group 25A.

[0141] To prevent the aforementioned problem, there is a method of increasing the transistor size of diode-connected transistors NM11 and NM12. If this method is used, even if the drain current Id increases, the differential voltage ΔV can be kept relatively small, thus preventing the voltage VGMH at node P from exceeding the required value relative to the voltage VGMH at node N. However, in this method, because the area of ​​diode-connected transistors NM11 and NM12 increases, the circuit area of ​​the voltage generation circuit 28 increases, and consequently, the chip area used to construct the non-volatile memory 2 also increases.

[0142] (Voltage difference generation circuit)

[0143] Therefore, in this embodiment, the voltage difference generating circuit 45 is configured as follows: in addition to the current path of the transistor connected by the diode, which generates two voltages with a voltage difference at both ends, a bypass current path is also provided, and a bypass current source is configured in the bypass current path.

[0144] In addition, in this specification, "transistor" refers not only to a single physical transistor, but also to a transistor consisting of multiple transistors connected in parallel.

[0145] Figure 17 This is a circuit diagram illustrating an example of the specific configuration of the voltage generation circuit 45.

[0146] At the output terminal (node ​​P) of charge pump circuit 41, the output voltage VPGMH of charge pump circuit 41 appears. The current path of NMOS transistor NM21 and the current path of NMOS transistor NM22 are connected in series between node P and output node N. The drain and gate of transistor NM21 are connected to node P. The drain and gate of transistor NM22 are connected to the source of transistor NM21, and the source is connected to output node N.

[0147] The current paths of transistors NM21 and NM22 connected by diodes constitute the current path for generating a voltage difference. A voltage difference ΔV is generated across this current path based on the forward voltages of transistors NM21 and NM22. An example of using two transistors NM21 and NM22 in the voltage difference generation current path is given, but the number can be one or more, depending on the desired voltage difference ΔV. Furthermore, the voltage difference ΔV is set to take into account the withstand voltage of each transistor in the 25A switching circuit group.

[0148] In this embodiment, a bypass current path is provided in parallel with the current path for generating the voltage difference between node P and output node N. The bypass current path is formed by the current path of NMOS transistor NM23, whose drain is connected to node P, source is connected to output node N, and gate is connected to the gate of transistor NM22.

[0149] The gate-source voltage of transistor NM23 is consistent with that of transistor NM22. By operating transistor NM23 in the saturation region, the ratio of the current flowing through the current path of transistor NM23 to the current flowing through the current path of transistor NM22 is approximately consistent with the transistor size ratio of NM23 and NM22. In other words, transistor NM23 functions as a bypass current source, setting the ratio of the current flowing through the bypass current path to the current flowing through the voltage difference-generated current path to a specific fixed value.

[0150] Figure 17 In one example, the transistor size of transistor NM23 is shown to be three times that of transistor NM22. As will be described later, the transistor size ratios of transistors NM21, NM22, and NM23 can be appropriately set. Figure 17 In the example, if the current flowing through output node N is set as I, then the current flowing through the bypass current path is 3 × I / 4, and the current flowing through the voltage difference generation current path is 1 × I / 4. That is to say, Figure 17 In the example, the current drive capability of transistor NM23 is 3 times that of transistor NM22, and it can set the current flowing through the voltage difference-generated current path to 1 / 3 of the current flowing through the bypass current path.

[0151] The differential voltage ΔV increases or decreases with the amount of current flowing through the current path used to generate the voltage difference. However, in this embodiment, even if the current I flowing through the output node N increases, the increase in the amount of current flowing through the current path used to generate the voltage difference can be suppressed, preventing the differential voltage ΔV from increasing beyond what is desired. Therefore, even if the current I flowing through the output node N increases, the voltage VGMH can be prevented from increasing and exceeding the withstand voltage of the transistor in the switching circuit group of 25A.

[0152] Furthermore, the area ratio of the voltage difference generating circuit 45 is [not specified]. Figure 16 The voltage difference generating circuit 45A is small. The transistor dimensions of transistors NM11 and NM12 in the voltage difference generating circuit 45A, that is, the gate width of transistors NM11 and NM12, is 1W. In this case, the current flowing through the output node N is I, and a voltage difference ΔV is generated between node P and the output node N.

[0153] On the other hand, in the voltage difference generating circuit 45 of this embodiment, the characteristics of transistors NM21 and NM22 are the same as those of transistors NM11 and NM12. Since I / 4 of the current flows in the current path of transistors NM21 and NM22, a voltage difference ΔV is generated between node P and output node N when the gate width of transistors NM21 and NM22 is W / 4. Since the gate width of transistor NM23 is 3W / 4, the total gate width of transistors NM21 to NM23 constituting the voltage difference generating circuit 45 is {(1 / 4) + (1 / 4) + (3 / 4)}W = 5W / 4.

[0154] Therefore, the ratio (size ratio) of the total gate width of transistors NM21, NM22, and NM23 in the voltage difference generating circuit 45 of this embodiment to the total gate width of transistors NM11 and NM12 in the voltage difference generating circuit 45A is (5W / 4): (2W) = 5 / 8 = 0.625. Thus, by employing... Figure 17 The voltage difference generating circuit 45 does not change the voltage difference ΔV, does not reduce the current driving capability, and can reduce the area to 62.5% compared with the voltage difference generating circuit 45A.

[0155] Furthermore, the gate voltage of transistor NM22 differs slightly from that of transistor NM23. More precisely, the ratio of the current flowing through the voltage difference-generating current path to the current flowing through the bypass current path is not the same as the ratio of the gate width of transistor NM22 to the gate width of transistor NM23. To ensure that the current flowing through the bypass current path accurately matches the ratio of the gate widths of transistors NM22 and NM23, a transistor with a diode connection (hereinafter referred to as a cascode transistor) is used in the bypass current path between node P and the gate of transistor NM23, similar to that of transistor NM23.

[0156] However, the drain voltage dependence of the current flowing through the bypass current path is relatively small, even if Figure 17The voltage difference generation circuit 45 is configured such that the ratio of the current flowing through the voltage difference generation current path to the current flowing through the bypass current path is approximately consistent with the size ratio of transistors NM22 and NM23. Furthermore, even if the ratio of the current flowing through the voltage difference generation current path to the current flowing through the bypass current path is not strictly consistent with the size ratio of transistors NM22 and NM23, the voltage difference generation circuit 45 can still set the voltage VPGMH to a sufficiently large value relative to the voltage VPGM, and prevent the voltage VPGMH from rising excessively. In other words, this embodiment, focusing on the function of the voltage difference generation circuit 45 in the non-volatile memory 2, found that the cascode transistor can be omitted, correspondingly reducing the area of ​​the voltage difference generation circuit 45 and suppressing excessively large differential voltage ΔV.

[0157] When transistor manufacturing deviations and bypass current sources are negligible, the ratio of the gate width of transistor NM23 to the gate widths of transistors NM21 and NM22 can be set to a maximum value. In this case, the areas of transistors NM21 and NM22 can be ignored compared to the area of ​​transistor NM23. By employing the voltage difference generating circuit 45 of this embodiment, the area can be reduced to 50% compared to the voltage difference generating circuit 45A.

[0158] In addition, to adjust the differential voltage ΔV, multiple diodes with current paths are sometimes connected to the transistor in parallel with the current path of the transistor NM21. In this case, the multiple transistors connected in parallel can also be configured with the same gate width as the transistor NM21, resulting in a significant area reduction.

[0159] (Transistor size ratio)

[0160] also, Figure 17 The example illustrates setting the size ratio of transistor NM23, which constitutes the bypass current source, to transistor NM22, which generates the differential voltage ΔV, to 3 / 4:1 / 4, but the size ratio only needs to be (the size of transistor NM23 constituting the bypass current source).

[0161] >(the size of transistor NM22 that generates the differential voltage ΔV), then various size ratios can be used, such as 7 / 8:1 / 8, 15 / 16:1 / 16, etc. For example, if the transistor size ratio of transistors NM21, NM22, and NM23 is 1 / 8:1 / 8:7 / 8, then the total gate width of transistors NM21 to NM23 is {(1 / 8)+(1 / 8)+(7 / 8)}W=9W / 8.

[0162] Furthermore, the transistor size of transistor NM21 can differ from that of transistor NM22. For example, the ratio of the transistor sizes of NM21 and NM22 can be set to 2 / 4:1 / 4. As long as the differential voltage ΔV can be set to an appropriate value, the smaller the transistor size of NM22 compared to the crystal dot size of NM21, the greater the current ratio between the current path used for generating the voltage difference and the bypass current path, resulting in a higher area reduction effect.

[0163] For example, if the transistor size ratio of transistors NM21, NM22, and NM23 is 1 / 8:1 / 4:3 / 4, then the size of the cascode transistor omitted in the bypass current path is 3 / 4. Similarly, for example, if the transistor size ratio of transistors NM21, NM22, and NM23 is 1 / 8:1 / 8:7 / 8, then the size of the cascode transistor omitted in the bypass current path is 7 / 8. Furthermore, for example, if the transistor size ratio of transistors NM21, NM22, and NM23 is 4 / 8:1 / 8:7 / 8, then the size of the cascode transistor omitted in the bypass current path is 28 / 8. In other words, the smaller the transistor size of transistor NM22 compared to that of transistor NM21, the greater the current ratio between the voltage difference generation current path and the bypass current path can be while maintaining the overall current drive capability of the voltage difference generation circuit 45. By omitting the cascode transistor, the area reduction effect is greater.

[0164] (effect)

[0165] Next, the function of this implementation method will be explained.

[0166] During programming, sequence generator 27 is controlled by applying a programming voltage VPGM to the select word lines and a voltage VPASS to turn on each memory cell to the non-select word lines. Sequence generator 27 sets the voltage VPGM appearing at output node N to the desired voltage by providing a reference voltage VREF to VPGM generation circuit 40 in voltage generation circuit 28. That is, the output voltage VPGMH of charge pump circuit 41 changes based on the operation of clock control circuit 42 controlled by comparator 44. The voltage VPGM appears at output node N as the voltage difference voltage ΔV, obtained by voltage difference generation circuit 45, which reduces the voltage VPGMH.

[0167] When the voltage VPGM at output node N increases or decreases from the specified programming voltage VPGM, the voltage at the connection point of resistors R1 and R2 increases or decreases compared to the reference voltage VREF. As a result, the output voltage of charge pump circuit 41 decreases or increases, and the voltage at output node N maintains the specified programming voltage VPGM. In the feedback control of voltage VPGM, the voltage VGMMH from charge pump circuit 41 is fixed as voltage VPGM + differential voltage ΔV through voltage difference generation circuit 45.

[0168] like Figure 11 As shown, the sequence generator 27 increases the voltage VPGM in stages according to each programmed cycle. Even in this case, the ratio of the current flowing through the bypass current path to the current flowing through the voltage difference generation current path does not change, and the voltage VPGMH is always maintained at a voltage higher than the voltage VPGM by the differential voltage ΔV. That is, compared to the current I flowing through the output node N, the current flowing through the voltage difference generation current path is reduced, preventing the differential voltage ΔV from becoming too large, and thus preventing the voltage VPGMH exceeding the withstand voltage from being applied to the transistors of the switching circuit group 25A.

[0169] Furthermore, considering that the drain voltage dependence of the current flowing through transistor NM23, which constitutes the bypass current source, is relatively small, the same common-source and common-gate transistor as transistor NM23 is omitted from the bypass current path. Therefore, the area of ​​the voltage difference generation circuit 45 can be smaller than that of transistors NM11 and NM12, which use two layers of diodes connected together. Figure 16 The voltage difference generation circuit is 45A.

[0170] Thus, in this embodiment, by setting a bypass current path to reduce the current flowing through the current path used to generate the voltage difference, the increase of the voltage difference ΔV can be suppressed, and the circuit area can be reduced.

[0171] (Second Implementation)

[0172] Figure 18 This is a circuit diagram showing the voltage difference generating circuit 50 used in the second embodiment of the present invention. Figure 18 In the middle, to and Figure 17 The same constituent elements are marked with the same symbol, and the explanation is omitted.

[0173] Voltage difference generation circuit 50 and Figure 17 The difference in voltage difference generation circuit 45 is that NMOS transistors NM23a, NM23b, and NM23c are used instead of transistor NM23, and NMOS transistors NM24a, NM24b, and NM24c are employed. NM23a, NM23b, and NM23c all have the same characteristics as transistor NM23, with a gate width that is 1 / 3 that of transistor NM23. Therefore, if from... Figure 18If transistors NM24a to NM24c are removed, then the following can be obtained: Figure 17 The voltage difference generation circuit is the same as that of circuit 45.

[0174] Between node P and output node N, the current path of transistor NM24a is connected in series with the current path of transistor NM23a. The drain and gate of transistor NM24a are connected to node P, and its source is connected to the drain of transistor NM23a. The gates of transistor NM23a are connected to the gate of transistor NM22, and its source is connected to output node N.

[0175] Similarly, between node P and output node N, the current path of transistor NM24b is connected in series with the current path of transistor NM23b. The drain and gate of transistor NM24b are connected to node P, and its source is connected to the drain of transistor NM23b. The gate of transistor NM23b is connected to the gate of transistor NM22, and its source is connected to output node N.

[0176] Furthermore, between nodes P and N, the current path of transistor NM24c is connected in series with the current path of transistor NM23c. The drain and gate of transistor NM24c are connected to node P, and its source is connected to the drain of transistor NM23c. The gate of transistor NM23c is connected to the gate of transistor NM22, and its source is connected to the output node N.

[0177] Figure 18 The circuit is supplemented with transistors NM24a to NM24c, which are smaller than the transistor size and required to properly maintain the current ratio, as... Figure 17 The circuit of the common-source cascode transistor is omitted in the circuit. Figure 16 In the comparative example, transistors NM11 and NM12 have a transistor size of 1 / 4, while transistors NM21, NM22, and NM23a to NM23c have a transistor size of 1 / 4. For example, transistors NM24a to NM24c have a transistor size of 1 / 16. Furthermore, the ratio of the transistor sizes of NM24a to NM24c required to correctly maintain the current ratio is 1 / 4.

[0178] In this configuration, since the difference between the drain voltage of NM23a to NM23c and the drain voltage of transistor NM22 is relatively small, the ratio of the current flowing through the voltage difference generation current path to the current flowing through the bypass current path can be controlled more accurately.

[0179] Furthermore, since the drain voltage of NM23a to NM23c, which constitute the bypass current source, is lower than that of NM24a to NM24c when NM24a to NM24c are omitted, it has the advantage of mitigating the withstand voltage requirements of NM23a to NM23c.

[0180] Furthermore, transistors NM23a to NM23c function as current sources by operating in the saturation region. Therefore, the drain-source voltage of transistors NM23a to NM23c needs to be higher than the pinch-off voltage to ensure their operation in the saturation region. In other words, the lower limit of the transistor size of the cascode transistor in the bypass current path can be determined solely by the drain voltage of transistors NM23a to NM23c used to maintain operation in the saturation region.

[0181] Thus, in this embodiment, a cascode transistor is provided in the bypass current path, and the size ratio of the transistor constituting the bypass current source to the cascode transistor is smaller than the size ratio of the two transistors NM22 and NM21 in the voltage difference generation current path. This has the following effects: it suppresses the increase in the area of ​​the voltage difference generation circuit, more accurately controls the current ratio, correctly generates the voltage difference ΔV, and simultaneously alleviates the voltage withstand requirements of the transistor constituting the bypass current source.

[0182] (Third Implementation)

[0183] Figure 19 and Figure 20 This is a circuit diagram showing the voltage difference generating circuit 51 used in the third embodiment of the present invention. Figure 19 and Figure 20 In the middle, to and Figure 18 The same constituent elements are marked with the same symbol, and the explanation is omitted.

[0184] The sequence generator 27 can select four-plane programming (simultaneous writing to four planes from PB0 to PB3) and two-plane programming (simultaneous writing to two planes). In the VPGM generation circuit 40, the load capacitance for four-plane programming is twice that for two-plane programming. Therefore, Figure 18 In the circuit, the current flowing from node P to output node N is twice that in 2-plane programming. Therefore, Figure 18 In the circuit, the differential voltage ΔV becomes twice that of the 2-plane programming.

[0185] Therefore, in this embodiment, by adjusting the number of bypass current paths according to the change in the amount of current output from the output node N of the voltage difference generation circuit, the change in the current flowing through the voltage difference generation current path can be suppressed, and the deviation of the differential voltage ΔV can be reduced.

[0186] Voltage difference generation circuit 51 and Figure 18The voltage difference generating circuit 50 differs in that it includes switches SWA to SWc. Switch SWA switches between connecting node P to the gate of transistor NM24a (ON state) and connecting node P to a reference potential point (OFF state). Similarly, switch SWb switches between connecting node P to the gate of transistor NM24b (ON state) and connecting node P to a reference potential point (OFF state). Furthermore, switch SWc switches between connecting node P to the gate of transistor NM24c (ON state) and connecting node P to a reference potential point (OFF state). The switching between the ON and OFF states of switches SWA to SWc is controlled by a sequence generator 27. Figure 19 and Figure 20 The diagram shows three bypass current paths, but the number of bypass current paths is not limited to three.

[0187] Next, the operation of the implementation method configured as described will be explained.

[0188] The sequence generator 27 controls switches SWA to SWc according to the number of planes being written to simultaneously. For example, in 2-plane programming, as shown in Figure 50, switch SWc is controlled to be turned on when switches SWA and SWb are off. If the size ratio of each transistor in the voltage difference generation circuit 51 is... Figure 18 The transistors in the voltage difference generating circuit 50 shown have the same size ratio. Therefore, in the state shown in Figure 50, the same current I flows in the voltage difference generating current path and the bypass current path, and a current 2I flows at the output node N.

[0189] Next, the sequence generator 27 performs 4-plane programming. In this case, as shown in Figure 51, the sequence generator 27 controls switches SWA~SWc to be in the ON state. Therefore, in this case, a current 4I flows at the output node N, and a current I flows in each bypass current path and the voltage difference generation current path. Thus, regardless of whether the load capacitance changes, a current I flows in the voltage difference generation current path to obtain a stable differential voltage ΔV.

[0190] Therefore, in 2-plane programming and 4-plane programming, the on-resistance of each transistor in the switching circuit group 25A is consistent, reducing the dependence of the on-resistance on the number of planes.

[0191] Thus, in this embodiment, the number of bypass current paths can be adjusted according to the change in the output current, achieving the same effect as in the second embodiment, and the differential voltage ΔV can be fixed regardless of the output current.

[0192] This invention is not limited to the described embodiments; various changes can be made during the implementation phase without departing from its spirit. Furthermore, the embodiments include inventions at various stages, and various inventions can be extracted from the disclosed multiple constituent elements through appropriate combinations. For example, if even if several constituent elements are deleted from all the constituent elements shown in the embodiments, the problems described in the "Problem to be Solved by the Invention" column can be solved, and the effects described in the "Effects of the Invention" column can be obtained, then the configuration after deleting the constituent elements can be extracted as an invention.

[0193] [Symbol Explanation]

[0194] 1. Memory controller

[0195] 2. Non-volatile memory

[0196] 11 RAM

[0197] 12 processors

[0198] 13 Host Interface

[0199] 14 ECC Circuit

[0200] 15. Memory Interface

[0201] 16 Internal Bus

[0202] 21 Logic Control Circuit

[0203] 22 Input / Output Circuit

[0204] 23-cell storage array

[0205] 24 Sensing Amplifier

[0206] 24A Sensing Amplifier Unit Group

[0207] 24B Data Register

[0208] 25-line decoder

[0209] 25A Switching Circuit Group

[0210] 25B block decoder

[0211] 26 Registers

[0212] 27 Sequence Generator

[0213] 28 Voltage Generation Circuit

[0214] 29A~29C switch

[0215] 29 MUX Switch

[0216] 32 Input / Output Pad Group

[0217] 34 Logic Control Pad Group

[0218] 35 Power input terminal blocks

[0219] 40 VPGM generation circuit

[0220] 41 Charge Pump Circuit

[0221] 42 Clock control circuit

[0222] 43 Output Circuit

[0223] 44 Comparators

[0224] 45 Voltage Difference Generation Circuit

[0225] 46 VPASS generation circuit

[0226] NM21~NM23, NM23a~NM23c, NM24a~NM24c transistors

[0227] N output nodes

[0228] P node.

Claims

1. A semiconductor memory device, comprising: A block has multiple storage units; Word lines are connected to the gates of the plurality of memory cells; Multiple bit lines are respectively connected to one end of the multiple memory cells; First wiring; Connect the transistor, and electrically connect the first wiring to the word line based on the signal supplied to the gate; A block decoder supplies the signal to the gate of the connected transistor; and The voltage generating circuit has the following characteristics: The first node supplies the block decoder with a first voltage for generating the signal; The second node supplies the second voltage to the first wiring; and A voltage difference generation circuit is connected between the first node and the second node; and The voltage difference generating circuit has the following features: The first transistor has: The first end is connected to the first node; Gate, connected to the first node; and End 2; The second transistor has: The first terminal is connected to the second terminal of the first transistor; The gate is connected to the second terminal of the first transistor; and The second end is connected to the second node; and The third transistor has: The first end is connected to the first node; A gate, connected to the gate of the second transistor; and The second end is connected to the second node; and The current driving capability of the third transistor is greater than that of the second transistor.

2. The semiconductor memory device according to claim 1, wherein The current driving capability of the first transistor is greater than or equal to the current driving capability of the second transistor.

3. The semiconductor memory device according to claim 1 or 2, wherein The third transistor is composed of a plurality of transistors that connect the first terminal of the third transistor in parallel with the second terminal.

4. The semiconductor memory device according to claim 1 or 2, comprising: The fourth transistor has: The first end is connected to the first node; Gate, connected to the first node; and The second end; and The first terminal of the third transistor is connected to the second terminal of the fourth transistor in place of the first node. The ratio of the current drive capability of the fourth transistor to the current drive capability of the third transistor is less than the ratio of the current drive capability of the first transistor to the current drive capability of the second transistor.

5. The semiconductor memory device according to claim 4, wherein The third transistor is composed of a plurality of transistors connected in parallel with the first terminal and the second terminal of the third transistor. The fourth transistor is composed of a plurality of transistors connected in parallel with the first terminal and the second terminal of the fourth transistor. The third and fourth transistors form multiple current paths between the first node and the second node.

6. The semiconductor memory device according to claim 5, comprising: A switching circuit controls the conduction of each of the multiple current paths formed by the third and fourth transistors between the first and second nodes. The switching circuit controls the conduction of each of the plurality of current paths based on the load capacitor connected to the second node.

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