Semiconductor memory device

Abstract

This disclosure provides a semiconductor memory device capable of suppressing erroneous reads of memory cells. The semiconductor memory device includes: a first semiconductor pillar having i first memory cells and i second memory cells connected in series; i first word lines connected to the i first memory cells; i second word lines stacked in a second direction and connected to the i second memory cells; a driver capable of supplying voltage to each of the i first word lines and the i second word lines; and a logic control circuit for controlling write and read operations of the i first memory cells and the i second memory cells. When the order of the sensing operations for determining whether a j-th threshold voltage has been reached during a verification operation differs from the order of the sensing operations for determining whether a j-th threshold voltage has been reached during a read operation from the k-th first memory cell, the voltage applied to the k-th first word line is different.

Description

[0001] Related applications

[0002] This application claims priority to Japanese Patent Application No. 2021-208661 (filed on December 22, 2021). This application incorporates the entire contents of that basic application by reference. Technical Field

[0003] Embodiments of this disclosure relate to semiconductor memory devices. Background Technology

[0004] NAND flash memory is known as a non-volatile semiconductor memory device. Summary of the Invention

[0005] This disclosure provides a semiconductor memory device capable of suppressing erroneous reads of memory cells.

[0006] One embodiment of a semiconductor memory device includes: a first semiconductor pillar having i first memory cells and i second memory cells, the first semiconductor pillar extending in a second direction intersecting a first direction and electrically connected to a first word line; the i first memory cells being connected in series, each of the i first memory cells being capable of setting m or more threshold voltages (m is an integer greater than or equal to 4); the i second memory cells being connected in series, each of the i second memory cells being capable of setting m or more threshold voltages; i first word lines (i is an integer greater than or equal to 4), the i first word lines being stacked in the second direction and electrically connected to the i first memory cells one-to-one; i second word lines (i is an integer greater than or equal to 4), the i second word lines being stacked in the second direction and electrically connected to the i second memory cells one-to-one; and a driver capable of transmitting signals to the i first word lines and the i second word lines. Each of the word lines is supplied with a voltage; and a logic control circuit controls write operations to the i first memory cells and the i second memory cells, and read operations to the i first memory cells and the i second memory cells, wherein the write operation comprises multiple loops, each loop comprising a programming operation and a verification operation, wherein when the write operation is performed to the kth (k is an integer less than i and greater than 1) first memory cell, the order of the sensing operations for determining whether the jth (j is an integer greater than 1 and less than m) threshold voltage is different from the order of the sensing operations for determining whether the jth threshold voltage is reached in the read operation from the kth first memory cell, so as to determine whether the jth threshold voltage is reached in the verification operation. Attached Figure Description

[0007] Figure 1 This is a block diagram illustrating the configuration of a memory system including the semiconductor memory device according to the first embodiment.

[0008] Figure 2 This is a diagram showing the circuit configuration of the memory cell array in the semiconductor memory device according to the first embodiment.

[0009] Figure 3 This is a diagram showing the planar layout of the select gate line, bit line, and memory pillars according to the first embodiment.

[0010] Figure 4 This is a diagram showing the planar layout of the word lines and memory pillars according to the first embodiment.

[0011] Figure 5 yes Figure 4 The diagram shows the cut-off end face of the semiconductor memory device along A1-A2.

[0012] Figure 6 yes Figure 4 The diagram shows the cut-off end face of the semiconductor memory device along B1-B2.

[0013] Figure 7 This is a diagram illustrating the electrical connections of the voltage generation circuit, driver group, and select gate line or word line involved in the first embodiment.

[0014] Figure 8 In the first case Figure 5 The diagram shows the cut-off end face of the memory cell transistor along line C1-C2.

[0015] Figure 9 yes Figure 8 The diagram shows the cut-off end face of the memory cell transistor along line D1-D2.

[0016] Figure 10 In the second case Figure 5 The diagram shows the cut-off end face of the memory cell transistor along line C1-C2.

[0017] Figure 11 yes Figure 10 The diagram shows the cut-off end face of the memory cell transistor along the E1-E2 line.

[0018] Figure 12 This is a diagram showing the equivalent circuit of adjacent strings in a semiconductor memory device according to the first embodiment.

[0019] Figure 13This is a circuit diagram showing an example of the circuit configuration of the sensing amplifier unit according to the first embodiment.

[0020] Figure 14 This is a diagram showing the threshold distribution of the memory cell transistors according to the first embodiment.

[0021] Figure 15 This is a diagram used to illustrate the state in which a gate line is selected or not selected in the semiconductor memory device according to the first embodiment.

[0022] Figure 16 This is a diagram used to illustrate the state in which word lines are selected or not selected in the semiconductor memory device according to the first embodiment.

[0023] Figure 17 yes Figure 16 The cut-off end view of the semiconductor memory device shown along A1-A2 is a diagram used to illustrate whether the gate line and word line are selected or not.

[0024] Figure 18 yes Figure 16 The cut-off end view of the semiconductor memory device shown along B1-B2 is a diagram used to illustrate whether the gate line and word line are selected or not.

[0025] Figure 19 This is a diagram illustrating the programming loop in the semiconductor memory device according to the first embodiment.

[0026] Figure 20 This is a diagram illustrating an example of the sequence of sensing operations corresponding to the verification operation in the semiconductor memory device according to the first embodiment.

[0027] Figure 21 This is a diagram illustrating an example of the sequence of sensing operations corresponding to a read operation in the semiconductor memory device according to the first embodiment.

[0028] Figure 22 This is a diagram illustrating the reading of the first page during the read operation of the semiconductor memory device according to the first embodiment.

[0029] Figure 23 This is an example of a circuit diagram used to illustrate the various signal and current paths during the verification operation of the semiconductor memory device according to the first embodiment.

[0030] Figure 24 This is a timing diagram showing various signals during the verification operation in the semiconductor memory device according to the first embodiment.

[0031] Figure 25This is a timing diagram showing the various signals during the verification operation in the semiconductor memory device involved in the comparative example.

[0032] Figure 26 It is used for explanation Figure 24 An example of a circuit diagram showing the various signals and current paths during the first operation.

[0033] Figure 27 It is used for explanation Figure 24 An example of a circuit diagram showing the various signals and current paths during the second operation.

[0034] Figure 28 It is used for explanation Figure 24 An example of a circuit diagram showing the various signals and current paths during the third operation.

[0035] Figure 29 It is used for explanation Figure 24 An example of a circuit diagram showing the various signals and current paths during the fourth operation period.

[0036] Figure 30 This is a flowchart illustrating the verification operation in the semiconductor memory device according to the first embodiment.

[0037] Figure 31 This is a timing diagram showing various signals during the verification operation in the semiconductor memory device according to the second embodiment.

[0038] Figure 32 It is used for explanation Figure 31 An example of a circuit diagram showing the various signal and current paths during the fifth and sixth operation periods.

[0039] Figure 33 It is used for explanation Figure 31 An example of a circuit diagram showing the various signals and current paths during the seventh operation.

[0040] Figure 34 This is a flowchart illustrating the verification operation in the semiconductor memory device according to the second embodiment.

[0041] Figure 35 This is a diagram used to illustrate the operation related to the interference effect between memory cells in the semiconductor memory device according to the first embodiment.

[0042] Figure 36 This is a diagram used to illustrate the operation related to the interference effect between memory cells in the semiconductor memory device according to the first embodiment.

[0043] Figure 37This is a timing diagram showing various signals during the verification operation in the semiconductor memory device according to the first embodiment.

[0044] Figure 38 This is a timing diagram showing various signals during the verification operation in the semiconductor memory device according to the second embodiment. Detailed Implementation

[0045] The embodiments will now be described with reference to the accompanying drawings. Furthermore, in the following description, constituent elements having the same or similar functions and configurations are assigned common reference symbols. When distinguishing multiple constituent elements having common reference symbols, a subscript (e.g., uppercase letters, lowercase letters, numbers, hyphens, and uppercase letters and numbers, etc.) is added to the common reference symbol for differentiation.

[0046] In the following description, signal X<p:0> (where p is a natural number) refers to a (p+1)-bit signal, which is the set of 1-bit signals X<0>, X<1>, ..., and X. Component Y<p:0> refers to the set of components Y<0>, Y<1>, ..., and Y that correspond one-to-one with the input or output of signal X<p:0>.

[0047] <First Implementation>

[0048] The semiconductor memory device 1 according to the first embodiment will now be described.

[0049] <1-1. Example of Composition>

[0050] <1-1-1. Storage System>

[0051] Figure 1 This is a block diagram illustrating an example of the configuration of a memory system 3 including a semiconductor memory device 1. For example... Figure 1 As shown, the storage system 3 includes a semiconductor storage device 1 and a memory controller 2. The storage system 3 may be, for example, a memory card such as an SSD (Solid State Drive) or an SDTM card. The storage system 3 may also include a host device (not shown in the diagram).

[0052] Semiconductor memory device 1 is connected to, for example, a memory controller 2 and is controlled by the memory controller 2. The memory controller 2 receives commands from a host device required for the operation of semiconductor memory device 1 and sends these commands to semiconductor memory device 1. The memory controller 2 sends these commands to semiconductor memory device 1 to control read operations (reading data from semiconductor memory device 1), write operations (writing data to semiconductor memory device 1), or erase operations (erasing data from semiconductor memory device 1). In a first embodiment, semiconductor memory device 1 is, for example, a NAND flash memory.

[0053] <1-1-2. Structure of Semiconductor Memory Devices>

[0054] like Figure 1 As shown, the semiconductor memory device 1 includes a memory cell array 21, an input / output circuit 22, a logic control circuit 23, a sequencer 24, a register 25, a ready / busy circuit 26, a voltage generation circuit 27, a driver set 28, a row decoder 29, a sense amplifier module 70, an input / output pad set 71, and a logic control pad set 72. In the semiconductor memory device 1, various operations are performed, such as writing data DAT to the memory cell array 21 and reading data DAT from the memory cell array 21.

[0055] The memory cell array 21 is connected, for example, to the sense amplifier module 70, the line decoder 29, and the driver group 28. The memory cell array 21 includes blocks BLK1, BLK0, ..., BLKn (n is an integer greater than or equal to 1). Each block BLK contains multiple memory groups MG (MG0, MG1, MG2, ...), details of which will be described later. Each memory group MG contains multiple non-volatile memory cells associated with bit lines and word lines. The block BLK serves as, for example, a data erasure unit. The memory cell transistors MTe0 to MTe7 and MTo0 to MTo7 (...) are contained within the same block BLK. Figure 2 The data stored therein was also erased.

[0056] In semiconductor memory device 1, for example, a QLC (Quadruple Level Cell) method can be applied. In the QLC method, 4 bits of data are stored in each memory cell. Alternatively, 3 bits (8 values) of data, 2 bits (4 values) or less of data, or 5 bits or more of data can be stored in each memory cell.

[0057] Input / output circuit 22 is connected, for example, to register 25, logic control circuit 23, and sense amplifier module 70. Input / output circuit 22 controls the transmission and reception of data signal DQ<7:0> between memory controller 2 and semiconductor storage device 1.

[0058] The data signals DQ<7:0> are 8-bit signals. The data signals DQ<7:0> are entities representing data transmitted and received between the semiconductor memory device 1 and the memory controller 2, including command CMD, data DAT, address information ADD, and status information STS. Command CMD includes, for example, commands for executing commands sent from the host device (memory controller 2) to the semiconductor memory device 1. Data DAT includes write data DAT written to the semiconductor memory device 1 or read data DAT read from the semiconductor memory device 1. Address information ADD includes, for example, column and row addresses for selecting multiple non-volatile memory cells associated with bit lines and word lines. Status information STS includes, for example, information related to the status of the semiconductor memory device 1 associated with write and read operations.

[0059] Specifically, the input / output circuit 22 includes an input circuit and an output circuit, which perform the following processing: The input circuit receives write data DAT, address information ADD, and command CMD from the memory controller 2. The input circuit sends the received write data DAT to the sense amplifier module 70 and sends the received address information ADD and command CMD to register 25. On the other hand, the output circuit receives status information STS from register 25 and read data DAT from the sense amplifier module 70. The output circuit sends the received status information STS and read data DAT to the memory controller 2.

[0060] The logic control circuit 23 is connected, for example, to the memory controller 2 and the sequencer 24. The logic control circuit 23 receives from the memory controller 2, for example, a chip enable signal CEn, a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal WEn, a read enable signal REn, and a write protection signal WPn. The logic control circuit 23 controls the input / output circuit 22 and the sequencer 24 based on the received signals.

[0061] The chip enable signal CEn is used to activate (enable) the semiconductor memory device 1. The command latch enable signal CLE is used to notify the input / output circuit 22 that the signal DQ input to the semiconductor memory device 1 contains the command CMD. The address latch enable signal ALE is used to notify the input / output circuit 22 that the signal DQ input to the semiconductor memory device 1 contains the address information ADD. The write enable signal WEn and the read enable signal REn are, for example, signals used to command the input / output circuit 22 to input and output the data signal DQ. The write protect signal WPn is used to indicate to the semiconductor memory device 1 that writing and erasing data are prohibited.

[0062] The sequencer 24 is connected, for example, to the ready / busy control circuit 26, the sense amplifier module 70, and the driver group 28. The sequencer 24 controls the operation of the entire semiconductor memory device 1 according to the command CMD held in the command register. For example, the sequencer 24 controls the sense amplifier module 70, the line decoder 29, the voltage generation circuit 27, and the driver group 28 to perform various operations such as write and read operations. Furthermore, the sequencer 24 has a counter circuit 24A that counts the order of verification operations (which verification operation is the nth one within the programming cycle) for each programming cycle, identifying the order of verification operations; details will be described later. Additionally, the sequencer 24 uses internally generated signals to identify which state's verification operation begins at a given time, and uses an internal table to identify the order of verification operations starting at that time; details will be described later.

[0063] Register 25 includes, for example, a status register (not shown in the diagram), an address register (not shown in the diagram), and an instruction register (not shown in the diagram). The status register receives and holds status information STS from the sequencer 24, and sends the status information STS to the input / output circuit 22 according to the instructions of the sequencer 24. The address register receives and holds address information ADD from the input / output circuit 22. The address register sends the column address in the address information ADD to the sense amplifier module 70, and sends the row address in the address information ADD to the row decoder 29. The command register receives and holds the command CMD from the input / output circuit 22, and sends the command CMD to the sequencer 24.

[0064] The ready / busy control circuit 26 generates a ready / busy signal R / Bn according to the control of the sequencer 24, and sends the generated ready / busy signal R / Bn to the memory controller 2. The ready / busy signal R / Bn is used to notify the semiconductor memory device 1 whether it is in a ready state that accepts commands from the memory controller 2, or in a busy state that does not accept commands.

[0065] The voltage generation circuit 27 is connected, for example, to the driver assembly 28. Based on the control of the sequencer 24, the voltage generation circuit 27 generates the voltage used in write operations and read operations, and supplies the generated voltage to the driver assembly 28.

[0066] Driver group 28, for example, includes an even word line driver 28A. Figure 7 ) and Odd word line driver 28B ( Figure 7 The driver assembly 28 is connected to the memory cell array 21, the sense amplifier module 70, and the line decoder 29. The driver assembly 28 generates, for example, a select gate line SGD (selection signal) based on the voltage supplied from the voltage generation circuit 27 or the control signal supplied from the sequencer 24, for various operations such as read and write operations. Figure 2 ), Word line WL ( Figure 2 ), source line SL ( Figure 2 ) and bit line BL ( Figure 2 Various voltages or control signals are supplied by the driver group 28. The generated voltages or control signals are supplied to the sense amplifier module 70, the line decoder 29, the source line SL, etc.

[0067] The row decoder 29 receives the row address from the address register and decodes the received row address. Based on the decoding result, the row decoder 29 selects the block BLK to which various operations such as read and write operations are performed. The row decoder 29 can supply the voltage supplied from the driver group 28 to the selected block BLK.

[0068] The sense amplifier module 70 receives a column address from an address register, for example, and decodes the received column address. Furthermore, based on the decoding result, the sense amplifier module 70 performs data transmission and reception operations (DAT) between the memory controller 2 and the memory cell array 21. The sense amplifier module 70 includes, for example, a sense amplifier unit SAU (Sensor Unit) set for each bit line BL (BL0 to BL(L-1), where (L-1) is a natural number greater than 2). Figure 13 The sense amplifier unit SAU is electrically connected to the bit line BL and can supply voltage to the bit line BL. For example, the sense amplifier module 70 can use the sense amplifier unit SAU to supply voltage to the bit line. In addition, the sense amplifier module 70 senses the data read from the memory cell array 21, generates read data DAT, and sends the generated read data DAT to the memory controller 2 via the input / output circuit 22. In addition, the sense amplifier module 70 receives write data DAT from the memory controller 2 via the input / output circuit 22 and sends the received write data DAT to the memory cell array 21.

[0069] The input / output pad group 71 sends the data signal DQ<7:0> received from the memory controller 2 to the input / output circuit 22. The input / output pad group 71 sends the data signal DQ<7:0> received from the input / output circuit 22 to the memory controller 2.

[0070] The logic control pad group 72 transmits the chip enable signal CEn, command latch enable signal CLE, address latch enable signal ALE, write enable signal WEn, and read enable signal REn received from the memory controller 2 to the logic control circuit 23. The logic control pad group 72 transmits the ready / busy signal R / Bn received from the ready / busy control circuit 26 to the memory controller 2.

[0071] <1-1-3. Memory Cell Array>

[0072] Figure 2 yes Figure 1 An example of the circuit configuration of the storage cell array 21 shown. Figure 2 This is a diagram illustrating the circuit configuration of one of the multiple blocks BLK included in the memory cell array 21. For example, each of the multiple blocks BLK included in the memory cell array 21 has... Figure 2 The circuit configuration is shown. Figure 2 In the description, sometimes the terms "and" are omitted. Figure 1 Description of identical or similar structures.

[0073] like Figure 2 As shown, block BLK contains multiple memory groups MG (MG0, MG1, MG2, MG3). In this embodiment, each memory group MG contains multiple NAND strings 50. For example, memory groups MG0 and MG2 contain multiple NAND strings 50e, and memory groups MG1 and MG3 contain multiple NAND strings 50o.

[0074] Each NAND string NS contains, for example, eight memory cell transistors MT (MT0 to MT7) and select transistors ST1 and ST2. The memory cell transistors MT have a control gate and a charge storage layer, which non-volatilely retain data. The memory cell transistors MT are connected in series between the source of select transistor ST1 and the drain of select transistor ST2.

[0075] The gate of the selection transistor ST1 in each memory group MG is connected to the selection gate line SGD (SGD0, SGD1, ...). The selection gate line SGD is independently controlled by the row decoder 29. Additionally, the gate of the selection transistor ST2 in each even-numbered memory group MGe (MG0, MG2, ...) is connected to the even-numbered selection gate line SGSe, for example, and the gate of the selection transistor ST2 in each odd-numbered memory group MGo (MG1, MG3, ...) is connected to the odd-numbered selection gate line SGSo, for example. The even-numbered selection gate line SGSe and the odd-numbered selection gate line SGSo can be interconnected and controlled in the same way, or they can be set independently and controlled independently.

[0076] Within the same block BLK, the control gates of the memory cell transistors MT (MTe0~MTe7) in memory group MGe are all connected to the even-numbered lines WLe (WLe0~WLe7). Similarly, the control gates of the memory cell transistors MT (MTo0~MTo7) in memory group MGo within the same block BLK are all connected to the odd-numbered lines WLo (WLo0~WLo7). The even-numbered lines WLe and WLo are independently controlled by the line decoder 29.

[0077] Each memory group (MG) contains multiple pages corresponding to multiple word lines (WL). For example, in memory group MG0 or MG2, multiple memory cell transistors (MT) whose control gates are commonly connected to one of the even-number lines WLe0 to WLe7 correspond to a page. Similarly, in memory group MG1 or MG3, multiple memory cell transistors (MT) whose control gates are commonly connected to one of the odd-number lines WLo0 to WLo7 correspond to a page. Write and read operations are performed on a page-by-page basis.

[0078] Within the memory cell array 21, the drains of the select transistors ST1 of the NAND strings 50 located in the same column are commonly connected to bit lines BL (BL0 to BL(L-1), where (L-1) is a natural number greater than 2). That is, bit lines BL commonly connect the NAND strings 50 between multiple memory groups MG. The sources of multiple select transistors ST2 are commonly connected to source lines SL. Source lines SL are electrically connected to driver groups 28, for example, and are supplied with voltage from the voltage generation circuit 27 or driver group 28 by means of the control of the voltage generation circuit 27 of the sequencer 24 and the driver group 28. Alternatively, the semiconductor memory device 1 may also have multiple source lines SL. For example, multiple source lines SL may be electrically connected to the driver group 28 respectively, and the multiple source lines SL may be supplied with different voltages from the voltage generation circuit 27 or driver group 28 by means of the control of the voltage generation circuit 27 of the sequencer 24 and the driver group 28.

[0079] The memory group MG contains multiple NAND strings 50, which are connected to different bit lines BL and to the same select gate line SGD. Block BLK contains multiple memory groups MG sharing a word line WL. The memory cell array 21 contains multiple blocks BLK sharing a bit line BL. Within the memory cell array 21, the select gate line SGS, word line WL, and select gate line SGD are stacked above the source line layer, and the memory cell transistors MT are stacked in three dimensions.

[0080] <1-1-4. Planar Layout of Storage Cell Array>

[0081] Figure 3 This is a diagram showing the planar layout of the select gate line (SGD) in an in-plane (XY plane) parallel to the source line layer of a certain block BLK. (See diagram below.) Figure 3 As shown, in semiconductor memory device 1, for example, four select gate lines (SGDs) are included within one block BLK. Figure 3 In the description, sometimes the terms "and" are omitted. Figure 1 and Figure 2 Description of identical or similar structures.

[0082] like Figure 3 As shown, in semiconductor memory device 1, for example, three wiring layers 10-0a, 10-0b, and 10-0c extending along the X direction are connected using a first connecting section 10-0d extending along the Y direction. Wiring layers 10-0a and 10-0c are located at opposite ends in the Y direction. Wiring layers 10-0a and 10-0b sandwich another wiring layer (wiring layer 10-1a) and are adjacent in the Y direction. The first connecting section 10-0d is located at one end in the X direction. The three wiring layers 10-0a, 10-0b, and 10-0c function as a select gate line SGD0. In the first embodiment, for example, the Y direction is orthogonal or substantially orthogonal to the X direction.

[0083] Wiring layers 10-1a and 10-1b extending along the X direction are connected by a second connecting section 10-1d extending along the Y direction. Wiring layer 10-1a is located between wiring layers 10-0a and 10-0b. Wiring layer 10-1b is located between wiring layer 10-0b and another wiring layer (wiring layer 10-2a). The second connecting section 10-1d is located at the opposite end of the first connecting section 10-0d in the X direction. The two wiring layers 10-1a and 10-1b function as the select gate line SGD1.

[0084] Wiring layers 10-2a and 10-2b extending along the X direction are connected using a first connecting portion 10-2d extending along the Y direction. Similarly, wiring layers 10-3a and 10-3b extending along the X direction are connected using a second connecting portion 10-3d extending along the Y direction. Wiring layer 10-2a is located between wiring layer 10-1b and wiring layer 10-3a. Wiring layer 10-3a is located between wiring layer 10-2a and wiring layer 10-2b. Wiring layer 10-2b is located between wiring layer 10-3a and wiring layer 10-3b. Wiring layer 10-3b is located between wiring layer 10-2b and wiring layer 10-0c. The first connecting portion 10-2d is located at one end on the same side as the first connecting portion 10-0d in the X direction. The second connecting portion 10-3d is located at the other end on the opposite side of the first connecting portion 10-0d in the X direction. Two wiring layers, 10-2a and 10-2b, function as the select gate line SGD2. Two wiring layers, 10-3a and 10-3b, function as the select gate line SGD3.

[0085] In the first embodiment, a configuration is illustrated in which each wiring layer is connected using first connection portions 10-0d, 10-2d or second connection portions 10-1d, 10-3d. However, the configuration of each wiring layer is not limited to the configuration shown in the first embodiment. For example, control can also be implemented in such a way that each wiring layer is independent, wiring layers 10-0a, 10-0b, and 10-0c are supplied with the same voltage, wiring layers 10-1a and 10-1b are supplied with the same voltage, wiring layers 10-2a and 10-2b are supplied with the same voltage, and wiring layers 10-3a and 10-3b are supplied with the same voltage.

[0086] Within block BLK, adjacent wiring layers 10 in the Y direction are insulated. The region that insulates adjacent wiring layers 10 is called slit SLT2. At slit SLT2, for example, the region from the plane parallel to the source line layer to the layer where at least wiring layers 10 are disposed is filled with an insulating film (not shown). Additionally, within the memory cell array 21, for example, multiple [missing information - likely referring to a specific array or configuration] are arranged in the Y direction. Figure 3 The block BLK is shown. Similar to the wiring layers 10 adjacent to the block BLK in the Y direction, an insulating film (not shown) is used to fill the space between adjacent blocks BLK in the Y direction, and the blocks BLK are also insulated from each other. The area that insulates adjacent blocks BLK is called slit SLT1. Similar to slit SLT2, at slit SLT1, the insulating film fills the area from the plane parallel to the source line layer to the layer where at least the wiring layer 10 is located.

[0087] Multiple memory pillars MP (MP0 to MP15) are disposed between adjacent wiring layers 10 in the Y direction. The multiple memory pillars MP are disposed within a memory cell section. Each of the multiple memory pillars MP is disposed along the Z direction. In the first embodiment, for example, the Z direction is a direction orthogonal or substantially orthogonal to the XY direction, and a direction perpendicular or substantially perpendicular to the direction parallel to the source line layer. In the first embodiment, the memory pillar MP is sometimes referred to as a "semiconductor pillar," the X direction is sometimes referred to as a "first direction," the Y direction is sometimes referred to as a "second direction," and the Z direction is sometimes referred to as a "third direction."

[0088] Specifically, storage pillars MP4 and MP12 are provided between routing layers 10-0a and 10-1a. Storage pillars MP0 and MP8 are provided between routing layers 10-1a and 10-0b. Storage pillars MP5 and MP13 are provided between routing layers 10-0b and 10-1b. Storage pillars MP1 and MP9 are provided between routing layers 10-1b and 10-2a. Storage pillars MP6 and MP14 are provided between routing layers 10-2a and 10-3a. Storage pillars MP2 and MP10 are provided between routing layers 10-3a and 10-2b. Storage pillars MP7 and MP15 are provided between routing layers 10-2b and 10-3b. Storage pillars MP3 and MP11 are provided between routing layers 10-3b and 10-0c.

[0089] The memory pillar MP is the structure that forms the select transistors ST1 and ST2 and the memory cell transistor MT. The detailed structure of the memory pillar MP will be described later.

[0090] Storage columns MP0 to MP3 are arranged along the Y direction. Storage columns MP8 to MP11 are arranged along the Y direction at positions adjacent to storage columns MP0 to MP3 in the X direction. That is, storage columns MP0 to MP3 and storage columns MP8 to MP11 are arranged in parallel.

[0091] Storage columns MP4-MP7 and MP12-MP15 are configured along the Y direction. Storage columns MP4-MP7 are located between storage columns MP0-MP3 and storage columns MP8-MP11 in the X direction. Storage columns MP12-MP15 are located along the X direction, sandwiching storage columns MP8-MP11 together with storage columns MP4-MP7. That is, storage columns MP4-MP7 and storage columns MP12-MP15 are configured in parallel.

[0092] Two bit lines, BL0 and BL1, are provided above memory cylinders MP0 to MP3. Bit line BL0 is connected to memory cylinders MP1 and MP3. Bit line BL1 is connected to memory cylinders MP0 and MP2. Two bit lines, BL2 and BL3, are provided above memory cylinders MP4 to MP7. Bit line BL2 is connected to memory cylinders MP5 and MP7. Bit line BL3 is connected to memory cylinders MP4 and MP6.

[0093] Two bit lines, BL4 and BL5, are located above memory cylinders MP8 to MP11. Bit line BL4 is commonly connected to memory cylinders MP9 and MP11. Bit line BL5 is commonly connected to memory cylinders MP8 and MP10. Two bit lines, BL6 and BL7, are located above memory cylinders MP12 to MP15. Bit line BL6 is commonly connected to memory cylinders MP13 and MP15. Bit line BL7 is commonly connected to memory cylinders MP12 and MP14.

[0094] As described above, the storage column MP is positioned across two wiring layers 10 in the Y direction and is configured to fill a portion of one of the multiple slots SL2, SLT2. Additionally, a slot SLT2 is provided between adjacent storage columns MP in the Y direction.

[0095] In addition, no storage pillar MP is placed between the wiring layers 10-0a and 10-0c adjacent to the slit SLT1.

[0096] Figure 4 This is a diagram showing the planar layout of the word lines WL on the XY plane. Figure 4 The layout shown is Figure 3 The layout of a single block corresponds to the setting in [location]. Figure 3 The layout of the wiring layer 11 below the wiring layer 10 is shown. Figure 3 and Figure 4 The example of the planar layout shown only illustrates 8 bit lines (bit lines BL0 to BL7), but for example, a number of bit lines equivalent to data lengths of 4kByte, 8kByte, or 16kByte can be set; the number of bit lines is not particularly limited. Figure 4 In the description, sometimes the terms "and" are omitted. Figures 1-3 Description of identical or similar structures.

[0097] like Figure 4As shown, nine wiring layers 11 (wiring layers 11-0 to 11-7, where wiring layer 11-0 includes wiring layers 11-0a and 11-0b) extending along the X direction are arranged along the Y direction. Each wiring layer 11-0 to 11-7 is arranged relative to the Z direction below each wiring layer 10-0 to 10-7. An insulating film is provided between wiring layers 11-0 to 11-7 and wiring layers 10-0 to 10-7, thus insulating wiring layers 11-0 to 11-7 from each other.

[0098] Each routing layer 11 functions as word line WL7. Other word lines WL0 to WL6 also have the same structure and function as word line WL7. Figure 4 In the example shown, wiring layers 11-0a, 11-2, 11-4, 11-6, and 11-0b function as even-number lines WLe7. Wiring layers 11-0a, 11-2, 11-4, 11-6, and 11-0b are connected using a first connecting section 11-8 extending in the Y direction. The first connecting section 11-8 is located at one end in the X direction. Wiring layers 11-0a, 11-2, 11-4, 11-6, and 11-0b are connected to the line decoder 29 at the first connecting section 11-8. In the first embodiment, the first connecting section 11-8 and wiring layers 11-0a, 11-2, 11-4, 11-6, and 11-0b are sometimes collectively referred to as wiring layer 11e.

[0099] Additionally, wiring layers 11-1, 11-3, 11-5, and 11-7 function as odd-number lines WLo7. Wiring layers 11-1, 11-3, 11-5, and 11-7 are connected using a second connecting section 11-9 extending in the Y direction. The second connecting section 10-9 is located in the X direction at the opposite end to the first connecting section 11-8. Wiring layers 11-1, 11-3, 11-5, and 11-7 are connected to the line decoder 29 via the second connecting section 11-9. In the first embodiment, the second connecting section 11-9 and wiring layers 11-1, 11-3, 11-5, and 11-7 are sometimes collectively referred to as wiring layer 11o.

[0100] The memory cell section is disposed between the first connection section 11-8 and the second connection section 11-9. In the memory cell section, adjacent wiring layers 11 in the Y direction are... Figure 3 The slit SLT2 shown is used to separate the BLK blocks. Similarly, the wiring layers 11 between adjacent blocks BLK in the Y direction are separated by slit SLT1, just like slit SLT2. Figure 3 Similarly, the storage cell section includes storage columns MP0 to MP15.

[0101] Select gate line SGS and word lines WL0~WL6 have the same Figure 4 The character line WL7 shown has the same structure.

[0102] <1-1-5. Construction of the cut-off end face of the memory cell array>

[0103] Figure 5 It is shown Figure 4 The diagram shows the end face of the A1-A2 cut section. Figure 5 In the description, sometimes the terms "and" are omitted. Figures 1-4 Description of identical or similar structures.

[0104] like Figure 5 As shown, wiring layer 12 is disposed above the p-well region of semiconductor substrate 13 along the Z direction. Semiconductor substrate 13 functions as source line SL. Wiring layer 12 functions as select gate line SGS. Eight wiring layers 11 are stacked above wiring layer 12 along the Z direction. Wiring layer 11 functions as word lines WL. Furthermore, the eight wiring layers 11 correspond one-to-one with word lines WL0 to WL7. Figure 4 This is a diagram showing the planar layout of the wiring layer 11, which functions as the word line WL. Figure 3 This is a diagram showing the planar layout of wiring layer 10, which functions as the gate selector (SGD). The planar layout of wiring layer 12, which functions as the gate selector (SGS), is, for example, [illustrated as follows]. Figure 3 The layout shown is obtained by replacing the wiring layer 10, which functions as the select gate line SGD, with the wiring layer 12, which functions as the select gate line SGS.

[0105] Wiring layer 12 functions as either the even-numbered gate selection line SGSe or the odd-numbered gate selection line SGSo. The even-numbered gate selection lines SGSe and SGSo are alternately arranged in the Y direction, separated by a slit SLT2. A storage pillar MP is provided between adjacent even-numbered gate selection lines SGSe and odd-numbered gate selection lines SGSo in the Y direction. Furthermore, the even-numbered gate selection lines SGSe and SGSo do not need to be electrically driven independently. The even-numbered gate selection lines SGSe and SGSo can also be electrically connected.

[0106] The wiring layer 11 functions as either even-numbered lines WLe or odd-numbered lines WLo. Even-numbered lines WLe and odd-numbered lines WLo are alternately arranged in the Y direction, separated by a slit SLT2. A memory column MP is positioned between adjacent even-numbered lines WLe and odd-numbered lines WLo in the Y direction. Memory cells, described later, are positioned between memory columns MP and even-numbered lines WLe, and between memory columns MP and odd-numbered lines WLo.

[0107] A slit SLT1 is provided between adjacent blocks BLK in the Y direction. An insulating layer is provided in slit SLT1, for example. The width of slit SLT1 in the Y direction is approximately the same as the width of slit SLT2 in the Y direction.

[0108] In the semiconductor memory device 1, source lines SL are disposed on the main surface of the semiconductor substrate 13. The source lines SL can be formed by extending an unpatterned conductive layer into the region of the memory cell array 21, or by extending a patterned conductive layer in the form of lines into that region. In other words, the source lines SL extend in both the X and Y directions.

[0109] like Figure 3 and Figure 4 As shown, memory cylinders MP are electrically connected to bit lines BL. For example, memory cylinder MP0 is connected to bit line BL1 via contact plug 16. Additionally, memory cylinder MP1 is connected to bit line BL0 via contact plug 16, memory cylinder MP2 is connected to bit line BL1 via contact plug 16, and memory cylinder MP3 is connected to bit line BL0 via contact plug 16. Similarly, memory cylinders MP4 to MP7 are connected to bit lines BL2 or BL3, memory cylinders MP8 to MP11 are connected to bit lines BL4 or BL5, and memory cylinders MP12 to MP15 are connected to bit lines BL6 or BL7.

[0110] Figure 6 It is shown Figure 4 A diagram showing the cut-off end faces of the semiconductor memory device, specifically the B1-B2 portion. Figure 6 In the description, sometimes the terms "and" are omitted. Figures 1-5 Description of similar or identical configurations. The stack-up structure of wiring layer 12, wiring layer 11, and wiring layer 10, and the configuration of the storage cell section, as used... Figure 5 As explained, the explanation is omitted here. Additionally, in Figure 6 In the diagram, the structure existing in the depth direction of the cut-off end face of B1-B2 is depicted with dashed lines.

[0111] like Figure 6As shown, in the first connecting section 17d, wiring layers 10, 11, and 12 are formed in a stepped shape. That is, when viewed in the XY plane, the upper surfaces of the ends of each of wiring layer 10, wiring layer 11, and wiring layer 12 are exposed in the first connecting section 17d. Contact plugs 17 are provided on the upper surfaces of the ends of each of wiring layer 10, wiring layer 11, and wiring layer 12 exposed in the first connecting section 17d. The contact plugs 17 are connected to the metal wiring layer 18. For example, wiring layer 10, which functions as even-numbered select gate lines SGD0 and SGD2, wiring layer 11, which functions as an even-numbered line WLe, and wiring layer 12, which functions as an even-numbered select gate line SGSe, use the metal wiring layer 18 to pass through the line decoder 29. Figure 1 It is electrically connected to the even digital line driver 28A.

[0112] Similar to the first connecting section 17d, in the second connecting section 19d, wiring layers 10, 11, and 12 are formed in a stepped shape. Viewed in the XY plane, the upper surfaces of the ends of each of wiring layer 10, the eight wiring layers 11, and 12 are exposed in the second connecting section 19d. Contact plugs 19 are provided on the upper surfaces of the ends of wiring layer 10, the eight wiring layers 11, and 12 exposed in the second connecting section 19d, and these contact plugs 19 are connected to the metal wiring layer 20. For example, the odd-numbered select gate lines SGD1 and SGD3, the wiring layer 11 which functions as the odd-numbered line WLo, and the wiring layer 12 which functions as the odd-numbered select gate line SGSo, all utilize the metal wiring layer 20 and are transmitted via the line decoder 29. Figure 1 It is electrically connected to the odd number line driver 28B.

[0113] The wiring layer 10 can be electrically connected to the line decoder 29, or the even digital line driver 28A and the odd digital line driver 28B via the second connection portion 19d instead of via the first connection portion 17d, or it can be electrically connected to the line decoder 29, or the even digital line driver 28A and the odd digital line driver 28B via both the first connection portion 17d and the second connection portion 19d.

[0114] Figure 7 This diagram illustrates the electrical connections of the voltage generation circuit 27, driver group 28, and select gate line SGD or word line WL according to the first embodiment. Figure 7 In the description, sometimes the terms "and" are omitted. Figures 1-6 Description of identical or similar structures.

[0115] like Figure 7As shown, alternatively, wiring layer 11, which functions as the even-number line WLe, is connected to the even-number line driver 28A, and wiring layer 11, which functions as the odd-number line WLo, is electrically connected to the odd-number line driver 28B. As explained in "1-1-2. Configuration of a Semiconductor Memory Device," the even-number line driver 28A and the odd-number line driver 28B are included in driver assembly 28. Driver assembly 28 is electrically connected to voltage generation circuit 27. Alternatively, the even-number line driver 28A and the odd-number line driver 28B can use the voltage supplied from voltage generation circuit 27 to generate various voltages, with even-number line driver 28A supplying the generated voltage to even-number line WLe and odd-number line driver 28B supplying the generated voltage to odd-number line WLo.

[0116] <1-1-6. Cut-off end face of memory column MP and memory cell transistor MT>

[0117] <1-1-6-1. The first example>

[0118] In the construction of the memory cell transistor MT, the following is used Figure 8 and Figure 9 The construction of the first example shown. Figure 8 It is shown Figure 5 A diagram of the cut end face along line C1-C2. Figure 9 It is shown Figure 8 The diagram shows the cut-off end face of the memory cell transistor MT along the D1-D2 line. Figure 8 and Figure 9 This is a cut-off end view of a region containing two memory cell transistors MT. In the first example, the charge storage layer contained in the memory cell transistor MT is a conductive film. In the first example, the memory cell transistor MT is a floating-gate type memory cell transistor MT. Figure 8 and Figure 9 In the description, sometimes the terms "and" are omitted. Figures 1 to 7 Description of identical or similar structures.

[0119] like Figure 8 and Figure 9 As shown, the memory pillar MP includes insulating layers 48 and 43, a semiconductor layer 40, an insulating layer 41, a conductive layer 42, and insulating layers 46a-46c disposed along the Z direction. The insulating layer 48 is formed, for example, using a silicon oxide film. The semiconductor layer 40 is disposed to surround the insulating layer 48. The semiconductor layer 40 functions as the region forming the channel of the memory cell transistor MT. The semiconductor layer 40 is formed, for example, using a polysilicon layer. The semiconductor layer 40 is continuously disposed between the memory cell transistors MT located within the same memory pillar MP and is not separated between the memory cell transistors MT. Therefore, the channels formed in each of the two memory cell transistors MT share a portion of the memory pillar MP.

[0120] Semiconductor layer 40 is continuous between two opposing memory cell transistors MT. Therefore, the channels formed in each of the two opposing memory cell transistors MT share a portion of the memory pillar MP. Specifically, in Figure 8 and Figure 9 In the first embodiment, in the memory cell transistor MT (first memory cell) on the left and the memory cell transistor MT (third memory cell) on the right, which are opposite each other, the channel formed in the first memory cell (first channel) and the channel formed in the third memory cell (second channel) share a portion of the memory pillar MP. Here, "two channels sharing a portion of the memory pillar MP" means that the two channels are formed on the same memory pillar MP, and a portion of the two channels overlaps. In the first embodiment, there are cases where the two memory cell transistors MT share a channel or the two memory cell transistors MT are opposite each other.

[0121] An insulating layer 41 is disposed around the semiconductor layer 40, serving as a gate insulating film for each memory cell transistor MT. The insulating layer 41... Figure 8 The XY plane shown is divided into two regions. The insulating layer 41 separating the two regions functions as the gate insulating film for the two memory cell transistors MT within the same memory pillar MP. The insulating layer 41 is formed, for example, using a stacked structure of silicon oxide film and silicon nitride film.

[0122] A conductive layer 42 is disposed around the insulating layer 41 and is divided into two regions along the Y direction by the insulating layer 43. The conductive layer 42, divided into two regions, functions as the charge storage layer for each of the two memory cell transistors MT. The conductive layer 42 is formed, for example, using a polysilicon layer.

[0123] The insulating layer 43 is formed, for example, using a silicon oxide film. Around the conductive layer 42, insulating layers 46a, 46b, and 46c are sequentially disposed from the side closest to the conductive layer 42. Insulating layers 46a and 46c are formed, for example, using silicon oxide films, and insulating layer 46b is formed, for example, using a silicon nitride film. Insulating layers 46a, 46b, and 46c function as barrier insulating films for the memory cell transistor MT. Insulating layers 46a, 46b, and 46c are divided into two regions along the Y direction. An insulating layer 43 is disposed between the two regions of insulating layer 46c. Furthermore, the insulating layer 43 is embedded within the slit SLT2. The insulating layer 43 is formed, for example, using a silicon oxide film.

[0124] An AlO layer 45 is provided around the first example of the memory column MP. A barrier metal layer 47 is provided around the AlO layer 45. The barrier metal layer 47 is formed, for example, using a TiN film. A wiring layer 11, which functions as a word line WL, is provided around the barrier metal layer 47. The wiring layer 11 of the memory column MP according to the first embodiment is formed, for example, using a tungsten film.

[0125] exist Figure 8 and Figure 9 In the configuration of the memory cell transistor MT shown, two memory cell transistors MT are arranged along the Y direction within one memory pillar MP. Selector transistors ST1 and ST2 have the same configuration as the memory cell transistors MT. An insulating layer (not shown) is provided between adjacent memory cell transistors MT in the Z direction. Through this insulating layer and insulating layers 43 and 46, the conductive layer 42 is insulated for each memory cell transistor MT.

[0126] <1-1-6-2. Second Example>

[0127] MT (Metal Storage Transistor) can also be used Figure 10 and Figure 11 The construction of the second example shown. Figure 10 It is shown Figure 5 A diagram of the cut end face along line C1-C2. Figure 11 It is shown Figure 10 The diagram shows the E1-E2 cut-off end face of the memory cell transistor MT. Figure 10 and Figure 11 This is a cut-off end view of a region containing two memory cell transistors MT. In the second example, the charge storage layer contained in the memory cell transistor MT is an insulating film. In the second example, the memory cell transistor MT is a MONOS type memory cell transistor MT. Figure 10 and Figure 11 In the description, sometimes the terms "and" are omitted. Figures 1 to 7 Description of identical or similar structures.

[0128] like Figure 10 and Figure 11 As shown, the memory pillar MP includes an insulating layer 30, a semiconductor layer 31, an insulating layer 32, an insulating layer 33, and an insulating layer 34 disposed along the Z direction. The insulating layer 30 is formed, for example, using a silicon oxide film. The semiconductor layer 31 is disposed around the insulating layer 30 and functions as the region forming the channel of the memory cell transistor MT. The semiconductor layer 31 is formed, for example, using a polysilicon layer. The semiconductor layer 31 is not separated between the memory cell transistors MT located within the same memory pillar MP, but is disposed continuously. Therefore, the channels formed in each of the two memory cell transistors MT share a portion of the memory pillar MP.

[0129] An insulating layer 32 is disposed around the semiconductor layer 31 and functions as a gate insulating film for the memory cell transistor MT. The insulating layer 32 is formed, for example, using a laminated structure of silicon oxide and silicon nitride. An insulating layer 33 is disposed around the semiconductor layer 31 and functions as a charge storage layer for the memory cell transistor MT. The insulating layer 33 is formed, for example, using a silicon nitride film. An insulating layer 34 is disposed around the insulating layer 33 and functions as a barrier insulating film for the memory cell transistor MT. The insulating layer 34 is formed, for example, using a silicon oxide film. An insulating layer 37 is buried within the slit SLT2, excluding the memory pillar MP portion. The insulating layer 37 is formed, for example, using a silicon oxide film.

[0130] In the second example, an AlO layer 35 is disposed around the memory column MP. A barrier metal layer 36 is disposed around the AlO layer 35, for example. The barrier metal layer 36 is formed, for example, using a TiN film. A wiring layer 11, which functions as a word line WL, is disposed around the barrier metal layer 36. The wiring layer 11 is formed, for example, using a tungsten film.

[0131] Similar to the first example, the second example involves a single memory column MP containing two memory cell transistors MT along the Y direction. Also similar to the single memory column MP, selection transistors ST1 and ST2 each contain two transistors along the Y direction.

[0132] <1-1-7. Equivalent Circuit of a Series>

[0133] Figure 12 This is the equivalent circuit diagram of adjacent strings in semiconductor memory device 1. Figure 12 In the description, sometimes the terms "and" are omitted. Figures 1 to 11 Description of identical or similar structures.

[0134] like Figure 12 As shown, two NAND strings 50e and 50o are formed in one storage column MP. Specifically, NAND string 50o is provided on the first (third) side of the storage column MP. NAND string 50e is provided on the second (fourth) side of the storage column MP.

[0135] NAND string 50o has a select transistor STo1, i (i is an integer of 2 or more) memory cell transistors MTo, and a select transistor STo2 connected in series. In the first embodiment, i is 8. Eight memory cell transistors MTo0 to MTo7 are electrically connected between select transistor STo1 and select transistor STo2. Additionally, NAND string 50e has a select transistor STe1, i memory cell transistors MTe, ​​and a select transistor STe2 connected in series. Eight memory cell transistors MTe0 to MTe7 are electrically connected between select transistor STe1 and select transistor STe2.

[0136] NAND string 50e and NAND string 50o are arranged in a way that faces each other (relative to each other). Therefore, the select transistor STe1, memory cell transistors MTe0 to MTe7, and select transistor STe2 contained in NAND string 50e and the select transistor STo1, memory cell transistors MTo0 to MTo7, and select transistor STo2 contained in NAND string 50o are arranged in a one-to-one correspondence facing each other (relative to each other).

[0137] Relative to the source line SL, in the Z direction, there are one layer of odd-numbered select gate lines SGSo, even-numbered select gate lines SGSe, i-layer of odd-numbered lines WLo, i-layer of even-numbered lines WLe, and one layer of select gate lines SGD0 and SGD1. In the first embodiment, i is 8, and odd-numbered lines WLo0 to WLo7 and even-numbered lines WLe0 to WLe7 are provided.

[0138] In the first embodiment, for example, when it is not necessary to distinguish between NAND strings 50o and 50e, they are sometimes simply referred to as "NAND string 50". The components included in NAND string 50 and the wiring connected to those components are also represented in the same way as when distinguishing between NAND strings 50o and 50e. For example, when it is not necessary to distinguish between memory cell transistors MT0o and MTe, ​​they are sometimes simply referred to as "memory cell transistor MT".

[0139] The following description primarily focuses on the first storage column MP (e.g., Figure 4 MP0) and the second storage column MP adjacent to the first storage column MP (e.g. Figure 4Examples of two memory pillars MP (MP5). The first memory pillar MP is sometimes referred to as the "first semiconductor pillar", the NAND string 50o set in the first memory pillar MP is sometimes referred to as the "first string", the memory cell transistors MTo0 to MTo7 contained in the first string are sometimes referred to as the "first memory cell", and the side where the first string is set is sometimes referred to as the "first side". The NAND string 50e set in the first memory pillar MP is sometimes referred to as the "second string", the memory cell transistors MTe0 to MTe7 contained in the second string are sometimes referred to as the "second memory cell", and the side where the second string is set is sometimes referred to as the "second side". Similar to the first storage column MP, the second storage column MP is sometimes referred to as the "second semiconductor column," the NAND string 50o disposed in the second storage column MP is sometimes referred to as the "third string," the memory cell transistors MTo0 to MTo7 contained in the third string are sometimes referred to as the "third memory cell," and the side where the third string is disposed is sometimes referred to as the "third side." Similarly, the NAND string 50e disposed in the second storage column MP is sometimes referred to as the "fourth string," the memory cell transistors MTe0 to MTe7 contained in the fourth string are sometimes referred to as the "fourth memory cell," and the side where the fourth string is disposed is sometimes referred to as the "fourth side." Furthermore, the second side is the opposite side of the first side in the first storage column MP, and the fourth side is the opposite side of the third side in the second storage column MP. Additionally, the first side and the third side are opposite to each other.

[0140] The select transistor STo1 of NAND string 50o is connected to the select gate line SGD1, for example. The select transistor STe1 of NAND string 50e is connected to the select gate line SGD0, for example. Select transistors STo1 and STe1 are connected to one of the 2n select gate lines SGD0 to SGD3.

[0141] The memory cell transistors MTo0 to MTo7 of NAND string 50o are electrically connected in series, arranged along the Z direction, and connected to the odd-numbered lines WLo0 to WLo7 of layer i, respectively. The memory cell transistors MTe0 to MTe7 of NAND string 50e are electrically connected in series, arranged along the Z direction, and connected to the even-numbered lines WLe0 to WLe7 of layer i, respectively. The select transistor STo2 of NAND string 50o is connected, for example, to the odd-numbered select gate line SGSo. The select transistor STe2 of NAND string 50e is connected, for example, to the even-numbered select gate line SGSe. In the first memory column MP, the i memory cell transistors MTo0 to MTo7 (first memory cell), the i memory cell transistors MTe0 to MTe7 (second memory cell), the select transistors STo1 and STe1, and the select transistors STo2 and STe2 share a common semiconductor layer. Similar to the first storage column MP, in the second storage column MP, i storage cell transistors MTo0 to MTo7 (third storage cell) and i storage cell transistors MTe0 to MTe7 (fourth storage cell), selection transistors STo1 and STe1, and selection transistors STo2 and STe2 share a common semiconductor layer.

[0142] The odd-numbered lines WLo0 to WLo7 connected to the memory cell transistors MTo0 to MTo7 (first and third memory cells) contained in NAND string 50o (first and third strings) are sometimes referred to as "first word lines", and the even-numbered lines WLe0 to WLe7 connected to the memory cell transistors MTe0 to MTe7 (second and fourth memory cells) contained in NAND string 50e (second and fourth strings) are sometimes referred to as "second word lines".

[0143] In NAND strings 50e and 50o, the sources and drains of the opposite select transistors STo1 and STe1 are electrically connected to each other. Similarly, the sources and drains of the opposite memory cell transistors MTo0 to MTo7 and MTe0 to MTe7 are electrically connected to each other. The sources and drains of the opposite select transistors STo2 and STe2 are also electrically connected. This electrical connection arises because the channels formed in the opposite transistors share a portion of the memory pillar MP.

[0144] Two NAND strings 50e and 50o in the same memory cylinder MP are connected to the same bit line BL and the same source line SL. For example, memory cylinder MP0 is connected to bit line BL1 and source line SL, and memory cylinder MP5 is connected to bit line BL0 and source line SL.

[0145] Among the 8 odd-number lines WLo0 to WLo7 (first word lines), the first odd-number line WLo0 is closest to the source line SL and furthest from the bit line BL. The eighth odd-number line WLo7 is furthest from the source line SL and closest to the bit line BL. Similarly, among the 8 even-number lines WLe0 to WLe7 (second word lines), the first even-number line WLe0 is closest to the source line SL and furthest from the bit line BL. The eighth even-number line WLe7 is furthest from the source line SL and closest to the bit line BL.

[0146] <1-1-8. Circuit configuration of the sensing amplifier unit SAU>

[0147] Figure 13 This is a circuit diagram illustrating an example of the circuit configuration of the sense amplifier unit SAU according to the first embodiment. Sometimes, details related to... Figures 1 to 13 Description of identical or similar structures.

[0148] The sense amplifier module 70 includes multiple sense amplifier units SAUs respectively associated with bit lines BL0 to BL(L-1). Figure 13 The circuit configuration of a sense amplifier unit (SAU) is shown.

[0149] The sense amplifier unit (SAU) can, for example, temporarily hold data corresponding to the threshold voltage of the corresponding bit line BL that has been read. Furthermore, the sense amplifier unit (SAU) can perform logical operations using the temporarily stored data. The semiconductor memory device 1 can use the sense amplifier unit (SAU) to perform read and write operations, as detailed later.

[0150] like Figure 13As shown, the sense amplifier unit SAU includes a sense amplifier section SA and latching circuits SDL, ADL, BDL, CDL, and XDL. The sense amplifier section SA and the latching circuits SDL, ADL, BDL, CDL, and XDL are interconnected via a bus LBUS to transmit and receive data. The sense amplifier section SA is connected between a power supply line and a node SRC. A voltage lower than the voltage supplied to the power supply line is supplied to the node SRC. The power supply line is a voltage supply line that supplies a high-level voltage to the sense amplifier section SA. The node SRC is a node that supplies a low-level voltage to the sense amplifier section SA. The sense amplifier section SA operates by being supplied with voltage by the power supply line and the node SRC. Alternatively, the power supply line and the node SRC can be configured to supply voltage to components other than the sense amplifier section SA within the sense amplifier unit SAU. A high-level voltage is, for example, voltage VDD, and a low-level voltage is, for example, voltage VSS. Power lines are sometimes referred to as “high voltage supply lines”, “voltage supply terminals”, or “high voltage supply terminals”, while nodes SRC are sometimes referred to as “voltage supply terminals” or “low voltage supply terminals”.

[0151] For example, during a read operation, the sensing amplifier section SA senses the data (threshold voltage) of the corresponding bit line BL that has been read, and determines whether the data corresponding to the read threshold voltage is "0" or "1". The sensing amplifier section SA includes, for example, a p-channel MOS transistor 120, n-channel MOS transistors 121 to 128, and a capacitor 129.

[0152] One end of transistor 120 is connected to the power supply line, and its gate is connected to node INV within the latch circuit SDL. One end of transistor 121 is connected to the other end of transistor 120, and its other end is connected to node SCOM. The gate of transistor 121 is input with the control signal BLX. One end of transistor 122 is connected to node SCOM, and its gate is input with the control signal BLC. Transistor 123 is a high-voltage MOS transistor; one end of transistor 123 is connected to the other end of transistor 122, and its other end is connected to the corresponding bit line BL. The gate of transistor 123 is input with the control signal BLS. Additionally, transistor 128 is sometimes referred to as the "control transistor".

[0153] Transistor 124 has one end connected to node SCOM and the other end connected to node SRC. Its gate is connected to node INV. Transistor 125 has one end connected to the other end of transistor 120 and the other end connected to node SEN. Its gate is fed with the control signal HHL. Transistor 126 has one end connected to node SEN and the other end connected to node SCOM. Its gate is fed with the control signal XXL.

[0154] One end of transistor 127 is grounded, and its gate is connected to node SEN. One end of transistor 128 is connected to the other end of transistor 127, and the other end of transistor 128 is connected to the bus LBUS. The gate of transistor 128 is fed with the control signal STB. One end of capacitor 129 is connected to node SEN, and the other end of capacitor 129 is fed with the clock signal CLK. For example, the clock signal CLK is supplied with voltage VSS.

[0155] Control signals BLX, BLC, BLS, HHL, XXL, STI, STL, and STB are generated, for example, by sequencer 24. Additionally, a power supply line connected to one end of transistor 120 is supplied, for example, with voltage VDD, which serves as the internal power supply voltage of the semiconductor memory device 1, and node SRC is supplied, for example, with voltage VSS, which serves as the ground voltage of the semiconductor memory device 1.

[0156] The latch circuits SDL, ADL, BDL, CDL, and XDL temporarily hold the read data. The latch circuit XDL, for example, is connected to register 25 and is used to sense the input and output of data between the amplifier unit SAU and the input / output circuit 22.

[0157] The latch circuit SDL includes, for example, inverters 130 and 131, and n-channel MOS transistors 132 and 133. The input node of inverter 130 is connected to node LAT, and the output node of inverter 130 is connected to node INV. The input node of inverter 131 is connected to node INV, and the output node of inverter 131 is connected to node LAT. One end of transistor 132 is connected to node INV, and the other end of transistor 132 is connected to the bus LBUS. The gate of transistor 132 is input with the control signal STI. One end of transistor 133 is connected to node LAT, and the other end of transistor 133 is connected to the bus LBUS. The gate of transistor 133 is input with the control signal STL. For example, the data held in node LAT is equivalent to the data held in the latch circuit SDL, and the data held in node INV is equivalent to the inverted data of the data held in node LAT. The circuit configurations of latch circuits ADL, BDL, CDL, and XDL are, for example, the same as the circuit configuration of latch circuit SDL, and therefore are omitted from the description.

[0158] In the sense amplifier unit (SAU), the timing by which each sense amplifier unit (SAU) determines the data corresponding to the threshold voltage read from the bit line BL is based on the timing when the control signal STB is activated. In the first embodiment, the timing by which each sense amplifier unit (SAU) determines the data corresponding to the threshold voltage read from the bit line BL is referred to, for example, as a sensing operation. In the semiconductor memory device 1, "the sequencer 24 activates the control signal STB" corresponds to the sequencer 24 changing the control signal STB from an "L" level to an "H" level.

[0159] The configuration of the sensing amplifier unit (SAU) is not limited to using... Figure 13 The structure and function are explained. For example, in the sense amplifier unit SAU, the transistor 128 whose gate is input with the control signal STB can also be composed of a p-channel MOS transistor. In this case, "the sequencer 24 activates the control signal STB" corresponds to the sequencer 24 changing the control signal STB from the "H" level to the "L" level.

[0160] Furthermore, the number of latching circuits in a sense amplifier unit (SAU) can be designed to be arbitrary. In this case, the number of latching circuits is designed, for example, based on the number of bits of data held by one memory cell transistor (MT). Additionally, multiple bit lines (BL) can be connected to a single sense amplifier unit (SAU) via selectors.

[0161] <1-1-9. Threshold Distribution of MT in Memory Cell Transistors>

[0162] Figure 14 This is a diagram illustrating an example of the threshold distribution, data allocation, read voltage, and verification voltage of each memory cell transistor MT. Figure 14 The vertical axis of the threshold distribution shown corresponds to the number of memory cell transistors MT (number of memory cells), and the horizontal axis corresponds to the threshold voltage Vth of the memory cell transistor MT.

[0163] In the first embodiment, the distribution of the threshold voltage of the memory cell transistor MT in the memory system 3 is shown as follows: Figure 14The example shown is a Quad Level Cell (QLC). In the QLC method, the threshold voltage distribution of multiple memory cell transistors MT is divided into 16 groups. However, the distribution of threshold voltage of memory cell transistors MT is not limited to 16 groups. In the memory system 3, a Triple Level Cell (TLC) method with 8 groups of threshold voltage distribution can also be used, as can a Multi Level Cell (MLC) method with 4 groups of threshold voltage distribution, or a Single Level Cell (SLC) method with 2 groups of threshold voltage distribution can also be used.

[0164] like Figure 14 As shown, the 16 threshold distributions in the QLC mode are represented, for example, in order of threshold voltage from low to high as "0" level, "1" level, "2" level, "3" level, "4" level, "5" level, "6" level, "7" level, "8" level, "9" level, "A" level, "B" level, "C" level, "D" level, "E" level, and "F" level.

[0165] In the threshold distribution described above, the "0" level corresponds to the erase state (state S0) of the memory cell transistor MT. The "1" level corresponds to state S1 of the memory cell transistor MT. The "2" level corresponds to state S2 of the memory cell transistor MT. The "3" level corresponds to state S3 of the memory cell transistor MT. The "4" level corresponds to state S4 of the memory cell transistor MT. Similarly, the "5" level to the "F" level corresponds to... Figure 14 The states shown are S5 to S15.

[0166] The levels “0” through “F” are assigned different 4-bit data as shown below. The memory transistor MT holds data “1111” in level “0”. The memory transistor MT holds data “0111” in level “1”. The memory transistor MT holds data “0011” in level “2”. The memory transistor MT holds data “1011” in level “3”. The memory transistor MT holds data “1001” in level “4”. The memory transistor MT holds data “1000” in level “5”. The memory transistor MT holds data “1010” in level “6”. The memory transistor MT holds data “0010” in level “7”. The memory transistor MT holds data “0110” in level “8”. The memory transistor MT holds data “0100” in level “9”. The memory transistor MT holds data “0000” in level “A”. The memory cell transistor MT holds data "0001" at the "B" level. The memory cell transistor MT holds data "0101" at the "C" level. The memory cell transistor MT holds data "1101" at the "D" level. The memory cell transistor MT holds data "1100" at the "E" level. The memory cell transistor MT holds data "1110" at the "F" level.

[0167] For example, these 4 bits of data are named sequentially from the least significant bit (LSB) to the top bit (TOP). Furthermore, the set of LSBs held by the memory cell transistor MT connected to the same word line (WL) is called the LSB page, the set of LSBs the middle bit page, the set of TOP SBs the high bit page, and the set of TOP SBs the top bit page. Data write and read operations are performed in units of these pages.

[0168] Between adjacent threshold distributions, voltages used in each verification action are set. For example, voltages V1, V2, V3, V4, V5, V6, V7, V8, V9, VA, VB, VC, VD, VE, and VF are set. The verification actions using voltages V1, V2, V3, V4, V5, V6, V7, V8, V9, VA, VB, VC, VD, VE, and VF are respectively denoted as verification actions 1VR, 2VR, 3VR, 4VR, 5VR, 6VR, 7VR, 8VR, 9VR, AVR, BVR, CVR, DVR, EVR, and FVR, respectively. Details are described later.

[0169] During the verification process, voltages V1 to VF are supplied to the word line WL, and the target memory cell transistor MT becomes in the on state. Then, the threshold voltage of the target memory cell transistor MT is read, and it is determined that the threshold voltage corresponding to each state has been reached.

[0170] For example, voltage V2 is set between the maximum threshold voltage at level "1" and the minimum threshold voltage at level "2". When voltage V2 is supplied to the memory cell transistor MT, the memory cell transistor MT with a threshold voltage at level "1" becomes on, and the memory cell transistor MT with a threshold voltage at level "2" or above becomes off. As a result, the memory system 3 can determine that the threshold voltage of the target memory cell transistor MT has reached the threshold voltage corresponding to state S2 at level "2".

[0171] Other voltages V1, V3, V4, V5, V6, V7, V8, V9, VA, VB, VC, VD, VE, and VF are set in the same way as voltage V2, and the state of the memory cell transistor MT when each voltage is supplied is the same as the state of the memory cell transistor MT when voltage V2 is supplied. For example, voltage V3 is set between the maximum threshold voltage at level "2" and the minimum threshold voltage at level "3". When voltage V3 is supplied to the memory cell transistor MT, the memory cell transistor MT with a threshold voltage included in level "2" becomes in the on state, and the memory cell transistor MT with a threshold voltage included in the threshold distribution above level "3" becomes in the off state. As a result, the memory system 3 can determine that the threshold voltage of the target memory cell transistor MT has reached the threshold voltage corresponding to state S3 at level "3". Furthermore, for example, the verification voltage VF is set between the maximum threshold voltage at the "E" level and the minimum threshold voltage at the "F" level. When voltage VF is supplied to the memory cell transistor MT, the memory cell transistor MT with a threshold voltage within the "E" level becomes in the on state, and the memory cell transistor MT with a threshold voltage within the threshold distribution above the "F" level becomes in the off state. As a result, the memory system 3 can determine that the threshold voltage of the target memory cell transistor MT has reached the threshold voltage corresponding to state S15 at the "F" level.

[0172] Furthermore, a read voltage used in each read operation is set between adjacent threshold distributions. In the first embodiment, for the sake of simplicity, the voltages V1, V2, V3, V4, V5, V6, V7, V8, V9, VA, VB, VC, VD, VE, and VF used in the verification operation are used as read voltages. The read operations using voltages V1, V2, V3, V4, V5, V6, V7, V8, V9, VA, VB, VC, VD, VE, and VF are respectively denoted as read operations 1R, 2R, 3R, 4R, 5R, 6R, 7R, 8R, 9R, AR, BR, CR, DR, ER, and FR. In read operation 1R, the storage system 3 determines whether the threshold voltage of the storage cell transistor is included in the "0" level or included in the "1" level or above. In the other read operations 2R to FR, similarly to read operation 1R, the storage system 3 determines the threshold voltage corresponding to the level of each read operation.

[0173] In other read operations 2R to FR, similarly to read operation 1R, the storage system 3 determines the threshold voltage corresponding to each read operation level. For example, in read operation 2R, the storage system 3 determines whether the threshold voltage is contained in the "1" level or the "2" level. In read operation FR, the storage system 3 determines whether the threshold voltage is contained in the "E" level or the "F" level.

[0174] Additionally, the voltage VREAD is set to a value higher than the maximum threshold voltage (VF) of the highest threshold distribution (e.g., "F" level). For example, the voltage VREAD is the voltage supplied to the unselected word line USEL-WL during a read operation. The voltage VREAD can also be the voltage supplied to the select word line SEL-WL, the select gate line SGD, or the select gate line SGS. Regardless of the stored data, the memory cell transistor MT with the gate electrode to which the voltage VREAD is applied is turned on.

[0175] When reading data allocated as described above, the data for the low-order page is determined by read actions 5R, BR, and ER. The data for the middle-order page is determined by read actions 4R, 6R, 9R, and FR. The data for the high-order page is determined by read actions 2R, 8R, AR, and CR. The data for the first-order page is determined by read actions 1R, 3R, 7R, and DR. That is, the data for the low-order, middle-order, high-order, and first-order pages are determined by 3, 4, 4, and 4 read actions, respectively. The data allocation described above is referred to as "4-4-4-3 code" or "4-4-4-3 encoding." With the data allocated as described above, adjacent states become Gray codes that differ by 1 bit.

[0176] <1-2. Examples of Actions>

[0177] <1-2-1. Overview of Write and Read Operations>

[0178] use Figure 15 This describes the selection of the gate line SGD during the write and read operations of semiconductor memory device 1, indicating whether it is selected or not. Figure 15 It is shown in Figure 3 The diagram shows the selected gate line SGD in a planar layout. For example, when a predetermined voltage (e.g., voltage VREAD) is supplied to wiring layer 10-1d, the selected gate line SGD1 is selected, and the eight selected transistors STo1 disposed on the first side of each of the memory pillars MP0, MP1, MP4, MP5, MP8, MP9, MP12, and MP13 are turned on. At this time, when a predetermined voltage (e.g., voltage VSS) is supplied to wiring layer 10-0d, the eight selected transistors STe1 disposed on the second side of each of the memory pillars MP0, MP1, MP4, MP5, MP8, MP9, MP12, and MP13 are turned off.

[0179] Next, use Figures 16-18 This indicates whether the text line WL is selected or not. Figure 16 It is shown in Figure 4 The diagram shows the selection and non-selection of the character line WL in the planar layout. Figure 17 and Figure 18 It is used to explain in Figure 16 The end cross-sectional view shown illustrates whether the gate line and word line are selected or not.

[0180] For example, when wiring layer 11, which includes wiring layers 11-1 and 11-3, is supplied with a predetermined voltage (e.g., voltage VREAD), the odd-numbered lines WLo (WLo0 to WLo7) provided on the first side of each of the memory pillars MP0, MP1, MP4, MP5, MP8, MP9, MP12, and MP13 become either on or off depending on the supplied voltage. At this time, when wiring layer 11, which includes wiring layer 11-0a, is supplied with a predetermined voltage (e.g., voltage VSS), the even-numbered lines WLe (WLe0 to WLe7) provided on the second side of each of the memory pillars MP0, MP1, MP4, MP5, MP8, MP9, MP12, and MP13 become either on or off depending on the supplied voltage.

[0181] As a result, the memory cell transistor MT belonging to the memory pillar corresponding to the select gate line SGD1 in block BLK is selected. The memory cell transistor MT selected by each select gate line forms a memory group MG. In addition, one page is formed by the memory cell transistor MT corresponding to the selected word line WL in the memory group MG. Therefore, block BLK contains memory groups MG with a number corresponding to the number of select gate lines SGD, and each memory group MG contains pages with a number corresponding to the number of layers of word lines WL. The operation is the same when a wiring layer other than the above wiring layer is selected, and the explanation is omitted here.

[0182] Next, use Figure 19 This describes the programming loop included in the write operation. Semiconductor memory device 1, for example... Figure 19 As shown, multiple programming loops (e.g., X times, where X is an integer greater than 1) are executed during a write operation. Each programming loop contains at least one programming action and one or more verification actions (e.g., Y times, where Y is an integer greater than 1) executed afterward. During a write operation, the programming loop containing both programming and verification actions is executed multiple times. Additionally, verification actions are sometimes omitted within each programming loop.

[0183] During a programming operation, electrons are injected into the charge storage layer of the memory cell transistor MT that is to be written to, causing its threshold voltage to rise. Conversely, electron injection into the charge storage layer of the memory cell transistor MT that is not to be written to is prohibited, and its threshold voltage is maintained. During a programming operation, for example, a voltage VPGM is supplied to the select word line SEL-WL. This selects multiple memory cell transistors MT connected to the select word line SEL-WL. The threshold voltage of each memory cell transistor MT rises or is maintained according to the voltage supplied to its corresponding bit line BL. The voltage VPGM in a programming operation within a certain programming cycle is higher than the voltage VPRG in the programming operation within the previous programming cycle by a voltage ΔVPGM. That is, the voltage VPRG in a programming operation increases stepwise as the programming cycle progresses.

[0184] Verification is performed after programming. It involves reading the selected memory cell transistor MT using a specified voltage (e.g., VA) to confirm whether its threshold voltage has reached a target level. A memory cell transistor MT whose threshold voltage reaches the target level is considered to have passed the verification process and is subsequently not writable, preventing the injection of electrons into the charge storage layer.

[0185] Here, use Figure 19 or Figure 20 This is an example illustrating the order of sensing actions corresponding to verification actions. Within the same programming loop, sensing actions in different verification actions are executed consecutively. Specifically, as follows... Figure 19As shown, when two verification actions (mutually different verification actions 2VR and 1VR) are performed in the same programming loop, the order of the sensing actions is as follows: the first is the sensing action of verification action 2VR (verification of the threshold voltage of state S2), and the second is the sensing action of verification action 1VR (verification of the threshold voltage of state S1). Similarly, for example, when performing three verification actions (mutually different verification actions 3VR, 2VR, and 1VR), the order of sensing actions is as follows: the first is the sensing action of verification action 3VR (verification of the threshold voltage in state S3), the second is the sensing action of verification action 2VR (verification of the threshold voltage in state S2), and the third is the sensing action of verification action 1VR (verification of the threshold voltage in state S1). Furthermore, when performing three verification actions (mutually different verification actions 9VR, 8VR, and 7VR), the order of sensing actions is as follows: the first is the sensing action of verification action 9VR (verification of the threshold voltage in state S9), the second is the sensing action of verification action 8VR (verification of the threshold voltage in state S8), and the third is the sensing action of verification action 7VR (verification of the threshold voltage in state S7).

[0186] In verification actions, such as verification action 2VR or verification action 1VR, the order of sensing actions differs between different programming loops. For example, as... Figure 19 As shown, in the verification actions within the initial programming cycle, the sensing action of verification action 1VR (verification of the threshold voltage of state S1) is the second in order, and in the verification actions within the next programming cycle, the sensing action of verification action 1VR is the third in order. Similarly, in the verification actions within the initial programming cycle, the sensing action of verification action 2VR (verification of the threshold voltage of state S2) is the first in order, and in the verification actions within the next programming cycle, the sensing action of verification action 2VR is the second in order. Likewise, for verification actions 3VR to EVR, the order of sensing actions sometimes differs between different programming cycles. For example, to confirm whether the threshold voltage of the selected memory cell transistor MT has reached the target level, sometimes, as in state S15 of the highest bit, one sensing action of verification action FVR is performed. Figure 20 In cases other than S15, sometimes 2 to 6 sensing actions are performed for confirmation. The order of the sensing actions 1VR to EVR can be all of 1 to 6. Figure 20In semiconductor memory device 1, if the threshold voltage of the selected memory cell transistor MT in the sensing action of the verification action in a certain programming cycle does not reach the target level, the selected memory cell transistor MT is considered to have failed the verification action. The level of the selected memory cell transistor MT is the level of the verification object, and the verification action of the selected memory cell transistor MT is also performed in the following programming cycle.

[0187] For example, in verification action 2VR, voltage V2 is supplied to the select word line SEL-WL, and the memory cell transistor MT connected to the select word line SEL-WL is selected. It is determined whether the threshold voltage of the selected memory cell transistor MT reaches voltage V2 (whether it enters the "2" level). That is, it is determined whether the selected memory cell transistor is in state S2. In verification action 7VR, voltage V7 is supplied to the select word line SEL-WL, and the memory cell transistor MT connected to the select word line SEL-WL is selected. It is determined whether the threshold voltage of the selected memory cell transistor MT reaches voltage V7 (whether it enters the "7" level). That is, it is determined whether the selected memory cell transistor is in state S7.

[0188] In semiconductor memory device 1, by repeatedly executing a programming cycle that includes programming and verification operations, the threshold voltage of the selected memory cell transistor MT rises to a target level. More specifically, in semiconductor memory device 1, if the threshold voltage of the selected memory cell transistor MT does not reach the target level (e.g., voltage VA), the selected memory cell transistor MT is considered to have failed the verification operation. Then, semiconductor memory device 1 gradually increases the level of the prescribed voltage from the previous programming cycle until the threshold voltage of the selected memory cell transistor MT reaches the target level. If the threshold voltage of the selected memory cell transistor MT reaches the target level, the verification operation is considered to have passed, and it is subsequently excluded from the programmable operations. Thus, the threshold voltages of the multiple memory cell transistors MT that are the targets of the write operation rise to their respective target levels.

[0189] Next, use Figure 21 and Figure 22 Explain the read operation of semiconductor memory device 1. Figure 21 This is a diagram illustrating an example of the sequence of sensing actions corresponding to a read operation in semiconductor memory device 1. Figure 22 This diagram illustrates the reading of the first page during a read operation of semiconductor memory device 1. Figure 22The diagram shows the selected odd-number line WLo1, the unselected even-number line WLe1, the unselected even-number line WLe0, the unselected even-number line WLe2, and the control signal STB. The selected gate lines SGD and SGS, source lines, etc., are omitted. In the semiconductor memory device 1, the read operation is performed after the write operation.

[0190] like Figure 21 As shown, the threshold voltages corresponding to the states S13, S7, S3, and S1 are read in the order of reading actions DR, 7R, 3R, and 1R, thereby determining the data of the first page. That is, regarding the order of sensing actions in the first page, the first is the sensing action of reading action DR (reading the threshold voltage of state S13), the second is the sensing action of reading action 7R (reading the threshold voltage of state S7), the third is the sensing action of reading action 3R (reading the threshold voltage of state S3), and the fourth is the sensing action of reading action 1R (reading the threshold voltage of state S1). Similar to the first page, the order of sensing actions in the high-order pages is as follows: the first is the sensing action CR (reading the threshold voltage in state S12), the second is the sensing action AR (reading the threshold voltage in state S10), the third is the sensing action 8R (reading the threshold voltage in state S8), and the fourth is the sensing action 2R (reading the threshold voltage in state S2). Similarly to the first and high-order pages, the order of sensing actions in the middle page is as follows: the first is the sensing action FR (reading the threshold voltage in state S15), the second is the sensing action 9R (reading the threshold voltage in state S9), the third is the sensing action 6R (reading the threshold voltage in state S6), and the fourth is the sensing action 4R (reading the threshold voltage in state S4). In addition, regarding the order of sensing actions in the low-order page, the first is the sensing action of reading action ER (reading the threshold voltage in state S14), the second is the sensing action of reading action BR (reading the threshold voltage in state S11), and the third is the sensing action of reading action 5R (reading the threshold voltage in state S5).

[0191] like Figure 22As shown, during the first page read operation, before time t0, the odd-numbered lines SEL-WLo1 and the unselected even-numbered lines USEL-WLe0~2 (USEL-WLe2, USEL-WLe1, and USEL-WLe0) are supplied with voltage VSS. The transistors MT of each memory cell are in the off state. Before time t3, the control signal STB is supplied with voltage VSS. In the first embodiment, voltage VSS is, for example, a voltage that allows other voltages to be defined based on voltage VSS; voltage VSS can be called a reference voltage, or it can be 0V, or it can be ground voltage.

[0192] During time t0 to t1, the odd-numbered lines SEL-WLo1 and the unselected even-numbered lines USEL-WLe0 to 2 are supplied with voltage VREAD.

[0193] Next, during times t1 to t4, the read operation DR is performed. The odd-numbered lines SEL-WLo1 are supplied with voltage VCG_S13. Voltage VCG_S13 is, for example, voltage VD. The unselected even-numbered lines USEL-WLe0 to 2 are supplied with voltage VBB. During times t3 to t4, the control signal STB is activated, and the voltage of the control signal STB changes from "H" level (VDD) to "L" level (VSS). Thus, the threshold voltage corresponding to state 13 can be determined.

[0194] Furthermore, voltage VBB is lower than voltage VSS, and is a negative voltage. The unselected even-number line USEL-WLe1 is opposite to the selected odd-number line SEL-WLo1. Additionally, the unselected even-number lines USEL-WLe0 and USEL-WLe2 are adjacent to the unselected even-number line USEL-WLe1. By supplying voltage VBB (a negative voltage) to the even-number lines USEL-WLe0~2, the memory cell transistors MTe0~2 (MTe0, MTe1, and MTe2) connected to the even-number lines USEL-WLe0~2 can be fully turned off. As a result, the current flowing through memory cell transistors MTo1 connected to the selected odd-number line SEL-WLo1 can be suppressed, thus suppressing fluctuations in the threshold voltage of memory cell transistor MTo1 and preventing erroneous reads. Furthermore, from time t4 to t10, the voltage supplied to the unselected even-number lines USEL-WLe0~2 changes from voltage VREAD to voltage VBB.

[0195] Furthermore, the unselected even-numbered lines USEL-WLe to which voltage VBB is supplied are not limited to unselected even-numbered lines USEL-WLe0 to 2. For example, voltage VBB can be supplied to unselected even-numbered lines USEL-WLe0 to 4 (WLe0, WLe1, WLe2, WLe3, WLe4), and voltage VBB can also be supplied to unselected even-numbered lines USEL-WLe0 to 7 (WLe0, WLe1, WLe2, WLe3, WLe4, WLe5, WLe6, WLe7). Voltage VBB can be supplied to unselected even-numbered lines USEL-WLe within the range that does not affect the selected odd-numbered lines SEL-WLo1.

[0196] Next, during times t4 to t6, read operation 7R is executed. The odd-number line SEL-WLo1 is supplied with voltage VCG_S7. Voltage VCG_S7 is, for example, voltage V7. During times t5 to t6, control signal STB is activated, and similarly to state S13, the threshold voltage corresponding to state S7 can be determined.

[0197] Next, during times t6 to t8, read operation 3R is executed. The odd-number line SEL-WLo1 is supplied with voltage VCG_S3. Voltage VCG_S3 is, for example, voltage V3. During times t7 to t8, the control signal STB is activated, and similarly to state S13, the threshold voltage corresponding to state S3 can be determined.

[0198] Next, during times t8 to t10, read operation 1R is executed. The odd-number line SEL-WLo1 is supplied with voltage VCG_S1. Voltage VCG_S1 is, for example, voltage V1. During times t9 to t10, the control signal STB is activated, and similarly to state S13, the threshold voltage corresponding to state S1 can be determined.

[0199] As described above, the first page read operation is completed. However, during the read operation, for example, the time Tr13 from the moment the voltage VBB is supplied to the memory cell transistor MTe1 opposite to the selected memory cell transistor MTo1 (from time t2) to the sensing operation of the read operation DR (time t3) is different from the time Tr7 from the moment the voltage VBB is supplied to the memory cell transistor MTe1 opposite to the selected memory cell transistor MTo1 (from time t2) to the sensing operation of the read operation 7R (time t5). Time Tr13 is shorter than time Tr7.

[0200] Here, use Figure 8 , Figure 35 as well as Figure 36 This describes the actions in semiconductor memory device 1 related to the interference effect between memory cells. Figure 35 It shows the... Figure 9The diagram shows an example of a word line being supplied with voltage, thereby exciting holes. Figure 36 This is a schematic diagram illustrating the relationship between the time when the voltage VBB is applied to the word line (VBB application time) and the effective threshold voltage of the selected memory cell transistor. In the description of operations related to the interference effect between memory cells in semiconductor memory device 1, the relationship between... Figures 1 to 22 Description of identical or similar structures. Additionally, in Figure 36 The diagram schematically illustrates the relationship between the applied voltage VBB and the effective threshold voltage of a selected memory cell transistor. An example is shown where the effective threshold voltage of the selected memory cell transistor changes linearly with respect to voltage VBB; however, the effective threshold voltage of the selected memory cell transistor can also change non-linearly with respect to voltage VBB. In the semiconductor memory device 1 according to the first embodiment, for example, as... Figure 8 As shown, two word lines WL are arranged opposite each other across a memory pillar MP. Therefore, the conductive layer 42 contained in the memory cell transistor (e.g., memory cell transistor MTo) corresponding to a word line (e.g., word line WLo) Figure 35 ), and the conductive layer 42 contained in the memory cell transistor (e.g., memory cell transistor MTe) corresponding to another word line (e.g., word line WLe). Figure 35 Relative. That is, two memory cell transistors (e.g., memory cell transistors MTo and MTe) are configured relative to each other. In this case, the threshold voltage of the selected memory cell transistor (e.g., memory cell transistor MTo1) may vary due to the inter-cell interference effect experienced by the relative memory cell transistor (e.g., memory cell transistor MTe1). On the other hand, as Figure 35 As shown, if a voltage VCG is supplied to the selected memory cell transistor (memory cell transistor MTo1) and a voltage VBB is supplied to the opposing memory cell transistor (memory cell transistor MTe1), a hole 60 will be induced. When a hole 60 is induced in the opposing memory cell transistor MTe1, it acts as a shield, thus reducing the inter-cell interference effect experienced by the selected memory cell transistor MTo1 and lowering its effective threshold voltage. The longer the opposing memory cell transistor (e.g., memory cell transistor MTe1) is supplied with voltage VBB, the easier it is to induce a hole 60. Therefore, as time passes, the inter-cell interference effect decreases, and the effective threshold voltage of the selected memory cell transistor (e.g., memory cell transistor MTo1) gradually decreases. That is, in the semiconductor memory device 1, as... Figure 36As shown, the longer the relative memory cell transistor is supplied with voltage VBB, the lower the effective threshold voltage of the selected memory cell transistor can be. Conversely, when the supplied voltage VBB time is short, a higher voltage should be applied to the select word line (e.g., WLo1) during read or check operations; when the supplied voltage VBB time is long, a lower voltage should be applied to the select word line (e.g., WLo1) during read or check operations. For example, as mentioned above, the effect of inter-cell interference is smaller during the sensing operation of read operation 7R compared to the sensing operation of read operation DR.

[0201] On the other hand, even when the order of sensing actions in the verification operation differs from the order of sensing actions in the reading operation in each state, the timing of the supplied voltage VBB also differs. Therefore, when the order of sensing actions in the verification operation differs from the order of sensing actions in the reading operation in each state, the threshold voltage of the selected memory cell transistor will also change due to the inter-cell interference effect experienced by the relative memory cell transistor.

[0202] In the semiconductor memory device 1, even if the order of sensing actions in the verification operation is different from the order of sensing actions in the reading operation in each state, by making the voltage supplied to the select word line during the verification operation higher or lower than the voltage supplied to the select word line during the reading operation, the inter-cell interference effect borne by the opposite memory cell transistor can be suppressed, thereby suppressing erroneous readings. Details will be described later.

[0203] <1-2-2. An example of a verification action>

[0204] In the following description relating to the first embodiment, the use of Figures 23-30 , Figure 37 This illustrates an example of executing the sensing action in the first page after performing the three verification actions mentioned above (the three different verification actions 9VR, 8VR, and 7VR).

[0205] use Figure 23This section explains the various signal and current paths during the verification operation in semiconductor memory device 1. In an example of the verification operation in semiconductor memory device 1, an example of performing the verification operation in memory cell MP0 is described. The odd-number lines WLo1 included in the NAND string 50o of memory cell MP0 are supplied with a specified voltage VM (e.g., VCG_S7), and the memory cell transistor MTo1 connected to the odd-number lines WLo1 is selected. When the memory cell transistor MTo1 is selected, the selection gate lines SGD1 and SGSo are selected, and the odd-number lines WLo0, 2 to 7 (WLo0, WLo2, WLo3, WLo4, WLo5, WLo6, WLo7) other than the odd-number lines SEL-WLo1 are not selected (become unselected). Additionally, when the memory cell transistor MTo1 is selected, the select gate lines SGD0 and SGSe, as well as the even-numbered lines WLe0~2 (WLo0, WLo1, WLo2) contained in the NAND string 50e, are not selected (become unselected), and the even-numbered lines WLo3~7 (WLo3, WLo4, WLo5, WLo6, WLo7) other than the even-numbered lines SEL-WLo0~2 are not selected (become unselected). As a result, current flows through... Figure 23 The path indicated by the thick arrow determines whether current flows through the path indicated by the dashed arrow, based on the threshold voltage corresponding to each state determined by the sensing action in the verification process of the selected memory cell transistor MTo1. Specifically, it determines whether current flows from the bit line BL1 to the source line SL.

[0206] Additionally, in the following description, in NAND strings 50o and 50e, the word line WL connected to the memory cell transistor MT selected as the object of the verification operation is called the select word line SEL-WL, and the word line connected to other memory cell transistors MT is called the unselected word line USEL-WL. The select gate line electrically connected to the select word line SEL-WL is called the select gate line SEL-SGD or SEL-SGS, and the other select gate lines are called the unselected gate lines USEL-SGD or USEL-SGS. Furthermore, sometimes the various signal lines included in NAND string 50o are labeled "odd number," and the various signal lines included in NAND string 50e are labeled "even number." For example, the select gate line included in NAND string 50o is called the select odd number select gate line SEL-SGDo or SEL-SGSo, and the select word line is called the select odd number line SEL-WLo0 to 7 (e.g., SEL-WLo1). Similar to NAND string 50o, the unselected select gate lines included in NAND string 50e are called unselected odd select gate lines USEL-SGDe or USEL-SGSe, and the unselected word lines are called unselected even number lines USEL-WLe1 to 7 (e.g., USEL-WLe1).

[0207] <1-2-2-1. Example of verification actions before time tv0>

[0208] use Figure 24 as well as Figure 25 This section provides an example of a verification action being performed before time tv0. Figure 24 This is a timing diagram showing the various signals during the verification operation in semiconductor memory device 1. Figure 25 This is a timing diagram showing the various signals during the verification operation in the semiconductor memory device involved in the comparative example.

[0209] like Figure 24 and Figure 25 As shown, the verification operation before time tv0 is, for example, setting the state of semiconductor memory device 1 to standby mode. Standby mode is, for example, a state waiting to determine whether to perform a verification operation. Before time tv0, the following are supplied with voltage VSS: select gate lines SEL-SGD and SGS (select gate lines SGD1 and SGSo), unselect gate lines USEL-SGS (select gate line SGSe), unselect gate lines USEL-SGD (select gate line SGD0), select odd-number lines SEL-WLo1, unselect even-number lines WLe0~2 (WLe0, WLe1, WLe2), unselected word lines other than even-number lines WLe0~2 USEL-WL, control signal STB, and source line SL. Furthermore, before time t3, control signal STB is supplied with voltage VSS. Additionally, at least before time tv8, source line SL is supplied with voltage VSS. Each select transistor ST1 and ST2 and each memory cell transistor MT are in the off state.

[0210] <1-2-2-2. Example of verification actions during the first action period (from time tv0 to time tv1)>

[0211] use Figures 24-26 This section provides an example of how the verification actions are performed during the first action. Figure 26 It is used for explanation Figure 24 An example of a circuit diagram showing the various signals and current paths during the first operation.

[0212] like Figure 24 and Figure 25As shown, the first operation period is, for example, the period during which the voltage VREAD is supplied to the odd-number selection line SEL-WLo1. Specifically, the select gate lines SEL-SGD and SGS, the unselected gate lines USEL-SGS and USEL-SGD, the select odd-number selection line SEL-WLo1, the unselected even-number selection lines WLe0~2, and the unselected word line USEL-WL (other than WLe0~2) are supplied with the voltage VREAD. Each select transistor ST1 and ST2, and each memory cell transistor MT, are in the on state. Therefore, the current... Figure 26 The flow occurs along the path indicated by the thick arrow (from bit line BL1 to source line SL). Additionally, the unselected word lines USEL-WL (excluding the unselected even-number lines WLe0-2), the select gate lines SEL-SGD and SGS, and the unselected gate line USEL-SGS are supplied with voltage VREAD before time tv8.

[0213] <1-2-2-3. Examples of verification actions during the second action period (from time tv1 to time tv4)>

[0214] use Figure 24 , Figure 25 as well as Figure 27 An example of the verification action being performed during the second action is provided. Figure 27 It is used for explanation Figure 24 This is an example of a circuit diagram showing the various signals and current paths during the second operation period. In the description of "1-2-2-3. Second Operation Period," details related to... Figures 1 to 26 Description of identical or similar structures.

[0215] like Figure 24 and Figure 25 As shown, the second operation period is the period during which the sensing operation of the verification operation 9VR is performed. During the second operation period, the voltage supplied to the unselected even number lines USEL-WLe0~2 changes from voltage VREAD to voltage VBB, and the voltage supplied to the unselected selection gate line USEL-SGD changes from voltage VREAD to voltage VSS. The selected odd number line SEL-WLo1 is supplied with voltage VCG_S9U. Voltage VCG_S9U is, for example, a voltage higher than voltage V9, and is higher than in the comparison example ( Figure 25 The voltage VCG_S9 supplied to the word line in the semiconductor memory device involved is high. At times tv3 to tv4, the control signal STB is activated (the control signal STB changes from the "L" level to the "H" level), and the semiconductor memory device 1 can determine the threshold voltage corresponding to state S9.

[0216] like Figure 27As shown, selector transistors STo1 and STo2, memory cell transistor MTo0, memory cell transistors MTo2-7 (MTo2, MTo3, MTo4, MTo5, MTo6, MTo7), memory cell transistors MTe3-7 (MTe3, MTe4, MTe5, MTe6, MTe7), and selector transistor STe2 are in the on state, while memory cell transistors MTe0-2 are in the off state. Therefore, the current is... Figure 27 The path, indicated by the thick arrow, flows from bit line BL1 to the selected memory cell transistor MTo0. Furthermore, based on the result of determining the threshold voltage corresponding to state S9, the current... Figure 27 The flow passes through the path indicated by the thick arrow. As a result, the semiconductor memory device 1 is able to determine the threshold voltage corresponding to state S9.

[0217] In the verification process at this time, the sensing action of 9VR in state S9 is executed first in the programming loop. Figure 20 and Figure 24 On the other hand, in the read operation, the sensing action of read action 9R in state S9 is the second read action of the middle page (). Figure 21 For example, when the sensing sequence in the verification operation is earlier than the sensing sequence in the read operation, the threshold voltage of the memory cell transistor appears to be higher during the sensing sequence in the verification operation. Therefore, in the semiconductor memory device 1, when the sensing sequence in the verification operation is different from the sensing sequence in the read operation, and the sensing sequence in the verification operation is earlier than the sensing sequence in the read operation, the voltage supplied to the select word line (the word line corresponding to the selected memory cell transistor) during the verification operation is set to be higher than the voltage supplied to the select word line during the read operation. As a result, in the semiconductor memory device 1, the change in the threshold voltage of the selected memory cell transistor can be minimized, thereby suppressing erroneous reads. Furthermore, in Figure 24 The example shown illustrates that the verification action 9VR of state S9 is executed first. However, in subsequent programming loops, the verification action 9VR of state S9 can be executed second or third. In a programming loop where the verification action 9VR of state S9 is executed second, for example, the voltage supplied to the select word line during the verification action is set to be the same as the voltage supplied to the select word line during the read action. Conversely, in a programming loop where the verification action 9VR of state S9 is executed third or later, for example, the voltage supplied to the select word line during the verification action is set to be lower than the voltage supplied to the select word line during the read action.

[0218] Additionally, similar to the read operation, voltage VBB is lower than voltage VSS, and is a negative voltage. Furthermore, at least from time tv2 to tv8, the unselected gate line USEL-SGD is supplied with voltage VSS, and the unselected even-number lines USEL-WLe0 to 2 are supplied with voltage VBB.

[0219] Furthermore, similarly to the read operation, during the verification operation, by supplying a voltage VBB (negative voltage) to the unselected even-number lines USEL-WLe0~2, the memory cell transistors MTe0~2 (MTe0, MTe1, and MTe2) connected to the unselected even-number lines USEL-WLe0~2 can be fully turned off. As a result, the current flowing through the memory cell transistors MTo1 connected to the selected odd-number line SEL-WLo1 can be suppressed, thus suppressing fluctuations in the threshold voltage of the memory cell transistor MTo1 and preventing erroneous reads.

[0220] <1-2-2-4. Examples of verification actions during the third action period (from time tv4 to time tv6)>

[0221] use Figure 24 , Figure 25 as well as Figure 28 An example of the verification action being performed during the third action is provided. Figure 28 It is used for explanation Figure 24 This is an example of a circuit diagram showing the various signals and current paths during the third operation period. In the description of "1-2-2-4. Third Operation Period," details related to... Figures 1 to 27 Description of identical or similar structures.

[0222] like Figure 24 and Figure 25 As shown, the third operation period is the period during which the sensing operation of verification operation 8VR is performed. During the third operation period, the voltage supplied to the odd-number line SEL-WLo1 changes from voltage VCG_S9U to voltage VCG_S8U. The voltage supplied to the other signal lines is the same as the voltage supplied at time tv4 during the second operation period. Voltage VCG_S8U is, for example, a voltage higher than voltage V8, and is higher than in the comparison example ( Figure 25 The voltage VCG_S8 supplied to the word line in the semiconductor memory device involved is high. At times tv5 to tv6, the control signal STB is activated (the control signal STB changes from the "L" level to the "H" level), and the semiconductor memory device 1 can determine the threshold voltage corresponding to state S8.

[0223] In the verification action at this time, the verification action 8VR sensing action in state S8 is executed second in the programming loop. Figure 20 On the other hand, in the read operation, the sensing operation of read operation 8R in state S8 is the third read operation of the high-order page. Therefore, in the verification operation 8VR in state S8, similarly to the verification operation 9VR in state S9, the voltage supplied to the select word line during the verification operation is set to be higher than the voltage supplied to the select word line during the read operation. As a result, for read operation 8R in state S8, the change in the threshold voltage of the selected memory cell transistor in the semiconductor memory device 1 can be minimized, thereby suppressing erroneous reads.

[0224] and Figure 27 Similarly, during the third action, such as Figure 28 As shown, transistors STo1 and STo2, memory cell transistors MTo0, MTo2-7 (MTo2, MTo3, MTo4, MTo5, MTo6, MTo7), and MTe3-7 (MTe3, MTe4, MTe5, MTe6, MTe7), as well as selection transistor STe2, are in the on state, while memory cell transistors MTe0-2 are in the off state. Therefore, the current is... Figure 28 The path, indicated by the thick arrow, flows from bit line BL1 to the selected memory cell transistor MTo0. Furthermore, based on the result of determining the threshold voltage corresponding to state S8, the current... Figure 28 The flow passes through the path indicated by the thick arrow. As a result, the semiconductor memory device 1 is able to determine the threshold voltage corresponding to state S8.

[0225] <1-2-2-5. Example of a verification action during the fourth action period (from time tv6 to time tv8)>

[0226] use Figure 24 , Figure 25 as well as Figure 29 An example of the verification action being performed during the fourth action is provided. Figure 29 It is used for explanation Figure 24 This is an example of a circuit diagram showing the various signal and current paths during the fourth operation period. In the description of "1-2-2-5. Fourth Operation Period," details related to... Figures 1 to 27 Description of identical or similar structures.

[0227] like Figure 24 and Figure 25As shown, the fourth operation period is the period during which the sensing operation of verification operation 7VR is performed. During the fourth operation period, the voltage supplied to the odd-number line SEL-WLo1 changes from voltage VCG_S8U to voltage VCG_S7D. The voltage supplied to the other signal lines is the same as the voltage supplied at time tv6 during the second operation period. Voltage VCG_S7D is, for example, a voltage lower than voltage V7, and is lower than in the comparison example (…). Figure 25 The voltage VCG_S7 supplied to the word line in the semiconductor memory device involved is low. At times tv7 to tv8, the control signal STB is activated (the control signal STB changes from the "L" level to the "H" level), and the semiconductor memory device 1 can determine the threshold voltage corresponding to state S7.

[0228] In the verification process at this time, the sensing action of 7VR in state S7 is executed second in the programming loop. Figure 20 On the other hand, during the read operation, the sensing action of read operation 7R in state S7 is the third read operation of the first page. For example, if the sequence of sensing actions in the verification operation is later than the sequence of sensing actions in the read operation, the threshold voltage of the memory cell transistor appears to be lower during the sensing actions in the verification operation. Therefore, in the semiconductor memory device 1, when the sequence of sensing actions in the verification operation is different from the sequence of sensing actions in the read operation, and the sequence of sensing actions in the verification operation is later than the sequence of sensing actions in the read operation, the voltage supplied to the select word line during the verification operation is set to be lower than the voltage supplied to the select word line during the read operation. As a result, in the semiconductor memory device 1, the change in the threshold voltage of the selected memory cell transistor can be minimized, thereby suppressing erroneous reads.

[0229] and Figure 27 and Figure 28 Similarly, during the fourth action, such as Figure 29 As shown, transistors STo1 and STo2, memory cell transistors MTo0, MTo2-7 (MTo2, MTo3, MTo4, MTo5, MTo6, MTo7), and MTe3-7 (MTe3, MTe4, MTe5, MTe6, MTe7), as well as selection transistor STe2, are in the on state, while memory cell transistors MTe0-2 are in the off state. Therefore, the current is... Figure 29 The path, indicated by the thick arrow, flows from bit line BL1 to the selected memory cell transistor MTo0. Furthermore, based on the threshold voltage corresponding to state S7, the current... Figure 29 The flow passes through the path indicated by the thick arrow. As a result, the semiconductor memory device 1 is able to determine the threshold voltage corresponding to state S8.

[0230] <1-2-2-6. An example of the write operation process>

[0231] use Figure 30 and Figure 37 This is an example illustrating the process of a write operation. Figure 30 This is a flowchart illustrating the verification operation in semiconductor memory device 1. Figure 37 This is a timing diagram showing the various signals during the verification operation of semiconductor memory device 1. In the description of "1-2-2-6. An Example of the Write Operation Flow", the timing diagrams are sometimes omitted. Figures 1 to 29 , Figure 35 , Figure 36 Description of identical or similar structures. Figure 37 The selection of odd-numbered lines SEL-WLo1 and its use are shown. Figure 24 The selection of odd-numbered lines SEL-WLo1 is the same, so it is omitted here. Figure 37 The following is an explanation of selecting the odd-numbered line SEL-WLo1.

[0232] In the semiconductor memory device 1, when the write operation begins, in step S10, the sequencer 24 controls the sense amplifier module 70, the line decoder 29, the voltage generation circuit 27, and the driver group 28, etc., to perform the programming operation.

[0233] In step S20, which follows step S10, sequencer 24 controls sensing amplifier module 70, line decoder 29, voltage generation circuit 27 and driver group 28, etc., to start the verification operation.

[0234] Next, in step S30, the sequencer 24 compares the sensing action order during the verification action with the sensing action order during the reading action, generates a comparison result, and uses the comparison result to determine the relationship between the sensing action order during the verification action and the sensing action order during the reading action.

[0235] For example, sequencer 24 has a storage device that stores... Figure 14 The table showing the correlation between each state and the voltage during the read or check operation. Figure 21 The table showing the relationship between each state and the read action, and Figure 20 The table showing the association between each state and the verification action. The sequencer 24 uses counter circuit 24A ( Figure 1 For each programming loop, Figure 37 The counter circuit shown counts the value (the sequence of sensing actions during the verification operation) for counting. Additionally, the sequencer 24 uses internal signals generated within the sequencer 24 (e.g., Figure 37The state selection signals S9SEL, S8SEL, and S7SEL are shown. Figure 21 The table shown identifies the state at that moment and the order of the verification actions.

[0236] In step S30, the sequencer 24 uses its internal signal to identify the state of the verification action that begins at that moment, compares the sensing action sequence during the reading action with the count value of the counter circuit (the sensing action sequence during the verification action), and generates a comparison result. The count value of the counter circuit 24A (the sensing action sequence during the verification action) is set to 1. For example, as... Figure 37 As shown, from time tv01 in the first operation period to tv4 in the second operation period, the state S9 selection signal S9SEL is supplied to VDD, and the state S8 selection signal S8SEL and the state S7 selection signal S7SEL are supplied to VSS. From time tv01 to time tv4, the sequencer 24 recognizes that the verification operation 9VR of state S9 has started. The sequence of sensing actions during the reading operation of state S9, which has started the verification operation 9VR, is the second. The sequencer 24 compares the sequence of sensing actions during the reading operation of state S9 (the second) with the count value of the counter circuit (the sequence of sensing actions during the verification operation, the first), and generates a comparison result.

[0237] Similar to the process from time tv01 to time tv4, such as Figure 37 As shown, from time tv4 to time tv6, the state S8 selection signal S8SEL is supplied to VDD, and the state S9 selection signal S9SEL and the state S7 selection signal S7SEL are supplied to VSS. During this period, the sequencer 24 detects that the verification action VR8 in state S8 has started. Furthermore, the sequencer 24 uses the counter circuit 24A to increment the counter value (the sequence of sensing actions during the verification action) by 1 (set to 2). The sequence of sensing actions during the reading action of state S8, which has already started verification action 8VR, is the 3rd. The sequencer 24 compares the sequence of sensing actions (3rd) during the reading action with the counter value (the sequence of sensing actions during the verification action, 2nd) to generate a comparison result.

[0238] Similar to the transition from time tv4 to time tv6, such as Figure 37As shown, from time tv6 to time tv8, the state S7 selection signal S7SEL is supplied to VDD, and the state S8 selection signal S8SEL and the state S9 selection signal S9SEL are supplied to VSS. During this period, the sequencer 24 detects that the verification action 7VR in state S7 has begun. Furthermore, the sequencer 24 uses the counter circuit 24A to increment the counter value (the sequence of sensing actions during the verification action) by 1 (set to 3). The sequence of sensing actions during the reading action of state S7, where the verification action 7VR has begun, is the second. The sequencer 24 compares the sequence of sensing actions in the reading action (the second) with the counter value (the sequence of sensing actions during the verification action, the third), generating a comparison result.

[0239] Next, the sequencer 24 uses the comparison result to determine whether the sensing action sequence during the verification action is the same as the sensing action sequence during the reading action, or whether the sensing action sequence during the verification action is earlier than the sensing action sequence during the reading action, or whether the sensing action sequence during the verification action is later than the sensing action sequence during the reading action. Based on the determination result, it proceeds to step S40, step S50, or step S50. Additionally, Figure 14 The table showing the correlation between each state and the voltage during the read or check operation. Figure 21 The table showing the relationship between each state and the read action, and Figure 20 The table showing the various states and their associated verification actions can also be stored in the memory cell array 21. In this case, the semiconductor memory device 1 can, for example, read the information from the memory cell array 21 when the power is turned on and store the information in a register circuit (not shown) in the sequencer 24.

[0240] If the sensing action sequence during the verification action is the same as the sensing action sequence during the reading action (CASE1 in step S30), proceed to step S40. If the sensing action sequence during the verification action is earlier than the sensing action sequence during the reading action (CASE2 in step S30), proceed to step S50. If the sensing action sequence during the verification action is later than the sensing action sequence during the reading action (CASE3 in step S30), proceed to step S60.

[0241] In step S40, for example, the sequencer 24 sets the voltage supplied to the select word line during the verification operation to be the same as the voltage supplied to the select word line during the read operation. In step S50, for example, the sequencer 24 sets the voltage supplied to the select word line during the verification operation to be higher than the voltage supplied to the select word line during the read operation. In step S60, for example, the sequencer 24 sets the voltage supplied to the select word line during the verification operation to be lower than the voltage supplied to the select word line during the read operation.

[0242] Furthermore, in this embodiment, it is assumed that the reference value of the voltage supplied to the select word line for sensing a certain state during the verification operation is the same as the voltage supplied to the select word line for sensing that state during the read operation, but this is not limited to this. For example, the reference value of the voltage supplied to the select word line for sensing a certain state during the verification operation may also be set to be higher than the voltage supplied to the select word line for sensing that state during the read operation. In this case, in step S40, the sequencer 24 sets the voltage supplied to the select word line during the verification operation to be higher than the voltage supplied to the select word line during the read operation. Additionally, in step S50, the sequencer 24 sets the voltage supplied to the select word line during the verification operation to be higher than the voltage set in step S40. Similarly, in step S60, the sequencer 24 sets the voltage supplied to the select word line during the verification operation to be lower than the voltage set in step S40.

[0243] In step S70, which follows step S40, step S50, or step S60, the Yth verification operation is performed by controlling the sense amplifier module 70, line decoder 29, voltage generation circuit 27, and driver group 28, etc., in a manner that the voltage supplied to the select word line is set to be higher than the voltage during the read operation.

[0244] Next, in step S80, for example, the sequencer 24 determines whether all verification operations have been completed for the memory cell transistor MT, which is the level of the verification target, that has not reached the target level. If the determination result is that all verification operations have been completed ("Yes" in step S80), step S90 is executed. If all verification operations have not been completed ("No" in step S80), step S82 is executed.

[0245] In step S82, for example, sequencer 24 increments the value Y by 1 to become Y+1, and then executes step S30. In step S30 following step S82, sequencer 24 compares the sensing action order during the verification action with the sensing action order during the reading action for the (Y+1)th verification action, generates a comparison result, and uses this comparison result to determine whether the sensing action order during the verification action is earlier than the sensing action order during the reading action. Further, after steps S40, S50, or S60, step S70 is executed.

[0246] Next, in step S90 following step S80, for example, the sequencer 24 determines whether all write operations (programming loops) have ended and generates a determination result. If the determination result is that all write operations (programming loops) have ended ("Yes" in step S90), the semiconductor memory device 1 ends the write operation. Alternatively, if the determination result is that not all write operations (programming loops) have ended ("No" in step S90), the semiconductor memory device 1 returns to step S10, starts a different programming loop, and executes the programming operations corresponding to the different programming loops.

[0247] For example, as described in "1-2-2-3. During the second action" and in step S30 above, if the sensing action of the verification action 9VR in state S9 is earlier than the sensing action of the reading action 9R in state S9, in step S30, the sequencer 24 compares the order of the sensing actions of the verification action 9VR in state S9 (first) with the order of the sensing actions of the reading action 9R in state S9 (second) and generates a comparison result. Furthermore, using the comparison result, the sequencer 24 determines that the sensing action of the verification action 9VR in state S9 is earlier than the sensing action of the reading action 9R in state S9, and generates a determination result that includes the statement that the sensing action of the verification action 9VR in state S9 is earlier than the sensing action of the reading action 9R in state S9. Next, in step S50, the sequencer 24 uses the determination result (the sensing action of the verification action 9VR in state S9 is earlier than the sensing action of the reading action 9R in state S9) to set the voltage used in the verification action 9VR to a higher voltage VCG_S9U than the voltage VCG_S9 used in the reading action 9R. Further, in step S70 after step S50, for example... Figure 24 and Figure 37 As shown, the sequencer 24 controls the sense amplifier module 70, line decoder 29, voltage generation circuit 27, and driver group 28 to perform the verification operation by using voltage VCG_S9U to perform the first verification operation 9VR.

[0248] For example, in step S70, the first verification action 9VR is executed. The first verification action 9VR ends when the threshold voltage of the selected memory cell transistor MTo1, connected to the selected odd-number line SEL-WLo1, reaches the target level. Of the three verification actions mentioned above (the mutually different verification actions 9VR, 8VR, and 7VR), the second verification action 8VR and the third verification action 7VR have not ended. Therefore, the sequencer 24 determines that not all verification actions have ended and executes step S82.

[0249] In step S82, sequencer 24 increments the value Y (1 here) by 1 to set it to the value 2, and executes step S30. In step S30 following step S82, sequencer 24 compares the sensing action order during the verification action with the sensing action order during the reading action for the second verification action 8VR, generates a comparison result, and uses the comparison result to determine whether the sensing action order during the verification action is earlier than the sensing action order during the reading action. For example, as described in "1-2-2-4. During the third action" and in step S30 above, if the sensing action of the verification action 8VR in state S8 is earlier than the sensing action of the reading action 8R in state S8, in step S30, sequencer 24 compares the sensing action order (second) of the verification action 8VR in state S8 with the sensing action order (third) of the reading action 8R in state S8 as described above, and generates a comparison result. Based on the comparison result, it is determined whether the sensing action of the verification action 8VR in state S8 is earlier than the sensing action of the reading action 8R in state S8. More specifically, for example, a determination result containing the information that the sensing action of the verification action 8VR in state S8 is earlier than the sensing action of the reading action 8R in state S8 is generated. In this case, in step S50, using the determination result (the sensing action of the verification action 8VR in state S8 is earlier than the sensing action of the reading action 8R in state S8), the voltage used in the verification action 8VR is set to a voltage VCG_S8U that is higher than the voltage VCG_S8 used in the reading action 8R. Further, in step S70 after step S50, as... Figure 24 and Figure 37 As shown, the sequencer 24 uses voltage VCG_S8U to control the sense amplifier module 70, line decoder 29, voltage generation circuit 27 and driver group 28 to perform the second verification action 8VR, thereby performing the verification action.

[0250] For example, in step S70, the second verification action 8VR is executed. The second verification action 8VR ends when the threshold voltage of the selected memory cell transistor MTo1, connected to the odd-number selection line SEL-WLo1, reaches the target level. Of the three verification actions mentioned above (the mutually different verification actions 9VR, 8VR, and 7VR), the third verification action 7VR has not ended. Therefore, the sequencer 24 determines that not all verification actions have ended and executes step S82.

[0251] In step S82, sequencer 24 increments the value Y (2 in this case) by 1 to set it to the value 3, and executes step S30. In step S30 following step S82, sequencer 24 compares the sensing action order during the verification action with the sensing action order during the reading action for the third verification action 7VR, generates a comparison result, and uses this comparison result to determine whether the sensing action order during the verification action is earlier than the sensing action order during the reading action. For example, as explained in "1-2-2-5. During the fourth action" and in step S30 above, if the sensing action of the verification action 7VR in state S7 is later than the sensing action of the reading action 7R in state S7, in step S30, sequencer 24 compares the sensing action order (third) of the verification action 7VR in state S7 with the sensing action order (second) of the reading action 7R in state S7, and generates a comparison result. Based on the comparison result, it is determined whether the sensing action of the verification action 7VR in state S7 is earlier than the sensing action of the reading action 7R in state S7. More specifically, for example, a determination result containing the information that the sensing action of the verification action 7VR in state S7 is later than the sensing action of the reading action 7R in state S7 is generated. In this case, in step S60, using the determination result (the sensing action of the verification action 7VR in state S7 is later than the sensing action of the reading action 7R in state S7), the voltage used in the verification action 7VR is set to a voltage VCG_S7D that is lower than the voltage VCG_S7 used in the reading action 7R. Further, in step S70 after step S50, for example as... Figure 24 and Figure 37 As shown, the sequencer 24 uses voltage VCG_S7D to control the sense amplifier module 70, line decoder 29, voltage generation circuit 27 and driver group 28 to perform the third verification action 7VR, thereby performing the verification action.

[0252] For example, in step S70, the third verification action 7VR is executed. The third verification action 7VR ends when the threshold voltage of the selected memory cell transistor MTo1, connected to the odd-number selection line SEL-WLo1, reaches the target level. Therefore, in step S80 following step S70, the sequencer 24 determines that the above three verification actions (the mutually different verification actions 9VR, 8VR, and 7VR) have ended, and all verification actions are complete.

[0253] In step S90, following step S80, for example, sequencer 24 determines whether all write operations (programming loops) have ended and generates a determination result. If the determination result indicates that all write operations (programming loops) have ended ("Yes" in step S90), semiconductor memory device 1 ends the write operation. Alternatively, if the determination result indicates that not all write operations (programming loops) have ended ("No" in step S90), semiconductor memory device 1 returns to step S10, begins a different programming loop, and executes the programming operations corresponding to the different programming loops.

[0254] <Second Implementation>

[0255] In the semiconductor memory device 1 according to the second embodiment, an example of a verification operation different from that according to the first embodiment will be described. Compared to the example of the verification operation according to the first embodiment, the example of the verification operation in the semiconductor memory device 1 according to the second embodiment differs in that the voltage supplied to the odd-number selection lines SEL-WLo1 and the voltage supplied to the unselected even-number lines WLe0-2 (WLe0, WLe1, WLe2) are different; all other aspects are the same. In the semiconductor memory device 1 according to the second embodiment, the voltage supplied to the odd-number selection lines SEL-WLo1 and the voltage supplied to the unselected even-number lines WLe0-2 (WLe0, WLe1, WLe2) will be mainly described.

[0256] Similarly to the first embodiment, in the following description relating to the second embodiment, the term "second embodiment" is used. Figures 31-34 This section describes an example of performing a sensing operation in the first page after executing the three verification operations described above (mutually different verification operations 9VR, 8VR, and 7VR). Additionally, in one example of the verification operation in the semiconductor memory device 1 according to the second embodiment, similar to the first embodiment, an example of performing the verification operation in the memory column MPO is mainly described. In the description of the semiconductor memory device 1 according to the second embodiment, details related to... Figures 1 to 30 , Figures 35-37 Description of identical or similar structures.

[0257] Furthermore, similar to the first embodiment, in the following description of the second embodiment, in NAND strings 50o and 50e, the word line WL connected to the memory cell transistor MT selected as the object of the verification operation is called the select word line SEL-WL, the word line connected to other memory cell transistors MT is called the unselected word line USEL-WL, the select gate line electrically connected to the select word line SEL-WL is called the select select gate line SEL-SGD or SEL-SGS, and other select gate lines are called the unselected select gate lines USEL-SGD or USEL-SGS. Additionally, sometimes the various signal lines included in NAND string 50o are labeled "odd number," and the various signal lines included in NAND string 50e are labeled "even number." For example, the select select gate line included in NAND string 50o is called the select odd number select gate line SEL-SGDo or SEL-SGSo, and the select word line is called the select odd number line SEL-WLo0 to 7 (e.g., SEL-WLo1). Similar to NAND string 50o, the unselected select gate lines included in NAND string 50e are called unselected odd select gate lines USEL-SGDe or USEL-SGSe, and the unselected word lines are called unselected even number lines USEL-WLe1 to 7 (e.g., USEL-WLe1).

[0258] use Figure 31 This describes a timing diagram of various signals during the verification operation in the semiconductor memory device 1 according to the second embodiment. Figure 31 The timing diagrams shown are for selecting odd-number lines SEL-WLo1, selecting gate lines SEL-SGD and SGS (select gate lines SGD1 and SGSo), not selecting gate lines USEL-SGS (select gate line SGSe), not selecting gate lines USEL-SGD (select gate line SGD0), not selecting even-number lines WLe0~2, unselected word lines USEL-WL, control signal STB, and source line SL. Figure 24 or Figure 25 The verification operation involved in the first embodiment described herein is the same as that described in one example, so it will be described here as needed.

[0259] The verification actions before time tv0 and during the first action are the same as those described in "1-2-2-1. Example of verification actions before time tv0" and "1-2-2-2. Example of verification actions during the first action (from time tv0 to time tv1)," so the description is omitted here.

[0260] <2-1. Example of a verification action during the fifth action period (from time tv1 to time tv4)>

[0261] use Figure 31 as well as Figure 32 An example of the verification action being performed during the fifth action is provided. Figure 32 It is used for explanation Figure 31 An example of a circuit diagram showing the various signals and current paths during the fifth operation.

[0262] like Figure 31 As shown, similar to the second operation period, the fifth operation period is the period during which the sensing operation of the verification operation 9VR is performed. During the fifth operation period, the voltage supplied to the unselected even-number lines USEL-WL (excluding unselected even-number lines USEL-WLe0~2) changes from voltage VREAD to voltage VREAD_A. Voltage VREAD_A is higher than that in the comparison example ( Figure 25 The voltage VREAD supplied to the unselected even-numbered lines USEL-WL (excluding USEL-WLLe0 to 2) in the semiconductor memory device involved is high. At times tv3 to tv4, the control signal STB is activated (the control signal STB changes from the "L" level to the "H" level), and the semiconductor memory device 1 according to the second embodiment can determine the threshold voltage corresponding to state S9.

[0263] like Figure 32 As shown, during the fifth operation, selection transistors STo1 and STo2, memory cell transistor MTo0, memory cell transistors MTo2-7 (MTo2, MTo3, MTo4, MTo5, MTo6, MTo7), memory cell transistors MTe3-7 (MTe3, MTe4, MTe5, MTe6, MTe7), and selection transistor STe2 are in the on state, while memory cell transistors MTe0-2 are in the off state. Therefore, the current is... Figure 32 The path, indicated by the thick arrow, flows from bit line BL1 to the selected memory cell transistor MTo0. Furthermore, based on the result of determining the threshold voltage corresponding to state S9, the current... Figure 32 The flow passes through the path indicated by the thick arrow. As a result, the semiconductor memory device 1 according to the second embodiment is able to determine the threshold voltage corresponding to state S9.

[0264] Similar to the second operation, the sensing actions of the verification operation 9VR in state S9 occur earlier than the sensing actions of the read operation 9R in state S9. In the semiconductor memory device 1 according to the second embodiment, when the order of sensing actions in the verification operation differs from the order of sensing actions in the read operation, and the order of sensing actions in the verification operation occurs earlier than the order of sensing actions in the read operation, the voltage supplied to the unselected word line during the verification operation is set higher than the voltage supplied to the unselected word line during the read operation. As a result, in the semiconductor memory device 1 according to the second embodiment, by controlling the voltage supplied to the unselected word line, the change in the threshold voltage of the selected memory cell transistor can be minimized, thereby suppressing erroneous reads.

[0265] <2-2. Example of a verification action during the sixth action period (from time tv4 to time tv6)>

[0266] use Figure 31 as well as Figure 32 An example of the verification action being performed during the sixth action is provided.

[0267] like Figure 31 As shown, the sixth operation period is the period during which the sensing operation of the verification operation 8VR is performed. During the sixth operation period, similar to the fifth operation period, the voltage supplied to the unselected even-number lines USEL-WL (excluding USEL-WLe0 to 2) changes from voltage VREAD to voltage VREAD_A. At times tv4 to tv6, the control signal STB is activated (changing the control signal STB from "L" level to "H" level), and the semiconductor memory device 1 according to the second embodiment can determine the threshold voltage corresponding to state S8.

[0268] During the sixth action, also with Figure 32 Similarly, during the fifth operation shown, voltage is supplied to each signal to control each transistor, and the current flows... Figure 32 The current flows from bit line BL1 to the selected memory cell transistor MTo0 along the path indicated by the thick arrow. Additionally, based on the threshold voltage corresponding to state S8, the current... Figure 32 The flow passes through the path indicated by the thick arrow. As a result, the semiconductor memory device 1 according to the second embodiment is able to determine the threshold voltage corresponding to state S8.

[0269] In the verification action at this time, the verification action 8VR sensing action in state S8 is executed second in the programming loop. Figure 20 On the other hand, in the read operation, the sensing action of read action 8R in state S8 is the third read action of the middle page ( Figure 21Therefore, in the verification operation 8VR of state S8, similarly to the verification operation 9VR of state S9, the voltage supplied to the select word line during the verification operation is set to be higher than the voltage supplied to the select word line during the read operation. As a result, for the read operation 8R of state S8, in the semiconductor memory device 1 according to the second embodiment, the change in the threshold voltage of the selected memory cell transistor can be minimized, thereby suppressing erroneous reads. In addition, the semiconductor memory device 1 according to the second embodiment can determine the threshold voltage corresponding to state S8.

[0270] <2-3. Examples of verification actions during the seventh action period (from time tv6 to time tv8)>

[0271] use Figure 31 as well as Figure 33 An example of the verification action being performed during the seventh action is provided. Figure 33 It is used for explanation Figure 31 An example of a circuit diagram showing the various signals and current paths during the seventh operation.

[0272] like Figure 31 As shown, similar to the fourth operation period, the seventh operation period is the period during which the sensing operation of the verification operation 7VR is performed. During the seventh operation period, the voltage supplied to the unselected even-number lines USEL-WL (excluding USEL-WLe0~2) changes from voltage VREAD to voltage VREAD_B. Voltage VREAD_B is higher than that in the comparison example ( Figure 25 In the semiconductor memory device involved, the voltage VREAD supplied to the unselected even digital lines USEL-WL (excluding unselected even digital lines USEL-WLe0 to 2) is low. At times tv6 to tv8, the control signal STB is activated (the control signal STB changes from the "L" level to the "H" level), and the semiconductor memory device 1 according to the second embodiment can determine the threshold voltage corresponding to state S7.

[0273] like Figure 33 As shown, during the seventh operation, the gate electrodes of select transistors STo1 and STo2, memory cell transistors MTo0, memory cell transistors MTo2-7 (MTo2, MTo3, MTo4, MTo5, MTo6, MTo7), memory cell transistors MTe3-7 (MTe3, MTe4, MTe5, MTe6, MTe7), and select transistor STe2 are supplied with voltage VREAD_B, putting them in the on state. The gate electrodes of memory cell transistors MTe0-2 are supplied with voltage VSS, putting them in the off state. Therefore, the current... Figure 33The path, indicated by the thick arrow, flows from bit line BL1 to the selected memory cell transistor MTo0. Furthermore, based on the threshold voltage corresponding to state S7, the current... Figure 33 The flow passes through the path indicated by the thick arrow. As a result, the semiconductor memory device 1 according to the second embodiment is able to determine the threshold voltage corresponding to state S7.

[0274] Similar to the second operation, the sensing actions of the verification operation 7VR in state S7 are performed later than the sensing actions of the read operation 7R in state S7. In the semiconductor memory device 1 according to the second embodiment, when the order of sensing actions in the verification operation is different from the order of sensing actions in the read operation, and the order of sensing actions in the verification operation is later than the order of sensing actions in the read operation, the voltage supplied to the unselected word line during the verification operation is set lower than the voltage supplied to the unselected word line during the read operation. As a result, in the semiconductor memory device 1 according to the second embodiment, by controlling the voltage supplied to the unselected word line, the change in the threshold voltage of the selected memory cell transistor can be minimized, thereby suppressing erroneous reads.

[0275] <2-4. An example of the write operation process>

[0276] use Figure 34 and Figure 38 This is an example illustrating the flow of the write operation involved in the second embodiment. Figure 34 This is a flowchart illustrating the verification operation in the semiconductor memory device 1 according to the second embodiment. The write operation flow according to the second embodiment differs from that according to the first embodiment in steps S42, S52, and S62; all other points are the same. In the example of the write operation flow according to the second embodiment, the differences from those of the write operation flow according to the first embodiment will be mainly explained. Furthermore, Figure 38 The selection of odd-number lines SEL-WLo1 and the unselection of even-number lines USEL-WL (excluding even-number lines USEL-WLe0~2) are shown in the diagram. Figure 31 The instructions for selecting odd-number lines SEL-WLo1 and not selecting even-number lines USEL-WL (excluding USEL-WLe0 to 2 for not selecting even-number lines) are the same and are omitted here. Figure 38 The explanation shown is for selecting the odd-numbered line SEL-WLo1. Additionally, regarding... Figure 38The diagram shows the selection of odd-number lines SEL-WLo1 and the non-selection of even-number lines USEL-WL (excluding USEL-WLe0~2), the explanation of the state S9 selection signal S9SEL, state S8 selection signal S8SEL, state S7 selection signal S7SEL, the sensing action sequence during the read operation, and the counter value of the counter circuit (sensing action sequence during the verification operation), and is related to the use of... Figure 37 The description is the same if the second, third, and fourth action periods are replaced with the fifth, sixth, and seventh action periods, so detailed explanations are omitted here.

[0277] Similar to the first embodiment, in step S30, the sequencer 24 uses the internal signal to identify the state of the verification action that started at that moment. Then, the sequencer 24 uses the internal signal to compare the sensing action sequence during the reading action of the state of the started verification action with the count value of the counter circuit (sensing action sequence during the verification action) to generate a comparison result.

[0278] In addition, the sequencer 24 uses the comparison results to determine the relationship between the sensing action order during the verification action and the sensing action order during the reading action.

[0279] If the sensing action sequence during the verification action is the same as the sensing action sequence during the reading action (CASE1 in step S30), proceed to step S42. If the sensing action sequence during the verification action is earlier than the sensing action sequence during the reading action (CASE2 in step S30), proceed to step S52. If the sensing action sequence during the verification action is later than the sensing action sequence during the reading action (CASE3 in step S30), proceed to step S62.

[0280] In step S52, for example, the sequencer 24 sets the voltage supplied to the unselected word line during the verification operation to be higher than the voltage supplied to the unselected word line during the read operation. Furthermore, in step S52, the sense amplifier module 70, the line decoder 29, the voltage generation circuit 27, and the driver group 28 are controlled to perform the verification operation using a voltage set higher than the voltage supplied to the unselected word line during the read operation.

[0281] For example, as explained in "2-1. During the fifth operation" and in step S30 of "1-2-2-6. An example of the write operation process", if the sensing action of the verification action 9VR in state S9 is earlier than the sensing action of the read action 9R in state S9, in step S30, the sequencer 24 compares the order of the sensing actions of the verification action 9VR in state S9 (first) with the order of the sensing actions of the read action 9R in state S9 (second) and generates a comparison result. If, based on this comparison result, it is determined that the sensing action of the verification action 9VR in state S9 is earlier than the sensing action of the read action 9R in state S9, a determination result containing the content that the sensing action of the verification action 9VR in state S9 is earlier than the sensing action of the read action 9R in state S9 is generated. Additionally, in step S52, the sequencer 24 uses the determination result (the sensing action of the verification action 9VR in state S9 is earlier than the sensing action of the reading action 9R in state S9) to set the voltage supplied to the unselected word line during the reading action to a voltage VREAD_A that is higher than the voltage VREAD. Further, in step S70 after step S52, for example... Figure 31 and Figure 38 As shown, the sequencer 24 controls the sense amplifier module 70, line decoder 29, voltage generation circuit 27, and driver group 28 to perform the verification operation 9VR by using voltage VREAD_A.

[0282] In step S82, sequencer 24 increments the value Y (1 in this case) by 1 to set it to the value 2, and executes step S30. In step S30 following step S82, sequencer 24 compares the sensing action order during the verification action with the sensing action order during the read action for the second verification action 8VR, and generates a comparison result. For example, as explained in step S30 of "2-2. During the sixth action" and "1-2-2-6. An example of the write action process", if the sensing action of the verification action 8VR in state S8 is earlier than the sensing action of the read action 8R in state S8, in step S30, sequencer 24 compares the sensing action order of the verification action 8VR in state S8 (second) with the sensing action order of the read action 8R in state S8 (third), and generates a comparison result. If, based on the comparison result, it is determined that the sensing action of the verification action 8VR in state S8 is earlier than the sensing action of the reading action 8R in state S8, a determination result containing the information that the sensing action of the verification action 8VR in state S8 is earlier than the sensing action of the reading action 8R in state S8 is generated. Next, in step S52, the sequencer 24 uses this determination result (the sensing action of the verification action 8VR in state S8 is earlier than the sensing action of the reading action 8R in state S8) to set the voltage supplied to the unselected word line during the reading action to a voltage VREAD_A that is higher than the voltage VREAD. Further, in step S70 after step S52, as... Figure 31 and Figure 38 As shown, the sequencer 24 uses voltage VCG_S8U to control the sense amplifier module 70, line decoder 29, voltage generation circuit 27 and driver group 28 to perform the second verification action 8VR, thereby performing the verification action.

[0283] For example, as explained in step S30 of "2-3. During the seventh operation" and "1-2-2-6. An example of the write operation process", if the sensing operation of the verification operation 7VR in state S7 is later than the sensing operation of the read operation 7R in state S7, in step S30, the sequencer 24 compares the order of the sensing operations of the verification operation 7VR in state S7 (third) with the order of the sensing operations of the read operation 7R in state S7 (second) and generates a comparison result. If, based on this comparison result, it is determined that the sensing operation of the verification operation 7VR in state S7 is later than the sensing operation of the read operation 7R in state S7, a determination result containing the content that the sensing operation of the verification operation 7VR in state S7 is later than the sensing operation of the read operation 7R in state S7 is generated. Additionally, in step S62, sequencer 24 uses the determination result (the sensing action of the verification action 7VR in state S7 is later than the sensing action of the reading action 7R in state S7) to set the voltage supplied to the unselected word line during the reading action to a voltage VREAD_B that is lower than the voltage VREAD. Further, in step S70 following step S62, for example... Figure 31 and Figure 38 As shown, the sequencer 24 uses voltage VREAD_B to control the sense amplifier module 70, line decoder 29, voltage generation circuit 27, and driver group 28 to perform the verification operation by executing the third verification operation 7VR.

[0284] In addition, although Figure 38 Not illustrated, in step S42, for example, the sequencer 24 sets the voltage supplied to the unselected word line during the verification operation to be the same as the voltage supplied to the unselected word line during the read operation. In this case, in step S42, the verification operation is performed by controlling the sense amplifier module 70, the line decoder 29, the voltage generation circuit 27, and the driver group 28, etc., in a manner that the verification operation is performed using a voltage set to be the same as the voltage supplied to the unselected word line during the read operation.

[0285] Furthermore, in this embodiment, it is assumed that the reference value of the voltage supplied to the unselected word line during the verification operation is the same as the voltage supplied to the unselected word line during the read operation, but this is not a limitation. For example, the reference value of the voltage supplied to the unselected word line during the verification operation may also be set to be lower than the voltage supplied to the unselected word line during the read operation. In this case, in step S42, the sequencer 24 sets the voltage supplied to the unselected word line during the verification operation to be lower than the voltage supplied to the unselected word line during the read operation. Additionally, in step S62, the sequencer 24 sets the voltage supplied to the unselected word line during the verification operation to be lower than the voltage set in step S42. Similarly, in step S52, the sequencer 24 sets the voltage supplied to the unselected word line during the verification operation to be higher than the voltage set in step S42.

[0286] In the verification operation of the semiconductor memory device 1 according to the second embodiment, the change of the threshold voltage of the selected memory cell transistor can be minimized by controlling the voltage supplied to the unselected word line during the read operation, thereby suppressing erroneous reads.

[0287] In the first and second embodiments, "connection" means electrical connection and does not exclude the possibility of another element being interposed therebetween.

[0288] The foregoing has described several embodiments of the non-volatile semiconductor memory device of this disclosure. However, these embodiments are presented as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and can be appropriately combined, omitted, substituted, or modified without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, and are included within the scope equivalent to the invention described in the claims.

[0289] Symbol Explanation

[0290] 1: Semiconductor memory device; 2: Memory controller; 3: Memory system; 8: Wiring layer; 10: Wiring layer; 10-0: Wiring layer; 10-0a: Wiring layer; 10-0b: Wiring layer; 10-0c: Wiring layer; 10-0d: First connecting section; 10-1: Wiring layer; 10-1a: Wiring layer; 10-1b: Wiring layer; 10-1d: Second connecting section. 10-2: Wiring layer, 10-2a: Wiring layer, 10-2b: Wiring layer, 10-2d: First connecting section, 10-3: Wiring layer, 10-3a: Wiring layer, 10-3b: Wiring layer, 10-3d: Second connecting section, 10-4: Wiring layer, 10-5: Wiring layer, 10-6: Wiring layer, 10-7: Wiring layer, 11: Wiring layer, 11-0: Wiring layer, 11-0a: Wiring layer, 11-0b: Wiring layer, 11-1: Wiring layer, 11-2: Wiring layer, 11-3: Wiring layer, 11-4: Wiring layer, 11-5: Wiring layer, 11-6: Wiring layer, 11-7: Wiring layer, 11-8: First connecting section, 11-9: Second connecting section 11e: Wiring layer, 11o: Wiring layer, 12: Wiring layer, 13: Semiconductor substrate, 16: Contact plug, 17: Contact plug, 17d: First connecting section, 18: Metal wiring layer, 19: Contact plug, 19d: Second connecting section, 20: Metal wiring layer, 21: Memory cell array, 22: Input / output circuit, 23: Logic control circuit, 24: Sequencer, 24A: Counter circuit, 25: Register, 26: Ready / busy circuit, 27: Voltage generation circuit, 28: Driver set, 28A: Even word line driver, 28B: Odd word line driver, 29: Row decoder decoder), 30: insulating layer, 31: semiconductor layer, 32: insulating layer, 33: insulating layer, 34: insulating layer, 35: AlO layer, 36: barrier metal layer, 37: insulating layer, 40: semiconductor layer, 41: insulating layer, 42: conductive layer, 43: insulating layer45: AlO layer, 46: Insulating layer, 46a: Insulating layer, 46b: Insulating layer, 46c: Insulating layer, 47: Barrier metal layer, 48: Insulating layer, 50: Serial, 50e: Serial, 50o: Serial, 70: Sense amplifier module, 71: Input / output pad group, 72: Logic control pad group, 120: Transistor, 121: Transistor, 122: Transistor, 123: Transistor, 124: Transistor, 125: Transistor, 126: Transistor, 127: Transistor, 128: Transistor, 129: Capacitor, 130: Inverter, 131: Inverter, 132: Transistor, 133: Transistor.

Claims

1. A semiconductor memory device, comprising: A first semiconductor pillar having i first memory cells and i second memory cells, the first semiconductor pillar extending in a second direction intersecting a first direction and electrically connected to a first line, the i first memory cells being connected in series, each of the i first memory cells being able to set more than m threshold voltages, the i second memory cells being connected in series, each of the i second memory cells being able to set more than m threshold voltages; i first word lines, which are stacked in the second direction and electrically connected to i first memory cells one-to-one, wherein... i is an integer greater than or equal to 4; i second word lines, which are stacked in the second direction and electrically connected to i second memory cells in a one-to-one correspondence, wherein i is an integer greater than or equal to 4; A driver capable of supplying voltage to each of the i first word lines and the i second word lines; and A logic control circuit controls write operations to the i first storage cells and the i second storage cells, and read operations to the i first storage cells and the i second storage cells. The write operation consists of multiple loops. Each loop contains programming actions and validation actions. When the write operation is performed on the k-th first storage cell... If the order in which the sensing actions for determining whether the j-th threshold voltage has been reached are performed in the verification operation differs from the order in which the sensing actions for determining whether the j-th threshold voltage has been reached are performed in the read operation from the k-th first memory cell, then the voltage applied to the k-th first word line in the verification operation is different from the voltage applied to the k-th first word line in the read operation from the k-th first memory cell, so that the determination of whether the j-th threshold voltage has been reached is made in the verification operation. Where m is an integer greater than or equal to 4, k is an integer less than i and greater than 1, and j is an integer greater than or equal to 1 and less than m.

2. The semiconductor memory device according to claim 1, wherein, If the order in which the sensing action to determine whether the j-th threshold voltage has been reached is performed during the verification operation is earlier than the order in which the sensing action to determine whether the j-th threshold voltage has been reached is performed during the read operation from the k-th first memory cell, The voltage applied to the k-th first word line during the verification operation is higher than the voltage applied to the k-th first word line during the read operation.

3. The semiconductor memory device according to claim 1, wherein, If the order in which the sensing action for determining whether the j-th threshold voltage has been reached is performed during the verification operation is later than the order in which the sensing action for determining whether the j-th threshold voltage has been reached is performed during the read operation from the k-th first memory cell, The voltage applied to the k-th first word line during the verification operation is lower than the voltage applied to the k-th first word line during the read operation.

4. The semiconductor memory device according to claim 2 or claim 3, wherein, The voltage applied to the kth second word line connected to the kth second memory cell is a negative voltage.

5. The semiconductor memory device according to claim 4, wherein, The voltage applied to the (k+1)th second word line connected to the (k+1)th second memory cell and the voltage applied to the (k-1)th second word line connected to the (k-1)th second memory cell are negative voltages.

6. The semiconductor memory device according to claim 5, wherein, m threshold voltages are 16 threshold voltages.

7. The semiconductor memory device according to claim 6, wherein, The kth first storage unit is opposite to the kth second storage unit. The (k+1)th first storage unit is opposite to the (k+1)th second storage unit. The (k-1)th first storage unit is opposite to the (k-1)th second storage unit.

8. A semiconductor memory device, comprising: A first semiconductor pillar having i first memory cells and i second memory cells, the first semiconductor pillar extending in a second direction intersecting a first direction and electrically connected to a first line, the i first memory cells being connected in series, each of the i first memory cells being able to set more than m threshold voltages, the i second memory cells being connected in series, each of the i second memory cells being able to set more than m threshold voltages; i first word lines, which are stacked in the second direction and electrically connected to i first memory cells one-to-one, wherein... i is an integer greater than or equal to 4; i second word lines, which are stacked in the second direction and electrically connected to i second memory cells in a one-to-one correspondence, wherein i is an integer greater than or equal to 4; A driver capable of supplying voltage to each of the i first word lines and the i second word lines; and A logic control circuit controls write operations to the i first storage cells and the i second storage cells, and read operations to the i first storage cells and the i second storage cells. The write operation consists of multiple loops. Each loop contains programming actions and validation actions. When the write operation is performed on the k-th first storage cell... If the order in which the sensing actions for determining whether the j-th threshold voltage has been reached are performed in the verification operation differs from the order in which the sensing actions for determining whether the j-th threshold voltage has been reached are performed in the read operation from the k-th first memory cell, then the voltage applied to the first word line other than the k-th word line in the verification operation is different from the voltage applied to the first word line other than the k-th word line in the read operation from the k-th first memory cell, so as to determine whether the j-th threshold voltage has been reached in the verification operation. Where m is an integer greater than or equal to 4, k is an integer less than i and greater than 1, and j is an integer greater than or equal to 1 and less than m.

9. The semiconductor memory device according to claim 8, wherein, If the order in which the sensing action to determine whether the j-th threshold voltage has been reached is performed during the verification operation is earlier than the order in which the sensing action to determine whether the j-th threshold voltage has been reached is performed during the read operation from the k-th first memory cell, The voltage applied to the first word line other than the kth word line during the verification operation is higher than the voltage applied to the first word line other than the kth word line during the read operation.

10. The semiconductor memory device according to claim 9, wherein, If the order in which the sensing action for determining whether the j-th threshold voltage has been reached is performed during the verification operation is later than the order in which the sensing action for determining whether the j-th threshold voltage has been reached is performed during the read operation from the k-th first memory cell, The voltage applied to the first word line other than the kth word line during the verification operation is lower than the voltage applied to the first word line other than the kth word line during the read operation.

11. The semiconductor memory device according to claim 9 or claim 10, wherein, The voltage applied to the kth second word line connected to the kth second memory cell is a negative voltage.

12. The semiconductor memory device according to claim 11, wherein, The voltage applied to the (k+1)th second word line connected to the (k+1)th second memory cell and the voltage applied to the (k-1)th second word line connected to the (k-1)th second memory cell are negative voltages.

13. The semiconductor memory device according to claim 12, wherein, m threshold voltages are 16 threshold voltages.

14. The semiconductor memory device according to claim 13, wherein, The kth first storage unit is opposite to the kth second storage unit. The (k+1)th first storage unit is opposite to the (k+1)th second storage unit. The (k-1)th first storage unit is opposite to the (k-1)th second storage unit.

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