A laminated chip common mode inductor with magnetic shielding structure

Abstract

The application provides a laminated chip common mode inductor with a magnetic shielding structure, comprising a magnetic shielding layer, a hollow slot part being formed in the inside of the magnetic shielding layer; a connecting layer being arranged in the hollow slot part, an annular slot part being formed between the outer wall of the connecting layer and the inner wall of the hollow slot part, the top surface and the bottom surface of the connecting layer being connected with the magnetic shielding layer respectively; a dielectric layer being filled in the annular slot part; two inductors being arranged oppositely and spaced apart, each inductor being arranged in the dielectric layer and being wound around the connecting layer, the two ends of each inductor extending out of the dielectric layer and extending into the magnetic shielding layer. The application arranges two inductors oppositely and spaced apart in the dielectric layer, winds each inductor around the connecting layer, and forms a magnetic shielding layer outside the dielectric layer, the magnetic shielding layer can surround the dielectric layer, the two inductors and the connecting layer inside the magnetic shielding layer, thereby effectively improving the ability of suppressing radiation interference of the inductor and improving the wide adaptability of the laminated chip common mode inductor.

Description

Technical Field

[0001] This application belongs to the field of electronic components technology, and more specifically, relates to a multilayer chip common-mode inductor with a magnetic shielding structure. Background Technology

[0002] Inductors, as an important component of magnetic elements, are widely used in power electronic circuits, especially in power supply circuits where they are indispensable. In power supply circuits, rapid changes in current or voltage within rectifier diodes, filter capacitors, and inductors generate electromagnetic interference sources. Simultaneously, the input power supply also contains high-order harmonic noise beyond the mains frequency. If these interferences are not controlled, they will damage the load equipment.

[0003] Currently, although multilayer chip common-mode inductors manufactured using LTCC (low temperature co-fired ceramics) technology have functions such as common-mode signal suppression and interference suppression of differential-mode signals, their ability to suppress radiated interference still cannot meet the requirements, and their adaptability is poor. Summary of the Invention

[0004] The purpose of this application is to provide a multilayer chip common-mode inductor with a magnetic shielding structure to solve the problems existing in related technologies: the current multilayer chip common-mode inductors have insufficient ability to suppress radiated interference and poor adaptability.

[0005] To achieve the above objectives, the technical solution adopted in the embodiments of this application is as follows:

[0006] A multilayer chip common-mode inductor with a magnetically shielded structure is provided, comprising:

[0007] A magnetic shielding layer, wherein a hollow groove is formed inside the magnetic shielding layer;

[0008] A connecting layer is disposed in the hollow groove, and an annular groove is formed between the outer wall of the connecting layer and the inner wall of the hollow groove. The top and bottom surfaces of the connecting layer are respectively connected to the magnetic shielding layer.

[0009] A dielectric layer is filled in the annular groove.

[0010] Two inductors are arranged at a relative distance from each other. Each inductor is disposed in the dielectric layer and wound around the connection layer. The two ends of each inductor extend out of the dielectric layer and into the magnetic shielding layer, respectively.

[0011] In this structure, the present application places two relatively spaced inductors in the dielectric layer, and winds each inductor around the connecting layer. A magnetic shielding layer is formed on the outside of the dielectric layer. This magnetic shielding layer can surround the dielectric layer, the two inductors and the connecting layer located inside it, thereby effectively improving the ability to suppress radiation interference of the inductors and improving the wide adaptability of the multilayer chip common mode inductor.

[0012] In one embodiment, the magnetic shielding layer and the connecting layer are magnetic conductors made of ferrite material.

[0013] This structure allows for a significant reduction in the size of the magnetic core, meeting the needs of component manufacturing towards miniaturization and lightweight design.

[0014] In one embodiment, each of the inductors is a spiral inductor.

[0015] This structure, compared to discrete wire-wound inductors, offers advantages such as lower cost, easier integration, lower power consumption, and lower noise. By increasing the coil thickness, the ohmic loss of the inductor can be reduced, making it suitable for optimized design of low-frequency inductors.

[0016] In one embodiment, each inductor includes two parallel and spaced-apart wound electrodes and an electrode layer connecting the two wound electrodes; the dielectric layer is respectively formed with a first hole for accommodating each wound electrode and a second hole for accommodating each electrode layer, and each first hole is connected to the corresponding second hole; the magnetic shielding layer is respectively provided with openings for each wound electrode to extend into.

[0017] This structure allows for screen printing of the portion of each wound electrode located in the dielectric layer via the first hole, screen printing of each electrode layer via the second hole, and screen printing of the portion of each wound electrode extending into the magnetic shielding layer via the opening.

[0018] In one embodiment, each of the wound electrodes includes a helical electrode and a connecting electrode connected to the outer end of the helical electrode, and the inner ends of two adjacent helical electrodes are connected through the corresponding electrode layers.

[0019] In this structure, the second hole is a vertical through hole, and the connection of two spiral electrodes can be achieved through the electrode layer formed by screen printing in the second hole.

[0020] In one embodiment, each of the spiral electrodes includes a first electrode, a second electrode perpendicular to one end of the first electrode, a third electrode perpendicular to the end of the second electrode away from the first electrode and parallel to the first electrode, a fourth electrode perpendicular to the end of the third electrode away from the second electrode and parallel to the second electrode, a fifth electrode perpendicular to the end of the fourth electrode away from the third electrode and parallel to the third electrode, and a sixth electrode perpendicular to the end of the fifth electrode away from the fourth electrode and parallel to the fourth electrode, wherein the end of the sixth electrode away from the fifth electrode is provided with a corresponding connecting electrode.

[0021] This structure, by setting each spiral electrode as a first electrode, second electrode, third electrode, fourth electrode, fifth electrode, and sixth electrode, can achieve a spiral configuration and be wound to the target number of turns.

[0022] In one embodiment, the width of each of the connecting electrodes is greater than the width of the corresponding spiral electrode.

[0023] This structure, by increasing the width of each connecting electrode, facilitates the connection of each connecting electrode to external devices.

[0024] In one embodiment, each of the inductors is a conductor made of silver.

[0025] This structure provides advantages for silver electrodes, including stable potential, robust electrode structure, low temperature hysteresis, and suitability for use at high temperatures.

[0026] In one embodiment, a clearance hole is formed in the middle of the dielectric layer, and the clearance hole is filled with the printed connecting layer.

[0027] In this structure, each inductor is wound around the connecting layer, meaning the connecting layer is located inside the inductor. The magnetic shielding layer covers each inductor, effectively encasing them from both inside and outside, thus further improving the suppression of radiation interference.

[0028] In one embodiment, the dielectric layer is an insulator made of a low dielectric constant ceramic material.

[0029] In this structure, the low dielectric constant ceramic material can reduce the interactive coupling loss between the substrate and the metal electrode, and shorten the signal propagation delay time. Attached Figure Description

[0030] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or exemplary technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0031] Figure 1 This is a three-dimensional structural diagram of a multilayer chip common-mode inductor provided in an embodiment of this application;

[0032] Figure 2 for Figure 1 A schematic diagram of the decomposition process;

[0033] Figure 3 for Figure 2 Perspective view;

[0034] Figure 4 A three-dimensional structural diagram of the inductor provided in an embodiment of this application;

[0035] Figure 5 This is a three-dimensional structural diagram of the wound electrode provided in an embodiment of this application.

[0036] The main markings in the attached figures are as follows:

[0037] 1. Magnetic shielding layer; 11. Hollow slot; 12. Opening;

[0038] 2. Connecting layer; 21. Annular groove;

[0039] 3. Medium layer; 31. First hole position; 32. Second hole position; 33. Clearance hole;

[0040] 4. Inductor; 41. Winded electrode; 411. Spiral electrode; 4111. First electrode; 4112. Second electrode; 4113. Third electrode; 4114. Fourth electrode; 4115. Fifth electrode; 4116. Sixth electrode; 412. Connecting electrode; 42. Electrode layer. Detailed Implementation

[0041] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.

[0042] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0043] Furthermore, the terms "first," "second," "third," "fourth," "fifth," and "sixth" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first," "second," "third," "fourth," "fifth," or "sixth" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more unless otherwise expressly specified. "Several" means one or more unless otherwise expressly specified.

[0044] In the description of this application, it should be understood that the terms "center", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0045] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0046] Throughout this specification, references to "an embodiment" or "an embodiment" mean that a particular feature, structure, or characteristic described in connection with an embodiment is included in at least one embodiment of this application. Therefore, the phrases "in one embodiment" or "in some embodiments" appear in various places throughout the specification, and not all refer to the same embodiment. Furthermore, in one or more embodiments, particular features, structures, or characteristics may be combined in any suitable manner.

[0047] Please see Figures 1 to 3The multilayer chip common-mode inductor with a magnetic shielding structure provided in this application embodiment will now be described. This multilayer chip common-mode inductor with a magnetic shielding structure includes a magnetic shielding layer 1, a connecting layer 2, a dielectric layer 3, and two inductors 4. The magnetic shielding layer 1 may be cuboid in shape, and a hollow slot 11 is formed inside the magnetic shielding layer 1. The hollow slot 11 may also be cuboid in shape. A connecting layer 2 is provided in the hollow slot 11, and an annular slot 21 is formed between the outer wall of the connecting layer 2 and the inner wall of the hollow slot 11. The connecting layer 2 may be cuboid in shape, having a top surface, a bottom surface parallel to the top surface, and four side surfaces connecting the top and bottom surfaces. The "outer wall of the connecting layer 2" can be understood as the four side surfaces. The top and bottom surfaces of the connecting layer 2 are connected to the magnetic shielding layer 1, specifically, the top surface of the connecting layer 2 is connected to the top surface of the hollow slot 11, and the bottom surface of the connecting layer 2 is connected to the bottom surface of the hollow slot 11. The dielectric layer 3 fills the annular groove 21, thereby enabling the dielectric layer 3 to wrap around the connecting layer 2 and the magnetic shielding layer 1 to wrap around the dielectric layer 3. Two inductors 4 are arranged relatively spaced apart, or the two inductors 4 can be arranged parallel to each other. Each inductor 4 is disposed in the dielectric layer 3 and is wound around the connecting layer 2, that is, the connecting layer 2 is the main body of the winding, and the middle part of each inductor 4 is wound to form a hole for the connecting layer 2 to pass through. The two ends of each inductor 4 extend out of the dielectric layer 3 and into the magnetic shielding layer 1, and the protruding ends of each inductor 4 can be flush with the outer wall of the magnetic shielding layer 1.

[0048] In this structure, the present application places two relatively spaced inductors 4 in the dielectric layer 3 and winds each inductor 4 around the connecting layer 2, and forms a magnetic shielding layer 1 on the outside of the dielectric layer 3. The magnetic shielding layer 1 can surround the dielectric layer 3, the two inductors 4 and the connecting layer 2 located inside it, thereby effectively improving the ability to suppress radiation interference of the inductors 4 and improving the wide adaptability of the multilayer chip common mode inductor.

[0049] The multilayer chip common-mode inductor with magnetic shielding structure provided in this application is fabricated using the LTCC process. The fabrication method of this multilayer chip common-mode inductor with magnetic shielding structure includes the following steps:

[0050] 1. Casting: The prepared mixture is cast in a casting machine to obtain a green ceramic tape of a certain thickness for further use. Mixing can be completed in the pulping step. The components and proportions of the mixture can be adjusted according to the performance of the multilayer common mode inductor, and are not limited to a single parameter here.

[0051] 2. Cutting: The rolled green ceramic strip is cut into single-piece strips of the target size to meet the requirements of subsequent processes. The size of the strips can be determined based on the size of the multilayer common-mode inductor to be manufactured.

[0052] In some embodiments, the manufacturer can purchase pre-cut strips directly from the manufacturer, which meet the requirements for producing multilayer chip common mode inductors, thereby eliminating the need for casting and cutting steps.

[0053] 3. Printing: The screen printing process is adopted. The material strip is fixed on the multi-hole worktable by vacuum suction. The holes are opened on each material strip and then filled. The above-mentioned dielectric layer 3, connecting layer 2 and inductor 4 are formed by screen printing on the corresponding positions on each material strip by a screen printing machine.

[0054] 4. Stacking: Multiple printed strips are stacked sequentially. A CCD (Charge-coupled Device) lens can be used to stack the strips, improving alignment accuracy. The magnetic shielding layer 1, connecting layer 2, dielectric layer 3, and inductor 4 on each strip are stacked to form a block or sheet with thickness.

[0055] 5. Equalizing Pressure: Multiple stacked strips are pressed into a pre-finished product, aligning the magnetic shielding layer 1, dielectric layer 3, inductor 4, and connecting layer 2 on each strip. This pre-finished product possesses a complete magnetic shielding layer 1, dielectric layer 3, inductor 4, and connecting layer 2. A press can be used to simultaneously apply pressure from both the top and bottom of the stacked strips to improve the final product quality. Equalizing pressure can be achieved using hot pressing or isostatic pressing to prevent delamination.

[0056] 6. Cutting: The pre-finished products are divided into sections according to the target size using a cutting machine.

[0057] 7. Debinding and Sintering: Place the cut product on the sintering plate in the sintering furnace, set the product sintering temperature profile, and then sinter. While ensuring uniform temperature, slowly increase the temperature to achieve debinding and sintering of the product. The sintering temperature is approximately 850℃-900℃.

[0058] The debinding and sintering process is crucial to the amount of gas in the product, the degree of bonding between particles, and the mechanical strength of the substrate. The key to the sintering process is the consistency between the sintering curve and the furnace temperature, which determines the flatness and shrinkage rate of the substrate after sintering. The heating rate should not be too fast, otherwise it will lead to poor flatness, reduced shrinkage, and even warping of the sintered substrate. A sintering furnace is used to optimize the relationship between the debinding heating rate and holding time and the product's size, number of layers, and metallization amount. Typically, debinding is performed first, followed by sintering, requiring both a debinding furnace and a sintering furnace.

[0059] 8. Post-processing: The sintered products undergo end electrode treatment, and the formed products are inspected to obtain multilayer chip common-mode inductors with magnetic shielding structures that meet the requirements. Inspection includes visual inspection and testing. Visual inspection mainly checks the appearance, such as flatness, consistency, and the smoothness of the conductive strips. Testing uses a testing instrument with testing software to verify the product's wiring connections and determine whether the electrical performance of the LTCC substrate is qualified.

[0060] In one embodiment, as a specific implementation of the multilayer common-mode inductor with a magnetic shielding structure provided in this application, the magnetic shielding layer 1 and the connecting layer 2 are magnetically conductive materials made of ferrite material. Specifically, the magnetic shielding layer 1 and the connecting layer 2 are formed by opening and filling holes in the printing process and then printing. Manganese-zinc ferrite materials with an initial permeability greater than 5000 are generally referred to as high-permeability ferrites. The main characteristic of high-permeability ferrites is their exceptionally high permeability, typically exceeding 10000, which allows for a significant reduction in core size, meeting the needs of component miniaturization and lightweight design.

[0061] In one embodiment, see Figure 4 In one specific embodiment of the multilayer chip common-mode inductor with a magnetically shielded structure provided in this application, each inductor 4 is a spiral inductor. Two oppositely arranged inductors 4 are spiral inductors. Common-mode inductors with different center frequencies correspond to different numbers of spiral inductor layers and turns. Different numbers of spiral inductor layers can be understood as different spiral inductor lengths; that is, common-mode inductors with different center frequencies correspond to different spiral inductor lengths and turns. In this embodiment, the two inductors 4 have the same length and number of turns. This structure, compared to discrete wire-wound inductors, offers advantages such as lower cost, easier integration, lower power consumption, and lower noise. By increasing the coil thickness, the ohmic loss of the inductor 4 can be reduced, making it suitable for optimized design of low-frequency inductors.

[0062] In one embodiment, see Figure 3 and Figure 4As a specific embodiment of the multilayer common-mode inductor with a magnetic shielding structure provided in this application, each inductor 4 includes two wound electrodes 41 and an electrode layer 42; the dielectric layer 3 is respectively formed with a first hole 31 for accommodating each wound electrode 41 and a second hole 32 for accommodating each electrode layer 42, and each first hole 31 is connected to the corresponding second hole 32. Specifically, the two wound electrodes 41 in each inductor 4 are arranged in parallel and spaced apart, and the tail ends of the two wound electrodes 41 can be connected through the electrode layer 42, and the head ends of the two wound electrodes 41 can pass through the dielectric layer 3 and extend into the magnetic shielding layer 1. The portion of each wound electrode 41 located in the first hole 31 and the portion of each electrode layer 42 located in the second hole 32 are achieved by opening and filling holes in each strip during the printing process. The magnetic shielding layer 1 is provided with openings 12 for each wound electrode 41 to extend into. The portion of each wound electrode 41 located in the opening 12 is also achieved by opening and filling holes in each strip during the printing process. With this structure, the portion of each wound electrode 41 located in the dielectric layer 3 can be screen-printed through the first hole 31, the electrode layer 42 can be screen-printed through the second hole 32, and the portion of each wound electrode 41 extending into the magnetic shielding layer 1 can be screen-printed through the openings 12.

[0063] In one embodiment, see Figure 4 and Figure 5 As a specific embodiment of the multilayer chip common-mode inductor with a magnetically shielded structure provided in this application, each wound electrode 41 includes a helical electrode 411 and a connecting electrode 412 connected to the outer end of the helical electrode 411. The inner ends of two adjacent helical electrodes 411 are connected through corresponding electrode layers 42. Specifically, each helical electrode 411 is aligned with a corresponding first hole 31, and each connecting electrode 412 is aligned with a corresponding opening 12. The "inner end of the helical electrode 411" can be understood as the end of the helical electrode 411 close to the connecting layer 2, and the "outer end of the helical electrode 411" can be understood as the other end away from the connecting layer 2. The inner ends of two adjacent helical electrodes 411 are connected through an electrode layer 42 formed by screen printing from a corresponding second hole 32. In this structure, the second hole 32 is a vertical through-hole, and the connection of two helical electrodes 411 can be achieved through the electrode layer 42 formed by screen printing in the second hole 32. The depth of the second hole 32 determines the thickness of the electrode layer 42 and also affects the performance of the multilayer common mode inductor. Therefore, the depths of the first hole 31, the second hole 32 and the opening 12 can be adjusted accordingly as needed, and no single limitation is made here.

[0064] In one embodiment, see Figure 5As a specific embodiment of the multilayer chip common-mode inductor with a magnetically shielded structure provided in this application, each spiral electrode 411 includes a first electrode 4111, a second electrode 4112, a third electrode 4113, a fourth electrode 4114, a fifth electrode 4115, and a sixth electrode 4116. The second electrode 4112 is connected to the end of the first electrode 4111 furthest from the connecting layer 2, and the second electrode 4112 is perpendicular to the first electrode 4111. The other ends of two adjacent first electrodes 4111 are connected through corresponding electrode layers 42. The third electrode 4113 is connected to the end of the second electrode 4112 furthest from the first electrode 4111, and the third electrode 4113 is perpendicular to the second electrode 4112 and parallel to the first electrode 4111. The length of the third electrode 4113 is greater than the length of the first electrode 4111. The fourth electrode 4114 is connected to the end of the third electrode 4113 furthest from the second electrode 4112. The fourth electrode 4114 is perpendicular to the third electrode 4113 and parallel to the second electrode 4112. The length of the fourth electrode 4114 is greater than the length of the second electrode 4112. The fifth electrode 4115 is connected to the end of the fourth electrode 4114 furthest from the third electrode 4113. The fifth electrode 4115 is perpendicular to the fourth electrode 4114 and parallel to the third electrode 4113. The length of the fifth electrode 4115 is greater than the length of the third electrode 4113. The sixth electrode 4116 is connected to the end of the fifth electrode 4115 furthest from the fourth electrode 4114. The sixth electrode 4116 is perpendicular to the fifth electrode 4115 and parallel to the fourth electrode 4114. The length of the sixth electrode 4116 is greater than the length of the fourth electrode 4114. The connecting electrode 412 is connected to the end of the sixth electrode 4116 away from the fifth electrode 4115. The connecting electrode 412 is parallel to the fifth electrode 4115, and the connecting electrode 412 and the fifth electrode 4115 are located on opposite sides of the sixth electrode 4116. Correspondingly, the configuration of each first hole 31 is consistent with the configuration of the corresponding spiral electrode 411, and the configuration of each first hole 31 will not be described in detail here. This structure, by setting each spiral electrode 411 as the first electrode 4111, the second electrode 4112, the third electrode 4113, the fourth electrode 4114, the fifth electrode 4115, and the sixth electrode 4116, can achieve a spiral configuration and be wound to the target number of turns. Of course, in other embodiments, the number of turns of the winding electrode 41 can also be adjusted according to actual needs, and is not limited here.

[0065] In one embodiment, see Figure 5As a specific embodiment of the multilayer chip common-mode inductor with a magnetically shielded structure provided in this application, the width of each connecting electrode 412 is greater than the width of the corresponding spiral electrode 411. Specifically, the first electrode 4111, second electrode 4112, third electrode 4113, fourth electrode 4114, fifth electrode 4115, and sixth electrode 4116 of each spiral electrode 411 have the same width and thickness, but different lengths; the thickness of the connecting electrode 412 is the same as the thickness of the spiral electrode 411, but the length and width of the connecting electrode 412 are different from those of the spiral electrode 411. This structure, by increasing the width of each connecting electrode 412, facilitates the connection of each connecting electrode 412 to external devices.

[0066] In one embodiment, see Figure 1 and Figure 5 The magnetic shielding layer 1 can be rectangular in shape, having a top surface, a bottom surface, two narrow side surfaces, and two wide side surfaces. Each connecting electrode 412 can also be rectangular in shape, with a thickness significantly less than the thickness of the magnetic shielding layer 1. Each connecting electrode 412 has a top surface, a bottom surface, two narrow side surfaces, and two wide side surfaces. One wide side surface of each connecting electrode 412 is flush with the corresponding narrow side surface of the magnetic shielding layer 1, and another narrow side surface of each connecting electrode 412 is flush with the corresponding wide side surface of the magnetic shielding layer 1. That is, each narrow side surface of the magnetic shielding layer 1 has two wide side surfaces of the connecting electrodes 412, and each wide side surface of the magnetic shielding layer 1 has two narrow side surfaces of the connecting electrodes 412. This structure, by placing the side surfaces of each connecting electrode 412 on different side surfaces of the magnetic shielding layer 1, allows for adjustment of the connection direction and angle, facilitating connection with external devices.

[0067] In one embodiment, as a specific implementation of the multilayer chip common-mode inductor with a magnetically shielded structure provided in this application, each inductor 4 is a conductor made of silver material. This structure offers advantages such as stable potential, robust electrode structure, low temperature hysteresis, and suitability for use at high temperatures.

[0068] In one embodiment, see Figure 3 As a specific embodiment of the multilayer common-mode inductor with a magnetically shielded structure provided in this application, a clearance hole 33 is formed in the middle of the dielectric layer 3, and a connecting layer 2 is printed and filled in the clearance hole 33. Specifically, the clearance hole 33 is formed by opening holes in each strip during the printing step, the connecting layer 2 is filled in the clearance hole 33 of each strip, and the connecting layer 2 is stacked after the stacking step to form a connecting layer 2 of a certain thickness. In this structure, each inductor 4 is wound around the connecting layer 2, that is, the connecting layer 2 is located inside the inductor 4, and the magnetic shielding layer 1 covers each inductor 4, which can achieve the clamping of each inductor 4 from the inside and outside, further improving the effect of suppressing radiation interference.

[0069] In one embodiment, as a specific implementation of the multilayer chip common-mode inductor with a magnetically shielded structure provided in this application, the dielectric layer 3 is an insulator made of a low-dielectric-constant ceramic material. In this structure, the low-dielectric-constant ceramic material can reduce the interactive coupling loss between the substrate and the metal electrodes, shortening the signal propagation delay time.

[0070] The above description is merely an optional embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A multilayer chip common-mode inductor with a magnetically shielded structure, characterized in that, include: A magnetic shielding layer, wherein a hollow groove is formed inside the magnetic shielding layer; A connecting layer is disposed in the hollow groove, and an annular groove is formed between the outer wall of the connecting layer and the inner wall of the hollow groove. The top and bottom surfaces of the connecting layer are respectively connected to the magnetic shielding layer. A dielectric layer is filled in the annular groove. Two inductors are arranged at a relative interval, each inductor is disposed in the dielectric layer and wound around the connection layer, and the two ends of each inductor extend out of the dielectric layer and into the magnetic shielding layer respectively; Each inductor includes two parallel, spaced-apart wound electrodes and an electrode layer connecting the two wound electrodes; the dielectric layer has a first aperture for accommodating each wound electrode and a second aperture for accommodating each electrode layer, with each first aperture communicating with a corresponding second aperture; each first aperture and each second aperture are apertures opened in the dielectric layer and formed by screen printing and filling with conductive material to form the wound electrode and electrode layer; the magnetic shielding layer has openings for each wound electrode to extend into; Each of the wound electrodes includes a helical electrode and a connecting electrode connected to the outer end of the helical electrode, and the inner ends of two adjacent helical electrodes are connected through the corresponding electrode layers; Each of the spiral electrodes includes a first electrode, a second electrode perpendicular to one end of the first electrode, a third electrode perpendicular to the end of the second electrode away from the first electrode and parallel to the first electrode, a fourth electrode perpendicular to the end of the third electrode away from the second electrode and parallel to the second electrode, a fifth electrode perpendicular to the end of the fourth electrode away from the third electrode and parallel to the third electrode, and a sixth electrode perpendicular to the end of the fifth electrode away from the fourth electrode and parallel to the fourth electrode. The end of the sixth electrode away from the fifth electrode is provided with a corresponding connecting electrode. One wide side of each of the connecting electrodes is flush with the corresponding narrow side of the magnetic shielding layer, and one narrow side of each of the connecting electrodes is flush with the corresponding wide side of the magnetic shielding layer.

2. The multilayer chip common-mode inductor with magnetic shielding structure as described in claim 1, characterized in that: The magnetic shielding layer and the connecting layer are magnetic conductors made of ferrite material.

3. The multilayer chip common-mode inductor with magnetic shielding structure as described in claim 1, characterized in that: The inductors mentioned are all spiral inductors.

4. The multilayer chip common-mode inductor with magnetic shielding structure as described in claim 1, characterized in that: The width of each of the connecting electrodes is greater than the width of the corresponding spiral electrode.

5. The multilayer chip common-mode inductor with a magnetically shielded structure as described in any one of claims 1-4, characterized in that: Each of the aforementioned inductors is a conductor made of silver.

6. The multilayer chip common-mode inductor with a magnetically shielded structure as described in any one of claims 1-4, characterized in that: An clearance hole is formed in the middle of the dielectric layer, and the clearance hole is filled with the printed connecting layer.

7. The multilayer chip common-mode inductor with a magnetically shielded structure as described in any one of claims 1-4, characterized in that: The dielectric layer is an insulator made of a low dielectric constant ceramic material.

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