Method of forming a semiconductor device structure

Abstract

Methods of forming semiconductor device structures are described. In some embodiments, the methods include forming a fin from a substrate; forming a gate stack over some portions of the fin; forming epitaxial source / drain regions adjacent to the gate stack; depositing a dielectric layer over the epitaxial source / drain regions; forming an opening in the dielectric layer; forming a gapfill in the opening in a bottom-up manner. The gapfill includes Si or W. The methods also include forming a conductive feature over the epitaxial source / drain regions; and replacing the gapfill with a dielectric material.

Description

Technical Field

[0001] This disclosure relates to a method for forming a semiconductor device structure. Background Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers of material on a semiconductor substrate, and using photolithography to pattern the individual material layers to form circuit components and elements thereon.

[0003] The semiconductor industry is continuously increasing the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by constantly reducing the minimum feature size, which allows more components to be integrated into a given area. However, as the minimum feature size decreases, additional problems arise that need to be addressed. Summary of the Invention

[0004] According to one aspect of this disclosure, a method for forming a semiconductor device structure is provided, comprising: forming a fin from a substrate; forming a gate stack over some portions of the fin; forming an epitaxial source / drain region adjacent to the gate stack; depositing a dielectric layer over the epitaxial source / drain region; forming an opening in the dielectric layer; forming a gap filler in the opening in a bottom-up manner, wherein the gap filler comprises Si or W; forming a conductive feature over the epitaxial source / drain region; and replacing the gap filler with a dielectric material.

[0005] According to one aspect of this disclosure, a method for forming a semiconductor device structure is provided, comprising: forming a fin from a substrate; forming a first gate stack over a portion of the fin; forming an epitaxial source / drain region adjacent to the first gate stack; depositing a dielectric layer over the epitaxial source / drain region; forming a first opening in the dielectric layer; forming a gap filler in the first opening, comprising: depositing a material in the opening; etching a portion of the material; and repeating the deposition and etching to fill the opening; selectively removing a portion of the dielectric layer to form a second opening; and forming a conductive feature in the second opening.

[0006] According to one aspect of this disclosure, a method of forming a semiconductor device structure is provided, comprising: forming a fin from a substrate; forming a gate stack over portions of the fin; forming an epitaxial source / drain region adjacent to the gate stack; depositing a first dielectric layer over the epitaxial source / drain region; depositing a second dielectric layer over the first dielectric layer; forming an opening in the second dielectric layer; forming a gap filler in the opening; selectively removing portions of the first dielectric layer and the second dielectric layer to expose the epitaxial source / drain region; forming a conductive feature over the epitaxial source / drain region; and removing at least a portion of the second dielectric layer and the gap filler. Attached Figure Description

[0007] This disclosure is best understood by reading in conjunction with the accompanying drawings and through the following detailed description. It should be noted that, according to standard industry practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily enlarged or reduced.

[0008] Figure 1 Examples of semiconductor device structures are shown in three-dimensional views according to some embodiments.

[0009] Figures 2 to 37 Various views of intermediate stages in the fabrication of semiconductor device structures are shown according to some embodiments.

[0010] Figures 38A to 38G Various views of intermediate stages in the fabrication of semiconductor device structures, according to alternative embodiments, are shown.

[0011] Figures 39A to 44B Various views of intermediate stages in the fabrication of semiconductor device structures, according to alternative embodiments, are shown. Detailed Implementation

[0012] The following disclosure provides numerous different embodiments or examples for implementing various features of the proposed subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and not intended to be limiting. For example, in the following description, forming a first feature on or over a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples throughout this disclosure. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0013] In addition, spatially related terms (e.g., "below," "under," "down," "above," "above," "top," "upper," etc.) may be used to readily describe the relationship between one element or feature shown in the accompanying drawings and another element(s) or feature(s). Besides the orientations shown in the accompanying drawings, these spatially related terms are also intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially related descriptors used herein can be interpreted similarly.

[0014] Figure 1 An example of a semiconductor device structure 10 in a three-dimensional view according to some embodiments is shown. In some embodiments, the semiconductor device structure 10 includes a FinFET, such as... Figure 1 As shown in the diagram, the semiconductor device structure 10 includes fins 24 located on a substrate 20 (e.g., a semiconductor substrate). Isolation regions 22 are disposed in the substrate 20, and the fins 24 project from between adjacent isolation regions 22 and over adjacent isolation regions 22. Although the isolation regions 22 are described / shown as separate from the substrate 20, as used herein, the term "substrate" may be used to refer only to the semiconductor substrate, or may be used to refer to the semiconductor substrate including the isolation regions. Furthermore, the fins 24 may be a single continuous material, or the fins 24 and / or the substrate 20 may include multiple materials. In this document, fin 24 refers to the portion extending between adjacent isolation regions 22.

[0015] A gate dielectric layer 32 is located along the sidewall of fin 24 and also on the top surface of fin 24, with a gate electrode 34 located above the gate dielectric layer 32. In this illustration, the gate electrode 34 and gate dielectric layer 32 may be dummy and can be replaced by a gate electrode in subsequent processes. A mask 36 is located above the gate electrode 34. Epitaxial source / drain regions 42 are disposed on the opposite side of fin 24 relative to the gate dielectric layer 32 and gate electrode 34. The gate dielectric layer 32 and gate electrode 34, together with any interface layers (not shown), form a gate stack 30. Gate spacers 38 are disposed on each side of the gate stack 30 and surround the epitaxial source / drain regions 42. Figure 1 Reference cross sections used in the following figures are also shown. Cross section AA is along the longitudinal axis of the gate electrode 34. Cross section BB is perpendicular to cross section AA and along the longitudinal axis of the fin 24. Cross section CC is parallel to cross section AA and extends through the epitaxial source / drain region 42 of the FinFET. Cross section DD is parallel to cross section BB and extends through the fin 24. For clarity, the following figures refer to these reference cross sections.

[0016] Some embodiments discussed herein are discussed in the context of FinFETs formed using a post-gate process, and gate stack 30 is a dummy gate stack. In other embodiments, a pre-gate process may be used. Furthermore, some embodiments contemplate aspects used in planar devices (e.g., planar FETs) or in nanostructure devices (e.g., gate-around-around-(GAA) FETs, nanosheet FETs, or nanowire FETs).

[0017] Figures 2 to 8 These are various views of intermediate stages in the fabrication of semiconductor device structure 10 according to some embodiments. Reference Figure 1 The cross section defined by line AA, Figure 2 , Figure 3 , Figure 4 , Figure 6 and Figure 8 The cross section along section AA is shown. Figure 5 and Figure 7 It is a perspective view.

[0018] refer to Figure 2 A substrate 20 is provided. The substrate 20 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc., which may be doped (e.g., doped with p-type or n-type dopant) or undoped. The substrate 20 may be a wafer, such as a silicon wafer. Typically, an SOI substrate is a layer of semiconductor material formed on an insulating layer. The insulating layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulating layer is disposed on the substrate, which is typically a silicon or glass substrate. Other substrates may also be used, such as multilayer or gradient substrates. In some embodiments, the semiconductor material of the substrate 20 may include silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium arsenide phosphide; or combinations thereof.

[0019] Substrate 20 has region 20N and region 20P. Region 20N can be used to form an n-type device, such as an NMOS transistor, or an n-type FinFET. Region 20P can be used to form a p-type device, such as a PMOS transistor, or a p-type FinFET. Region 20N can be physically separated from region 20P (as shown by separator 21), and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) can be formed between region 20N and region 20P.

[0020] exist Figure 3In this process, fins 24 are formed in substrate 20. Fins 24 are semiconductor strips. In some embodiments, fins 24 can be formed in substrate 20 by etching trenches in substrate 20. Etching can be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), or combinations thereof. Etching can be anisotropic.

[0021] The fin 24 can be patterned using any suitable method. For example, the fin 24 can be patterned using one or more photolithography processes, including dual patterning or multiple patterning processes. Typically, dual patterning or multiple patterning processes are combined with photolithography and self-aligned processes to allow the creation of patterns with, for example, smaller pitches than that achievable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed on a substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the fin. In some embodiments, a mask (or other layer) may be retained on the fin 24.

[0022] exist Figure 4 In this embodiment, an insulating material 25 is formed on the substrate 20 between adjacent fins 24. The insulating material 25 can be an oxide (e.g., silicon oxide), a nitride, or a combination thereof, and can be formed by high-density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD) (e.g., depositing a CVD-based material in a remote plasma system and post-curing it to transform it into another material, e.g., an oxide), or a combination thereof. Other insulating materials formed by any acceptable process can be used. In the illustrated embodiment, the insulating material 25 is silicon oxide formed by an FCVD process. Once the insulating material is formed, an annealing process can be performed. In one embodiment, the insulating material 25 is formed such that excess insulating material 25 covers the fins 24. Although the insulating material 25 is shown as a single layer, some embodiments may use multiple layers. For example, in some embodiments, a pad (not shown) may first be formed along the surfaces of the substrate 20 and the fins 24. Subsequently, a filler material, such as that discussed above, may be formed on the pad.

[0023] Figure 5 A perspective view applicable to area 20N or area 20P is shown. Figure 6 It shows Figure 5 The cross-sectional view of the structure shown is derived from a structure including, for example, Figure 1 The plane of line AA shown is obtained. Figure 5 and Figure 6In this process, a removal process is applied to the insulating material 25 to remove excess insulating material 25 above the fin 24. In some embodiments, a planarization process, such as chemical mechanical polishing (CMP), etch-back process, or a combination thereof, may be used. The planarization process exposes the fin 24 such that, after the planarization process is completed, the top surface of the fin 24 is flush with the top surface of the insulating material 25. In embodiments where the mask remains on the fin 24, the planarization process may expose or remove the mask such that, after the planarization process is completed, the top surface of the corresponding mask or fin 24 is flush with the top surface of the insulating material 25.

[0024] Figure 7 A perspective view applicable to area 20N or area 20P is shown. Figure 8 It shows Figure 7 The cross-sectional view of the structure shown is derived from a structure including, for example, Figure 1 The plane of line AA shown is obtained. Figure 7 and Figure 8 In this process, the insulating material 25 is recessed to form shallow trench isolation (STI) regions (isolation regions 22). The insulating material 25 is recessed such that the upper portions (channel regions 24') of the fins 24 in regions 20N and 20P protrude between adjacent isolation regions 22. Furthermore, the top surface of the isolation region 22 can have a flat surface (as shown), a convex surface, a concave surface (e.g., dish-shaped), or a combination thereof. The top surface of the isolation region 22 can be formed as flat, convex, and / or concave by appropriate etching. An acceptable etching process can be used to recess the isolation region 22, for example, an etching process selective for the material of the insulating material 25 (e.g., etching the material of the insulating material 25 at a faster rate than etching the material of the fins 24). For example, an oxidation removal process can be used, such as an oxidation removal process using dilute hydrofluoric acid (dHF).

[0025] against Figures 2 to 8 The described process is only one example of how fin 24 can be formed. Other processes can be performed to form fin 24.

[0026] Figures 9 to 37 Various additional intermediate stages in the fabrication of semiconductor device structure 10 according to some embodiments are shown. Figures 9 to 37 Features of either region 20N or region 20P are shown, and regions 20N and 20P will not be shown separately. Structural differences between regions 20N and 20P (if any) are described in the accompanying text of each figure. Reference Figure 1 The cross section defined by lines AA, BB, CC, and DD. Figure 10A , Figure 12A , Figure 15A , Figure 17A , Figure 19A and Figure 21A The cross section along line AA is shown. Figure 24A , Figure 25A , Figure 26A , Figure 27A , Figure 28A , Figure 29A , Figure 30A , Figure 31A , Figure 32A and Figure 33A The cross section along line BB is shown. Figure 13A , Figure 13B , Figure 24B , Figure 25B , Figure 26B , Figure 27B , Figure 28B , Figure 29B , Figure 30B , Figure 31B , Figure 32B , Figure 33B , Figure 36 and Figure 37 The cross section along line CC is shown. Figure 10B , Figure 12B , Figure 15B , Figure 17B , Figure 19B and Figure 21B The cross section along line DD is shown.

[0027] Figure 10A It shows Figure 9 The cross-sectional view of the structure shown is derived from a structure including, for example, Figure 1 The plane of line AA shown is obtained. Figure 10B It shows Figure 9 The cross-sectional view of the structure shown is derived from a structure including, for example, Figure 1 The line DD shown is obtained from the plane. Figure 9 , Figure 10A and Figure 10BIn this process, a dummy dielectric layer is formed on fin 24. The dummy dielectric layer can be, for example, silicon oxide, silicon nitride, a combination thereof, etc., and can be deposited or thermally grown according to acceptable techniques. A dummy gate layer is formed on the dummy dielectric layer, and a mask layer is formed on the dummy gate layer. The dummy gate layer can be deposited on the dummy dielectric layer and then planarized, for example, by CMP. The mask layer can be deposited on the dummy gate layer. The mask layer can be patterned using acceptable photolithography and etching techniques to form a mask 36. The pattern of the mask 36 can then be transferred to the dummy gate layer to form a dummy gate electrode 34. In some embodiments, the pattern of the mask 36 can also be transferred to the dummy dielectric layer by acceptable etching techniques to form a gate dielectric layer 32. The gate dielectric layer 32 and the dummy gate electrode 34 together form a dummy gate stack 30. The dummy gate stack 30 covers the corresponding channel region 24'. The longitudinal direction of the dummy gate stack 30 can be substantially perpendicular to the longitudinal direction of each epitaxial fin 24.

[0028] The dummy gate electrode 34 can be a conductive or non-conductive material, and can be selected from the group consisting of amorphous silicon, polysilicon, poly-SiGe, metal nitrides, metal silicides, metal oxides, and metals. The dummy gate electrode 34 formed by the dummy gate layer can be deposited by physical vapor deposition (PVD), CVD, sputtering deposition, or other techniques known in the art for depositing the selected material. It should be noted that the gate dielectric layer 32 is shown only covering the fin 24, and this is for illustrative purposes only.

[0029] Also in Figure 9 , Figure 10A and Figure 10B A gate sealing spacer 38A can be formed on the exposed surfaces of the dummy gate stack 30, mask 36, and / or fins 24 (channel region 24'). Thermal oxidation or deposition followed by anisotropic etching can be used to form the gate sealing spacer 38A. The gate sealing spacer 38A can be formed from silicon oxide, silicon nitride, silicon oxynitride, etc. After the gate sealing spacer 38A is formed, implantation for lightly doped source / drain (LDD) regions (not explicitly shown) can be performed.

[0030] Also in Figure 9 , Figure 10A and Figure 10B A gate spacer 38B is formed on the gate spacer 38A along the sidewalls of the dummy gate stack 30 and the mask 36. The gate spacer 38B can be formed by conformally depositing an insulating material and then anisotropically etching the insulating material. The insulating material of the gate spacer 38B can be silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, or combinations thereof.

[0031] For simplicity, gate sealing spacer 38A and gate spacer 38B may be collectively referred to as gate spacer 38. It should be noted that the above disclosure generally describes the process of forming the spacer and LDD region. Other processes and sequences may be used.

[0032] Figure 12A It shows Figure 11 The cross-sectional view of the structure shown is derived from a structure including, for example, Figure 1 The plane of line AA shown is obtained. Figure 12B It shows Figure 11 The cross-sectional view of the structure shown is derived from a structure including, for example, Figure 1 The plane of line DD shown is obtained. Figure 13A and Figure 13B It shows Figure 11 The cross-sectional view of the structure shown is derived from a structure including, for example, Figure 1 The line CC shown is obtained from the plane. Figure 11 , Figure 12A , Figure 12B , Figure 13A and Figure 13B In the fin 24, epitaxial source / drain regions 42 are formed to apply stress in the respective channel regions 24', thereby improving performance. The epitaxial source / drain regions 42 are formed in the fin 24 such that each dummy gate stack 30 is disposed between correspondingly adjacent pairs of epitaxial source / drain regions 42. In some embodiments, the epitaxial source / drain regions 42 may extend into and penetrate the fin 24. In some embodiments, gate spacers 38 are used to space the epitaxial source / drain regions 42 from the dummy gate stacks 30 by an appropriate lateral distance so that the epitaxial source / drain regions 42 are not short-circuited with the gate of the subsequently formed final FinFET.

[0033] The epitaxial source / drain region 42 in region 20N (e.g., an NMOS region) can be formed by masking region 20P (e.g., a PMOS region) and etching the source / drain region in region 20N of fin 24 to form a groove in fin 24. The epitaxial source / drain region 42 in region 20N is then epitaxially grown in the groove. The epitaxial source / drain region 42 can comprise any acceptable material, such as materials suitable for n-type FinFETs. For example, if fin 24 is silicon, the epitaxial source / drain region 42 in region 20N can comprise a material to which tensile strain is applied in channel region 24', such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, etc. The epitaxial source / drain region 42 in region 20N can have a surface higher than the corresponding surface of fin 24 and can have facets.

[0034] The epitaxial source / drain region 42 in region 20P (e.g., a PMOS region) can be formed by masking region 20N (e.g., an NMOS region) and etching the source / drain region in region 20P of fin 24 to form a groove in fin 24. The epitaxial source / drain region 42 in region 20P is then epitaxially grown in the groove. The epitaxial source / drain region 42 can comprise any acceptable material, such as materials suitable for p-type FinFETs. For example, if fin 24 is silicon, the epitaxial source / drain region 42 in region 20P can comprise a material to which compressive strain is applied in channel region 24', such as silicon-germanium, boron-doped silicon-germanium, germanium, germanium-tin, etc. The epitaxial source / drain region 42 in region 20P can also have a surface higher than the corresponding surface of fin 24 and can have a facet.

[0035] Dopant can be implanted into the epitaxial source / drain region 42 and / or fin 24 to form the source / drain region, similar to the previously discussed process for forming lightly doped source / drain regions, followed by an annealing process. The impurity concentration of the epitaxial source / drain region 42 can be approximately 10. 19 cm -3 Up to approximately 10 21 cm -3 Between. The n-type and / or p-type impurities used for the epitaxial source / drain region 42 can be any impurities discussed previously. In some embodiments, the epitaxial source / drain region 42 can be doped in situ during growth.

[0036] As a result of the epitaxial process used to form the epitaxial source / drain regions 42 in regions 20N and 20P, the upper surfaces of the epitaxial source / drain regions have small facets that extend laterally outward beyond the sidewalls of the fin 24. In some embodiments, these small facets cause adjacent epitaxial source / drain regions 42 of the same FinFET to merge, such as... Figure 13A As shown in the diagram. In other embodiments, after the epitaxial process is completed, adjacent epitaxial source / drain regions 42 remain separated, as illustrated. Figure 13B As shown. In Figure 13A and Figure 13B In the illustrated embodiment, the gate spacer 38 is formed to cover the portion of the sidewall of the fin 24 that extends beyond the STI region 22 (channel region 24'), thereby preventing epitaxial growth. In some other embodiments, the spacer etching for forming the gate spacer 38 can be adjusted to remove spacer material to allow the epitaxial source / drain region 42 to extend to the surface of the isolation region 22.

[0037] Figure 15A It shows Figure 14 The cross-sectional view of the structure shown is derived from a structure including, for example, Figure 1The plane of line AA shown is obtained. Figure 15B It shows Figure 14 The cross-sectional view of the structure shown is derived from a structure including, for example, Figure 1 The line DD shown is obtained from the plane. Figure 14 , Figure 15A and Figure 15B In Figure 11 , Figure 12A and Figure 12B A dielectric layer 48 is deposited on the semiconductor device structure 10 shown. The dielectric layer 48 may be a first interlayer dielectric (ILD). The dielectric layer 48 may be formed of a dielectric material and may be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. The dielectric material may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc. Other insulating materials formed by any acceptable process may be used. In some embodiments, a contact etch stop layer (CESL) 46 is disposed between the dielectric layer 48 and the epitaxial source / drain region 42, mask 36, and gate spacer 38. The CESL 46 may include a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, etc., having an etch rate different from that of the dielectric layer 48.

[0038] Figure 17A It shows Figure 16 The cross-sectional view of the structure shown is derived from a structure including, for example, Figure 1 The plane of line AA shown is obtained. Figure 17B It shows Figure 16 The cross-sectional view of the structure shown is derived from a structure including, for example, Figure 1 The line DD shown is obtained from the plane. Figure 16 , Figure 17A and Figure 17B A planarization process (e.g., CMP) can be performed to make the top surface of the dielectric layer 48 flush with the top surface of the dummy gate stack 30 or the mask 36 (e.g., as shown in Figure 36). Figure 17B (As shown in the diagram). The planarization process can also remove the mask 36 (or a portion thereof) on the dummy gate stack 30, as well as a portion of the gate spacer 38 along the sidewalls of the mask 36. After the planarization process, the mask 36 may be retained, in which case the top surface of the mask 36, the top surface of the gate spacer 38, and the top surface of the dielectric layer 48 are flush with each other. In some embodiments, the top surfaces of the dummy gate stack 30, the top surfaces of the gate spacer 38, and the top surfaces of the dielectric layer 48 are planarized due to the planarization process. In such an embodiment, the top surface of the dummy gate electrode 34 is exposed through the dielectric layer 48.

[0039] Figure 19A It shows Figure 18 The cross-sectional view of the structure shown is derived from a structure including, for example, Figure 1 The plane of line AA shown is obtained. Figure 19B It shows Figure 18 The cross-sectional view of the structure shown is derived from a structure including, for example, Figure 1 The plane of line DD shown is obtained. Figure 18 , Figure 19A and Figure 19B The gate replacement process is illustrated. A dummy gate electrode 34, a mask 36 (if present), and an optional gate dielectric layer 32 are removed by one or more etching processes and replaced by a replacement gate. In some embodiments, the mask 36 (if present) and the dummy gate electrode 34 are removed by an anisotropic dry etching process. During removal, the gate dielectric layer 32 can be used as an etch stop layer when etching the dummy gate electrode 34. The gate dielectric layer 32 can then be optionally removed after the dummy gate electrode 34 has been removed.

[0040] Next, a gate dielectric layer 52 and a gate electrode 56 are formed. The gate dielectric layer 52 is conformally deposited in a recess, for example, on the top surface and sidewalls of the fin 24, and on the sidewalls of the gate spacer 38. The gate dielectric layer 52 may also be formed on the top surface of the dielectric layer 48. According to some embodiments, the gate dielectric layer 52 comprises silicon oxide, silicon nitride, or a multilayer thereof. In some embodiments, the gate dielectric layer 52 may comprise a high-k dielectric material, and in these embodiments, the gate dielectric layer 52 may have a k value greater than about 7.0, and may comprise metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. The gate dielectric layer 52 may be formed by molecular beam deposition (MBD), atomic layer deposition (ALD), PECVD, etc.

[0041] Gate electrode 56 is deposited on gate dielectric layer 52 and fills the remainder of the trench. Gate electrode 56 may include a metallic material, such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multilayers thereof. For example, although... Figure 19BThe gate electrode 56 is shown as having a single layer, but it may include any number of pad layers, any number of work function tuning layers, and fill material, all of which are shown together as the gate electrode 56. The work function tuning layer may include a conductive material, such as a metal nitride, for example, TiN or TaN. The fill material may include a conductive material, such as a metal. After filling the trench, a planarization process (e.g., CMP) may be performed to remove excess portions of the gate dielectric layer 52 and excess portions of the gate electrode 56 above the top surface of the dielectric layer 48. The remaining portions of the gate dielectric layer 52 and the gate electrode 56 thus form the alternative gate of the resulting FinFET. The alternative gate, gate electrode 56, and gate dielectric layer 52 may be collectively referred to as gate stack 60.

[0042] The formation of the gate dielectric layer 52 in regions 20N and 20P can occur simultaneously, such that the gate dielectric layer 52 in each region is formed of the same material, and the formation of the gate electrode 56 can occur simultaneously, such that the gate electrode 56 in each region is formed of the same material. In some embodiments, the gate dielectric layer 52 in each region can be formed using different processes so that the gate dielectric layer 52 can be made of different materials, and / or the gate electrode 56 in each region can be formed using different processes so that the gate electrode 56 can be made of different materials. When using different processes, various masking steps can be used to mask and expose appropriate regions.

[0043] Figure 21A It shows Figure 20 The cross-sectional view of the structure shown is derived from a structure including, for example, Figure 1 The plane of line AA shown is obtained. Figure 21B It shows Figure 20 The cross-sectional view of the structure shown is derived from a structure including, for example, Figure 1 The plane of line DD shown is obtained. Figure 20 , Figure 21A and Figure 21B As shown, a hard mask 62 is formed. The material of the hard mask 62 may be the same as or different from the material of the CESL 46, the dielectric layer 48, and / or the gate spacer 38. In some embodiments, the hard mask 62 is formed of silicon nitride, silicon oxynitride, silicon oxycarbide, silicon oxycarbonitride, etc. In some embodiments, the hard mask 62 comprises silicon or tungsten. Forming the hard mask 62 may include: recessing the gate stack 60 to form a trench, filling the trench with dielectric material, and performing planarization to remove excess portions of the dielectric material. The remaining portion of the dielectric material located in the trench constitutes the hard mask 62.

[0044] Figure 22A top view of an example portion of a FinFET layout according to some embodiments is shown. In this view, the dielectric layer 48 is not shown to more clearly show the gate stack 60 with a hard mask 62 and the fins 24 with epitaxial source / drain regions 42. Vertical lines correspond to the gate stack 60 with the hard mask 62 formed. Horizontal lines correspond to the fins 24 with the epitaxial source / drain regions 42 formed. Dashed lines correspond to openings 70, which are regions located between adjacent gate stacks 60 and adjacent fins 24. It should be noted that in some embodiments, openings 70 may be located above the regions between adjacent gate stacks 60 and adjacent fins 24. In other words, in some embodiments, openings 70 may not extend between adjacent gate stacks 60 and adjacent fins 24. Multiple openings 70 may be formed between adjacent gate stacks 60 and adjacent fins 24. Lines BB and CC correspond to... Figure 1 The lines in the diagram represent cross-sectional views obtained from the plane that includes the corresponding line.

[0045] Figures 22 to 37 A reverse-cut contact process for forming conductive contacts for epitaxial source / drain regions 42 is illustrated. The diagrams for subsequent processes are numbered with the letters "A" or "B". Unless otherwise stated, diagrams numbered with the letter "A" are derived from, for example, those including... Figure 1 The line BB in the diagram is obtained from the same vertical plane as the vertical plane in the diagram. The diagrams numbered with the letter "B" are, for example, those including... Figure 1 The line CC is obtained from the same vertical plane as the vertical plane.

[0046] Figure 23 , Figure 24A and Figure 24B The formation of a bottom layer 64, an intermediate layer 66, and a top layer 68 is shown. In some embodiments, the bottom layer 64 is a bottom anti-reflective coating (BARC), the intermediate layer 66 is an oxide or nitride (e.g., SiN, SiON, SiCN, SiOCN, etc.), and the top layer 68 may be a patterned photoresist. An opening 70 is formed in the top layer 68.

[0047] like Figure 25A and Figure 25B As shown, opening 70 extends into dielectric layer 48. For example, opening 70 may be located between adjacent gate stacks 60 and adjacent epitaxial source / drain regions 42. The bottom layer 64, intermediate layer 66, and top layer 68 may be removed. In some embodiments, opening 70 does not extend through dielectric layer 48, but rather the bottom of opening 70 is dielectric layer 48. In some embodiments, as... Figure 26A and Figure 26BAs shown, opening 70 extends through dielectric layer 48, and the bottom of opening 70 is CESL 46. In some embodiments, opening 70 extends through dielectric layer 48 and CESL 46 and into isolation region 22.

[0048] like Figure 27A and Figure 27B As shown, material 72 is deposited in the opening 70 and on the dielectric layer 48. Material 72 may have different etch selectivity than the materials of the dielectric layer 48, hard mask 62, and CESL 46. In some embodiments, material 72 comprises Si, W, SiN, SiCN, SiCO, or any suitable material. In some embodiments, material 72 comprises the same material as the hard mask 62. Material 72 can be deposited by any suitable deposition process. In some embodiments, a CVD process (e.g., PECVD process) is performed to form material 72. Figure 27A and Figure 27B As shown, material 72 is formed on the sidewalls of opening 70 and dielectric layer 48. The distance D1 between the portions of material 72 disposed on dielectric layer 48 is significantly smaller than the distance D2 between the portions of material 72 disposed on the sidewalls of opening 70. Therefore, if the process for forming material 72 continues, opening 70 may be filled with voids or seams formed therein. To fill opening 70 seamlessly or without voids, an etching process is performed to remove the portions of material 72 formed on dielectric layer 48 and to enlarge the top of opening 70, as shown. Figure 28A and Figure 28B As shown in the image.

[0049] The etching process can be any suitable etching process, such as dry etching. In some embodiments, anisotropic plasma etching is performed to remove portions of material 72. In some embodiments, the etching process is a physical sputtering process. In some embodiments, the remaining material 72 in the opening 70 may have a U-shaped cross-section, such as... Figure 28A and Figure 28B As shown in the figure. In some embodiments, the remaining material 72 in the opening 70 may have a "V" shaped cross section, as shown in the figure. Figure 29A and Figure 29B As shown in some embodiments, such as Figure 28A , Figure 28B , Figure 29A , Figure 29B As shown, a portion of the remaining material 72 is disposed on the dielectric layer 48. In some embodiments, the remaining material 72 is disposed only in the opening 70. In other words, the portion of material 72 disposed on the dielectric layer 48 is removed by an etching process.

[0050] The deposition and etching processes can be repeated until opening 70 is filled. The deposition and etching processes can be a single cycle, and multiple cycles can be performed to fill opening 70. For example, as... Figure 30A , Figure 30B , Figure 31A , Figure 31B As shown, three loops are executed to form layers 72a, 72b, and 72c in opening 70. Layer 72a can be as follows: Figure 28A Figure 28b Figure 29A and Figure 29B Material 72 is shown. The number of cycles is not limited to three. In some embodiments, the number of cycles ranges from about 2 to about 10. As a result of the process cycles, gap filler 74 seamlessly and without voids fills the opening 70, which in turn improves yield. Gap filler 74 may include multiple layers from deposition and etching cycles, such as layer 72a, layer 72b, and layer 72c. A planarization process may be performed after the deposition process of the last cycle, instead of an etching process. As a result, as Figure 30A , Figure 30B , Figure 31A , Figure 31B As shown, the gap filler 74 may be substantially coplanar with the dielectric layer 48 and the hard mask 62. In some embodiments, the gap filler 74 is disposed in the dielectric layer 48. In some embodiments, the gap filler 74 is configured to pass through the dielectric layer 48 and be located on the CESL 46. In some embodiments, the gap filler 74 is configured to pass through the dielectric layer 48 and the CESL 46 and be located on the isolation region 22.

[0051] In some embodiments, the gap filler 74 may be formed in a bottom-up manner, such as... Figure 32A and Figure 32BAs shown in the diagram. In some embodiments, the interstitial filler 74 comprises silicon or tungsten, and certain precursors used to form the interstitial filler 74 have a very low adhesion coefficient, which can easily reach the bottom of the opening 70 and fill the opening 70 in a bottom-up manner. For example, the interstitial filler 74 comprises silicon, and silane (SiH4) is used as a precursor for forming silicon. A plasma-enhanced process is performed, and the plasma-decomposed silane has an adhesion coefficient of less than 0.01 at a processing temperature ranging from about 250 degrees Celsius to about 650 degrees Celsius. Utilizing such a low adhesion coefficient, high step coverage is achieved, and the opening 70 is seamlessly and void-free using the interstitial filler 74 (i.e., silicon). In another example, the interstitial filler 74 comprises tungsten, and tungsten hexafluoride (WF6) and hydrogen (H2) are used as precursors for forming tungsten. Plasma-enhanced CVD was performed at a processing temperature ranging from approximately 250°C to approximately 650°C, where the plasma-fractured WF6 and H2 exhibited an adhesion coefficient of less than 0.01. This low adhesion coefficient enabled high coverage, and the openings 70 were seamlessly and void-free using interstitial filler 74 (i.e., tungsten). A planarization process can be performed to remove any interstitial filler 74 formed on the dielectric layer 48.

[0052] In some embodiments, a bottom-up gap filler 74 is formed in a low-pressure processing chamber using a low-pressure process. For example, the processing pressure for forming the bottom-up gap filler 74 is less than about 100 mTorr, for example, from about 3 mTorr to about 10 mTorr. In some embodiments, the processing pressure ranges from about 1 mTorr to about 100 mTorr. In some embodiments, the low-pressure process is a high-density plasma (HDP) process, where the plasma pyrolysis precursor has a very high mean free path from about 0.45 cm to about 4.5 cm. With such a high mean free path, the precursor can easily reach the bottom of the opening 70 and fill the bottom of the opening 70 in a bottom-up manner. A planarization process can be performed to remove any gap filler 74 formed on the dielectric layer 48. In some embodiments, the low-pressure processing chamber is an inductively coupled plasma (ICP) HDP chamber.

[0053] In some embodiments, such as Figure 33A and Figure 33B As shown, an ion-assisted deposition process 76 is performed to form interstitial filler 74. For example, in the ion-assisted deposition process 76, ions in the precursor are controlled such that the path to the substrate 20 is substantially perpendicular to the substrate 20. In other words, the deposition angle can be approximately 90 degrees. The deposition angle can be controlled by applying a bias voltage to the precursor in the processing chamber. As a result of the ion-assisted deposition process, the opening 70 is filled with interstitial filler 74 in a bottom-up manner. Figure 33A and Figure 33B The interstitial filler 74 shown is present during and at the end of the ion-assisted deposition process. Figure 33A and Figure 33B As shown, most of the interstitial filler 74 is formed on a horizontal surface, for example, at the bottom of the opening 70 and the top of the dielectric layer 48. Therefore, the opening 70 is filled with the interstitial filler 74 in a bottom-up manner. After the ion-assisted deposition process, a planarization process is performed to remove the portion of the interstitial filler 74 formed on the dielectric layer 48.

[0054] Various processes for filling the opening 70 with a seamless and void-free gap filler 74 (e.g., deposition and etching cycles, ion-assisted deposition, low-pressure processes, and the use of precursors with low adhesion coefficients) can be combined in any way to further improve the gap-filling properties of the gap filler 74.

[0055] Figure 34 This is a top view of a portion of the layout of a FinFET according to some embodiments. For clarity, various components of the FinFET, such as dielectric layer 48, CESL 46, and hard mask 62, may be omitted. Figure 34 As shown, in some embodiments, after the gap filler 74 is formed, a mask 77 is formed over the gate stack 60, exposing portions of the dielectric layer 48 formed over the epitaxial source / drain regions 42 and the gap filler 74. In some embodiments, the gap filler 74 may be located above the gate stack 60 and may partially overlap with the gate stack 60 along the z-axis to obtain a wider process window, such as... Figure 34 As shown. Next, as... Figure 35 and Figure 36As shown, a selective etching process is performed to remove the exposed portion of the dielectric layer 48 used to expose the epitaxial source / drain regions 42, and to form conductive features 78 over the source / drain regions 42. The conductive features 78 may be conductive contacts for the epitaxial source / drain regions 42. The selective etching process does not significantly affect, or only slightly affects, the gap filler 74 and the mask 77. The mask 77 may be removed after the conductive features 78 are formed. The conductive features 78 include conductive materials, such as copper, copper alloys, silver, gold, tungsten, cobalt, aluminum, nickel, etc. In some embodiments, a pad (not shown) and / or a barrier layer (not shown) may be formed first, and the conductive material may be formed on the pad and / or barrier layer. A silicide layer (not shown) may be formed between each epitaxial source / drain region 42 and the conductive feature 78. In some embodiments, each epitaxial source / drain region 42 has a different conductive feature 78 formed thereon. In some embodiments, conductive features 78 are formed over two or more epitaxial source / drain regions 42. A planarization process (e.g., CMP) can be performed to remove excess material from the top surface of the dielectric layer 48.

[0056] In some embodiments, the interstitial filler 74 comprises a dielectric material, such as SiN, SiCN, SiCO, or other suitable dielectric materials. Subsequent processes may be performed, such as forming a dielectric layer on the dielectric layer 48, the conductive feature 78, and the interstitial filler 74, and forming a conductive feature in the dielectric layer to electrically connect to the conductive feature 78 and the gate stack 60. In some embodiments, the interstitial filler 74 comprises Si or W, and the interstitial filler 74 is removed and replaced by a dielectric filler 80, such as... Figure 37 As shown in the image.

[0057] In some embodiments, the interstitial filler 74 comprises Si or W and is eventually replaced by a dielectric material, since a low-adhesion-coefficient precursor is used to form Si or W. For example, the interstitial filler 74 is removed by a selective etching process after the formation of the conductive feature 78. In embodiments where the hard mask 62 comprises the same material as the interstitial filler 74, the hard mask 62 is also removed by a selective etching process. Due to the removal of the interstitial filler 74, the opening 70 reappears, and a dielectric filler 80 is formed in the opening 70. The dielectric filler 80 may also be formed on the dielectric layer 48 and the conductive feature 78, and a planarization process (e.g., CMP process) may be performed to remove portions of the dielectric filler 80 formed on the dielectric layer 48 and the conductive feature 78. In some embodiments, the dielectric filler 80 may also replace the hard mask 62. The dielectric filler 80 comprises a dielectric material, such as an oxide, for example, silicon oxide or a low-k material. In some embodiments, the dielectric filler 80 comprises the same material as the dielectric layer 48. As described above, the gap filler 74 can be formed in the dielectric layer 48, through the dielectric layer 48, or through the dielectric layer 48 and CESL 46. Therefore, the dielectric filler 80 can also be formed in the dielectric layer 48, through the dielectric layer 48, or through the dielectric layer 48 and CESL 46.

[0058] Figures 38A to 38G Various views of an intermediate stage in the semiconductor device structure 10 according to an alternative embodiment are shown. Reference Figure 1 The cross section defined by lines AA, BB, CC, and DD. Figures 38A to 38G The cross-section along line CC is shown. (Example) Figure 38A As shown, after the gate stack 60 is formed, a dielectric layer 82 is formed on the dielectric layer 48. The dielectric layer 82 may be a second ILD. The dielectric layer 82 may include the same material as the dielectric layer 48.

[0059] Figure 38B This diagram illustrates the formation of a bottom layer 64, an intermediate layer 66, and a top layer 68 on a dielectric layer 82. An opening 84 is formed in the top layer 68. Figure 38C As shown, opening 84 extends into dielectric layer 82. In some embodiments, such as Figure 38C As shown, opening 84 extends through dielectric layer 82 and exposes dielectric layer 48.

[0060] like Figure 38DAs shown, a gap filler 86 is formed in the opening 84. The gap filler 86 may comprise the same material as the gap filler 74 and may be formed by the same process as the gap filler 74. The gap filler 86 comprises a material having a different etch selectivity than the material of the dielectric layers 48, 82. In some embodiments, the gap filler 86 comprises Si, W, SiN, SiCN, SiCO, or any suitable material. In some embodiments, the gap filler 86 comprises Si or W.

[0061] Next, a dielectric layer 82 above the gate stack 60 can be formed, for example, as shown below. Figure 34 The mask 77 shown exposes part of the gap filler 86 and dielectric layer 82. Figure 38E As shown, exposed portions of dielectric layer 82 and portions of dielectric layer 48 disposed therebelow are removed to form opening 88. Epitaxial source / drain regions 42 are exposed in opening 88. The removal of these portions of dielectric layers 82 and 48 can be performed using a selective etching process that substantially does not affect the spacer filler 86 and the mask. The mask can be removed after opening 88 has been formed. Since the spacer filler 86 has a different etch selectivity than the dielectric layers 82 and 48, patterning the mask to form opening 88 becomes easier.

[0062] like Figure 38F As shown, a conductive feature 90 is formed in the opening 88 and on the gap filler 86. The conductive feature 90 may be a conductive contact for the epitaxial source / drain region 42. The conductive feature 90 may include... Figure 37 The conductive feature 78 shown is made of the same material. In some embodiments, a pad (not shown) and / or a barrier layer (not shown) may be formed first, and the conductive material of the conductive feature 90 may be formed on the pad and / or barrier layer. A silicide layer (not shown) may be formed between each epitaxial source / drain region 42 and the conductive feature 90. Next, as Figure 38G As shown, a planarization process (e.g., CMP process) is performed to remove portions of the dielectric layer 82, the interstitial filler 86, and the conductive feature 90 formed on the interstitial filler 86 and in the dielectric layer 82. As a result, the top surface of the conductive feature 90 is substantially coplanar with the top surface of the dielectric layer 48.

[0063] Figures 39A to 44B Various views of intermediate stages in the structure of a semiconductor device according to alternative embodiments are shown. References Figure 1 The cross section defined by lines AA, BB, CC, and DD. Figure 39A , Figure 40A , Figure 41A , Figure 42A , Figure 43A and Figure 44AThe cross section along line CC is shown. Figure 39B , Figure 40B , Figure 41B , Figure 42B , Figure 43B and Figure 44B The cross-section along line BB is shown. (Example) Figure 39A and 39B As shown, an opening 84 is formed in the dielectric layer 82. In some embodiments, the opening 84 is also formed in the dielectric layer 48, for example, between adjacent gate stacks 60 and between adjacent epitaxial source / drain regions 42. Figure 40A and 40B As shown, a gap filler 86 is formed in the opening 84. Next, for example, a gap filler 86 can be formed on the dielectric layer 82 above the gate stack 60. Figure 34 The mask 77 shown exposes part of the gap filler 86 and dielectric layer 82. Figure 41A and 41B As shown, exposed portions of dielectric layer 82 and portions of dielectric layer 48 disposed therebelow are removed to form opening 88. Epitaxial source / drain regions 42 are exposed in opening 88. The removal of these portions of dielectric layers 82 and 48 can be performed using a selective etching process that substantially does not affect the spacer filler 86 and the mask. The mask can be removed after opening 88 has been formed. Since the spacer filler 86 has a different etch selectivity than the dielectric layers 82 and 48, patterning the mask to form opening 88 becomes easier.

[0064] like Figure 42A and 42B As shown, conductive features 90 are formed in the opening 88, on the gap filler 86, and on the dielectric layer 82. In some embodiments, a pad (not shown) and / or a barrier layer (not shown) may be formed first, and the conductive material of the conductive feature 90 may be formed on the pad and / or barrier layer. A silicide layer (not shown) may be formed between each epitaxial source / drain region 42 and the conductive feature 90. Next, as... Figure 43A and Figure 43B As shown, a planarization process (e.g., CMP process) is performed to remove portions of the dielectric layer 82, as well as the conductive features 90 and the interstitial filler 86, formed within the dielectric layer 82. As a result, the top surface of the conductive features 90 is substantially coplanar with the top surface of the interstitial filler 86 and the top surface of the dielectric layer 48.

[0065] In some embodiments, the interstitial filler 86 comprises a dielectric material, such as SiN, SiCN, SiCO, or other suitable dielectric materials. Subsequent processes may be performed, such as forming a dielectric layer on the dielectric layer 48, the conductive feature 90, and the interstitial filler 86, and forming a conductive feature in the dielectric layer to electrically connect with the conductive feature 90 and the gate stack 60. In some embodiments, the interstitial filler 86 comprises Si or W, and the interstitial filler 86 is removed and replaced by a dielectric filler 92, such as... Figure 44A and Figure 44B As shown in the diagram. The dielectric filler 92 may comprise the same material as the dielectric filler 80 and can be formed by the same process as the dielectric filler 80. In some embodiments, the hard mask 62 is also replaced by the dielectric filler 80, similar to... Figure 37 The process described in the text.

[0066] Figures 22 to 44B The processes described illustrate various embodiments for forming conductive contacts for epitaxial source / drain regions 42. In some embodiments, a process for forming a seamless and void-free gap filler is used. The process for forming the gap filler can be used in other stages of fabricating the semiconductor device structure 10. For example, the process can be used for metal gate dicing, dummy gate dicing, fin dicing, metal dicing, or other processes that include filling the opening. The various processes described above include forming an opening in a feature (e.g., a metal gate, dummy gate, fin, or metal) and then filling the opening with a gap filler (e.g., a dielectric material). In some embodiments, a gap filler is first formed in a first opening formed in a dielectric material, and then a portion of the dielectric material is removed by a selective etching process that substantially does not affect the gap filler to form a second opening, in which a feature is then formed.

[0067] The embodiment process advantageously forms a seamless and void-free gap fill between two conductive features (e.g., the contacts of the source / drain regions), which is produced by a reverse-cut contact process. This improves yield and reduces process complexity.

[0068] One embodiment is a method. The method includes: forming a fin from a substrate; forming a gate stack over portions of the fin; forming an epitaxial source / drain region adjacent to the gate stack; depositing a dielectric layer over the epitaxial source / drain region; forming an opening in the dielectric layer; and forming a gap filler in the opening in a bottom-up manner. The gap filler comprises Si or W. The method further includes: forming a conductive feature over the epitaxial source / drain region; and replacing the gap filler with a dielectric material.

[0069] Another embodiment is a method. The method includes: forming a fin from a substrate; forming a first gate stack over portions of the fin; forming an epitaxial source / drain region adjacent to the first gate stack; depositing a dielectric layer over the epitaxial source / drain region; forming a first opening in the dielectric layer; and forming a gap filler in the first opening. Forming the gap filler includes: depositing material in the opening; etching a portion of the material; and repeating the deposition and etching to fill the opening. The method further includes: selectively removing a portion of the dielectric layer to form a second opening; and forming a conductive feature in the second opening.

[0070] Another embodiment is a method. The method includes: forming a fin from a substrate; forming a gate stack over portions of the fin; forming an epitaxial source / drain region adjacent to the gate stack; depositing a first dielectric layer over the epitaxial source / drain region; depositing a second dielectric layer over the first dielectric layer; forming an opening in the second dielectric layer; forming a gap filler in the opening; selectively removing portions of the first dielectric layer and the second dielectric layer to expose the epitaxial source / drain region; forming a conductive feature over the epitaxial source / drain region; and removing at least a portion of the second dielectric layer and the gap filler.

[0071] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should appreciate that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments introduced herein. Those skilled in the art should also recognize that these equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

[0072] Example 1. A method for forming a semiconductor device structure, comprising:

[0073] Fins are formed from the substrate;

[0074] A gate stack is formed on some portions of the fin;

[0075] The adjacent gate stack forms an epitaxial source / drain region;

[0076] A dielectric layer is deposited on the epitaxial source / drain region;

[0077] An opening is formed in the dielectric layer;

[0078] A gap filler is formed in the opening in a bottom-up manner, wherein the gap filler comprises Si or W;

[0079] Conductive features are formed on the epitaxial source / drain regions; and

[0080] The gap filler is replaced with a dielectric material.

[0081] Example 2. The method according to Example 1, wherein the gap filler comprises Si, and forming the gap filler comprises using silane as a precursor at a processing temperature ranging from about 620 degrees Celsius to about 900 degrees Celsius.

[0082] Example 3. The method according to Example 1, wherein the gap filler comprises W, and forming the gap filler comprises using tungsten hexafluoride and hydrogen as precursors at a processing temperature ranging from about 250 degrees Celsius to about 650 degrees Celsius.

[0083] Example 4. The method according to Example 1, wherein the gap filler is formed by a low-pressure process having a processing pressure ranging from about 1 mTorr to about 100 mTorr.

[0084] Example 5. The method according to Example 4, wherein the gap filler is formed by an ion-assisted process.

[0085] Example 6. The method according to Example 1, wherein the dielectric material and the dielectric layer comprise the same material.

[0086] Example 7. The method according to Example 6 further includes: forming a contact etch stop layer over the epitaxial source / drain region, wherein the dielectric layer is formed on the contact etch stop layer.

[0087] Example 8. The method according to Example 7, wherein the opening is further formed in the contact etch stop layer.

[0088] Example 9. A method of forming a semiconductor device structure, comprising:

[0089] Fins are formed from the substrate;

[0090] A first gate stack is formed on some portions of the fin;

[0091] An epitaxial source / drain region is formed adjacent to the first gate stack;

[0092] A dielectric layer is deposited on the epitaxial source / drain region;

[0093] A first opening is formed in the dielectric layer;

[0094] Forming a gap filler in the first opening includes:

[0095] Material is deposited in the opening;

[0096] Etching a portion of the material; and

[0097] Repeat the deposition and etching to fill the opening;

[0098] Selectively removing a portion of the dielectric layer to form a second opening; and

[0099] A conductive feature is formed in the second opening.

[0100] Example 10. The method according to Example 9, wherein the gap filler comprises Si, W, SiN, SiCN or SiCO.

[0101] Example 11. The method according to Example 9 further includes: replacing the first gate stack with a second gate stack.

[0102] Example 12. The method according to Example 11 further includes: recessing the second gate stack, and forming a hard mask on the recessed second gate stack.

[0103] Example 13. The method according to Example 12, wherein the hard mask and the gap filler comprise Si or W.

[0104] Example 14. The method according to Example 13 further includes: selectively removing the hard mask and the gap filler.

[0105] Example 15. A method for forming a semiconductor device structure, comprising:

[0106] Fins are formed from the substrate;

[0107] A gate stack is formed on some portions of the fin;

[0108] The adjacent gate stack forms an epitaxial source / drain region;

[0109] A first dielectric layer is deposited on the epitaxial source / drain region;

[0110] A second dielectric layer is deposited on the first dielectric layer;

[0111] An opening is formed in the second dielectric layer;

[0112] A gap filler is formed in the opening;

[0113] Selectively remove portions of the first dielectric layer and the second dielectric layer to expose the epitaxial source / drain regions;

[0114] Conductive features are formed on the epitaxial source / drain regions; and

[0115] Remove at least a portion of the second dielectric layer and the gap filler.

[0116] Example 16. The method according to Example 15, wherein the opening is further formed in the first dielectric layer.

[0117] Example 17. The method according to Example 16, wherein the gap filler extends into the first dielectric layer.

[0118] Example 18. The method according to Example 17, wherein a planarization process is performed to remove at least a portion of the second dielectric layer and the gap filler.

[0119] Example 19. The method according to Example 18, wherein the top surface of the first dielectric layer, the top surface of the gap filler, and the top surface of the conductive feature are substantially coplanar.

[0120] Example 20. The method according to Example 15 further includes replacing the gap filler with a dielectric material.

Claims

1. A method for forming a semiconductor device structure, comprising: Fins are formed from the substrate; A gate stack is formed on some portions of the fin; The adjacent gate stack forms an epitaxial source / drain region; A dielectric layer is deposited on the epitaxial source / drain region; An opening is formed in the dielectric layer; A gap filler is formed in the opening in a bottom-up manner, wherein the gap filler comprises Si or W; Conductive features are formed on the epitaxial source / drain regions; and The gap filler is replaced with a dielectric material.

2. The method according to claim 1, wherein, The gap filler comprises Si, and forming the gap filler comprises using silane as a precursor at a processing temperature ranging from 620 degrees Celsius to 900 degrees Celsius.

3. The method according to claim 1, wherein, The gap filler includes W, and forming the gap filler includes using tungsten hexafluoride and hydrogen as precursors at a processing temperature ranging from 250 degrees Celsius to 650 degrees Celsius.

4. The method according to claim 1, wherein, The gap filler is formed by a low-pressure process having a processing pressure ranging from 1 mTorr to 100 mTorr.

5. The method according to claim 4, wherein, The gap filler is formed by an ion-assisted process.

6. The method according to claim 1, wherein, The dielectric material and the dielectric layer comprise the same material.

7. The method according to claim 6, further comprising: A contact etch stop layer is formed on the epitaxial source / drain region, wherein the dielectric layer is formed on the contact etch stop layer.

8. The method according to claim 7, wherein, The opening is also formed in the contact etch stop layer.

9. A method for forming a semiconductor device structure, comprising: Fins are formed from the substrate; A first gate stack is formed on some portions of the fin; An epitaxial source / drain region is formed adjacent to the first gate stack; A dielectric layer is deposited on the epitaxial source / drain region; A first opening is formed in the dielectric layer; Forming a gap filler in the first opening includes: Material is deposited in the opening; Etching a portion of the material; and Repeat the deposition and etching to fill the opening; Selectively removing a portion of the dielectric layer to form a second opening; and A conductive feature is formed in the second opening, wherein the conductive feature is a conductive contact for the epitaxial source / drain region.

10. The method according to claim 9, wherein, The interstitial filler includes Si, W, SiN, SiCN, or SiCO.

11. The method of claim 9, further comprising: The first gate stack is replaced with a second gate stack.

12. The method of claim 11, further comprising: The second gate stack is recessed, and a hard mask is formed on the recessed second gate stack.

13. The method according to claim 12, wherein, The hard mask and the gap filler comprise Si or W.

14. The method of claim 13, further comprising: The hard mask and the gap filler are selectively removed.

15. A method for forming a semiconductor device structure, comprising: Fins are formed from the substrate; A gate stack is formed on some portions of the fin; The adjacent gate stack forms an epitaxial source / drain region; A first dielectric layer is deposited on the epitaxial source / drain region; A second dielectric layer is deposited on the first dielectric layer; An opening is formed in the second dielectric layer; A gap filler is formed in the opening; Selectively remove portions of the first dielectric layer and the second dielectric layer to expose the epitaxial source / drain regions; Conductive features are formed on the epitaxial source / drain regions; as well as Remove at least a portion of the second dielectric layer and the gap filler.

16. The method according to claim 15, wherein, The opening is also formed in the first dielectric layer.

17. The method according to claim 16, wherein, The gap filler extends into the first dielectric layer.

18. The method according to claim 17, wherein, A planarization process is performed to remove at least a portion of the second dielectric layer and the gap filler.

19. The method according to claim 18, wherein, The top surface of the first dielectric layer, the top surface of the gap filler, and the top surface of the conductive feature are substantially coplanar.

20. The method of claim 15, further comprising: The gap filler is replaced with a dielectric material.

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