Semiconductor devices with multi-stacked carrier structures

Abstract

This disclosure provides a semiconductor device. The semiconductor device includes an intermediate dielectric layer on a substrate; a conductive pad in the intermediate dielectric layer; and a multi-stack carrier structure including a first layer on the intermediate dielectric layer, a second layer on the first layer, and a third layer on the second layer.

Description

[0001] Cross-referencing

[0002] This application claims priority to U.S. Patent Applications Nos. 17 / 561,151 and 17 / 560,548 (i.e., priority date "December 23, 2021"), the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] This disclosure relates to a semiconductor device. In particular, it relates to a semiconductor device having a multi-stacked carrier structure. Background Technology

[0004] Semiconductor components are used in a wide range of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. The size of semiconductor components continues to shrink to meet the ever-increasing demand for computing power. However, various problems arise during the miniaturization process, and these problems are constantly increasing. Therefore, challenges remain in achieving improvements in quality, yield, performance, and reliability, as well as reducing complexity.

[0005] The above description of "prior art" provides background information only and does not acknowledge that the above description of "prior art" discloses the subject matter of this disclosure. It does not constitute prior art of this disclosure, and no description of the above "prior art" should be considered part of this disclosure. Summary of the Invention

[0006] One aspect of this disclosure provides a semiconductor device, comprising: a substrate; an intermediate dielectric layer located on the substrate; a conductive pad located in the intermediate dielectric layer; and a multi-stack carrier structure. The multi-stack carrier structure includes: a first layer comprising a first passivation layer on the intermediate dielectric layer, a first insulating layer on the first passivation layer, and a first via, wherein the first via is disposed along the first passivation layer and the first insulating layer and is electrically connected to the conductive pad; a second layer on the first layer comprising a second passivation layer on the first insulating layer, a second insulating layer on the second passivation layer, and a second via, wherein the second via is disposed along the second passivation layer and the second insulating layer and is electrically connected to the first via; and a third layer on the second layer comprising a third passivation layer on the second insulating layer, a third insulating layer on the third passivation layer, and a third via, wherein the third via is disposed along the third passivation layer and the third insulating layer and is electrically connected to the second via.

[0007] Another aspect of this disclosure provides a multi-stacked carrier structure, comprising: an etch stop layer; a first layer including a first passivation layer on the etch stop layer, a first insulating layer on the first passivation layer, and a first via, wherein the first via is disposed along the first passivation layer and the first insulating layer; a second layer on the first layer including a second passivation layer on the first insulating layer, a second insulating layer on the second passivation layer, and a second via, wherein the second via is disposed along the second passivation layer and the second insulating layer and is electrically connected to the first via; and a third layer on the second layer including a third passivation layer on the second insulating layer, a third insulating layer on the third passivation layer, and a third via, wherein the third via is disposed along the third passivation layer and the third insulating layer and is electrically connected to the second via.

[0008] Another aspect of this disclosure provides a method for fabricating a semiconductor device, comprising: providing a substrate; forming an intermediate dielectric layer on the substrate; forming a conductive pad in the intermediate dielectric layer; forming a first layer on the intermediate dielectric layer, wherein the first layer includes a first passivation layer on the intermediate dielectric layer, a first insulating layer on the first passivation layer, and a first via, wherein the first via is disposed along the first passivation layer and the first insulating layer and is electrically connected to the conductive pad; forming a second layer on the first layer, wherein the second... The first layer includes a second passivation layer on the first insulating layer, a second insulating layer on the second passivation layer, and a second via, wherein the second via is disposed along the second passivation layer and the second insulating layer and is electrically connected to the first via; and a third layer is formed on the second layer, wherein the third layer includes a third passivation layer on the second insulating layer, a third insulating layer on the third passivation layer, and a third via, wherein the third via is disposed along the third passivation layer and the third insulating layer and is electrically connected to the second via. The first layer, the second layer, and the third layer together constitute a multi-stacked carrier structure.

[0009] Another aspect of this disclosure provides a method for fabricating a semiconductor device, comprising: providing a sacrificial carrier; temporarily attaching an etch stop layer to the sacrificial carrier; forming a multi-stack carrier structure on the etch stop layer, wherein the multi-stack carrier structure includes: a first layer on the etch stop layer; a second layer on the first layer; and a third layer on the second layer; providing a substrate; forming an intermediate dielectric layer on the substrate; forming a conductive pad in the intermediate dielectric layer; flipping the multi-stack carrier structure and bonding the multi-stack carrier structure to the intermediate dielectric layer; separating the sacrificial layer from the etch stop layer; and thinning the substrate.

[0010] Due to the semiconductor device design disclosed herein, the multi-stacked carrier structure can be used as a temporary carrier to assist in the substrate thinning process. Therefore, no carrier is needed during the substrate thinning process. As a result, the manufacturing cost of the semiconductor device can be reduced. Furthermore, after the thinning process, the multi-stacked carrier structure can provide electrical paths for the device components connected to the semiconductor device. Therefore, with the presence of the multi-stacked carrier structure, the performance of the semiconductor device can be easily analyzed.

[0011] The foregoing has provided a fairly broad overview of the technical features and advantages of this disclosure, thereby enabling a better understanding of the detailed description of this disclosure that follows. Other technical features and advantages forming the subject matter of the claims will be described below. Those skilled in the art to which this disclosure pertains will understand that the same purpose as this disclosure can be achieved quite readily by utilizing the concepts and specific embodiments disclosed below to modify or design other structures or processes. Those skilled in the art to which this disclosure pertains will also understand that such equivalent constructions cannot depart from the concept and scope of this disclosure as defined by the claims. Attached Figure Description

[0012] This disclosure can be read in conjunction with the following figures and detailed description for better understanding. It should be emphasized that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily enlarged or reduced.

[0013] Figure 1 A schematic cross-sectional view of a semiconductor device is shown according to an embodiment of the present disclosure.

[0014] Figure 2 A close-up cross-sectional schematic diagram of a first through-hole for fabricating a semiconductor device is shown according to an embodiment of the present disclosure.

[0015] Figures 3 to 5 A schematic cross-sectional view of a semiconductor device is shown according to some embodiments of this disclosure.

[0016] Figure 6 A method for fabricating a semiconductor device is shown in the form of a flowchart according to an embodiment of this disclosure.

[0017] Figures 7 to 21 A cross-sectional schematic diagram of the fabrication process of a semiconductor device is shown according to an embodiment of the present disclosure.

[0018] Figure 22 A cross-sectional schematic diagram of the fabrication process of a semiconductor device is shown according to another embodiment of this disclosure.

[0019] Figure 23 A method for fabricating a semiconductor element is shown in the form of a flowchart according to another embodiment of this disclosure.

[0020] Figures 24 to 32 A cross-sectional schematic diagram of the fabrication process of a semiconductor device is shown according to another embodiment of this disclosure.

[0021] Figure 33 A cross-sectional schematic diagram of the fabrication process of a semiconductor device is shown according to another embodiment of this disclosure.

[0022] Explanation of reference numerals in the attached figures:

[0023] 1A: Semiconductor components

[0024] 1B: Semiconductor components

[0025] 1C: Semiconductor components

[0026] 1D: Semiconductor components

[0027] 10: Method

[0028] 20: Method

[0029] 101: Substrate

[0030] 103: Intermediate dielectric layer

[0031] 105: Conductive pad

[0032] 200: Multi-stacked carrier structure

[0033] 203: Top passivation layer

[0034] 203O: First top opening

[0035] 205: Redistribution layer

[0036] 207: Etching Stop Layer

[0037] 207O: Second top opening

[0038] 210: First floor

[0039] 211: First passivation layer

[0040] 213: First insulating layer

[0041] 215: First through hole

[0042] 215BS: Bottom surface

[0043] 215O: First through hole opening

[0044] 215SW: Sidewall

[0045] 215TS: Top surface

[0046] 220: Second Floor

[0047] 221: Second passivation layer

[0048] 223: Second insulating layer

[0049] 225: Second through hole

[0050] 225O: Second through hole opening

[0051] 225TS: Top surface

[0052] 230: Third Floor

[0053] 231: Third passivation layer

[0054] 233: Third insulating layer

[0055] 235: Third through hole

[0056] 235O: Third through hole opening

[0057] 235TS: Top surface

[0058] 240: Fourth Floor

[0059] 241: Fourth passivation layer

[0060] 243: Fourth Insulation Layer

[0061] 245: Fourth through hole

[0062] 245TS: Top surface

[0063] 250: Fifth Floor

[0064] 251: Fifth passivation layer

[0065] 253: Fifth Insulation Layer

[0066] 255: Fifth through hole

[0067] 255TS: Top surface

[0068] 401: Sacrificial Layer

[0069] 510: First mask layer

[0070] 510O: First patterned opening

[0071] 520: Second mask layer

[0072] 520O: Second patterned opening

[0073] 530: Third mask layer

[0074] 530O: Third patterned opening

[0075] AL: Adhesion layer

[0076] BL: Barrier Layer

[0077] FL: Filler layer

[0078] IL: Isolation Layer

[0079] SL: Seed layer

[0080] S11: Steps

[0081] S13: Steps

[0082] S15: Steps

[0083] S21: Steps

[0084] S23: Steps

[0085] S25: Steps

[0086] T0: Thickness

[0087] T1: Thickness

[0088] T2: Thickness

[0089] TL: Thickness

[0090] W0: Width

[0091] W1: Width

[0092] W2: Width

[0093] W3: Width

[0094] W4: Width

[0095] W5: Width

[0096] W6: Width

[0097] W7: Width

[0098] W8: Width

[0099] W9: Width

[0100] W10: Width

[0101] WC: Width

[0102] Z: Direction Detailed Implementation

[0103] The following discloses various embodiments or examples of different components for implementing the embodiments of this disclosure. Specific examples of elements and their arrangements are described below to simplify the embodiments of this disclosure. These are merely examples and should not be construed as limiting the scope of the embodiments of this disclosure. For example, when the description refers to a first component being formed "on" or "on" a second component, it may include embodiments where the first and second components are in direct contact, or embodiments where other components are formed between them without direct contact. Furthermore, reference numerals and / or designations may be repeated in different embodiments of this disclosure. These repetitions are for simplification and clarity and are not intended to limit the relationship between the different embodiments and / or structures discussed.

[0104] Furthermore, this document uses spatially related terms such as "below," "below," "lower," "above," "higher," and similar terms to facilitate the description of the relationship between one element or component and another shown in the accompanying drawings. These spatial relation terms are used to cover different orientations of elements in use or operation, other than those depicted in the accompanying drawings. The device may be rotated to different orientations (90 degrees or other orientations), and the spatially related adjectives used therein can be interpreted in the same way.

[0105] It should be understood that when a component or layer is referred to as being "connected to" or "coupled to" another component or layer, it can be a direct connection or coupling to another component or layer, or there may be an intermediate component or layer.

[0106] It should be understood that although the terms "first," "second," etc., may be used herein to describe various elements, these elements should not be limited by these terms. Unless otherwise stated, these terms are used only to distinguish one element from another. Thus, for example, without departing from the teachings of this disclosure, a first element, first component, or first part discussed below may be referred to as a second element, second component, or second part.

[0107] Unless the context otherwise indicates, the use of terms such as “same,” “equal,” “planar,” or “coplanar” in reference to orientation, layout, location, shape, size, quantity, or other measures does not necessarily imply identical orientation, layout, location, shape, size, quantity, or other measures, but is intended to cover orientation, layout, location, shape, size, quantity, or other measures that are substantially identical, for example, due to manufacturing processes, within acceptable variations. The term “substantially” may be used in this document to reflect this meaning. For example, items described as “substantially same,” “substantially equal,” or “substantially planar” may be exactly the same, equal, or planar, or may be the same, equal, or planar, for example, due to manufacturing processes, within acceptable variations.

[0108] In this disclosure, a semiconductor element generally refers to an element that can perform a function by utilizing the properties of a semiconductor, and electro-optical elements, light-emitting display elements, semiconductor circuits, and electronic elements are all included in the category of semiconductor elements.

[0109] It should be noted that in the description of this disclosure, "above" or "up" corresponds to the direction of the arrow in the Z direction, and "below" or "down" corresponds to the direction of the arrow opposite to the Z direction.

[0110] Figure 1 A schematic cross-sectional view of semiconductor element 1A is shown according to an embodiment of the present disclosure. Figure 2 A close-up cross-sectional view of a first through-hole 215 for fabricating a semiconductor element 1A is shown according to an embodiment of the present disclosure. Figures 3 to 5 Cross-sectional schematic diagrams of semiconductor elements 1B, 1C, and 1D are shown according to some embodiments of this disclosure.

[0111] Reference Figure 1 Semiconductor element 1A may include a substrate 101, a plurality of device elements (not shown for clarity), an inter-dielectric layer 103, a plurality of conductive components, and a multi-stack carrier structure 200.

[0112] Reference Figure 1 The substrate 101 may include a bulk semiconductor substrate made entirely of at least one semiconductor material. The bulk semiconductor substrate may include, for example, elemental semiconductors such as silicon or germanium; compound semiconductors such as silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, or other group III-V compound semiconductors or group II-VI compound semiconductors, or combinations thereof.

[0113] In some embodiments, the thickness T0 of the substrate 101 may be less than about 200 μm, less than about 50 μm, or less than about 10 μm. For example, the thickness T0 of the substrate 101 may be about 3 μm.

[0114] Reference Figure 1These components can be formed on a bulk semiconductor substrate. Some portions of these components can be formed within the bulk semiconductor substrate. These components can be transistors, such as complementary metal-oxide-semiconductor transistors (CMOS), metal-oxide-semiconductor field-effect transistors (MOSFETs), fin field-effect transistors (FFETs), the like, or combinations thereof.

[0115] Reference Figure 1 An intermediate dielectric layer 103 may be disposed on a substrate 101. In some embodiments, the intermediate dielectric layer 103 may be a stacked structure. The intermediate dielectric layer 103 may include multiple insulator layers. Each of these insulator layers may have a thickness between approximately 0.5 micrometers and approximately 3.0 micrometers. These insulator layers may include, for example, silicon oxide, borosilicate glass, undoped silicate glass, fluorinated silicate glass, low-k dielectric materials, similar materials, or combinations thereof. These insulator layers may include, but are not limited to, different materials. Low-k dielectric materials may have a dielectric constant of less than 3.0 or even less than 2.5. In some embodiments, low-k dielectric materials may have a dielectric constant of less than 2.0. The fabrication techniques for these dielectric layers may include chemical vapor deposition, plasma-enhanced chemical vapor deposition, or similar techniques. A planarization process may be performed after the deposition process to remove excess material and provide a substantially flat surface for subsequent processing steps.

[0116] It should be noted that in the description of this disclosure, the term "approximately" used to modify the amount of ingredients, components, or reactants used in this disclosure refers to quantitative variations that may occur, for example, through typical measurement and liquid handling procedures used to prepare concentrates or solutions. Furthermore, variations may occur due to negligence or errors in measurement procedures, or differences in the manufacture, source, or purity of the ingredients used in the production of the composition or the implementation of the method. On one hand, the term "approximately" means within 10% of the reported value. On the other hand, the term "approximately" means within 5% of the reported value. Also, on another hand, the term "approximately" means within 10, 9, 8, 7, 6, 5, 4, 3, 2, or 1% of the reported value.

[0117] Reference Figure 1These conductive components can be disposed in the intermediate dielectric layer 103. These conductive components may include interconnect layers (not shown for clarity), conductive vias (not shown for clarity), and a plurality of conductive pads 105. The interconnect layers may be separated from each other and may be disposed horizontally in the dielectric layers along the Z direction. In this embodiment, the topmost interconnect layer may be designated as a conductive pad 105. The top surfaces of the conductive pads 105 and the top surface of the intermediate dielectric layer 103 may be substantially coplanar. The conductive vias may connect adjacent interconnect layers, adjacent component members and interconnect layers, and adjacent conductive pads 105 and interconnect layers along the Z direction. In some embodiments, the conductive vias may improve heat dissipation and provide structural support. In some embodiments, the conductive components may include, for example, tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (e.g., tantalum carbide, titanium carbide, magnesium tantalum carbide), metal nitrides (e.g., titanium nitride), transition metal aluminum nitrides, or combinations thereof. The conductive components may be formed during the formation of the dielectric layers.

[0118] In some embodiments, these components and conductive parts may together constitute a functional unit of semiconductor element 1A. In the description of this disclosure, a functional unit generally refers to a functionally related circuit that has been divided into different units for functional purposes. In some embodiments, a functional unit may typically be a highly complex circuit, such as a processor core or accelerator unit. In some other embodiments, the complexity and functionality of the functional unit may be more or less complex.

[0119] Reference Figure 1 The multi-stacked carrier structure 200 can be disposed on the intermediate dielectric layer 103. The multi-stacked carrier structure 200 may include a first layer 210, a second layer 220, a third layer 230, a fourth layer 240, a fifth layer 250, and a top passivation layer 203. In some embodiments, the thickness TL of the multi-stacked carrier structure 200 may be greater than about 500 micrometers. In some embodiments, the thickness ratio of the multi-stacked carrier structure 200 thickness TL to the thickness T0 of the substrate 101 may be between about 180:1 and about 50:1.

[0120] Reference Figure 1 The first layer 210 may be disposed on the intermediate dielectric layer 103. The first layer 210 may include a first passivation layer 211, a first insulating layer 213, and a plurality of first vias 215.

[0121] Reference Figure 1The first passivation layer 211 may be disposed on the intermediate dielectric layer 103. In some embodiments, the first passivation layer 211 may include, for example, an oxide material. In some embodiments, the first passivation layer 211 may include, for example, silicon oxide, borophosphosilicate glass, undoped silicate glass, fluorinated silicate glass, similar materials, or combinations thereof. In some embodiments, the thickness T1 of the first passivation layer 211 may be between approximately 1 μm and approximately 2 μm.

[0122] Reference Figure 1 A first insulating layer 213 may be disposed on a first passivation layer 211. In some embodiments, the first insulating layer 213 may comprise, for example, an oxide material. In some embodiments, the first insulating layer 213 may comprise the same material as the first passivation layer 211. In some embodiments, the first insulating layer 213 may comprise, for example, silicon oxide, borosilicate glass, undoped silicate glass, fluorinated silicate glass, similar materials, or combinations thereof. In some embodiments, the thickness T2 of the first insulating layer 213 may be less than about 200 μm. For example, the thickness T2 of the first insulating layer 213 may be between about 150 μm and about 190 μm.

[0123] Reference Figure 1 and Figure 2 In some embodiments, the first through holes 215 may be disposed along the first insulating layer 213 and the first passivation layer 211, disposed on the conductive pads 105, and electrically connected to the conductive pads 105 respectively and correspondingly.

[0124] For the sake of brevity, clarity and ease of description, only one first through hole 215 will be described.

[0125] In some embodiments, the sidewall 215SW of the first through-hole 215 may be tapered. The width W0 of the bottom surface 215BS of the first through-hole 215 may be smaller than the width W1 of the top surface 215TS of the first through-hole 215. In some embodiments, the first through-hole 215 may include a filler layer FL, a seed layer SL, an adhesive layer AL, a barrier layer BL, and an isolation layer IL.

[0126] It should be noted that, in the description of this disclosure, the surface of an element (or component) located at the highest vertical level along the Z direction is referred to as the top surface of the element (or component). The surface of an element (or component) located at the lowest vertical level along the Z direction is referred to as the bottom surface of the element (or component).

[0127] It should be noted that, in the description of this disclosure, "width" refers to the dimension of an element (e.g., layer, plug, groove, hole, opening, etc.) measured from one side surface to an opposite surface in a cross-sectional perspective view. Where specified, the term "thickness" may be used in place of "width".

[0128] The filler layer FL may be disposed along the first insulating layer 213 and the first passivation layer 211, and disposed on the conductive pad 105. In some embodiments, the filler layer FL may have an aspect ratio between approximately 1:2 and approximately 1:35, or between approximately 1:10 and approximately 1:25. The filler layer FL may comprise, for example, doped polycrystalline silicon, tungsten, copper, carbon nanotubes, or solder alloys.

[0129] Reference Figure 2 In some embodiments, the seed layer SL may have a U-shaped cross-sectional profile. The seed layer SL may be disposed between the filler layer FL and the first insulating layer 213, between the filler layer FL and the first passivation layer 211, and between the filler layer FL and the conductive pad 105. In some embodiments, the seed layer SL may have a thickness between approximately 10 nm and approximately 40 nm. In some embodiments, the seed layer SL may include, for example, copper. The seed layer SL may reduce the resistivity of the openings during the formation of the filler layer FL.

[0130] In some embodiments, the adhesive layer AL may have a U-shaped cross-sectional profile. The adhesive layer AL may be disposed between the seed layer SL and the first insulating layer 213, between the seed layer SL and the first passivation layer 211, and between the seed layer SL and the conductive pad 105. The seed layer SL may include, for example, titanium, tantalum, titanium, tungsten, or manganese nitride. The adhesive layer AL can improve the adhesion between the seed layer SL and the barrier layer BL.

[0131] In some embodiments, the barrier layer BL may have a U-shaped cross-sectional profile. The barrier layer BL may be located between the adhesive layer AL and the first insulating layer 213, between the adhesive layer AL and the first passivation layer 211, and between the adhesive layer AL and the conductive pad 105. The barrier layer BL may include, for example, tantalum, tantalum nitride, titanium, titanium nitride, rhenium, nickel boride, or a tantalum nitride / tantalum bilayer. The barrier layer BL may inhibit the diffusion of conductive material from the filler layer FL into the first insulating layer 213, the first passivation layer 211, or the intermediate dielectric layer 103.

[0132] In some embodiments, the isolation layer IL may be disposed between the barrier layer BL and the first insulating layer 213, and between the barrier layer BL and the first passivation layer 211. In some embodiments, the isolation layer IL may include, for example, silicon oxide, silicon nitride, silicon oxynitride, or tetraethyl orthosilicate. The isolation layer IL may have a thickness between about 50 nm and about 200 nm. In some embodiments, the isolation layer IL may include, for example, parylene, epoxy resin, or poly(p-xylene). The isolation layer IL may have a thickness between about 1 μm and about 5 μm. The isolation layer IL can ensure electrical isolation of the filler layer FL in the first insulating layer 213 and the first passivation layer 211.

[0133] Reference Figure 1 The second layer 220 can be disposed on the first layer 210. The second layer 220 may include a second passivation layer 221, a second insulating layer 223, and a plurality of second vias 225. The second passivation layer 221 can be disposed on the first insulating layer 213. The second insulating layer 223 can be disposed on the second passivation layer 221. The second vias 225 can be disposed along the second insulating layer 223 and the second passivation layer 221, disposed on the first vias 215, and electrically connected to the first vias 215 respectively and correspondingly. The second passivation layer 221, the second insulating layer 223, and the second vias 225 may each and correspondingly include the same material as the first passivation layer 211, the first insulating layer 213, and the first vias 215, and their description will not be repeated here.

[0134] Reference Figure 1 The width W2 of the top surface 225TS of the second through hole 225 can be greater than the width W1 of the top surface 215TS of the first through hole 215.

[0135] Reference Figure 1 The third layer 230 can be disposed on the second layer 220. The third layer 230 may include a third passivation layer 231, a third insulating layer 233, and a plurality of third vias 235. The third passivation layer 231 can be disposed on the second insulating layer 223. The third insulating layer 233 can be disposed on the third passivation layer 231. The third vias 235 can be disposed along the third insulating layer 233 and the third passivation layer 231, disposed on the second vias 225, and electrically connected to the second vias 225 respectively and correspondingly. The third passivation layer 231, the third insulating layer 233, and the third vias 235 may each and correspondingly include the same material as the first passivation layer 211, the first insulating layer 213, and the first vias 215, and their description will not be repeated here.

[0136] Reference Figure 1 The width W3 of the top surface 235TS of the third through hole 235 can be greater than the width W2 of the top surface 225TS of the second through hole 225.

[0137] Reference Figure 1 The fourth layer 240 may be disposed on the third layer 230. The fourth layer 240 may include a fourth passivation layer 241, a fourth insulating layer 243, and a plurality of fourth vias 245. The fourth passivation layer 241 may be disposed on the third insulating layer 233. The fourth insulating layer 243 may be disposed on the fourth passivation layer 241. The fourth vias 245 may be disposed along the fourth insulating layer 243 and the fourth passivation layer 241, disposed on the third vias 235, and electrically connected to the third vias 235 respectively and correspondingly. The fourth passivation layer 241, the fourth insulating layer 243, and the fourth vias 245 may each and correspondingly include the same material as the first passivation layer 211, the first insulating layer 213, and the first vias 215, and their description will not be repeated here.

[0138] Reference Figure 1 The width W4 of the top surface 245TS of the fourth through hole 245 can be greater than the width W3 of the top surface 235TS of the third through hole 235.

[0139] Reference Figure 1 The fifth layer 250 may be disposed on the fourth layer 240. The fifth layer 250 may include a fifth passivation layer 251, a fifth insulating layer 253, and a plurality of fifth vias 255. The fifth passivation layer 251 may be disposed on the fourth insulating layer 243. The fifth insulating layer 253 may be disposed on the fifth passivation layer 251. The fifth vias 255 may be disposed along the fifth insulating layer 253 and the fifth passivation layer 251, disposed on the fourth vias 245, and electrically connected to the fourth vias 245 respectively and correspondingly. The fifth passivation layer 251, the fifth insulating layer 253, and the fifth vias 255 may each and correspondingly include the same material as the first passivation layer 211, the first insulating layer 213, and the first vias 215, and their description will not be repeated here.

[0140] Reference Figure 1 The width W5 of the top surface 255TS of the fifth through hole 255 can be greater than the width W4 of the top surface 245TS of the fourth through hole 245.

[0141] It should be noted that, in the description of this disclosure, the number of layers of the multi-stacked carrier structure 200 is for illustrative purposes only. In other words, the multi-stacked carrier structure 200 may have more or fewer than five layers.

[0142] Reference Figure 1The top passivation layer 203 can be disposed on the topmost insulating layer (i.e., the fifth insulating layer 253 of the fifth layer 250). The top passivation layer 203 can be a single-layer structure or a multi-layer structure. In some embodiments, the top passivation layer 203 may include polybenzoxazole, polyimide, benzocyclobutene, ajinomoto buildup film, solder resist film, or similar materials, or combinations thereof. In some other embodiments, the top passivation layer 203 may be a dielectric layer. The dielectric layer may include nitrides such as silicon nitride, oxides such as silicon oxide, oxides such as silicon oxynitride, silicon nitride oxide, phosphosilicate glass, borosilicate glass, boron-doped phosphosilicate glass, similar materials, or combinations thereof.

[0143] It should be noted that, in the description of this disclosure, silicon oxynitride refers to a substance comprising silicon, nitrogen, and oxygen, wherein the proportion of oxygen is greater than the proportion of nitrogen. Silicon nitride oxide refers to a substance comprising silicon, oxygen, and nitrogen, wherein the proportion of nitrogen is greater than the proportion of oxygen.

[0144] Reference Figure 1 Multiple first top openings 203O can be provided along the top passivation layer 203 to expose the fifth vias 255 respectively and correspondingly. The exposed fifth vias 255 can be electrically coupled to probes for electrical characteristic testing.

[0145] During the thinning process of substrate 101, the multilayer stacked carrier structure 200 can serve as a temporary carrier. With the assistance of the multilayer stacked carrier structure 200, the performance of semiconductor device 1A, including substrate 101 less than 10 μm, can be analyzed. Conversely, conventional semiconductor devices including substrates less than 10 μm are covered by carriers, making it difficult to easily analyze their performance.

[0146] Reference Figure 3 The structure of semiconductor element 1B can be similar to Figure 1 The structures shown are similar. Figure 3 Zhongyu Figure 1 Identical or similar elements have been marked with similar reference symbols and repeated descriptions have been omitted.

[0147] Reference Figure 3 Multiple redistribution layers 205 may be disposed along the top passivation layer 203, disposed on the fifth vias 255, and electrically connected to the fifth vias 255 respectively and correspondingly. The redistribution layers 205 may re-route the fifth vias 255 to provide more flexible configuration and more contact area for electrical characteristic testing. The redistribution layers 205 may include, for example, tungsten, titanium, tin, nickel, copper, gold, aluminum, platinum, cobalt, or combinations thereof.

[0148] Reference Figure 4 The structure of semiconductor device 1C can be similar to Figure 1 The structures shown are similar. Figure 4 Zhongyu Figure 1 Identical or similar elements have been marked with similar reference symbols and repeated descriptions have been omitted.

[0149] Reference Figure 4 The fifth layer 250, the fourth layer 240, the third layer 230, the second layer 220, and the first layer 210 can be arranged according to... Figure 1 The multi-stacked carrier structure 200 shown is disposed on the intermediate dielectric layer 103 in reverse order. For example, a fifth insulating layer 253 is disposed on the intermediate dielectric layer 103, a fifth passivation layer 251 is disposed on the fifth insulating layer 253, a fourth insulating layer 243 is disposed on the fifth passivation layer 251, and a fourth passivation layer 241 is disposed on the fourth insulating layer 243.

[0150] Reference Figure 4 In some embodiments, the sidewall 215SW of the first through hole 215 may be tapered. The width W7 of the bottom surface 215BS of the first through hole 215 may be greater than the width W6 of the top surface 215TS of the first through hole 215.

[0151] Reference Figure 4 In some embodiments, an etch stop layer 207 may be disposed on the first insulating layer 213 of the first layer 210. In some embodiments, the etch stop layer 207 may preferably comprise a dielectric material with an etch selectivity different from that of adjacent layers. For example, the etch stop layer 207 may comprise silicon nitride, silicon carbonitride, silicon carbide, similar materials, or combinations thereof. A plurality of second top openings 207O may be disposed along the etch stop layer 207 to expose the first vias 215. The exposed first vias 215 may be electrically coupled to probes for electrical characteristic testing.

[0152] Reference Figure 5 The structure of a semiconductor device 1D can be compared with... Figure 4 The structures shown are similar. Figure 5 Zhongyu Figure 4 Identical or similar elements have been marked with similar reference symbols and repeated descriptions have been omitted.

[0153] Reference Figure 5The top passivation layer 203 may be disposed on the first insulating layer 213 of the first layer 210. The top passivation layer 203 may be a single-layer structure or a multi-layer structure. In some embodiments, the top passivation layer 203 may include polybenzoxazole, polyimide, benzocyclobutene, ajinomoto reinforcement film, solder photoresist film, or similar materials, or combinations thereof. In some other embodiments, the top passivation layer 203 may be a dielectric layer. The dielectric layer may include nitrides such as silicon nitride, oxides such as silicon oxide, oxynitride such as silicon oxynitride, silicon oxynitride oxide, phosphosilicate glass, borosilicate glass, boron-doped phosphosilicate glass, similar materials, or combinations thereof.

[0154] Reference Figure 5 The redistribution layers 205 can be disposed along the top passivation layer 203, disposed on the first vias 215, and electrically connected to the first vias 215 respectively and correspondingly. The redistribution layers 205 can redefine the first vias 215 to provide more flexible configuration and more contact area for electrical characteristic testing. The redistribution layers 205 may include, for example, tungsten, titanium, tin, nickel, copper, gold, aluminum, platinum, cobalt, or combinations thereof.

[0155] It should be noted that the terms “forming,” “formed,” and “form” can refer to and include any method of creating, building, patterning, implanting, or depositing elements, dopants, or materials. Examples of forming methods may include, but are not limited to, atomic layer deposition, chemical vapor deposition, physical vapor deposition, sputtering, co-sputtering, spin coating, diffusion, deposition, growth, implantation, photolithography, dry etching, and wet etching.

[0156] It should be noted that the functions or steps mentioned herein may appear in a different order than that shown in the accompanying drawings, depending on the functions or steps involved. For example, two drawings shown consecutively may actually be performed simultaneously or sometimes in reverse order.

[0157] Figure 6 A method 10 for fabricating a semiconductor element 1A is shown in flowchart form according to an embodiment of the present disclosure. Figures 7 to 21 A cross-sectional schematic diagram showing the fabrication process of semiconductor element 1A according to an embodiment of the present disclosure.

[0158] Reference Figure 6 and Figure 7 In step S11, a substrate 101 can be provided, and an intermediate dielectric layer 103 can be formed on the substrate 101.

[0159] Reference Figure 7 The material of substrate 101 is as follows Figure 1 As shown, its description will not be repeated here. In some embodiments, substrate 101 may include a semiconductor-on-insulator structure, which includes, from bottom to top, a processing substrate, an insulating layer, and a topmost semiconductor material layer. The processing substrate and the topmost semiconductor material layer may include the same materials as the bulk semiconductor substrate described above. The insulating layer may be a crystalline or amorphous dielectric material, such as oxides and / or nitrides. For example, the insulating layer may be a dielectric oxide, such as silicon oxide. Another example is that the insulating layer may be a dielectric nitride, such as silicon nitride or boron nitride. Yet another example is that the insulating layer may include a stack of dielectric oxides and dielectric nitrides, such as a stack of silicon oxide and silicon nitride or boron nitride in any order. The insulating layer may have a thickness between approximately 10 nm and approximately 200 nm. It should be noted that at this stage, the thickness T0 of substrate 101 may be greater than 700 μm or greater than 500 μm.

[0160] Reference Figure 7 Fabrication techniques for forming the intermediate dielectric layer 103 on the substrate 101 may include deposition processes such as chemical vapor deposition. Planarization processes such as chemical mechanical polishing may be performed to provide a substantially flat surface for subsequent process steps. Components (not shown for clarity) and conductive parts (not shown for clarity) may be formed during the formation of the intermediate dielectric layer 103. Fabrication techniques for forming the conductive pads 105 in the intermediate dielectric layer 103 may include, for example, damascene processes. The top surfaces of the conductive pads 105 and the top surface of the intermediate dielectric layer 103 may be substantially coplanar.

[0161] Reference Figure 6 and Figures 8 to 19 In step S13, a multi-stacked carrier structure 200 can be formed on the intermediate dielectric layer 103.

[0162] Reference Figure 8 A first passivation layer 211 can be formed on the intermediate dielectric layer 103, and the fabrication technique for the third passivation layer 231 can include, for example, chemical vapor deposition, plasma-assisted chemical vapor deposition, or other applicable deposition processes. In some embodiments, an oxide bonding process can be performed to form a first insulating layer 213 on the first passivation layer 211. The material of the first passivation layer 211 is as follows: Figure 1As shown, its description will not be repeated here.

[0163] Reference Figure 9 A first mask layer 510 can be formed on the first insulating layer 213. The first mask layer 510 may include a plurality of first patterned openings 510O, which define the locations of the first vias 215. The first patterned openings 510O may have a width W8. The width W8 of the first patterned openings 510O may be greater than the width WC of the conductive pad 105.

[0164] Reference Figure 10 The first mask layer 510 can be used as a pattern guide for an oxide etching process to remove a portion of the first insulating layer 213 and a portion of the first passivation layer 211, while simultaneously forming a plurality of first via openings 215O. In some embodiments, the sidewalls of these first via openings 215O may be tapered. After the oxide etching process, the first mask layer 510 can be removed.

[0165] Reference Figure 11 The fabrication techniques for forming the first vias 215 in the first via openings 215O may include, for example, chemical vapor deposition, physical vapor deposition, evaporation, sputtering, electroplating, or combinations thereof. Planarization processes such as chemical mechanical polishing may be performed to remove excess material and provide a substantially flat surface for subsequent processing steps. The materials and structures of the first vias 215 are as follows: Figure 1 and Figure 2 As shown, its description will not be repeated here. The first passivation layer 211, the first insulating layer 213, and the first through holes 215 together constitute the first layer 210.

[0166] Reference Figure 12 A second passivation layer 221 can be formed on the first insulating layer 213, a second insulating layer 223 can be formed on the second passivation layer 221, and a second mask layer 520 can be formed on the second insulating layer 223. The materials of the second passivation layer 221 and the second insulating layer 223 are as follows: Figure 1 As shown, its description will not be repeated here. It can be achieved through... Figures 8 to 11 The first layer 210 shown is formed using similar steps to form the second passivation layer 221, the second insulating layer 223, and the second mask layer 520, and their description will not be repeated here. The second mask layer 520 may include a plurality of second patterned openings 520O, which define the locations of the second vias 225. The width W9 of the second patterned openings 520O may be greater than the width W8 of the first patterned openings 510O.

[0167] Reference Figure 13The second mask layer 520 can be used as a pattern guide for an oxide etching process to remove a portion of the second insulating layer 223 and a portion of the second passivation layer 221, while simultaneously forming a plurality of second via openings 225O. In some embodiments, the sidewalls of these second via openings 225O may be tapered. After the oxide etching process, the second mask layer 520 can be removed.

[0168] Reference Figure 14 The second vias 225 can be formed in the second via openings 225O using a process similar to that used for the first vias 215, and will not be described again here. A planarization process, such as chemical mechanical polishing, can be performed to remove excess material and provide a substantially flat surface for subsequent processing steps. The second passivation layer 221, the second insulating layer 223, and the second vias 225 together constitute the second layer 220.

[0169] The greater width of the second patterned opening 520O can be transferred to the second via opening 225O, and then inherited by the second via 225. The greater width of the second via 225 can provide a larger tolerance window for subsequent photolithography processes (e.g., photolithography of the third via 235). As a result, the yield of semiconductor device 1A can be improved.

[0170] Reference Figure 15 A third passivation layer 231 can be formed on the second insulating layer 223, a third insulating layer 233 can be formed on the third passivation layer 231, and a third mask layer 530 can be formed on the third insulating layer 233. The materials of the third passivation layer 231 and the third insulating layer 233 are as follows: Figure 1 As shown, its description will not be repeated here. It can be achieved through... Figures 8 to 11 The first layer 210 shown is formed using similar steps to form the third passivation layer 231, the third insulating layer 233, and the third mask layer 530, and their description will not be repeated here. The third mask layer 530 may include a plurality of third patterned openings 530O, which define the locations of the third vias 235. The width W10 of the third patterned opening 530O may be greater than the width W9 of the second patterned opening 520O.

[0171] Reference Figure 16 The third mask layer 530 can be used as a pattern guide for an oxide etching process to remove a portion of the third insulating layer 233 and a portion of the third passivation layer 231, while simultaneously forming a plurality of third via openings 235O. In some embodiments, the sidewalls of these third via openings 235O may be tapered. After the oxide etching process, the third mask layer 530 can be removed.

[0172] Reference Figure 17The third through-holes 235 can be formed in the third through-hole openings 235O through steps similar to those for the first through-holes 215, and will not be described again here. A planarization process such as chemical mechanical polishing can be performed to remove excess material and provide a substantially flat surface for subsequent processing steps. The third passivation layer 231, the third insulating layer 233, and the third through-holes 235 together constitute the third layer 230.

[0173] It should be noted that the third via 235 appears to be offset from the second via 225 along the Z direction to emphasize the benefit of the larger tolerance window of the photolithography process obtained through the wider width of the second via 225. That is, even if the alignment of the photolithography process is misaligned, the vias 225 and 235 can still be electrically connected normally.

[0174] Reference Figure 18 It can be done by... Figures 8 to 11 The steps of the first layer 210 shown are similar to those for forming the fourth layer 240 and the fifth layer 250, which will not be described again here.

[0175] Reference Figure 19 A top passivation layer 203 can be formed on the fifth layer 250. The fabrication technique for the top passivation layer 203 can include, for example, spin coating, lamination, deposition, or similar techniques. Deposition can include chemical vapor deposition. The material of the top passivation layer 203 is such as... Figure 1 As shown, its description will not be repeated here. Layers 210, 220, 230, 240, 250 and the top passivation layer 203 together constitute the multi-stacked carrier structure 200.

[0176] In some embodiments, prior to the thinning process of substrate 101, the thickness ratio of the thickness TL of the multi-stacked carrier structure 200 to the thickness T0 of substrate 101 may be between approximately 5:7 and approximately 1:, or between approximately 1:1 and approximately 7:5.

[0177] Reference Figure 6 , Figure 20 ,and Figure 21 In step S15, the substrate 101 can be thinned and a plurality of first top openings 203O can be formed along the top passivation layer 203 of the multi-stacked carrier structure 200.

[0178] Reference Figure 20 The substrate 101 can be thinned using wafer grinding, mechanical abrasion, polishing, or similar techniques, or using a thinning process such as wet etching or chemical removal. It should be noted that no carrier is required during the thinning process. A multi-stacked carrier structure 200 can be used as a temporary carrier to assist in the thinning process of the substrate 101.

[0179] Reference Figure 20 After the thinning process, the thickness ratio of the multilayer stacked carrier structure 200 to the thickness T0 of the substrate 101 can be between approximately 180:1 and approximately 50:1.

[0180] Reference Figure 21 The first top openings 203O can be formed along the top passivation layer 203 to expose the fifth vias 255 respectively and correspondingly. The exposed fifth vias 255 can be electrically coupled to probes for electrical characteristic testing. That is, the performance of the semiconductor device 1A after substrate thinning can be easily analyzed.

[0181] Figure 22 A cross-sectional schematic diagram of the fabrication process of semiconductor element 1B is shown according to another embodiment of this disclosure.

[0182] Reference Figure 22 The structure of semiconductor element 1B can be similar to Figure 21 The structures shown are similar. Figure 22 Zhongyu Figure 21 Identical or similar elements have been marked with similar reference symbols and repeated descriptions have been omitted.

[0183] In semiconductor device 1B, the redistribution layers 205 can be formed respectively and correspondingly on the fifth vias 255. In some embodiments, the formation of the redistribution layers 205 may include forming one or more insulating layers (i.e., top passivation layers 203) and forming conductive components (i.e., the redistribution layers 205) in the insulating layers using any suitable method (e.g., spin coating, sputtering, or similar techniques). The formation of the conductive components may include patterning the insulating layer (e.g., using photolithography and / or etching processes) and forming the conductive components in the patterned insulating layer (e.g., defining the shape of the conductive components using a mask layer and depositing a seed layer using an electroless / electrochemical plating process). For example, the first top openings 203O may define the pattern of the redistribution layers 205. The redistribution layers 205 may be formed in the first top openings 203O.

[0184] Figure 23 A method 20 for fabricating a semiconductor element 1C is shown in flowchart form according to another embodiment of this disclosure. Figures 24 to 32 A cross-sectional schematic diagram of the fabrication process of a semiconductor element 1C is shown according to another embodiment of this disclosure.

[0185] Reference Figures 23 to 27 In step S21, a sacrificial carrier 401 can be provided, and a multi-stacked carrier structure 200 can be temporarily formed on the sacrificial carrier 401.

[0186] Reference Figure 24 An etch stop layer 207 can be formed on the sacrificial carrier 401. Generally, the etch stop layer 207 can provide a mechanism to stop the etching process during the formation of conductive components. The etch stop layer 207 can preferably comprise a dielectric material with an etch selectivity different from that of adjacent layers. For example, the etch stop layer 207 can comprise silicon nitride, silicon carbonitride, silicon carbide, or similar materials, and can be deposited by chemical vapor deposition or plasma-assisted chemical vapor deposition.

[0187] Reference Figure 24 The fabrication technique for forming a first insulating layer 213 on the etch stop layer 207 can include deposition processes such as chemical vapor deposition or plasma-assisted chemical vapor deposition. The material of the first insulating layer 213 is such as... Figure 1 As shown, its description will not be repeated here. A first mask layer 510 may be formed on the first insulating layer 213. The first mask layer 510 may include a pattern that defines the positions of a plurality of first vias 215.

[0188] Reference Figure 25 The first mask layer 510 can be used as a pattern guide for an oxide etching process to remove a portion of the first insulating layer 213 and simultaneously form the first via openings 215O. A portion of the etch stop layer 207 can be exposed through these first via openings 215O. During the oxide etching process, the etch rate ratio of the first insulating layer 213 to the etch stop layer 207 can be between approximately 100:1 and approximately 1.05:1, between approximately 15:1 and approximately 2:1, or between approximately 10:1 and approximately 2:1. The first mask layer 510 can be removed after the oxide etching process.

[0189] Reference Figure 26 Multiple first through-holes 215 can be formed in the openings 215O of ​​these first through-holes. A planarization process, such as chemical mechanical polishing, can be performed until the top surface of the first insulating layer 213 is exposed to remove excess material and provide a substantially flat surface for subsequent processing steps. The material of the first through-holes 215 is as follows: Figure 1 As shown, its description will not be repeated here. The first insulating layer 213 and the first through holes 215 together constitute the first layer 210.

[0190] Reference Figure 27 It can be done through something like Figures 12 to 19The steps shown form the second layer 220, the third layer 230, the fourth layer 240, and the fifth layer 250, which will not be described again here. The first layer 210, the second layer 220, the third layer 230, the fourth layer 240, the fifth layer 250, and the etch stop layer 207 together constitute the multi-stacked carrier structure 200.

[0191] Reference Figure 23 , Figure 28 ,and Figure 29 In step S23, a substrate 101 can be provided, an intermediate dielectric layer 103 can be formed on the substrate 101, a plurality of conductive pads 105 can be formed in the intermediate dielectric layer 103, and a plurality of stacked carrier structures 200 can be bonded to the intermediate dielectric layer 103.

[0192] Reference Figure 28 It can be done by... Figure 1 and Figure 7 The steps shown are similar to those used to form the substrate 101, the intermediate dielectric layer 103, and the conductive pads 105, and will not be described again here.

[0193] Reference Figure 29 The multi-stacked carrier structure 200 can be flipped and bonded to the intermediate dielectric layer 103. In some embodiments, the multi-stacked carrier structure 200 can be bonded to the intermediate dielectric layer 103 using a hybrid bonding process. In some embodiments, the hybrid bonding process can include, for example, thermo-compression bonding, passivation-capping-layer assisted bonding, or surface activation bonding. In some embodiments, the process pressure of the hybrid bonding process can be between about 100 MPa and about 150 MPa. In some embodiments, the process temperature of the hybrid bonding process can be between about room temperature (e.g., 25°C) and about 400°C. In some embodiments, surface treatments (such as wet chemical cleaning and gas / vapor phase heat treatment) can be used to reduce the process temperature of the hybrid bonding process or shorten the time consumption of the hybrid bonding process. In some embodiments, the hybrid bonding process can include, for example, dielectric-to-dielectric bonding, metal-to-metal bonding, and metal-to-dielectric bonding. In some embodiments, a thermal annealing process may be performed after the bonding process to enhance dielectric-to-dielectric bonding and cause thermal expansion of the metal-to-metal bonding, thereby further improving the bonding quality.

[0194] Reference Figure 30Prior to the thinning process of substrate 101, in some embodiments, the thickness ratio of the thickness TL of the multi-stacked carrier structure 200 to the thickness T0 of substrate 101 may be between approximately 5:7 and approximately 1:1, or between approximately 1:1 and approximately 7:5.

[0195] Reference Figure 23 and Figures 30 to 32 In step S25, the sacrificial carrier 401 can be separated, the substrate 101 can be thinned, and a plurality of second top openings 207O can be formed along the etch stop layer 207 of the multi-stacked carrier structure 200.

[0196] like Figure 30 As shown, the sacrificial carrier 401 can be separated from the etch stop layer 207.

[0197] Reference Figure 31 The substrate 101 can be thinned using wafer grinding, mechanical abrasion, polishing, or similar techniques, or using a thinning process such as wet etching or chemical removal. It should be noted that no carrier is required during the thinning process. A multi-stacked carrier structure 200 can be used as a temporary carrier to assist in the thinning process of the substrate 101.

[0198] Reference Figure 31 After the thinning process of substrate 101, the thickness ratio of the thickness TL of the multi-stacked carrier structure 200 to the thickness T0 of substrate 101 can be between approximately 180:1 and approximately 50:1.

[0199] Reference Figure 32 Multiple second top openings 207O can be formed along the etch stop layer 207 to expose the first vias 215 respectively and correspondingly. The exposed first vias 215 can be electrically coupled to probes for electrical characteristic testing. That is, the performance of the semiconductor device 1C after the substrate has been thinned can be easily analyzed.

[0200] Figure 33 A cross-sectional schematic diagram of the fabrication process of a semiconductor device 1D is shown according to another embodiment of this disclosure.

[0201] Reference Figure 33 The structure of a semiconductor device 1D can be compared with... Figure 31 The structures shown are similar. Figure 33 Zhongyu Figure 31 Identical or similar elements have been marked with similar reference symbols and repeated descriptions have been omitted.

[0202] In semiconductor device 1D, the etch stop layer 207 can be completely removed. This can be achieved through methods similar to... Figure 19The steps shown form a top passivation layer 203 on the first layer 210, and their description will not be repeated here. Multiple redistribution layers 205 can be formed along the top passivation layer 203 and respectively and correspondingly formed on the first vias 215. These redistribution layers 205 can redefine the first vias 215 to provide more flexible configuration and more contact area for electrical characteristic testing. The material of these redistribution layers 205 is as follows... Figure 3 As shown, its description will not be repeated here.

[0203] One aspect of this disclosure provides a semiconductor device, comprising: a substrate; an intermediate dielectric layer located on the substrate; a conductive pad located in the intermediate dielectric layer; and a multi-stack carrier structure. The multi-stack carrier structure includes: a first layer comprising a first passivation layer on the intermediate dielectric layer, a first insulating layer on the first passivation layer, and a first via, wherein the first via is disposed along the first passivation layer and the first insulating layer and is electrically connected to the conductive pad; a second layer on the first layer comprising a second passivation layer on the first insulating layer, a second insulating layer on the second passivation layer, and a second via, wherein the second via is disposed along the second passivation layer and the second insulating layer and is electrically connected to the first via; and a third layer on the second layer comprising a third passivation layer on the second insulating layer, a third insulating layer on the third passivation layer, and a third via, wherein the third via is disposed along the third passivation layer and the third insulating layer and is electrically connected to the second via.

[0204] Another aspect of this disclosure provides a multi-stacked carrier structure, comprising: an etch stop layer; a first layer including a first passivation layer on the etch stop layer, a first insulating layer on the first passivation layer, and a first via, wherein the first via is disposed along the first passivation layer and the first insulating layer; a second layer on the first layer including a second passivation layer on the first insulating layer, a second insulating layer on the second passivation layer, and a second via, wherein the second via is disposed along the second passivation layer and the second insulating layer and is electrically connected to the first via; and a third layer on the second layer including a third passivation layer on the second insulating layer, a third insulating layer on the third passivation layer, and a third via, wherein the third via is disposed along the third passivation layer and the third insulating layer and is electrically connected to the second via.

[0205] Another aspect of this disclosure provides a method for fabricating a semiconductor device, comprising: providing a substrate; forming an intermediate dielectric layer on the substrate; forming a conductive pad in the intermediate dielectric layer; forming a first layer on the intermediate dielectric layer, wherein the first layer includes a first passivation layer on the intermediate dielectric layer, a first insulating layer on the first passivation layer, and a first via, wherein the first via is disposed along the first passivation layer and the first insulating layer and is electrically connected to the conductive pad; forming a second layer on the first layer, wherein the second... The first layer includes a second passivation layer on the first insulating layer, a second insulating layer on the second passivation layer, and a second via, wherein the second via is disposed along the second passivation layer and the second insulating layer and is electrically connected to the first via; and a third layer is formed on the second layer, wherein the third layer includes a third passivation layer on the second insulating layer, a third insulating layer on the third passivation layer, and a third via, wherein the third via is disposed along the third passivation layer and the third insulating layer and is electrically connected to the second via. The first layer, the second layer, and the third layer together constitute a multi-stacked carrier structure.

[0206] Another aspect of this disclosure provides a method for fabricating a semiconductor device, comprising: providing a sacrificial carrier; temporarily attaching an etch stop layer to the sacrificial carrier; forming a multi-stack carrier structure on the etch stop layer, wherein the multi-stack carrier structure includes: a first layer on the etch stop layer; a second layer on the first layer; and a third layer on the second layer; providing a substrate; forming an intermediate dielectric layer on the substrate; forming a conductive pad in the intermediate dielectric layer; flipping the multi-stack carrier structure and bonding the multi-stack carrier structure to the intermediate dielectric layer; separating the sacrificial layer from the etch stop layer; and thinning the substrate.

[0207] Due to the design of the semiconductor device disclosed herein, the multi-stacked carrier structure 200 can be used as a temporary carrier to assist in the thinning process of the substrate 101. Therefore, no carrier is required during the thinning process of the substrate 101. As a result, the manufacturing cost of the semiconductor device 1A can be reduced. Furthermore, after the thinning process, the multi-stacked carrier structure 200 can provide an electrical path for the device components connected to the semiconductor device 1A. Therefore, with the presence of the multi-stacked carrier structure 200, the performance of the semiconductor device 1A can be easily analyzed.

[0208] While this disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alternatives can be made without departing from the concept and scope of this disclosure as defined in the claims. For example, many of the processes described above can be implemented using different methods, and other processes or combinations thereof can be substituted for many of the processes described above.

[0209] Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machinery, manufacturing, material compositions, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure of this publication that existing or future processes, machinery, manufacturing, material compositions, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used based on this disclosure. Accordingly, such processes, machinery, manufacturing, material compositions, means, methods, or steps are included within the scope of the claims of this application.

Claims

1. A semiconductor element, comprising: One substrate; An intermediate dielectric layer is located on the substrate; A conductive pad is located in the intermediate dielectric layer; as well as A multi-stacked carrier structure, including: A first layer includes a first passivation layer located on the intermediate dielectric layer, a first insulating layer located on the first passivation layer, and a first via, wherein the first via is disposed along the first passivation layer and the first insulating layer and is electrically connected to the conductive pad; A second layer, located on the first layer and including a second passivation layer on the first insulating layer, a second insulating layer on the second passivation layer, and a second through-hole, wherein the second through-hole is disposed along the second passivation layer and the second insulating layer and is electrically connected to the first through-hole; and A third layer, located on the second layer, includes a third passivation layer on the second insulating layer, a third insulating layer on the third passivation layer, and a third via, wherein the third via is disposed along the third passivation layer and the third insulating layer and is electrically connected to the second via, the second via having a conductive filler layer, wherein a top surface of the filler layer is coplanar with a top surface of the second insulating layer, and a bottom surface of the third via is at least partially outside a vertical projection region of one of the top surfaces of the second via.

2. The semiconductor device of claim 1, wherein the thickness of the multi-stacked carrier structure is greater than 500 micrometers.

3. The semiconductor device of claim 2, wherein the thickness of the first insulating layer is less than 200 micrometers.

4. The semiconductor device of claim 2, wherein the thickness of the first passivation layer is between 1 micrometer and 2 micrometers.

5. The semiconductor element of claim 2, wherein the width of a top surface of the first via is smaller than the width of the top surface of the second via.

6. The semiconductor element of claim 2, wherein the width of the top surface of the second via is smaller than the width of the top surface of the third via.

7. The semiconductor device of claim 2, wherein the thickness of the substrate is less than 200 micrometers.

8. The semiconductor device of claim 2, wherein the thickness of the substrate is less than 5 micrometers.

9. The semiconductor device of claim 2, wherein the first passivation layer comprises an oxide material.

10. The semiconductor device of claim 1, wherein the first insulating layer comprises an oxide material.

11. The semiconductor device of claim 2, further comprising a top passivation layer located on the third insulating layer of the third layer.

12. The semiconductor device of claim 11, further comprising a first top opening disposed along the top passivation layer to expose the third via.

13. The semiconductor device of claim 1, wherein the thickness ratio of the thickness of the multi-stacked carrier structure to the thickness of the substrate is between 180:1 and 50:

1.

14. The semiconductor element of claim 1, wherein one sidewall of the first via is tapered and the width of a top surface of the first via is greater than the width of a bottom surface of the first via.

15. The semiconductor device of claim 1, wherein the first via includes a filler layer and an isolation layer, wherein the filler layer of the first via is disposed along the first insulating layer and the first passivation layer and is located on the conductive pad, and the isolation layer is located between the filler layer and the first insulating layer and between the filler layer and the first passivation layer.

16. The semiconductor device of claim 15, wherein the first via includes a barrier layer located between the filler layer and the isolation layer and between the filler layer and the conductive pad.

17. The semiconductor device of claim 16, wherein the first via includes an adhesion layer located between the filler layer and the barrier layer.

18. The semiconductor device of claim 17, wherein the first via includes a sublayer located between the filler layer and the adhesive layer.

19. The semiconductor device of claim 1, wherein the multi-stack carrier structure includes a redistribution layer located on the third via and electrically coupled to the conductive pad through the third via, the second via, and the first via.

20. A multi-stacked carrier structure, comprising: One etch stop layer; A first layer includes a first passivation layer on the etch stop layer, a first insulating layer on the first passivation layer, and a first via, wherein the first via is disposed along the first passivation layer and the first insulating layer; A second layer, located on the first layer and including a second passivation layer on the first insulating layer, a second insulating layer on the second passivation layer, and a second through-hole, wherein the second through-hole is disposed along the second passivation layer and the second insulating layer and is electrically connected to the first through-hole; and A third layer, located on the second layer, includes a third passivation layer on the second insulating layer, a third insulating layer on the third passivation layer, and a third via, wherein the third via is disposed along the third passivation layer and the third insulating layer and is electrically connected to the second via, the second via having a conductive filler layer, wherein a top surface of the filler layer is coplanar with a top surface of the second insulating layer, and a bottom surface of the third via is at least partially outside a vertical projection region of one of the top surfaces of the second via.

21. The multi-stacked carrier structure of claim 20, wherein the thickness of the multi-stacked carrier structure is greater than 500 micrometers.

22. The multi-stacked carrier structure of claim 20, wherein the thickness of the first insulating layer is less than 200 micrometers.

23. The multi-stacked carrier structure of claim 20, wherein the thickness of the first passivation layer is between 1 micrometer and 2 micrometers.

24. The multi-stack carrier structure of claim 20, wherein the width of a top surface of the first through hole is smaller than the width of the top surface of the second through hole.

25. The multi-stack carrier structure of claim 20, wherein the width of the top surface of the second through hole is less than the width of the top surface of the third through hole.

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