Semiconductor structure and its formation method
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SEMICON MFG INT (SHANGHAI) CORP
- Filing Date
- 2021-12-23
- Publication Date
- 2026-05-26
AI Technical Summary
Existing embedded power line technology suffers from problems such as high contact resistance and difficulty in selective material growth in semiconductor structures, especially the inhomogeneity of titanium thin film layers and the adverse effects of chlorine corrosion on device performance.
Selective growth processes are employed to form the contact layer and barrier layer, including atomic layer deposition (ALD). Tungsten hexafluoride and hydrogen are used to form the tungsten contact layer and tungsten nitride barrier layer, avoiding the formation of the titanium nitride layer and improving the filling capacity of the contact holes and the quality of the conductive layer.
It reduces contact resistance, improves the adhesion between the contact layer and the conductive layer, reduces the risk of corrosion to the dielectric layer, and enhances the electrical performance of the semiconductor structure.
Smart Images
Figure CN116344536B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the same. Background Technology
[0002] As semiconductor chip miniaturization technology advances, it becomes increasingly difficult to miniaturize transistors in the front-end-of-line (FEOL) process and to improve contacts and wiring in the middle-of-line (MOL) and back-end-of-line (BEOL) processes.
[0003] Power lines are part of the power supply network and are traditionally implemented in the back-end processing layers of the chip (i.e., the Mint and M1 metal layers). Buried power rails (BPRs), embedded within the chip and formed in the front-end processing, help free up interconnect wiring resources, reduce the area of standard cell-level circuits, and facilitate track height miniaturization. In the prior art, a tungsten-based buried power rail has been proposed, which is connected to a ruthenium-based contact layer (via buried power rail, VBPR) for electrical connection to ruthenium metal lines on the source / drain layer surface. This structure achieves excellent resistance and electromigration performance.
[0004] However, existing embedded power cable technology needs further improvement. Summary of the Invention
[0005] The technical problem solved by this invention is to provide a semiconductor structure and a method for forming the same, so as to improve the performance of semiconductor structures.
[0006] To address the aforementioned technical problems, the present invention provides a semiconductor structure comprising: a substrate, the substrate including a base, a fin located on the surface of the base and an isolation layer, and a buried power line, wherein the fin has a source / drain layer, the top surface of the buried power line is lower than the top surface of the source / drain layer, and the bottom of the buried power line extends into the base, the isolation layer is also located on the surface of the buried power line and a portion of the sidewall of the fin, and exposes the source / drain layer; a dielectric layer located on the surface of the source / drain layer and the isolation layer; an opening located within the dielectric layer and a contact hole located at the bottom of the opening, the opening exposing the top surface of the source / drain layer, the contact hole being also located within the isolation layer and exposing the top surface of the buried power line; a contact layer located within the contact hole; a barrier layer located on the surface of the dielectric layer exposed by the opening; and a conductive layer on the surface of the barrier layer located within the opening, the conductive layer being also located on the top surface of the source / drain layer exposed by the opening.
[0007] Optionally, it may also include: an etch stop layer located on the surface of the isolation layer and a portion of the source / drain layer surface, the opening exposing the top surface of the source / drain layer.
[0008] Accordingly, the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including a base, a fin and an isolation layer located on the surface of the base, and a buried power line, wherein the fin has a source / drain layer, the top surface of the buried power line is lower than the top surface of the source / drain layer, and the bottom of the buried power line extends into the base, the isolation layer is also located on the surface of the buried power line and a portion of the sidewall of the fin, and exposes the source / drain layer; forming a dielectric layer on the surface of the source / drain layer and the isolation layer; forming an opening and a contact hole located at the bottom of the opening in the dielectric layer, the opening exposing the top surface of the source / drain layer, and the contact hole is also located in the isolation layer to expose the top surface of the buried power line; forming a contact layer on the surface of the buried power line exposed by the contact hole using a first selective growth process; forming a barrier layer on the surface of the dielectric layer exposed by the opening after forming the contact layer; and forming a conductive layer in the opening after forming the barrier layer.
[0009] Optionally, before forming the dielectric layer, an initial etch stop layer is formed on the surface of the source / drain layer and the isolation layer; the opening exposes the initial etch stop layer on the top surface of the source / drain layer; after forming the contact layer and before forming the barrier layer, the initial etch stop layer on the top surface of the source / drain layer is removed to form an etch stop layer, thereby exposing the top surface of the source / drain layer.
[0010] Optionally, the material of the contact layer includes tungsten.
[0011] Optionally, the first selective growth process includes atomic layer deposition or chemical vapor deposition.
[0012] Optionally, the process parameters of the first selective growth process include: the reaction gases include tungsten hexafluoride and hydrogen, the flow rate of tungsten hexafluoride is in the range of 10 sccm to 500 sccm, the flow rate of hydrogen is in the range of 1000 sccm to 10000 sccm, the gas pressure is in the range of 3 Torr to 100 Torr, and the reaction temperature is in the range of 200°C to 450°C.
[0013] Optionally, the barrier layer is formed using a second selective growth process.
[0014] Optionally, the material of the barrier layer includes tungsten nitride.
[0015] Optionally, the second selective growth process includes an atomic layer deposition process.
[0016] Optionally, the process parameters of the second selective growth process include: the reaction gas includes hydrogen or ammonia, the precursor includes bis(tert-butylimino)bis(dimethylamino)tungsten, the hydrogen flow rate ranges from 50 sccm to 5000 sccm, the ammonia flow rate ranges from 50 sccm to 5000 sccm, the gas pressure ranges from 3 Torr to 100 Torr, and the reaction temperature ranges from 200°C to 400°C.
[0017] Optionally, the conductive layer may be made of a metal, including tungsten or cobalt.
[0018] Optionally, the conductive layer is formed using an atomic layer deposition process.
[0019] Optionally, the conductive layer is made of tungsten.
[0020] Optionally, the process parameters for forming the conductive layer include: the reaction gases include tungsten hexafluoride and hydrogen, the flow rate of tungsten hexafluoride is in the range of 10 sccm to 500 sccm, the flow rate of hydrogen is in the range of 1000 sccm to 10000 sccm, the gas pressure is in the range of 3 Torr to 50 Torr, and the reaction temperature is in the range of 300℃ to 500℃.
[0021] Optionally, the aspect ratio of the opening is in the range of 3 to 14; the aspect ratio of the contact hole is in the range of 3 to 14.
[0022] Optionally, the thickness of the barrier layer ranges from 1 nm to 3 nm.
[0023] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects:
[0024] In the semiconductor structure formation method provided by the present invention, the contact layer can be selectively grown on the surface of the buried power line, which is beneficial to improving the filling ability of the contact hole. At the same time, it is not necessary to form a titanium nitride layer on the surface of the contact hole, thus avoiding the adverse effects of titanium nitride material on contact resistance. This is beneficial to improving the contact resistance between the conductive layer and the contact layer, and between the contact layer and the buried power line. In addition, the selective growth of the contact layer on the surface of the buried power line can improve the adhesion between the contact layer and the power line.
[0025] Furthermore, the barrier layer is formed using a second selective growth process, which ensures that the barrier layer is formed only on the surface of the dielectric layer exposed by the opening, reducing material deposition on the surface of the contact layer. This improves the quality of the conductive layer while reducing adverse effects on the contact resistance between the contact layer and the conductive layer. In addition, when the conductive layer is made of tungsten, the barrier layer can also protect the dielectric layer from erosion by tungsten hexafluoride during the formation of the tungsten conductive layer. Attached Figure Description
[0026] Figures 1 to 3 This is a schematic cross-sectional view of the semiconductor structure formation process;
[0027] Figures 4 to 8 This is a cross-sectional schematic diagram of the semiconductor structure formation process according to an embodiment of the present invention. Detailed Implementation
[0028] It should be noted that the terms "surface" and "on" in this specification are used to describe the relative spatial position and are not limited to whether there is direct contact.
[0029] As described in the background section, the existing embedded power line technology needs improvement, and its performance urgently needs to be enhanced. This will now be explained and analyzed in conjunction with a semiconductor structure.
[0030] Figures 1 to 3 This is a cross-sectional schematic diagram of the semiconductor structure formation process.
[0031] Please refer to Figure 1 A substrate is provided, the substrate including a base 101, a fin 102 located on the surface of the base 101, and an isolation layer 103. The fin 102 has a source / drain layer 104, and the isolation layer 103 is located on the sidewall of the fin 102 and exposes the source / drain layer 104. The substrate also has a buried power line 106, the top surface of which is lower than the top surface of the source / drain layer 104, and the bottom of which extends into the base 101. The isolation layer 103 is also located on the surface of the buried power line 106. An etch stop layer 105 is formed on the surface of layer 104 and the isolation layer 103; a first dielectric layer 100 is formed on the surface of the etch stop layer 105, the first dielectric layer 100 exposing the surface of the source / drain layer 104; a second dielectric layer 107 is formed on the surface of the first dielectric layer 100; the first dielectric layer 100 and the second dielectric layer 107 are etched to form an opening 108 and a contact hole 109 located in the opening 108, the opening 108 exposing the surface of the source / drain layer 104, and the contact hole 109 exposing the top surface of the buried power line 106.
[0032] Please refer to Figure 2 Remove the etching stop layer 105 on the surface of the source / drain layer 104 exposed by the opening 108, so that the top surface of the source / drain layer 104 is exposed; after the top surface of the source / drain layer 104 is exposed, a barrier layer 110 is formed on the sidewall and bottom surface of the opening 108 and the contact hole 109.
[0033] Please refer to Figure 3After the barrier layer 110 is formed, a contact layer 111 is formed in the contact hole 109, and a conductive layer 112 is formed in the opening 108.
[0034] In the above method, the buried power line 106 and the conductive layer 112 are electrically connected through the contact layer 111. The materials of the buried power line 106, the contact layer 111, and the conductive layer 112 are all ruthenium. The contact resistance between the buried power line 111 and the conductive layer 112 is relatively high, mainly due to the following reasons: 1) The contact hole 109 has a high aspect ratio, making it difficult to fill with metal material, resulting in increased contact resistance; 2) The barrier layer 110 is made of titanium, which is used to block the growth of metal material on the surface of the dielectric layer and improve the growth quality of the contact hole 109 and the conductive layer 112. However, the presence of a titanium thin film will increase the contact resistance, so a thin (approximately 0.3 nm or less) and uniform titanium thin film layer is required, which poses a great challenge to the existing titanium thin film material growth process. In existing titanium thin film processes, tetrakis(dimethylamino)titanium (TDMAT, Ti[N(CH3)2]4) is used as a raw material to form titanium nitride, which makes it difficult to achieve such high film thickness and uniformity requirements. In the process of forming titanium nitride using ALD, the source and drain layers (SiGe material) are easily corroded by chlorine generated during the process, which is detrimental to the performance of the device.
[0035] To address the aforementioned issues, this invention provides a semiconductor structure formation method in which the contact layer can be selectively grown on the surface of the buried power line, thereby improving the filling capability of the contact hole. Simultaneously, it eliminates the need to form a titanium nitride layer on the contact hole surface, thus avoiding the adverse effects of titanium nitride on contact resistance and improving the contact resistance between the conductive layer and the contact layer, and between the contact layer and the buried power line.
[0036] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
[0037] Figures 4 to 8 This is a cross-sectional schematic diagram of the semiconductor structure formation process according to an embodiment of the present invention.
[0038] Please refer to Figure 4 A substrate is provided, the substrate including a base 201, a fin 202 and an isolation layer 203 located on the surface of the base 201, and a buried power line 206, wherein the fin 202 has a source / drain layer 204, the top surface of the buried power line 206 is lower than the top surface of the source / drain layer 204, and the bottom of the buried power line 206 extends into the base 201, the isolation layer 203 is also located on the surface of the buried power line 206 and part of the sidewall of the fin 202, and exposes the source / drain layer 204.
[0039] In this embodiment, the substrate 201 is made of silicon. In other embodiments, the substrate material includes silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI). The multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP.
[0040] The buried power line 206 is made of ruthenium. In this embodiment, the buried power line 206 is made of ruthenium.
[0041] In this embodiment, the method for forming the buried power line 206 includes: forming a groove (not shown in the figure) in the isolation layer 203 and the base 201; and forming the buried power line 206 in the bottom and sidewall of the groove.
[0042] Subsequently, a dielectric layer is formed on the surface of the source / drain layer 204 and the isolation layer 203.
[0043] In this embodiment, before forming the dielectric layer, an initial etch stop layer 205 is also formed on the surface of the source / drain layer 204 and the isolation layer 203.
[0044] The initial etch stop layer 205 is made of silicon nitride. The initial etch stop layer 205 serves as a stop layer for the etching process, protecting the surfaces of the source / drain layer 204 and the isolation layer 203 in subsequent etching processes.
[0045] Please refer to Figure 5 A dielectric layer is formed on the surface of the source / drain layer 204 and the isolation layer 203; an opening 208 and a contact hole 209 located at the bottom of the opening 208 are formed in the dielectric layer, the opening 208 exposes the top surface of the source / drain layer 204, and the contact hole 209 is also located in the isolation layer 203 to expose the top surface of the buried power line 206.
[0046] The formation process of the opening 208 and the contact hole 209 includes one or both of dry etching and wet etching processes. In this embodiment, the formation process of the opening 208 and the contact hole 209 is dry etching. Dry etching is beneficial for improving the morphology of the formed opening.
[0047] Specifically, the dielectric layer includes a first dielectric material layer 306 located on the surface of the source / drain layer 204 and the isolation layer 203, and a second dielectric material layer 207 located on the surface of the first dielectric material layer 306.
[0048] Specifically, the opening 208 exposes the initial etch stop layer 205 on the top surface of the source / drain layer 204.
[0049] The aspect ratio of the opening 208 is in the range of 3 to 14; the aspect ratio of the contact hole 209 is in the range of 3 to 14.
[0050] In this embodiment, the width of the opening 208 is 12 nanometers, and the depth of the opening 208 is 22 nanometers to 60 nanometers. The width refers to the dimension along the direction of the substrate surface, and the depth refers to the dimension along the normal direction of the substrate surface.
[0051] Please refer to Figure 6 A first selective growth process is used to form a contact layer 210 on the surface of the buried power line 206 exposed by the contact hole 209.
[0052] The contact layer 210 can be selectively grown on the surface of the buried power line, which helps to improve the filling capacity of the contact hole 209. At the same time, it is not necessary to form a titanium nitride layer on the surface of the contact hole 209, thus avoiding the adverse effects of titanium nitride on the contact resistance and improving the contact resistance between the conductive layer and the contact layer 210, and between the contact layer 210 and the buried power line 206.
[0053] The contact layer 210 is made of tungsten. In this embodiment, the contact layer 210 is made of tungsten.
[0054] The first selective growth process includes atomic layer deposition (ALD) or chemical vapor deposition (CVD). In this embodiment, the first selective growth process is ALD, which is beneficial for improving the filling capacity and uniformity of the contact layer 210 material within the contact hole 209, thereby reducing contact resistance.
[0055] The process parameters of the first selective growth process include: the reaction gases include tungsten hexafluoride and hydrogen, the flow rate of tungsten hexafluoride ranges from 10 sccm to 500 sccm, the flow rate of hydrogen ranges from 1000 sccm to 10000 sccm, the gas pressure ranges from 3 Torr to 100 Torr, and the reaction temperature ranges from 200°C to 450°C.
[0056] Please refer to Figure 7 After the contact layer 210 is formed, a barrier layer 212 is formed on the surface of the medium layer exposed by the opening 208.
[0057] In this embodiment, after the contact layer 210 is formed and before the barrier layer is formed, the initial etch stop layer 205 on the top surface of the source / drain layer 204 is removed to form an etch stop layer 211, so that the top surface of the source / drain layer 204 is exposed.
[0058] Subsequently, after the barrier layer 212 is formed, a conductive layer is formed inside the opening 208.
[0059] The barrier layer 212 is formed using a second selective growth process. This second selective growth process ensures that the barrier layer 212 is formed only on the surface of the dielectric layer exposed by the opening 208, reducing material deposition on the surface of the contact layer 210. This improves the quality of the conductive layer while reducing adverse effects on the contact resistance between the contact layer 210 and the conductive layer. Furthermore, when the conductive layer is made of tungsten, the barrier layer 212 can also protect the dielectric layer from tungsten hexafluoride corrosion during the formation of the tungsten conductive layer.
[0060] The barrier layer 212 is made of tungsten nitride. In this embodiment, the barrier layer 212 is made of tungsten nitride.
[0061] The thickness of the barrier layer 212 ranges from 1 nm to 3 nm.
[0062] The second selective growth process includes atomic layer deposition (ALD). In this embodiment, the second selective growth process is ALD. The ALD process causes tungsten nitride material to grow on the surface of the dielectric layer exposed by the opening 208, but not on the surfaces of the contact layer 210 and the source / drain layer 204.
[0063] In this embodiment, the process parameters of the second selective growth process include: the reaction gas includes hydrogen or ammonia, the precursor includes tungsten bis(tert-butyl-imino)bis(dimethylamino)tungsten, the hydrogen flow rate ranges from 50 sccm to 5000 sccm, the ammonia flow rate ranges from 50 sccm to 5000 sccm, the gas pressure ranges from 3 Torr to 100 Torr, and the reaction temperature ranges from 200°C to 400°C. Specifically, tungsten bis(tert-butyl-imino)bis(dimethylamino)tungsten is tungsten bis(tert-butyl-imino)bis(dimethylamino).
[0064] Please refer to Figure 8 After the barrier layer 212 is formed, a conductive layer 213 is formed inside the opening 208.
[0065] The conductive layer 213 is made of metal; the metal includes tungsten and cobalt. In this embodiment, the conductive layer 213 is made of tungsten.
[0066] The conductive layer 213 is formed using an atomic layer deposition process. In this embodiment, the conductive layer 213 is formed using an atomic layer deposition process.
[0067] In this embodiment, the conductive layer 213 is made of tungsten.
[0068] In this embodiment, the process parameters for forming the conductive layer 213 include: the reaction gases are tungsten hexafluoride and hydrogen, the flow rate of tungsten hexafluoride is in the range of 10 sccm to 500 sccm, the flow rate of hydrogen is in the range of 1000 sccm to 10000 sccm, the gas pressure is in the range of 3 Torr to 50 Torr, and the reaction temperature is in the range of 300°C to 500°C. During this process, the relatively low flow rate of tungsten hexafluoride helps to reduce the corrosion of the substrate by fluoride ions, which is beneficial to improving the performance of the formed device.
[0069] Accordingly, this invention also provides a semiconductor structure, please refer to [the relevant documentation]. Figure 8 The system includes: a substrate, the substrate comprising a base 201, a fin 202 and an isolation layer 203 located on the surface of the base 201, and a buried power line 206, wherein the fin 202 has a source / drain layer 204, the top surface of the buried power line 206 is lower than the top surface of the source / drain layer 204, and the bottom of the buried power line 206 extends into the base 201; the isolation layer 203 is also located on the surface of the buried power line 206 and part of the sidewall of the fin 202, and exposes the source / drain layer 204; the source / drain layer 204 and the isolation layer 203 are located on the surface of the source / drain layer 204 and the isolation layer 203. A dielectric layer on the surface; an opening 208 located within the dielectric layer and a contact hole 209 located at the bottom of the opening 208, the opening 208 exposing the top surface of the source / drain layer 204, and the contact hole 209 exposing the top surface of the buried power line 206; a contact layer 210 located within the contact hole 209; a barrier layer 212 located on the surface of the dielectric layer exposed by the opening 208; a conductive layer 213 located on the surface of the barrier layer 212 within the opening 208, the conductive layer 213 also located on the top surface of the source / drain layer 204 exposed by the opening 208.
[0070] Specifically, the dielectric layer includes a first dielectric material layer 306 located on the surface of the source / drain layer 204 and the isolation layer 203, and a second dielectric material layer 207 located on the surface of the first dielectric material layer 306.
[0071] The semiconductor structure further includes an etch stop layer 211 located on the surface of the isolation layer 203 and a portion of the surface of the source / drain layer 204, and the opening 208 exposes the top surface of the source / drain layer 204.
[0072] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.
Claims
1. A semiconductor structure, characterized in that, include: The substrate includes a base, a fin located on the surface of the base and an isolation layer, and a buried power line, wherein the fin has a source / drain layer, the top surface of the buried power line is lower than the top surface of the source / drain layer, and the bottom of the buried power line extends into the base, and the isolation layer is also located on the surface of the buried power line and a portion of the sidewall of the fin, and exposes the source / drain layer. A dielectric layer located on the surfaces of the source / drain layer and the isolation layer; An opening located within the dielectric layer and a contact hole located at the bottom of the opening, the bottom of the opening exposing the top surface of the source / drain layer, the contact hole also being located within the isolation layer and exposing the top surface of the buried power line; The contact layer located within the contact hole; A barrier layer located on the surface of the dielectric layer exposed by the opening; A conductive layer is located on the surface of the barrier layer within the opening, and the conductive layer is also located on the top surface of the source / drain layer exposed by the opening, and on the top surface of the contact hole.
2. The semiconductor structure as described in claim 1, characterized in that, Also includes: An etch stop layer is located on the surface of the isolation layer and part of the surface of the source / drain layer, and the opening exposes the top surface of the source / drain layer.
3. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, the substrate including a base, a fin and an isolation layer located on the surface of the base, and a buried power line, the fin having a source / drain layer, the top surface of the buried power line being lower than the top surface of the source / drain layer, and the bottom of the buried power line extending into the base, the isolation layer also being located on the surface of the buried power line and a portion of the sidewall of the fin, and exposing the source / drain layer; A dielectric layer is formed on the surfaces of the source / drain layer and the isolation layer; An opening and a contact hole located at the bottom of the opening are formed within the dielectric layer. The opening exposes the top surface of the source / drain layer, and the contact hole is also located within the isolation layer to expose the top surface of the buried power line. A contact layer is formed on the surface of the buried power line exposed by the contact hole using a first selective growth process. After the contact layer is formed, a barrier layer is formed on the surface of the dielectric layer exposed by the opening; After the barrier layer is formed, a conductive layer is formed inside the opening.
4. The method for forming a semiconductor structure as described in claim 3, characterized in that, Before forming the dielectric layer, an initial etch stop layer is formed on the surface of the source / drain layer and the isolation layer; the opening exposes the initial etch stop layer on the top surface of the source / drain layer; after forming the contact layer and before forming the barrier layer, the initial etch stop layer on the top surface of the source / drain layer is removed to form an etch stop layer, thereby exposing the top surface of the source / drain layer.
5. The method for forming a semiconductor structure as described in claim 3, characterized in that, The material of the contact layer includes tungsten.
6. The method for forming a semiconductor structure as described in claim 5, characterized in that, The first selective growth process includes atomic layer deposition or chemical vapor deposition.
7. The method for forming a semiconductor structure as described in claim 5, characterized in that, The process parameters of the first selective growth process include: the reaction gases include tungsten hexafluoride and hydrogen, the flow rate of tungsten hexafluoride ranges from 10 sccm to 500 sccm, the flow rate of hydrogen ranges from 1000 sccm to 10000 sccm, the gas pressure ranges from 3 Torr to 100 Torr, and the reaction temperature ranges from 200 ℃ to 450 ℃.
8. The method for forming a semiconductor structure as described in claim 3, characterized in that, The barrier layer is formed using a second selective growth process.
9. The method for forming a semiconductor structure as described in claim 8, characterized in that, The barrier layer is made of tungsten nitride.
10. The method for forming a semiconductor structure as described in claim 9, characterized in that, The second selective growth process includes atomic layer deposition.
11. The method for forming a semiconductor structure as described in claim 9, characterized in that, The process parameters of the second selective growth process include: the reaction gas includes hydrogen or ammonia, the precursor includes bis(tert-butylimino)bis(dimethylamino)tungsten, the hydrogen flow rate ranges from 50 sccm to 5000 sccm, the ammonia flow rate ranges from 50 sccm to 5000 sccm, the gas pressure ranges from 3 Torr to 100 Torr, and the reaction temperature ranges from 200 ℃ to 400 ℃.
12. The method for forming a semiconductor structure as described in claim 3, characterized in that, The conductive layer is made of metal; the metal includes tungsten and cobalt.
13. The method for forming a semiconductor structure as described in claim 12, characterized in that, The process for forming the conductive layer includes atomic layer deposition.
14. The method for forming a semiconductor structure as described in claim 13, characterized in that, The conductive layer is made of tungsten.
15. The method for forming a semiconductor structure as described in claim 14, characterized in that, The process parameters for forming the conductive layer include: the reaction gases are tungsten hexafluoride and hydrogen, the flow rate of tungsten hexafluoride is in the range of 10 sccm to 500 sccm, the flow rate of hydrogen is in the range of 1000 sccm to 10000 sccm, the gas pressure is in the range of 3 Torr to 50 Torr, and the reaction temperature is in the range of 300 ℃ to 500 ℃.
16. The method for forming a semiconductor structure as described in claim 3, characterized in that, The aspect ratio of the opening is in the range of 3 to 14; the aspect ratio of the contact hole is in the range of 3 to 14.
17. The method for forming a semiconductor structure as described in claim 3, characterized in that, The thickness of the barrier layer ranges from 1 nm to 3 nm.