Insulated Gate Bipolar Transistor

Abstract

This invention discloses an insulated-gate bipolar transistor (IGBT) comprising a P-type III-V nitride layer, an N-type III-V nitride layer contacting one side of the P-type III-V nitride layer, a high electron mobility transistor disposed on the N-type III-V nitride layer, the high electron mobility transistor comprising a first III-V nitride layer and a second III-V nitride layer, the first III-V nitride layer being disposed on the N-type III-V nitride layer, the second III-V nitride layer being disposed on the first III-V nitride layer, a source electrode buried in the second III-V nitride layer and the first III-V nitride layer, wherein the source electrode comprises an N-type III-V nitride body and a metal junction, a drain electrode contacting the other side of the P-type III-V nitride layer, and a gate electrode disposed on the second III-V nitride layer.

Description

Technical Field

[0001] This invention relates to an insulated gate bipolar transistor (IGBT) structure, and more particularly to an IGBT structure composed of a high electron mobility transistor and a heterojunction bipolar transistor. Background Technology

[0002] Insulated-gate bipolar transistors (IGBTs) are commonly used power transistors in the industry. They combine the insulated-gate structure of metal-oxide-semiconductor field-effect transistors (MOSFETs) with the conduction characteristics of bipolar junction transistors (BJTs), thus offering the dual advantages of high output current and high input impedance. Their key features are high efficiency and fast switching speed, and they were developed to improve the operation of power-stage BJTs. In recent years, with the increasing demand for higher performance in semiconductor devices, there is a need to further improve the switching speed and voltage withstand capability of IGBTs to increase energy efficiency. Summary of the Invention

[0003] In view of this, the present invention provides an insulated gate bipolar transistor structure composed of a high electron mobility transistor and a heterojunction dual-carrier transistor to achieve the above requirements.

[0004] According to a first preferred embodiment of the present invention, an insulated gate bipolar transistor includes a P-type III-V nitride layer, an N-type III-V nitride layer contacts one side of the P-type III-V nitride layer, a high electron mobility transistor is disposed on the N-type III-V nitride layer, the high electron mobility transistor includes a first III-V nitride layer and a second III-V nitride layer, the first III-V nitride layer is disposed on the N-type III-V nitride layer, the second III-V nitride layer is disposed on the first III-V nitride layer, a source is buried in the second III-V nitride layer and the first III-V nitride layer, wherein the source includes an N-type III-V nitride body and a metal junction, a drain contacts the other side of the P-type III-V nitride layer, and a gate is disposed on the second III-V nitride layer.

[0005] According to a second preferred embodiment of the present invention, an insulated gate bipolar transistor includes a P-type III-V nitride layer, an N-type III-V nitride layer contacts one side of the P-type III-V nitride layer, a high electron mobility transistor is disposed on the N-type III-V nitride layer, the high electron mobility transistor includes a first III-V nitride layer and a second III-V nitride layer, the first III-V nitride layer is disposed on the N-type III-V nitride layer, the second III-V nitride layer is disposed on the first III-V nitride layer, a source is buried in the second III-V nitride layer and the first III-V nitride layer, wherein the source is entirely composed of metal, a drain contacts the other side of the P-type III-V nitride layer, and a gate is disposed on the second III-V nitride layer.

[0006] To make the above-mentioned objects, features, and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. However, the following preferred embodiments and drawings are for reference and illustration only and are not intended to limit the present invention. Attached Figure Description

[0007] Figure 1 A schematic diagram of an insulated gate bipolar transistor according to a first preferred embodiment of the present invention;

[0008] Figure 2 A schematic diagram of an insulated gate bipolar transistor illustrated in a second preferred embodiment of the present invention;

[0009] Figure 3 A schematic diagram of an insulated gate bipolar transistor illustrated in a third preferred embodiment of the present invention;

[0010] Figure 4 A schematic diagram of an insulated gate bipolar transistor according to a fourth preferred embodiment of the present invention;

[0011] Figure 5 This is a schematic diagram of the fabrication method of an insulated gate bipolar transistor in the first preferred embodiment.

[0012] Explanation of main component symbols

[0013] 10: P-type III-V group nitride layer

[0014] 10a: One side

[0015] 10b: The other side

[0016] 12: N-type III-V group nitride layer

[0017] 14: First III-V Nitride Layer

[0018] 16: Second III-V Nitride Layer

[0019] 18: Quantum Confinement Channel

[0020] 20: Undoped Group III-V nitride layer

[0021] 22: Group III-V nitride capping layer

[0022] 24: Protective layer

[0023] 26: Gallium nitride layer

[0024] 28: Base

[0025] 30: Buffer layer

[0026] D: Drain electrode

[0027] G: Gate

[0028] H1: High electron mobility transistor

[0029] H2: High electron mobility transistor

[0030] M: Source

[0031] S: Source

[0032] S1: N-type III-V group nitride host

[0033] S2: Metal junction

[0034] T1: Insulated Gate Bipolar Transistor

[0035] T2: Insulated Gate Bipolar Transistor

[0036] T3: Insulated Gate Bipolar Transistor

[0037] T4: Insulated Gate Bipolar Transistor Detailed Implementation

[0038] Figure 1 An insulated gate bipolar transistor illustrated according to a first preferred embodiment of the present invention.

[0039] like Figure 1As shown, an insulated-gate bipolar transistor T1 includes a P-type III-V nitride layer 10, an N-type III-V nitride layer 12 contacting one side 10a of the P-type III-V nitride layer 10, a high electron mobility transistor H1 disposed on the N-type III-V nitride layer 12, the high electron mobility transistor H1 including a first III-V nitride layer 14 disposed on the N-type III-V nitride layer 12, and a second III-V nitride layer 14. A group I-V nitride layer 16 is disposed on a first group III-V nitride layer 14. A quantum confinement channel 18 is disposed between the first group III-V nitride layer 14 and the second group III-V nitride layer 16, with the quantum confinement channel 18 contacting the first group III-V nitride layer 14. An undoped group III-V nitride layer 20 contacts the quantum confinement channel 18 and is located above it. A group III-V nitride capping layer 22 covers the second group III-V nitride layer 16. In other words, the first group III-V nitride layer 14, the quantum confinement channel 18, the undoped group III-V nitride layer 20, the second group III-V nitride layer 16, and the group III-V nitride capping layer 22 are stacked sequentially from bottom to top. A two-dimensional electron gas is formed in the quantum confinement channel 18.

[0040] A source electrode S is embedded in the second III-V nitride layer 16 and the first III-V nitride layer 14. Specifically, the source electrode S penetrates the III-V nitride capping layer 22, the second III-V nitride layer 16, the undoped III-V nitride layer 20, the quantum confinement channel 18, and contacts the first III-V nitride layer 14. Furthermore, the source electrode S includes an N-type III-V nitride body S1 and a metal junction S2. A drain electrode D contacts the other side 10b of the P-type III-V nitride layer 10, meaning that the drain electrode D and the source electrode S are located on opposite sides of the P-type III-V nitride layer 10. A gate electrode G is disposed on the second III-V nitride layer 16 and contacts the III-V nitride capping layer 22. A protective layer 24 covers the III-V nitride capping layer 22 and the source electrode S.

[0041] P-type III-V group nitride layer 10 contains In m Ga 1-m N, where m≤1, N-type III-V nitride layer 12 contains In n Ga 1-n N, where n≤1, the first III-V nitride layer 14 contains p-type GaN, and the second III-V nitride layer 16 contains n-type Al. y Ga 1-yN, where y < 1, according to a preferred embodiment of the present invention, the y value of the second III-V nitride layer 16 decreases from bottom to top, that is, the closer to the undoped III-V nitride layer 20, the larger the y value. For example, the y value of the second III-V nitride layer 16 in contact with the undoped III-V nitride layer 20 is 0.9, and the second III-V nitride layer 16 at this position is Al. 0.9 Ga 0.1 The y-value of the second III-V nitride layer 16, which is in contact with the III-V nitride capping layer 22, is 0.25. The second III-V nitride layer 16 at this location is Al. 0.25 Ga 0.75 N.

[0042] Quantum confinement channel 18 contains undoped In q Ga 1-q N, where q≤1, and the undoped III-V group nitride layer 20 contains Al. z Ga 1-z N, where z≤1, according to a preferred embodiment of the present invention, the undoped III-V nitride layer 20 is AlN, and the III-V nitride capping layer 22 is preferably GaN. The N-type III-V nitride body S1 in the source S is preferably In. r Ga 1-r N, where r≤1. Additionally, the dopants in the N-type III-V nitride layer 12 include group IV elements, the dopants in the P-type III-V nitride layer 10 include group II elements, and the N-type dopants in the second III-V nitride layer 16 include group IV elements. Group IV elements include C, Si, and Ge; in this embodiment, the N-type dopant is preferably Si. Group II elements include Mg, Ca, and Sr; in this embodiment, the P-type dopant is preferably Mg.

[0043] The metal junction S2, drain D, and gate G in the source S can each comprise a metal conductive material or other doped semiconductor material. The aforementioned metal conductive material may include Au, W, Co, Ni, Ti, Mo, Cu, Al, Ta, Pd, as well as compounds, composite layers, or alloys of the aforementioned materials.

[0044] Furthermore, the source S serves as the source S of the high electron mobility transistor H1, but also as the emitter of the insulated gate bipolar transistor T1; the drain D serves as the drain D of the high electron mobility transistor H1, but also as the collector of the insulated gate bipolar transistor T1.

[0045] In the insulated-gate bipolar transistor T1, an NPN transistor is formed by an N-type III-V nitride body S1 at the source S, a first III-V nitride layer 14, and an N-type III-V nitride layer 12. A PNP transistor is formed by the first III-V nitride layer 14, the N-type III-V nitride layer 12, and a P-type III-V nitride layer 10. In the first preferred embodiment, both the NPN and PNP transistors are heterojunctions. It is worth noting that the P-type dopant in the first III-V nitride layer 14 is used to adjust the threshold voltage of the high electron mobility transistor H1 and the voltage between the base and emitter of the NPN transistor. Generally, the concentration of the P-type dopant in the first III-V nitride layer 14 is adjusted to make the high electron mobility transistor H1 normally off. Therefore, in this embodiment, the high electron mobility transistor H1 is preferably a normally off N-type high electron mobility transistor.

[0046] Figure 2 The insulated gate bipolar transistor illustrated according to the second preferred embodiment of the present invention, wherein elements having the same function and location will use the element designations of the first preferred embodiment, and elements having the same element designations as those in the first preferred embodiment will not be described again in terms of their function and material.

[0047] Please also refer to Figure 1 and Figure 2 The difference between the insulated-gate bipolar transistor T2 of the second preferred embodiment and the insulated-gate bipolar transistor T1 of the first preferred embodiment is that the source M of the insulated-gate bipolar transistor T2 is entirely made of metal, while the positions and materials of other components are the same as in the first preferred embodiment. The source M may include Au, W, Co, Ni, Ti, Mo, Cu, Al, Ta, Pd, and compounds, composite layers, or alloys of the above materials.

[0048] Figure 3 The insulated gate bipolar transistor illustrated according to the third preferred embodiment of the present invention, wherein elements having the same function and location will use the element designations of the first preferred embodiment, and elements having the same element designations as those in the first preferred embodiment will not be described again in terms of their function and material.

[0049] The difference between the insulated-gate bipolar transistor illustrated in the third preferred embodiment and the insulated-gate bipolar transistor illustrated in the first preferred embodiment lies in the structure of the high electron mobility transistor. For example... Figure 3As shown, the high electron mobility transistor H2 includes a first III-V nitride layer 14, a gallium nitride layer 26 disposed on the first III-V nitride layer 14, a second III-V nitride layer 16 disposed on the gallium nitride layer 26, and a III-V nitride capping layer 22 covering the second III-V nitride layer 16. That is, the first III-V nitride layer 14, the gallium nitride layer 26, the second III-V nitride layer 16, and the III-V nitride capping layer 22 are stacked from bottom to top. The first III-V nitride layer 14 contacts the gallium nitride layer 26, the gallium nitride layer 26 contacts the second III-V nitride layer 16, and the second III-V nitride layer 16 contacts the III-V nitride capping layer 22. A two-dimensional electron gas is formed in the gallium nitride layer 26. The source electrode S is embedded in the III-V nitride capping layer 22, the second III-V nitride layer 16, the gallium nitride layer 26, and the first III-V nitride layer 14. The source electrode S is the same as that in the first preferred embodiment, consisting of an N-type III-V nitride body S1 and a metal junction S2. The positions of other components are the same as in the first preferred embodiment.

[0050] Figure 4 The insulated gate bipolar transistor illustrated according to the fourth preferred embodiment of the present invention, wherein elements having the same function and location will use the element designations of the third preferred embodiment, and elements having the same element designations as those in the third preferred embodiment will not be described again in terms of their function and material.

[0051] Please also refer to Figure 3 and Figure 4 The difference between the insulated-gate bipolar transistor T3 of the third preferred embodiment and the insulated-gate bipolar transistor T4 of the fourth preferred embodiment is that the source M of the insulated-gate bipolar transistor T4 is entirely made of metal, while the positions and materials of other components are the same as in the third preferred embodiment. The source M may include Au, W, Co, Ni, Ti, Mo, Cu, Al, Ta, Pd, and compounds, composite layers, or alloys of the above materials.

[0052] Figure 5 and Figure 1 The illustration depicts a method for fabricating an insulated gate bipolar transistor in a first preferred embodiment. Components with the same function and location will use the component designations in the first preferred embodiment, and the functions and materials of components with the same component designations as in the first preferred embodiment will not be described again.

[0053] like Figure 5As shown, the fabrication method of an insulated gate bipolar transistor (IGBT) may include providing a substrate 28, then forming a buffer layer 30 to cover the substrate 28, then forming a P-type III-V nitride layer 10, followed by sequentially forming an N-type III-V nitride layer 12, a first III-V nitride layer 14, a quantum confinement channel 18, an undoped III-V nitride layer 20, a second III-V nitride layer 16, and a III-V nitride capping layer 22 on one side 10a of the P-type III-V nitride layer 10, then forming a source S, followed by a protective layer 24, and then a gate G, and so on. Figure 1 As shown, the substrate 28 and buffer layer 30 are removed to expose the other side 10b of the P-type III-V nitride layer 10. Finally, the drain D is formed on the other side 10b of the P-type III-V nitride layer 10, thus completing the insulated gate bipolar transistor T1.

[0054] Furthermore, the insulated gate bipolar transistor T2 in the second preferred embodiment, the insulated gate bipolar transistor T3 in the third preferred embodiment, and the insulated gate bipolar transistor T4 in the fourth preferred embodiment can all adopt the above-described fabrication process. In the second preferred embodiment, only the source material needs to be replaced. In the third preferred embodiment, only the quantum confinement channel 18 and the undoped III-V group nitride layer 20 in the first preferred embodiment need to be replaced with a gallium nitride layer 26. In the fourth preferred embodiment, only the source material in the third preferred embodiment needs to be replaced with a metal.

[0055] This invention utilizes high electron mobility transistors to increase the switching speed and breakdown voltage of insulated-gate bipolar transistors (IGBTs). Furthermore, it employs NPN and PNP transistors to increase current flow. Therefore, the IGBT of this invention possesses advantages such as low on-resistance, high current handling capability, high voltage withstand capability, and high switching speed. Compared to conventional MOSFET-based IGBTs, the on-resistance of the IGBT of this invention is one-twentieth to one-tenth that of conventional IGBTs. Moreover, since the IGBT of this invention is a vertical transistor, it saves component area compared to horizontal transistors.

[0056] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

Claims

1. An insulated-gate bipolar transistor, comprising: P-type III-V group nitride layer; The N-type III-V nitride layer, on the side that contacts the P-type III-V nitride layer; A high electron mobility transistor is disposed on the N-type III-V group nitride layer, wherein the high electron mobility transistor comprises: A first III-V nitride layer, which is in contact with the N-type III-V nitride layer; A second III-V nitride layer is disposed on the first III-V nitride layer; The source electrode is embedded in the second III-V nitride layer and the first III-V nitride layer, wherein the source electrode comprises an N-type III-V nitride body and a metal junction; The drain electrode contacts the other side of the P-type III-V nitride layer; and The gate is disposed on the second III-V nitride layer. The source electrode serves as the source of the high electron mobility crystal and the emitter of the insulated gate bipolar transistor, while the drain electrode serves as the drain of the high electron mobility transistor and the collector of the insulated gate bipolar transistor.

2. The insulated-gate bipolar transistor of claim 1, wherein the P-type III-V nitride layer comprises In m Ga 1- m N, where m≤1.

3. The insulated-gate bipolar transistor of claim 1, wherein the N-type III-V nitride layer comprises In n Ga 1- n N, where n≤1.

4. The insulated-gate bipolar transistor of claim 1, further comprising a gallium nitride layer disposed on the first III-V group nitride layer, wherein the first III-V group nitride layer comprises GaN, and the second III-V group nitride layer comprises Al. x Ga 1- x N, where x < 1, forms a two-dimensional electron gas in the gallium nitride layer.

5. The insulated gate bipolar transistor of claim 1, wherein the second III-V nitride layer comprises an N-type dopant.

6. The insulated-gate bipolar transistor of claim 1, wherein the first III-V nitride layer comprises P-type GaN, and the second III-V nitride layer comprises N-type Al. y Ga 1-y N, where y < 1.

7. The insulated-gate bipolar transistor of claim 6, further comprising: A quantum confinement channel is disposed between the first III-V group nitride layer and the second III-V group nitride layer, the quantum confinement channel containing undoped In. q Ga 1-q N, where q≤1; An undoped III-V group nitride layer, contacting and above the quantum confinement channel; and A III-V group nitride overlay layer covers the second III-V group nitride layer.

8. The insulated gate bipolar transistor of claim 1, wherein the dopant in the N-type III-V nitride layer comprises a group IV element, and the dopant in the P-type III-V nitride layer comprises a group II element.

9. An insulated-gate bipolar transistor, comprising: P-type III-V group nitride layer; The N-type III-V nitride layer, on the side that contacts the P-type III-V nitride layer; A high electron mobility transistor is disposed on the N-type III-V group nitride layer, wherein the high electron mobility transistor comprises: A first III-V nitride layer, which is in contact with the N-type III-V nitride layer; A second III-V nitride layer is disposed on the first III-V nitride layer; The source electrode is embedded in the second III-V nitride layer and the first III-V nitride layer, wherein the source electrode is entirely composed of metal; The drain electrode contacts the other side of the P-type III-V nitride layer; and The gate is disposed on the second III-V nitride layer. The source electrode serves as the source of the high electron mobility crystal and the emitter of the insulated gate bipolar transistor, while the drain electrode serves as the drain of the high electron mobility transistor and the collector of the insulated gate bipolar transistor.

10. The insulated-gate bipolar transistor of claim 9, wherein the P-type III-V nitride layer comprises In m Ga 1- m N, where m≤1.

11. The insulated-gate bipolar transistor of claim 9, wherein the N-type III-V nitride layer comprises In n Ga 1- n N, where n≤1.

12. The insulated-gate bipolar transistor of claim 9, further comprising a gallium nitride layer disposed on the first III-V group nitride layer, wherein the first III-V group nitride layer comprises GaN, and the second III-V group nitride layer comprises Al. x Ga 1- x N, where x < 1, forms a two-dimensional electron gas in the gallium nitride layer.

13. The insulated gate bipolar transistor of claim 9, wherein the second III-V nitride layer comprises an N-type dopant.

14. The insulated-gate bipolar transistor of claim 9, wherein the first III-V nitride layer comprises P-type GaN, and the second III-V nitride layer comprises N-type Al. y Ga 1-y N, where y < 1.

15. The insulated-gate bipolar transistor of claim 14, further comprising: A quantum confinement channel is disposed between the first III-V group nitride layer and the second III-V group nitride layer, the quantum confinement channel containing undoped In. q Ga 1-q N, where q≤1; An undoped III-V group nitride layer, contacting and above the quantum confinement channel; and A III-V group nitride overlay layer covers the second III-V group nitride layer.

16. The insulated gate bipolar transistor of claim 9, wherein the dopant in the N-type III-V nitride layer comprises a group IV element, and the dopant in the P-type III-V nitride layer comprises a group II element.

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