Switched capacitor converter

Abstract

This invention discloses a switched capacitor converter, comprising: four switches connected in series between an input voltage and ground; a flying capacitor, the first end of which is coupled to a first node between the first and second switches of the four switches, and the second end of which is coupled to a second node between the third and fourth switches of the four switches; a first driver configured to output a first drive signal according to a first control signal; a soft-start circuit configured to output a second drive signal that gradually increases over time according to the first control signal; and a switching circuit configured to couple the gate of the first switch to the soft-start circuit during the soft-start period, and to couple the gate of the first switch to the first driver during the working period, thereby controlling the first switch to gradually turn on during the soft-start period, thereby controlling the charging current on the flying capacitor to increase slowly, which is beneficial to realize the soft start of the circuit, avoids the generation of large surge current during startup, and improves the stability and reliability of the circuit.

Description

Technical Field

[0001] This invention relates to the field of power converter technology, and more specifically, to a switched capacitor converter. Background Technology

[0002] With the increasing demand for power electronic products and the development of semiconductor technology, power management chips are being used more widely in portable computers, mobile phones, personal digital assistants, and other portable or non-portable electronic devices. Switching power supplies are widely used due to their advantages such as high conversion efficiency, large output current, low quiescent current, and wide output load range.

[0003] Switched-capacitor converters are typical non-magnetic component converters, consisting of a number of switching devices and voltage-dividing capacitors. The switching controls the capacitors' operating states to achieve the transfer and conversion of electrical energy. They can generate a higher number of output levels with fewer switching devices, and have advantages such as small size, high efficiency, and high power density, making them a growing trend in battery charging research.

[0004] Figure 1 A schematic diagram of a switched-capacitor converter according to the prior art is shown. Figure 1 As shown, the switched-capacitor converter 100 includes four switches Q1 to Q4 connected sequentially between the voltage input terminal Vin and ground, a flying capacitor CFly, and four drivers. The first terminal of the flying capacitor CFly is coupled to node CFH between switches Q1 and Q2, and the second terminal is coupled to node CFL between switches Q3 and Q4. A battery 101 is coupled between the voltage output terminal Vout between switches Q2 and Q3 and ground. The four drivers output drive signals according to the first to fourth control signals Drv1 to Drv4 to control the on and off states of switches Q1 to Q4, thereby obtaining a stable output voltage.

[0005] Figure 2 It shows Figure 1 The timing diagram of the switched capacitor converter in the diagram is shown. Figure 2 As shown, a complete charging cycle of the switched capacitor converter includes a charging phase and a discharging phase. When the switched capacitor converter 100 is in the charging phase, switches Q1 and Q3 are turned on, and current flows through switch Q1 and the flying capacitor CFly to the source terminal of switch Q3. When the switched capacitor converter 100 is in the discharging phase, switches Q2 and Q4 are turned on, and current flows from the upper end of the flying capacitor CFly through switch Q2 to the first terminal of battery 101, and then from the ground through the source terminal of switch Q4 to the second terminal of the flying capacitor CFly. The working principle of the switched capacitor converter is to achieve rapid and efficient high-current charging through continuous and repeated charging cycles.

[0006] The existing switched capacitor converter 100 has the following problems: the switched capacitor converter 100 may be subjected to large inrush currents of sensitive circuit elements. For example, when switches Q1 and Q3 are turned on, the input voltage Vin is much greater than the voltage on the flying capacitor CFly. Because there is no inductor in the switched capacitor converter to limit the current, the input inrush current will rise rapidly to a high level. This inrush current may exceed the safe operating current of the transistor, thereby affecting the reliability of the switched capacitor converter. Summary of the Invention

[0007] In view of the above problems, the purpose of this invention is to provide a switched capacitor converter that can realize soft-start control of the converter and improve the reliability of the converter.

[0008] According to an embodiment of the present invention, a switched capacitor converter is provided, comprising: four switches connected in series between an input voltage and ground; a flying capacitor, a first terminal of which is coupled to a first node between a first switch and a second switch of the four switches, and a second terminal of which is coupled to a second node between a third switch and a fourth switch of the four switches; a first driver configured to output a first drive signal according to a first control signal; a soft-start circuit configured to output a second drive signal that gradually increases over time according to the first control signal; and a switching circuit configured to couple the gate of the first switch to the soft-start circuit during a soft-start period, and to couple the gate of the first switch to the first driver during an operating period.

[0009] Optionally, the soft-start circuit includes: a current generation module and a first transistor coupled between a first voltage signal and the first node, wherein the current generation module is used to generate an output current that increases with time, and the gate and drain of the first transistor are coupled to generate the second drive signal according to the output current.

[0010] Optionally, the current generation module includes: a current source array comprising multiple current sources and switches, wherein the first terminals of the multiple first current sources are coupled to the first voltage signal, the second terminals of the multiple first current sources are respectively coupled to the first terminals of corresponding switches, and the second terminals of the multiple switches are coupled to the output terminals of the output current; and a switch control unit, configured to generate a switch control signal having multiple binary bits according to the first control signal, wherein each bit of the switch control signal is used to control the switching on and off of the switches of the corresponding branches of the current source array.

[0011] Optionally, the switch control unit includes: a plurality of cascaded flip-flops, wherein the data terminal and negative output terminal of each of the plurality of flip-flops are coupled, the positive output terminal is used to output each bit of the switch control signal, the clock terminal of the first flip-flop of the plurality of flip-flops is used to receive the inverted signal of the first control signal, and the clock terminals of the remaining plurality of flip-flops are coupled to the negative output terminal of the previous flip-flop.

[0012] Optionally, the plurality of first current sources in the current source array are incremented in a binary weighted manner from low to high.

[0013] Optionally, all of the multiple triggers are implemented using D triggers.

[0014] Optionally, the current generation module includes: a second current source and a first capacitor coupled between the power supply voltage and ground; an operational amplifier, the positive input terminal of which is coupled to the common terminal of the second current source and the first capacitor; a first transistor, the gate of which is coupled to the output terminal of the operational amplifier, and the source of which is coupled to the negative input terminal of the operational amplifier; a first resistor, the first terminal of which is coupled to the source of the first transistor, and the second terminal of which is grounded; a second transistor, the source of which is coupled to the drain of the first transistor, and the gate of which is coupled to the power supply voltage; a third transistor, the gate and drain of which are coupled to the drain of the second transistor, and the source of which is coupled to the first voltage signal; and a fourth transistor, the gate of which is coupled to the gate of the third transistor, the source of which is coupled to the first voltage signal, and the drain of which is coupled to the output terminal of the output current.

[0015] Optionally, the first transistor and the second transistor are N-type MOSFETs, and the third transistor and the fourth transistor are P-type MOSFETs.

[0016] Optionally, the second transistor is implemented using a high-voltage transistor.

[0017] Optionally, the switched capacitor converter further includes: second to fourth drivers configured to drive the second to fourth switches of the four switches respectively according to the second to fourth control signals.

[0018] In summary, the switched capacitor converter of this invention further includes a soft-start circuit and a switching circuit. The switching circuit is used to couple the gate of the first switch to the soft-start circuit during the soft-start period. During this period, the soft-start circuit provides the first switch with a drive signal that gradually increases over time, thereby controlling the first switch to gradually turn on during the soft-start period. This controls the charging current on the flying capacitor to increase slowly, which is beneficial for achieving soft-start of the circuit and avoids the generation of large surge current during startup, resulting in better circuit stability and reliability. Attached Figure Description

[0019] The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the invention with reference to the accompanying drawings, in which:

[0020] Figure 1 A schematic diagram of a switched capacitor converter according to the prior art is shown;

[0021] Figure 2 It shows Figure 1 Timing diagram of the switched capacitor converter in the diagram;

[0022] Figure 3 A schematic diagram of a switched capacitor converter according to an embodiment of the present invention is shown;

[0023] Figure 4 Show Figure 3 The waveform diagram of the switched capacitor converter during the startup process;

[0024] Figure 5 Show Figure 3 A circuit diagram of the soft-start circuit in the image;

[0025] Figure 6 Show Figure 5 A circuit diagram of the current generation module in the image;

[0026] Figure 7 Show Figure 6 The waveform of the output current of the current generation module in the image;

[0027] Figure 8 Show Figure 5 Another circuit diagram of the current generation module in the circuit;

[0028] Figure 9 Show Figure 8 The waveform of the output current of the current generation module in the image. Detailed Implementation

[0029] Various embodiments of the invention will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by the same or similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale.

[0030] It should be understood that, in the following description, "circuit" may include single or combined hardware circuits, programmable circuits, state machine circuits, and / or elements capable of storing instructions executed by the programmable circuit. When an element or circuit is said to be "coupled to" another element or "coupled between" two nodes, it can be directly coupled or connected to the other element, or there may be intermediate elements; the connection between elements can be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly coupled to" another element, it means that there are no intermediate elements between them.

[0031] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0032] Figure 3 A schematic diagram of a switched capacitor converter according to an embodiment of the present invention is shown. Figure 4 Show Figure 3 The waveform diagram of the switched capacitor converter during startup. (Example) Figure 3 As shown, the switched-capacitor converter 200 includes four switches Q1 to Q4 connected sequentially between the voltage input terminal Vin and ground, a flying capacitor CFly, and four drivers. The first terminal of the flying capacitor CFly is coupled to node CFH between switches Q1 and Q2, and the second terminal is coupled to node CFL between switches Q3 and Q4. A battery 101 is coupled between the voltage output terminal Vout between switches Q2 and Q3 and ground. The four drivers output drive signals according to the first to fourth control signals Drv1 to Drv4 to control the on and off states of switches Q1 to Q4, thereby obtaining a stable output voltage.

[0033] In one embodiment, Figure 3 Switches Q1 and Q3, located on the current charging path of the flying capacitor CFly, form one set of switches, while switches Q2 and Q4, located on the current discharging path of the flying capacitor CFly, form another set of switches. First to fourth control signals Drv1 to Drv4 are used to periodically turn the first and second sets of switches on and off in opposite directions to cyclically charge and discharge the flying capacitor CFly, providing output current at the voltage output terminal Vout. In some embodiments, switches Q1 and Q3 operate in unison, and switches Q2 and Q4 operate in unison. Furthermore, in each clock cycle, switches Q1 and Q2 turn on and off in a complementary manner, and switches Q3 and Q4 turn on and off in a complementary manner.

[0034] In one embodiment, switches Q1 to Q4 are selected from N-type MOSFETs (N-Type Metal-Oxide-Semiconductor). When the control signal is high, the corresponding transistor is turned on; when the control signal is low, the corresponding transistor is turned off. Furthermore, the high-level times of the first to fourth control signals Drv1 to Drv4 do not completely overlap (i.e., there is a certain dead time), preventing switches Q1 to Q4 from being turned on simultaneously.

[0035] Furthermore, the switched-capacitor converter 200 also includes a soft-start circuit 210 and a switching circuit 220. The soft-start circuit 210 is configured to output a drive signal Vgs2 that gradually increases over time according to the first control signal Drv1. The switching circuit 220 is configured to couple the gate of switch Q1 to the soft-start circuit 210 during the soft-start period of the switched-capacitor converter 200, and to couple the gate of switch Q1 to the output terminal of driver 230 during the operating period. The driver 230 can generate a fixed-voltage drive signal Vgs1 according to the first control signal Drv1.

[0036] Furthermore, the switching circuit 220 includes switches SJ1 and SJ2. Switch SJ1 is coupled between the output of the soft-start circuit 210 and the gate of switch Q1. The switching on and off of switch SJ1 is controlled by the signal PhaseSS, and it is turned on when the signal PhaseSS is high, thereby connecting the gate of switch Q1 to the output of the soft-start circuit 210. Switch SJ2 is coupled between the output of the driver 230 and the gate of switch Q1. The switching on and off of switch SJ2 is controlled by the signal PhaseN, and it is turned on when the signal PhaseN is high, thereby connecting the gate of switch Q1 to the output of the driver 230.

[0037] like Figure 4As shown, the startup process of the switched capacitor converter 200 in this embodiment includes three stages: a pre-charging period, a soft-start period, and a working period. During the pre-charging period, the voltage across the flying capacitor CFly is charged to the output voltage Vout. During the soft-start period, signal PhaseSS is high, signal PhaseN is low, switch SJ1 is turned on, and switch SJ2 is turned off. Switch SJ1 connects the gate of switch Q1 to the soft-start circuit 210. The soft-start circuit 210 provides a gradually increasing drive signal Vgs2 to switch Q1 according to the first control signal Drv1, causing switch Q1 to gradually turn on, thereby controlling the charging current on the flying capacitor CFly to increase slowly. Since the voltage across the flying capacitor CFly has already been pre-charged to the output voltage Vout at the initial moment of the soft-start period, its discharge current is relatively small. The slowly increasing charging current allows the voltage across its terminals to be gradually raised, thus ultimately completing the soft-start process. After the soft-start process, the signal PhaseN is high and the signal PhaseSS flips to low. Switch SJ1 is turned off and switch SJ2 is turned on. Switch SJ2 connects the gate of switch Q1 to driver 230. Driver 230 generates a normal drive signal Vgs1 according to the first control signal Drv1 to control switch Q1.

[0038] Figure 5 Show Figure 3 The circuit diagram of the soft-start circuit is shown below. Figure 5 As shown, in one embodiment, the soft-start circuit 210 includes a current generation module 211 and a transistor M0. The current generation module 211 and the transistor M0 are coupled between a bootstrap voltage signal BST and a node CFH. The bootstrap voltage signal BST is generated, for example, by raising the power supply voltage through an external bootstrap circuit; this embodiment is not limited to this. The current generation module 211 generates an output current Iout that gradually increases over time. The gate and drain of the transistor M0 are coupled to each other, and its source is coupled to the node CFH. It is used to generate the drive signal Vgs2 based on the output current Iout.

[0039] Figure 6 Show Figure 5 A circuit diagram of the current generation module in [the system]. Figure 7 Show Figure 6 The waveform of the output current of the current generation module in the image is shown. Figure 6As shown, in one embodiment, the current generation module 311 includes a switch control unit 3101 and a current source array 3102. The current source array 3102 includes multiple current sources I1 to In and multiple switches S1 to Sn, where n is an integer greater than 1. The multiple current sources I1 to In are connected in parallel, and the first terminal of each current source I1 to In is coupled to a bootstrap voltage signal BST, and the second terminal is coupled to the first terminal of the corresponding switch S1 to Sn. The second terminals of each switch S1 to Sn are all coupled to the output terminal of the output current Iout. The switch control circuit 3101 generates a switch control signal with multiple binary bits B1B2B3…Bn-1Bn according to a first control signal Drv1. Each bit of the switch control signal is used to control the conduction and cutoff of the corresponding branch in the current source array 3102, and the output current Iout is the sum of the currents of the selected branches. For example, each bit of a multi-bit binary number B1B2B3...Bn-1Bn has two states: "0" and "1". When B1 is "0", switch S1 is open; when B1 is "1", switch S1 is on.

[0040] Furthermore, the switch control unit 3101 includes multiple cascaded D flip-flops. The data terminal D of each D flip-flop is coupled to its negative input terminal Q-, and its positive output terminal Q- is used to output each bit of the switch control signal. The clock terminal CLK of the first D flip-flop is used to receive the inverted signal or the frequency-divided signal of the inverted signal Drv1. The clock terminals of the remaining D flip-flops are coupled to the negative output terminal Q- of the preceding D flip-flop. The inverted signal or the frequency-divided signal of the inverted signal Drv1 drives an n-bit binary counter composed of multiple cascaded D flip-flops. Its output controls the activation of multiple current sources I1 to In in the current source array 3102, thereby realizing that the output current Iout gradually increases with time, and stops counting when the counter reaches the upper limit value.

[0041] Furthermore, in this embodiment, the output currents of the multiple current sources in the current source array 3102 increase from low to high in a binary weighted manner. For example, the output currents of current sources I1-In are respectively set to I0, 2*I0, 4*I0, ..., 2*I0 in a binary weighted manner from low to high. (n-1) *I0 (I0 represents unit current).

[0042] Figure 8 Show Figure 5 Another circuit diagram of the current generation module in the image. Figure 9 Show Figure 8 The waveform of the output current of the current generation module in the image is shown. Figure 8As shown, the current generation module 411 includes a current source 4101, a capacitor C1, an operational amplifier OP1, a resistor R1, and transistors M1 to M4. The current source 4101 and capacitor C1 are coupled between the power supply voltage Vdd and ground. The positive input terminal of operational amplifier OP1 is coupled to the common node between the current source 4101 and capacitor C1, the negative input terminal is coupled to the source of transistor M1, and the output terminal is coupled to the gate of transistor M1. The first end of resistor R1 is coupled to the source of transistor M1, and the second end is grounded. The source of transistor M2 is coupled to the drain of transistor M1, and its gate is coupled to the power supply voltage Vdd. Transistors M3 and M4 form a current mirror, where the sources of both transistors M3 and M4 are coupled to the bootstrap voltage signal BST, the gates of transistors M3 and M4 are coupled to each other, and both are coupled to the drain of transistor M3. The drain of transistor M3 is also coupled to the drain of transistor M2, and the drain of transistor M4 is coupled to the output terminal of the output current Iout. In this process, current source 4101 charges capacitor C1, causing the voltage Vss at the common node between them to gradually increase over time. Due to the clamping control of operational amplifier OP1 and transistor M1, the current flowing through resistor R1 and the output current of the current mirrors of transistors M3 and M4 also gradually increase over time, resulting in a linear increase in the output current Iout over time. Figure 9 As shown.

[0043] In this embodiment, transistors M1 and M2 are, for example, N-type MOSFETs, transistors M3 and M4 are, for example, P-type MOSFETs (P-Type-Metal-Oxide-Semiconductor), and transistor M2 is, for example, implemented by a high-voltage transistor to isolate the power supply voltage Vdd and the bootstrap voltage signal BST.

[0044] In summary, the switched capacitor converter of this embodiment further includes a soft-start circuit and a switching circuit. The switching circuit is used to couple the gate of switch Q1 to the soft-start circuit during the soft-start period. During this period, the soft-start circuit provides a drive signal to switch Q1 that gradually increases over time, thereby controlling switch Q1 to gradually turn on during the soft-start period. This controls the charging current on the flying capacitor to increase slowly, which is beneficial for achieving soft-start of the circuit and avoids the generation of large surge current during startup, resulting in better circuit stability and reliability.

[0045] It should be noted that although devices are described herein as N-channel or P-channel devices, or N-type or P-type doped regions, those skilled in the art will understand that complementary devices are also possible according to the present invention. Those skilled in the art will understand that conductivity type refers to the mechanism by which conductivity occurs, such as conduction through holes or electrons; therefore, conductivity type relates to doping type, such as P-type or N-type, rather than doping concentration. Those skilled in the art will understand that the terms “during,” “when,” and “when…” used herein in relation to circuit operation are not strict terms indicating an action that occurs immediately at the start of a startup action, but rather that there may be one or more small but reasonable delays between the startup action and the reaction action initiated by it, such as various propagation delays. The terms “approximately” or “substantially” used herein mean that an element value has a parameter expected to be close to the declared value or location. However, as is well known in the art, there are always small deviations that make it difficult for the value or location to be strictly the declared value. It has been properly determined in the art that a deviation of at least 10 percent (10%) (or at least 20 percent (20%) for semiconductor doping concentration) is a reasonable deviation from the described accurate ideal target. When used in conjunction with signal states, the actual voltage value or logic state of the signal (e.g., "1" or "0") depends on whether positive or negative logic is used.

[0046] Furthermore, it should be noted that relational terms such as "first" and "second" used herein are merely used to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0047] As described above, these embodiments of the present invention do not exhaustively describe all details, nor do they limit the invention to specific embodiments. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to effectively utilize the invention and its modifications. The scope of protection of this invention should be determined by the scope defined in the claims of this invention.

Claims

1. A switched capacitor converter, comprising: Four switches connected in series between the input voltage and ground; The flying capacitor has its first end coupled to the first node between the first and second switches of the four switches, and its second end coupled to the second node between the third and fourth switches of the four switches. A first driver is configured to output a first drive signal according to a first control signal; The soft-start circuit is configured to output a second drive signal that gradually increases over time according to the first control signal; as well as The switching circuit is configured to couple the gate of the first switch to the soft-start circuit during a soft-start period, and to couple the gate of the first switch to the first driver during an operating period. The soft-start circuit includes: A current generation module and a first transistor are coupled between the first voltage signal and the first node. The current generation module is used to generate an output current that increases with time. The gate and drain of the first transistor are coupled together and used to generate the second drive signal based on the output current.

2. The switched capacitor converter according to claim 1, wherein, The current generation module includes: A current source array includes multiple first current sources and switches. First terminals of the multiple first current sources are coupled to a first voltage signal, second terminals of the multiple first current sources are respectively coupled to the first terminals of corresponding switches, and second terminals of the multiple switches are coupled to the output terminals of the output current. A switch control unit is used to generate a switch control signal with multiple binary bits according to the first control signal, wherein each bit of the switch control signal is used to control the switching on and off of the switch of the corresponding branch of the current source array.

3. The switched capacitor converter according to claim 2, wherein, The switch control unit includes: A series of cascaded flip-flops, wherein the data terminal and negative output terminal of each flip-flop are coupled, the positive output terminal is used to output each bit of the switch control signal, the clock terminal of the first flip-flop is used to receive the inverted signal of the first control signal, and the clock terminals of the remaining flip-flops are coupled to the negative output terminal of the previous flip-flop.

4. The switched capacitor converter according to claim 2, wherein, The multiple first current sources in the current source array increase in a binary weighted manner from low to high.

5. The switched capacitor converter according to claim 3, wherein, All of the aforementioned triggers are implemented using D triggers.

6. The switched capacitor converter according to claim 1, wherein, The current generation module includes: A second current source and a first capacitor are coupled between the power supply voltage and ground; The operational amplifier has its positive input terminal coupled to the common terminal of the second current source and the first capacitor; The first transistor has its gate coupled to the output terminal of the operational amplifier and its source coupled to the negative input terminal of the operational amplifier. The first resistor has its first end coupled to the source of the first transistor and its second end grounded. The second transistor has its source coupled to the drain of the first transistor and its gate coupled to the power supply voltage. The third transistor has its gate and drain coupled to the drain of the second transistor, and its source coupled to the first voltage signal; and The fourth transistor has its gate coupled to the gate of the third transistor, its source coupled to the first voltage signal, and its drain coupled to the output terminal of the output current.

7. The switched capacitor converter according to claim 6, wherein, The first transistor and the second transistor are N-type MOSFETs, and the third transistor and the fourth transistor are P-type MOSFETs.

8. The switched capacitor converter according to claim 6, wherein, The second transistor is implemented using a high-voltage transistor.

9. The switched capacitor converter according to claim 1, wherein, Also includes: The second to fourth drivers are configured to drive the second to fourth switches of the four switches respectively according to the second to fourth control signals.

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