A multi-gate drive circuit with dead-time control function

Abstract

This invention is a multi-gate drive circuit with dead-time control. The drive circuit includes a PWM generator (1), a MOS drive network (2), a multi-winding isolation transformer (3), a clamping circuit (4), and a dead-time control circuit (5). The output of the MOS drive network (2) is output to the clamping circuit (4) through the multi-winding isolation transformer (3), and the output signal of the clamping circuit (4) serves as the gate drive signal for the primary side of the LLC-DCX topology. The dead-time control circuit (5) is used to adjust the dead time to achieve soft switching of the LLC-DCX and reduce energy loss during switching. This makes the dead time controllable, provides multiple gate drive signals, reduces drive losses, and improves system stability.

Description

Technical Field

[0001] This invention relates to the gate drive circuit of a high-frequency DC transformer, and more specifically to a multi-channel gate drive circuit with dead-time control function. Background Technology

[0002] Switching power supplies are developing towards higher frequency, higher efficiency, and smaller size. However, the increase in switching frequency leads to a continuous increase in gate loss. In converters with switching frequencies reaching MHz, gate drive loss can no longer be ignored. Reducing gate drive loss can improve the efficiency of the converter and promote the progress of switching power supplies towards higher frequency and higher power density.

[0003] Traditional drive circuits obtain energy from a voltage source and charge the power MOSFET through a resistor. When the power MOSFET discharges, it sends energy to ground, failing to recover energy. Therefore, the higher the switching frequency, the more energy is lost at the gate. Resonant gate drive circuits, on the other hand, return energy to the power supply during discharge, achieving energy recovery. Furthermore, the dead time of the drive waveform output by the gate drive circuit is crucial for achieving soft switching in LLC topologies. Therefore, multi-gate drivers with dead-time control are of significant research value in reducing gate losses and achieving soft switching in topologies. Summary of the Invention

[0004] Technical problem: This invention addresses the shortcomings of existing technologies by proposing a multi-channel gate drive circuit with dead-time control, which makes the dead time controllable, can provide multiple gate drive signals, and at the same time reduces drive losses and improves system stability.

[0005] Technical solution: A multi-gate drive circuit with dead-time control function according to the present invention includes:

[0006] The drive circuit includes a PWM generator, a MOS drive network, a multi-winding isolation transformer, a clamping circuit, and a dead-time control circuit. The gate control signals for the first and second PMOS transistors, which act as drive transistors in the MOS drive network, are provided by the first and second PWM generators and their respective gate drivers. The output of the MOS drive network is output to the clamping circuit via the multi-winding isolation transformer. The output signal of the clamping circuit serves as the primary-side first, second, third, and fourth switches of the LLC-DCX topology, and the secondary-side first... The gate drive signals of the synchronous rectifier, the first synchronous rectifier, the third synchronous rectifier, and the fourth synchronous rectifier drive the primary-side first switch, the second switch, the third switch, and the fourth switch of the LLC-DCX topology, as well as the secondary-side first synchronous rectifier, the first synchronous rectifier, the third synchronous rectifier, and the fourth synchronous rectifier. The gate control signals of the ninth and tenth NMOS transistors in the dead-time control circuit are provided by the third gate driver connected to the third PWM generator. The dead-time control circuit is used to adjust the dead time to achieve soft switching of the LLC-DCX and reduce energy loss during switching.

[0007] The MOS driving network includes a first PMOS transistor and a second PMOS transistor. The sources of both the first and second PMOS transistors are connected to the power supply Vcc. The drain of the first PMOS transistor is connected to the same-name terminal of the first primary winding of the multi-winding isolation transformer, and the drain of the second PMOS transistor is connected to the opposite-name terminal of the third primary winding of the multi-winding isolation transformer.

[0008] The multi-winding isolation transformer has a primary winding comprising a first primary winding, a second primary winding, and a third primary winding. The same-named terminal of the first primary winding is connected to the drain of a first PMOS transistor. The opposite-named terminal of the first primary winding is connected to the gate of a fourth clamping transistor, the drain of the third clamping transistor, the source of a ninth NMOS transistor (which acts as a switch), a second capacitor, and the same-named terminal of the second primary winding. The same-named terminal of the second primary winding is connected to the gate of the fourth clamping transistor, the drain of the third clamping transistor, the source of the ninth NMOS transistor (which acts as a switch), a second capacitor, and the first primary winding. The opposite-named terminal of the first primary winding is connected to the drain of the fourth clamping transistor, the gate of the third clamping transistor, the source of the tenth NMOS transistor (which acts as a switch), the fourth capacitor, and the same-named terminal of the third primary winding. The same-named terminal of the third primary winding is connected to the drain of the fourth clamping transistor, the gate of the third clamping transistor, the source of the tenth NMOS transistor (which acts as a switch), the fourth capacitor, and the opposite-named terminal of the second primary winding. The opposite-named terminal of the third primary winding is connected to the drain of the second PMOS transistor. The same-named terminal of the first primary winding is connected to the gate of the fifth clamping transistor and the third capacitor.

[0009] The multi-winding isolation transformer has a secondary winding comprising a first winding, a second winding, and a third winding. The opposite-named terminal of the first winding is connected to the drain of the fifth clamping transistor. The same-named terminal of the second winding is connected to the drain of the sixth clamping transistor, and the opposite-named terminal of the second winding is connected to the gate of the sixth clamping transistor and the first capacitor. The same-named terminal of the third winding is connected to the gate of the seventh clamping transistor, the drain of the sixth clamping transistor, and the gate equivalent capacitance. The opposite-named terminal of the third winding is connected to the gate of the sixth clamping transistor and the gate equivalent capacitance.

[0010] The clamping circuit includes a third clamping transistor, a fourth clamping transistor, a fifth clamping transistor, a sixth clamping transistor, a seventh clamping transistor, and an eighth clamping transistor; among them,

[0011] The drain of the third clamping transistor is connected to the gate of the fourth clamping transistor, the source of the ninth NMOS transistor, the second capacitor, the opposite terminal of the first primary winding and the same terminal of the second primary winding, and its gate is connected to the drain of the fourth clamping transistor, the source of the tenth NMOS transistor, the fourth capacitor, the opposite terminal of the second primary winding and the same terminal of the fourth primary winding, and its source is grounded.

[0012] The source of the fourth clamping transistor is grounded, and its gate is connected to the drain of the third clamping transistor, the source of the ninth NMOS transistor (which serves as a switch), the second capacitor, the opposite terminal of the first primary winding, and the same terminal of the second primary winding. Its drain is connected to the gate of the third clamping transistor, the source of the tenth NMOS transistor (which serves as a switch), the fourth capacitor, the opposite terminal of the second primary winding, and the same terminal of the third primary winding.

[0013] The drain of the fifth clamping transistor is connected to the opposite terminal of the first winding, the gate is connected to the same terminal of the first winding, and the source is connected to the third capacitor.

[0014] The drain of the sixth clamping transistor is connected to the same-name terminal of the second stage winding, the gate is connected to the opposite-name terminal of the second stage winding, and the source is connected to the first capacitor.

[0015] The source of the seventh clamping transistor is grounded, the gate is connected to the same-name terminal of the third winding and the equivalent capacitance of the second gate, and the drain is connected to the opposite-name terminal of the third winding, the gate of the eighth clamping transistor and the equivalent capacitance of the first gate.

[0016] The source of the eighth clamping transistor is grounded, and its gate is connected to the drain of the seventh clamping transistor, the opposite terminal of the third winding, and the equivalent capacitance of the first gate. Its drain is connected to the same terminal of the third winding, the gate of the seventh clamping transistor, and the equivalent capacitance of the second gate.

[0017] The dead-time control circuit includes a ninth NMOS transistor and a tenth NMOS transistor as switching transistors. The drains of the ninth and tenth NMOS transistors are connected, and the gates of the ninth and tenth NMOS transistors are connected. The source of the ninth NMOS transistor is connected to the drain of the third clamping transistor, the gate of the fourth clamping transistor, the second capacitor, the opposite terminal of the first primary winding, and the same terminal of the second primary winding. The source of the tenth NMOS transistor is connected to the gate of the third clamping transistor, the drain of the fourth clamping transistor, the fourth capacitor, the opposite terminal of the second primary winding, and the same terminal of the third primary winding.

[0018] The same PWM generator, MOS drive network, multi-winding isolation transformer, clamping circuit, and dead-time control circuit as described above are used to drive the switching transistors and rectifier transistors in the LLC-DCX topology.

[0019] LLC-DCX is a series topology of resonant inductor, magnetizing inductor and resonant capacitor at the resonant frequency;

[0020] LLC is a series topology consisting of a resonant inductor, a magnetizing inductor, and a resonant capacitor.

[0021] Beneficial effects: The advantages of this invention are as follows:

[0022] 1) The inductor temporarily stores energy and returns the gate drive energy to the power supply as a current source, which greatly reduces drive loss;

[0023] 2) During the switching state transition, the charging and discharging current has an initial value and does not rise from zero, which enables rapid switching;

[0024] 3) A dead-time control circuit was added, which makes the dead time of the drive signal provided to the topology controllable, avoiding the dead time being too short, the capacitor voltage not being released to zero, and the inability to achieve zero-voltage switching; it also avoids the dead time being too long, which affects the power supply efficiency.

[0025] 4) It has multiple gate drive outputs, which can provide multiple suitable gate drive signals;

[0026] 5) The driving circuit has a simple control timing, requiring only three control timing signals, and timing matching is easy. Attached Figure Description

[0027] Figure 1 This is a schematic diagram of the circuit of the present invention;

[0028] Figure 2 This invention relates to an LLC full-bridge resonant converter circuit.

[0029] Figure 3 This is a timing waveform diagram of the main driving signals in this invention. Detailed Implementation

[0030] like Figure 1 This invention provides a multi-gate drive circuit with dead-time control function.

[0031] like Figure 2 This invention relates to an LLC full-bridge converter. The multi-output drive signal of this invention can provide suitable gate drive signals for the primary-side switching transistors and secondary-side synchronous rectifier transistors of the full-bridge converter, enabling them to function normally.

[0032] Figure 1 The output signals Vgs2, Vgs4, Vgs3, VHB2, Vgs1, VHB1, Vgsr1, Vgsr2 and Figure 2 Corresponding to the gate signal, the first switch S1, the second switch S2, the third switch S3, and the fourth switch S4 constitute a full-bridge topology. The leakage inductance of the transformer is Lr1 and Lr2, the magnetizing inductance of the transformer is Lm1 and Lm2, the resonant capacitor is Cr, the secondary-side synchronous rectifiers are the first synchronous rectifier SR1, the first synchronous rectifier SR2, the third synchronous rectifier SR3, and the fourth synchronous rectifier SR4, the output capacitor is Co, and the load is RL. Before the MOSFETs in the full-bridge are turned on, a dead time state is required to discharge the parasitic capacitance to zero voltage, creating conditions for zero-voltage turn-on. This invention makes the dead time of the provided gate drive signal controllable, meeting the requirements of the LLC topology.

[0033] A multi-gate drive circuit with dead-time control function according to the present invention includes a PWM generator 1, a MOS drive network 2, a multi-winding isolation transformer 3, a clamping circuit 4, and a dead-time control circuit 5. The gate control signals for the first PMOS transistor Q1 and the second PMOS transistor Q2, which serve as drive transistors in the MOS drive network 2, are provided by the first PWM generator PWM1, the second PWM generator PWM2, and the subsequent first gate driver U1 and second gate driver U2, respectively. The output of the MOS drive network 2 is output to the clamping circuit 4 via the multi-winding isolation transformer 3. The output signal of the clamping circuit 4 serves as the primary-side switching transistors S1, S2, S3, and S4 of the LLC-DCX topology. The gate drive signals of the first synchronous rectifier SR1, the first synchronous rectifier SR2, the third synchronous rectifier SR3, and the fourth synchronous rectifier SR4 on the secondary side drive the first switch S1, the second switch S2, the third switch S3, and the fourth switch S4 on the primary side of the LLC-DCX topology, as well as the first synchronous rectifier SR1, the first synchronous rectifier SR2, the third synchronous rectifier SR3, and the fourth synchronous rectifier SR4 on the secondary side. The gate control signals of the ninth NMOS transistor Q9 and the tenth NMOS transistor Q10 in the dead time control circuit 5 are provided by the third gate driver U3 after the third PWM generator PWM3. The dead time control circuit 5 is used to adjust the dead time to realize soft switching of the LLC-DCX and reduce the energy loss during switching.

[0034] The MOS driving network 2 includes a first PMOS transistor Q1 and a second PMOS transistor Q2. The sources of both the first PMOS transistor Q1 and the second PMOS transistor Q2 are connected to the power supply Vcc. The drain of the first PMOS transistor Q1 is connected to the same-name terminal of the first primary winding P1 of the multi-winding isolation transformer 3, and the drain of the second PMOS transistor Q2 is connected to the opposite-name terminal of the third primary winding P3 of the multi-winding isolation transformer 3.

[0035] The multi-winding isolation transformer 3 has a primary winding comprising a first primary winding P1, a second primary winding P2, and a third primary winding P3. The same-named terminal of the first primary winding P1 is connected to the drain of a first PMOS transistor Q1. The opposite-named terminal of the first primary winding P1 is connected to the gate of a fourth clamping transistor Q4, the drain of the third clamping transistor Q3, the source of a ninth NMOS transistor Q9 (which acts as a switch), a second capacitor Cg2, and the same-named terminal of the second primary winding P2. The same-named terminal of the second primary winding P2 is connected to the gate of the fourth clamping transistor Q4, the drain of the third clamping transistor Q3, the source of the ninth NMOS transistor Q9 (which acts as a switch), the second capacitor Cg2, and the first primary winding P1. The opposite-named terminals of the second primary winding P2 are connected to the drain of the fourth clamping transistor Q4, the gate of the third clamping transistor Q3, the source of the tenth NMOS transistor Q10 (which serves as a switch), the fourth capacitor Cg4, and the same-named terminal of the third primary winding P3. The same-named terminal of the third primary winding P3 is connected to the drain of the fourth clamping transistor Q4, the gate of the third clamping transistor Q3, the source of the tenth NMOS transistor Q10 (which serves as a switch), the fourth capacitor Cg4, and the opposite-named terminal of the second primary winding P2. The opposite-named terminal of the third primary winding P3 is connected to the drain of the second PMOS transistor Q2. The same-named terminal of the first primary winding B1 is connected to the gate of the fifth clamping transistor Q5 and the third capacitor Cg3.

[0036] The multi-winding isolation transformer 3 has a secondary winding including a primary winding B1, a secondary winding B2, and a tertiary winding B3. The opposite-named terminal of the primary winding B1 is connected to the drain of the fifth clamping transistor Q5. The same-named terminal of the secondary winding B2 is connected to the drain of the sixth clamping transistor Q6, and the opposite-named terminal of the secondary winding B2 is connected to the gate of the sixth clamping transistor Q6 and the first capacitor Cg1. The same-named terminal of the tertiary winding B3 is connected to the gate of the seventh clamping transistor Q7, the drain of the sixth clamping transistor Q6, and the second gate equivalent capacitance Cgsr2. The opposite-named terminal of the tertiary winding B3 is connected to the gate of the sixth clamping transistor Q6 and the first gate equivalent capacitance Cgsr1.

[0037] Clamping circuit 4 includes a third clamping transistor Q3, a fourth clamping transistor Q4, a fifth clamping transistor Q5, a sixth clamping transistor Q6, a seventh clamping transistor Q7, and an eighth clamping transistor Q8; wherein,

[0038] The drain of the third clamping transistor Q3 is connected to the gate of the fourth clamping transistor Q4, the source of the ninth NMOS transistor Q9, the second capacitor Cg2, the opposite terminal of the first primary winding P1 and the same terminal of the second primary winding P2. Its gate is connected to the drain of the fourth clamping transistor Q4, the source of the tenth NMOS transistor Q10, the fourth capacitor Cg4, the opposite terminal of the second primary winding P2 and the same terminal of the third primary winding P3. Its source is grounded.

[0039] The source of the fourth clamping transistor Q4 is grounded, and its gate is connected to the drain of the third clamping transistor Q3, the source of the ninth NMOS transistor Q9 (which serves as a switch), the second capacitor Cg2, the opposite terminal of the first primary winding P1, and the same terminal of the second primary winding P2. Its drain is connected to the gate of the third clamping transistor Q3, the source of the tenth NMOS transistor Q10 (which serves as a switch), the fourth capacitor Cg4, the opposite terminal of the second primary winding P2, and the same terminal of the third primary winding P3.

[0040] The drain of the fifth clamping transistor Q5 is connected to the opposite terminal of the first winding B1, the gate is connected to the same terminal of the first winding B1, and the source is connected to the third capacitor Cg3.

[0041] The drain of the sixth clamping transistor Q6 is connected to the same-name terminal of the second stage winding B2, the gate is connected to the opposite-name terminal of the second stage winding B2, and the source is connected to the first capacitor Cg1.

[0042] The source of the seventh clamping transistor Q7 is grounded, the gate is connected to the same-name terminal of the third winding B3 and the second gate equivalent capacitance Cgsr2, and the drain is connected to the opposite-name terminal of the third winding B3, the gate of the eighth clamping transistor Q8 and the first gate equivalent capacitance Cgsr1.

[0043] The source of the eighth clamping transistor Q8 is grounded, and its gate is connected to the drain of the seventh clamping transistor Q7, the opposite terminal of the third winding B3, and the first gate equivalent capacitance Cgsr1. Its drain is connected to the same terminal of the third winding B3, the gate of the seventh clamping transistor Q7, and the second gate equivalent capacitance Cgsr2.

[0044] The dead-time control circuit 5 includes a ninth NMOS transistor Q9 and a tenth NMOS transistor Q10 as switching transistors. The drains of the ninth NMOS transistor Q9 and the tenth NMOS transistor Q10 are connected. The gates of the ninth NMOS transistor Q9 and the tenth NMOS transistor Q10 are connected. The source of the ninth NMOS transistor Q9 is connected to the drain of the third clamping transistor Q3, the gate of the fourth clamping transistor Q4, the second capacitor Cg2, the opposite terminal of the first primary winding P1, and the same terminal of the second primary winding P2. The source of the tenth NMOS transistor Q10 is connected to the gate of the third clamping transistor Q3, the drain of the fourth clamping transistor Q4, the fourth capacitor Cg4, the opposite terminal of the second primary winding P2, and the same terminal of the third primary winding P3.

[0045] The first PWM generator PWM1 and the second PWM generator PWM2 control the first PMOS transistor Q1 and the second PMOS transistor Q2, respectively. PWM1 and PWM2 are two signals with a 180-degree phase difference. By changing their duty cycles, a gate drive signal that meets the requirements can be generated. The first PMOS transistor Q1 and the second PMOS transistor Q2 transmit the signal to the multi-winding isolation transformer. The third PWM generator PWM3 controls a dead-time control circuit composed of a switching pair, namely the ninth NMOS transistor Q9 and the tenth NMOS transistor Q10. The dead-time control circuit inserts a dead-time mode when the gate capacitor is fully discharged during the resonance process, thereby changing the dead time of the output gate drive signal. The first capacitor Cg1, the second capacitor Cg2, the third capacitor Cg3, the fourth capacitor Cg4, the first gate equivalent capacitance Cgsr1, and the second gate equivalent capacitance Cgsr2 are gate capacitors used for energy storage and release, and participate in resonance along with the inductor.

[0046] like Figure 3 This is the timing waveform diagram of the main driving signals in the invention, including control signals, current and output voltage signals.

[0047] The waveforms of currents I1 and I4 show that energy recovery and utilization are achieved. The dead time intervals between Vgs4 / Vgsr1 and Vgs2 / Vgsr2, and between Vgs1-VHB3 and Vgs3-VHB2, are used to meet the gate drive signal requirements of the LLC full-bridge converter. Meanwhile, the currents I2, I3, I5, I6, and I7 during switching states do not change from zero but have initial values, indicating that this circuit can switch quickly.

[0048] The working process of this invention is as follows:

[0049] like Figure 3 During the period t0-t1, the voltages on the fourth capacitor Cg4, the first capacitor Cg1, and the first gate equivalent capacitance Cgsr1 are at a high level. The third clamping transistor Q3, the sixth clamping transistor Q6, and the eighth clamping transistor Q8 are turned on. The fourth capacitor Cg4, the first capacitor Cg1, the first gate equivalent capacitance Cgsr1, and the excitation inductance of the transformer resonate. The current forms a resonant path through the third clamping transistor Q3, the sixth clamping transistor Q6, and the eighth clamping transistor Q8. During this process, the energy of the gate capacitor is transferred to the resonant inductor, causing the gate voltage to drop and the current flowing through the resonant inductor to rise. At time t1, the gate capacitor discharges to zero.

[0050] During the period t1-t2, the gate voltages of the ninth NMOS transistor Q9 and the tenth NMOS transistor Q10, which are controlled by dead time, are at a high level. The ninth NMOS transistor Q9 and the tenth NMOS transistor Q10 are turned on, which stops the resonance and lengthens the dead time between the output gate drive signals.

[0051] During the period t2-t3, the inductor current cannot change abruptly. The resonant inductor charges the gate capacitances of the fourth clamping transistor Q4, the fifth clamping transistor Q5, and the seventh clamping transistor Q7, as well as the second capacitor Cg2, the third capacitor Cg3, and the second gate equivalent capacitance Cgsr2, until the fourth clamping transistor Q4, the fifth clamping transistor Q5, and the seventh clamping transistor Q7 are turned on. The second capacitor Cg2, the third capacitor Cg3, the second gate equivalent capacitance Cgsr2, and the transformer inductor resonate, forming a circuit. The energy of the resonant inductor is transferred to the capacitors, and the gate voltage continues to rise until the driving transistor is turned on.

[0052] During the period t3-t4, the current flows through the body diode of the fourth clamping transistor Q4 and the first PMOS transistor Q1 to the power source, realizing energy recovery. Before the inductor current decreases to zero, it continues to flow into the current source.

[0053] During the period t4-t5, the first PMOS transistor Q1 and the fourth clamping transistor Q4 are turned on, the power supply is used to excite the magnetizing inductor, and the current direction is opposite to that during the period t3-t4, thus ending the first half of the cycle.

[0054] The resonance and excitation processes during the second half of the cycle, t5-t10, are similar to those during t0-t5, and together they constitute a complete cycle, forming a loop.

[0055] The waveform generated by the above gate drive circuit is adapted to the gate voltage signal of the LLC full-bridge topology.

Claims

1. A multi-channel gate drive circuit with dead-time control function, characterized in that: The driving circuit includes a PWM generator (1), a MOS driving network (2), a multi-winding isolation transformer (3), a clamping circuit (4), and a dead-time control circuit (5). The gate control signals for the first PMOS transistor (Q1) and the second PMOS transistor (Q2) in the MOS driving network (2) are provided by the first PWM generator (PWM1), the second PWM generator (PWM2), and the subsequent first gate driver (U1) and second gate driver (U2), respectively. The output of the MOS driving network (2) is output to the clamping circuit (4) via the multi-winding isolation transformer (3). The output signal of the clamping circuit (4) serves as the primary-side first switch (S1), second switch (S2), third switch (S3), fourth switch (S4) of the LLC-DCX topology, and the secondary-side first synchronous rectifier. The gate drive signals of the first synchronous rectifier (SR1), the first synchronous rectifier (SR2), the third synchronous rectifier (SR3), and the fourth synchronous rectifier (SR4) drive the primary side first switch (S1), the second switch (S2), the third switch (S3), and the fourth switch (S4) of the LLC-DCX topology, as well as the secondary side first synchronous rectifier (SR1), the first synchronous rectifier (SR2), the third synchronous rectifier (SR3), and the fourth synchronous rectifier (SR4). The gate control signals of the ninth NMOS transistor (Q9) and the tenth NMOS transistor (Q10) in the dead time control circuit (5) are provided by the third gate driver (U3) after the third PWM generator (PWM3). The dead time control circuit (5) is used to adjust the dead time to realize soft switching of the LLC-DCX and reduce the energy loss of the switching state.

2. The multi-channel gate drive circuit with dead-time control function according to claim 1, characterized in that: The MOS driving network (2) includes a first PMOS transistor (Q1) and a second PMOS transistor (Q2). The sources of both the first PMOS transistor (Q1) and the second PMOS transistor (Q2) are connected to the power supply Vcc. The drain of the first PMOS transistor (Q1) is connected to the same-name terminal of the first primary winding (P1) of the multi-winding isolation transformer (3). The drain of the second PMOS transistor (Q2) is connected to the opposite-name terminal of the third primary winding (P3) of the multi-winding isolation transformer (3).

3. The multi-channel gate drive circuit with dead-time control function according to claim 1, characterized in that: The multi-winding isolation transformer (3) has a primary winding comprising a first primary winding (P1), a second primary winding (P2), and a third primary winding (P3). The same-name terminal of the first primary winding (P1) is connected to the drain of the first PMOS transistor (Q1), and the opposite-name terminal of the first primary winding (P1) is connected to the gate of the fourth clamping transistor (Q4), the drain of the third clamping transistor (Q3), the source of the ninth NMOS transistor (Q9) which serves as a switch, the second capacitor (Cg2), and the same-name terminal of the second primary winding (P2). The same-name terminal of the second primary winding (P2) is connected to the gate of the fourth clamping transistor (Q4), the drain of the third clamping transistor (Q3), the source of the ninth NMOS transistor (Q9) which serves as a switch, the second capacitor (Cg2), and the first primary winding (P1). The opposite-named terminal of the second primary winding (P2) is connected to the drain of the fourth clamping transistor (Q4), the gate of the third clamping transistor (Q3), the source of the tenth NMOS transistor (Q10) which serves as a switch, the fourth capacitor (Cg4), and the same-named terminal of the third primary winding (P3); the same-named terminal of the third primary winding (P3) is connected to the drain of the fourth clamping transistor (Q4), the gate of the third clamping transistor (Q3), the source of the tenth NMOS transistor (Q10) which serves as a switch, the fourth capacitor (Cg4), and the opposite-named terminal of the second primary winding (P2); the opposite-named terminal of the third primary winding (P3) is connected to the drain of the second PMOS transistor (Q2); the same-named terminal of the first primary winding (B1) is connected to the gate of the fifth clamping transistor (Q5) and the third capacitor (Cg3).

4. The multi-channel gate drive circuit with dead-time control function according to claim 3, characterized in that: The multi-winding isolation transformer (3) has a secondary winding including a first winding (B1), a second winding (B2), and a third winding (B3). The opposite-named end of the first winding (B1) is connected to the drain of the fifth clamping transistor (Q5). The same-named end of the second winding (B2) is connected to the drain of the sixth clamping transistor (Q6). The opposite-named end of the second winding (B2) is connected to the gate of the sixth clamping transistor (Q6) and the first capacitor (Cg1). The same-named end of the third winding (B3) is connected to the gate of the seventh clamping transistor (Q7), the drain of the sixth clamping transistor (Q6), and the second gate equivalent capacitance (Cgsr2). The opposite-named end of the third winding (B3) is connected to the gate of the sixth clamping transistor (Q6) and the first gate equivalent capacitance (Cgsr1).

5. The multi-channel gate drive circuit with dead-time control function according to claim 1, characterized in that: The clamping circuit (4) includes a third clamping transistor (Q3), a fourth clamping transistor (Q4), a fifth clamping transistor (Q5), a sixth clamping transistor (Q6), a seventh clamping transistor (Q7), and an eighth clamping transistor (Q8); among which, The drain of the third clamping transistor (Q3) is connected to the gate of the fourth clamping transistor (Q4), the source of the ninth NMOS transistor (Q9), the second capacitor (Cg2), the opposite terminal of the first primary winding (P1), and the same terminal of the second primary winding (P2). Its gate is connected to the drain of the fourth clamping transistor (Q4), the source of the tenth NMOS transistor (Q10), the fourth capacitor (Cg4), the opposite terminal of the second primary winding (P2), and the same terminal of the third primary winding (P3). Its source is grounded. The source of the fourth clamping transistor (Q4) is grounded, and its gate is connected to the drain of the third clamping transistor (Q3), the source of the ninth NMOS transistor (Q9) which serves as a switch, the second capacitor (Cg2), the opposite terminal of the first primary winding (P1) and the same terminal of the second primary winding (P2). Its drain is connected to the gate of the third clamping transistor (Q3), the source of the tenth NMOS transistor (Q10) which serves as a switch, the fourth capacitor (Cg4), the opposite terminal of the second primary winding (P2) and the same terminal of the third primary winding (P3). The drain of the fifth clamping transistor (Q5) is connected to the opposite terminal of the first winding (B1), the gate is connected to the same terminal of the first winding (B1), and the source is connected to the third capacitor (Cg3). The drain of the sixth clamping transistor (Q6) is connected to the same-name terminal of the second stage winding (B2), the gate is connected to the opposite-name terminal of the second stage winding (B2), and the source is connected to the first capacitor (Cg1). The source of the seventh clamping transistor (Q7) is grounded, the gate is connected to the same-name terminal of the third winding (B3) and the second gate equivalent capacitance (Cgsr2), and the drain is connected to the opposite-name terminal of the third winding (B3), the gate of the eighth clamping transistor (Q8) and the first gate equivalent capacitance (Cgsr1). The source of the eighth clamping transistor (Q8) is grounded, and its gate is connected to the drain of the seventh clamping transistor (Q7), the opposite terminal of the third winding (B3), and the first gate equivalent capacitance (Cgsr1). Its drain is connected to the same terminal of the third winding (B3), the gate of the seventh clamping transistor (Q7), and the second gate equivalent capacitance (Cgsr2).

6. The multi-channel gate drive circuit with dead-time control function according to claim 1, characterized in that: The dead time control circuit (5) includes a ninth NMOS transistor (Q9) and a tenth NMOS transistor (Q10) as switching transistors. The drains of the ninth NMOS transistor (Q9) and the tenth NMOS transistor (Q10) are connected. The gates of the ninth NMOS transistor (Q9) and the tenth NMOS transistor (Q10) are connected. The source of the ninth NMOS transistor (Q9) is connected to the drain of the third clamping transistor (Q3), the gate of the fourth clamping transistor (Q4), the second capacitor (Cg2), the opposite terminal of the first primary winding (P1), and the same terminal of the second primary winding (P2). The source of the tenth NMOS transistor (Q10) is connected to the gate of the third clamping transistor (Q3), the drain of the fourth clamping transistor (Q4), the fourth capacitor (Cg4), the opposite terminal of the second primary winding (P2), and the same terminal of the third primary winding (P3).

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