Active dc bus voltage equalization circuit

Abstract

The invention relates to an active DC bus voltage equalization circuit. A system has a DC bus circuit with first and second terminals, an intermediate node, a first capacitor, and a second capacitor; a first depletion mode FET and a second depletion mode FET, and a first switch control circuit and a second switch control circuit, wherein: the first depletion mode FET has a drain coupled to the first bus terminal, a source coupled to the intermediate node, and a gate; the second depletion mode FET has a drain coupled to the intermediate node, a source coupled to the second bus terminal, and a gate; the first switch control circuit opens the first depletion mode FET in response to a first capacitor voltage of the first bus capacitor being less than or equal to a second capacitor voltage of the second bus capacitor; and the second switch control circuit opens the second depletion mode FET in response to the first capacitor voltage being greater than or equal to the second capacitor voltage.

Description

Background Technology

[0001] The topics disclosed herein relate to power converters and apparatuses and techniques for equalizing and discharging DC bus capacitors. Bus capacitor voltage equalization is useful in motor drives or other power conversion systems with high-voltage DC bus circuits, for example, when using electrolytic capacitors whose insulation resistance can vary based on applied voltage, temperature, aging, design and manufacturing tolerances, resulting in leakage current. Additionally, when control power is unavailable, DC bus capacitors store charge that is desired to discharge rapidly at lower voltage levels. Summary of the Invention

[0002] In one aspect, a system includes a DC bus circuit having a first bus terminal, a second bus terminal, a first bus capacitor, and a second bus capacitor. The first bus capacitor and the second bus capacitor are coupled in series with each other between the first bus terminal and the second bus terminal, and are coupled to each other at an intermediate node. The system also includes a first depletion-type field-effect transistor (FET) coupled between the first bus capacitor and a first switch control circuit, a second depletion-type FET coupled between the second bus capacitor and the second switch control circuit, and control circuitry configured to control the first depletion-type FET and the second depletion-type FET to equalize the first capacitor voltage of the first bus capacitor and the second capacitor voltage of the second bus capacitor.

[0003] In another aspect, a system includes a DC bus circuit, a first depletion-type FET, a second depletion-type FET, a voltage sensing circuit, a first switch control circuit, and a second switch control circuit. The DC bus circuit has a first bus terminal, a second bus terminal, an intermediate node, a first bus capacitor, and a second bus capacitor. The first bus capacitor has a first terminal coupled to the first bus terminal and a second terminal coupled to the intermediate node. The second bus capacitor has a first terminal coupled to the intermediate node and a second terminal coupled to the second bus terminal. The first depletion-type field-effect transistor (FET) has a drain coupled to the first bus terminal, a source coupled to the intermediate node, and a gate coupled to the intermediate node. The second depletion-type FET has a drain coupled to the intermediate node, a source coupled to the second bus terminal, and a gate coupled to the second bus terminal. The voltage sensing circuit is configured to sense the first capacitor voltage of the first bus capacitor and the second capacitor voltage of the second bus capacitor. The first switch control circuit is configured to turn off the first depletion-type FET in response to the first capacitor voltage being less than or equal to the second capacitor voltage. The second switch control circuit is configured to turn off the second depletion-type FET in response to the first capacitor voltage being greater than or equal to the second capacitor voltage.

[0004] In another aspect, the motor drive includes a rectifier, a DC bus circuit, an inverter, a first depletion-mode FET and a second depletion-mode FET, and control circuitry. The DC bus circuit has a first bus terminal coupled to the output of the rectifier, a second bus terminal coupled to the output of the rectifier, a first bus capacitor, and a second bus capacitor. The first bus capacitor and the second bus capacitor are connected in series between the first bus terminal and the second bus terminal, and are coupled to each other at an intermediate node. The inverter has inputs coupled to the first bus terminal and the second bus terminal, and an output configured to drive a motor load. The first depletion-mode FET is coupled between the first bus capacitor and a first switching control circuit. The second depletion-mode FET is coupled between the second bus capacitor and the second switching control circuit. The control circuitry is configured to control the first depletion-mode FET and the second depletion-mode FET to balance the first bus capacitor and the second bus capacitor. Attached Figure Description

[0005] Figure 1 This is a schematic diagram of a power conversion system with a motor drive device.

[0006] Figure 1A yes Figure 1 A schematic diagram of the bus equalization and discharge control circuit in the system.

[0007] Figure 1B yes Figure 1 A schematic diagram of the voltage sensing circuit in the system.

[0008] Figure 1C yes Figure 1 A schematic diagram of the regulator circuit in the system.

[0009] Figure 1D yes Figure 1 A schematic diagram of the switch control circuit in the system.

[0010] Figure 2 It is shown Figure 1 The flowchart of the system operation.

[0011] Figure 3 and Figure 4 This is a comparison chart of DC bus voltage discharge. Detailed Implementation

[0012] Now, referring to the accompanying drawings, several embodiments or implementations are described below in conjunction with the drawings, in which similar reference numerals are always used to refer to similar elements, and in which various features are not necessarily drawn to scale.

[0013] First refer to Figures 1 to 1D , Figure 1A power conversion system 100 with a motor drive power conversion system 101 is shown. This system receives single-phase or multi-phase AC input power from an external power source 102 and provides single-phase or multi-phase output signals to drive a motor load 104. The example shown receives a three-phase input, but other multi-phase implementations are also possible. The motor drive 101 includes an input filter circuit 106. In one example, the three-phase LCL filter has grid-side inductors L1, L2, and L3 connected to power leads of the power source 102, and converter-side inductors L4, L5, and L6 connected in series. The filter circuit 106 has filter capacitors C connected between the corresponding grid-side and converter-side inductors and a common connection node, which may, but is not required to, be connected to system ground. Although shown with a three-phase LCL filter circuit 106, other alternative circuit configurations, including but not limited to LC filters, can be used. Furthermore, although shown including the input filter circuit 106, it may be omitted or modified in other embodiments.

[0014] The motor drive unit 101 includes a rectifier 110, a DC bus or DC link circuit 120, a bus balancing and discharge control circuit 130, a power supply 140 such as a switch-mode power supply (SMPS), an output inverter 150, and a controller 160 for operating the rectifier 110 and the inverter 150. The rectifier 110 has an output configured to provide a DC bus voltage signal Vdc. In one example, the rectifier 110 is as follows: Figure 1The active front-end (AFE) rectifier is shown in the diagram. In another example, a passive diode-based rectifier is used. In yet another example, the rectifier is a non-regenerative but controlled (e.g., SCR-based) rectifier. DC bus circuit 120 has a first bus terminal 111 coupled to the output of rectifier 110 with a voltage labeled DC+, a second bus terminal 112 coupled to the output of rectifier 110 with a voltage labeled DC-, a first bus capacitor C1, and a second bus capacitor C2. The first bus capacitor C1 and the second bus capacitor C2 are coupled in series with each other between the first bus terminal 111 and the second bus terminal 112, and the bus capacitors C1 and C2 are coupled with each other at an intermediate node 121 with a voltage labeled MID. The first bus capacitor C1 has a first terminal coupled to the first bus terminal 111 and a second terminal coupled to the intermediate node 121. The second bus capacitor C2 has a first terminal coupled to intermediate node 121 and a second terminal coupled to second bus terminal 112. The inverter 150 has inputs coupled to the respective first bus terminal 111 and second bus terminal 112, and an output configured to drive a motor load 104. The first capacitor C1 can be a single capacitor component, or a combination of multiple capacitor components coupled between the first bus terminal 111 and intermediate node 121 in any series and / or parallel configuration. Similarly, the second capacitor C2 can be a single capacitor component, or a combination of multiple capacitor components coupled between intermediate node 121 and second bus terminal 112 in any series and / or parallel configuration. Furthermore, although illustrated in the example with a first equivalent capacitor C1 and a second equivalent capacitor C2, the concept of this disclosure includes other embodiments with more than two equivalent capacitors connected in series between bus terminals 111 and 112, for example, to facilitate higher voltage in medium-voltage power electronic products and systems through voltage equalization and discharge of any integer number of capacitors connected in series among two or more capacitors.

[0015] When system 101 is powered and operated, bus equalization and discharge control circuit 130 operates to equalize the first capacitor voltage VC1 of the first bus capacitor C1 and the second capacitor voltage VC2 of the second bus capacitor C2. Additionally, when system 101 is not powered, or when power supply 140 is off, or when one or more output voltages (e.g., VCCVP or VCCVN) are below their respective thresholds, bus equalization and discharge control circuit 130 causes the corresponding first bus capacitor C1 and second bus capacitor C2 to discharge at a high discharge rate. In one example, bus equalization and discharge control circuit 130 is designed such that the high discharge rate is independent of the presence of power supply, but depends on some other parameter value, such as the DC bus voltage level. When powered and operated, power supply 140 provides output voltage signals VCCVP and VCCVN, and corresponding first output 141 and second output 142 to operate the control circuitry of system 101. Power supply 140 has a reference node coupled to a reference with a voltage labeled REF.

[0016] Controller 160 includes rectifier controller 162 and inverter controller 166. Rectifier controller 162 and inverter controller 166 provide rectifier switch control signals 162a and inverter switch control signals 166a to rectifier 110 and inverter 150, respectively, to operate their respective switches S1 to S6 and S7 to S12. In some implementations, inverter switch controller 166 provides control signals 166a to selectively operate individual inverter switch devices S7 to S12 to provide variable frequency, variable amplitude output to drive motor load 104, and inverter switch controller 166 also provides a set point or desired DC signal or value to rectifier switch controller 162. The rectifier switch controller 162 generates a rectifier switch control signal 162a based on the desired or set point DC signal or value to operate the rectifier switch devices S1-S6 so as to provide a regulated DC voltage Vdc across the DC link capacitors C1 and C2 connected in series in the intermediate DC bus circuit 120.

[0017] The controller 160 and its components can be implemented as any suitable hardware, processor-executed software, processor-executed firmware, logic circuitry, and / or combinations thereof. The illustrated controller 160 can be largely implemented as processor-executed software or firmware providing various control functions. The controller 160 receives feedback and / or input signals and / or values ​​(e.g., setpoints) through these control functions and provides rectifier switch control signals 162a and inverter switch control signals 166a to operate rectifier switching devices S1 to S6 and inverter switches S7 to S12 of the inverter 150 to convert input power for providing AC output power to drive the load 104. Alternatively, the controller 160 and its components can be implemented as a single processor-based device (e.g., a microprocessor, microcontroller, FPGA, etc.), or one or more of the controller 160 and its components can be implemented individually by two or more processor devices in a unified or distributed manner.

[0018] Furthermore, switch controllers 162 and 166 can provide any suitable form of switch control, including providing switch control signals 162a and / or 166a and one or more forms of pulse width modulation (PWM) control in various embodiments. Additionally, switch control components 162 and 166 may include suitable driver circuitry for providing gate control signals to operate transistor-based switching devices S1 to S12.

[0019] The bus equalization and discharge control circuit 130 includes a first depletion-type field-effect transistor (FET) Q1 coupled between a first bus capacitor C1 and a first switch control circuit 131, and a second depletion-type FET Q2 coupled between a second bus capacitor C2 and a second switch control circuit 132. The first depletion-type FET Q1 has a drain coupled to a first bus terminal 111, and a source and gate coupled to an intermediate node 121. The second depletion-type FET Q2 has a drain coupled to an intermediate node 121, and a source and gate coupled to a second bus terminal 112.

[0020] The bus equalization and discharge control circuit 130 includes a corresponding first switch control circuit 131 and a second switch control circuit 132 (in Figure 1 The combination shown below Figure 1A and 1D (further shown in the diagram), corresponding first isolation circuit 133 and second isolation circuit 134 (in Figure 1 The combination shown below Figure 1A and Figure 1D (further shown in the text).

[0021] The bus equalization and discharge control circuit 130 also includes control circuitry with a voltage sensing circuit 136 (labeled VSENSE) and a regulator 138, the voltage sensing circuit 136 having a differential amplifier circuit 137 (labeled DAMP). Control circuits 136, 137, and 138 are configured to control a first depletion-mode FET Q1 and a second depletion-mode FET Q2 to equalize the first capacitor voltage VC1 and the second capacitor voltage VC2 during operation of system 101, and to rapidly discharge bus capacitors C1 and C2 when system 101 is not powered, when power supply 140 is off, or when VCCVP or VCCVN is less than the corresponding threshold.

[0022] Also refer to Figure 1A and Figure 1B The voltage sensing circuit 136 senses the first capacitor voltage VC1 of the first bus capacitor C1 and the second capacitor voltage VC2 of the second bus capacitor C2. Figure 1B An example implementation of voltage sensing circuit 136 is shown. This example voltage sensing circuit 136 includes a first resistive voltage divider circuit formed by resistors R1 and R2 to provide a voltage division representing the voltage DC+ at the first bus terminal 111. A second resistive voltage divider circuit formed by resistors R3 and R4 provides a second voltage division representing the voltage MID at the second bus terminal 112. In this example, the voltage division is stabilized by a capacitor connected in parallel with resistors R2 and R4. Furthermore, in this example, a clamping circuit including an advanced diode clamps the voltage divider output relative to the positive supply voltage VCCVP from the output 141 of the power supply 140 and the negative supply voltage VCCVN relative to the output 142 of the power supply 140. In this example, a stabilizing capacitor is connected across the voltage divider output at the input of a differential amplifier 137. This example differential amplifier 137 includes an operational amplifier having a non-inverting input coupled to the first voltage divider output via a resistor and an inverting input coupled to the second voltage divider output via another resistor. A resistor is coupled between the non-inverting input and the reference REF, and a feedback resistor is coupled between the inverting input and the output of the operational amplifier. The output of the operational amplifier provides the sensor voltage signal VS based on the first capacitor voltage VC1 and the second capacitor voltage VC2. In the example shown, the differential amplifier circuit 137 provides the sensor voltage signal VS based on the difference between the first capacitor voltage VC1 and the second capacitor voltage VC2.

[0023] Figure 1CFurther details of an example implementation of regulator 138 are shown. In this example, regulator 138 is a proportional-integral (PI) controller that receives a sensor voltage signal VS from voltage sensing circuit 136. Regulator 138 in this example includes an operational amplifier with a non-inverting input coupled to the output of voltage sensing circuit 136 via an RC low-pass filter and a second resistor. A capacitor of the low-pass filter is coupled to a second bus terminal 112. The inverting input of the operational amplifier is coupled to the second bus terminal 112 via a resistor. The feedback circuit includes a resistor and a capacitor coupled in series between the inverting input and the output of the operational amplifier. The operational amplifier output of regulator 138 provides a control output voltage signal VO.

[0024] Also refer to Figure 1D In one example, regulator 138 controls the corresponding first depletion-type FET Q1 and second depletion-type FET Q2 based on the sensor voltage signal VS. In the illustrated implementation, control output voltage signal VO is provided to the corresponding first switch control circuit 131 and second switch control circuit 132 via first isolation circuit 133 and second isolation circuit 134 to operate the first depletion-type FET Q1 and second depletion-type FET Q2 during normal operation when power supply 140 is powered and power supply voltage signals VCCVP and VCCVN are provided with appropriate amplitudes.

[0025] During normal power supply operation, regulator 138 provides a control output voltage signal VO based on the sensor voltage signal VS. In one example, the control output voltage signal VO has: a zero amplitude in response to the first capacitor voltage VC1 and the second capacitor voltage VC2 being equal; a positive amplitude in response to the first capacitor voltage VC1 being greater than the second capacitor voltage VC2; and a negative amplitude in response to the first capacitor voltage VC1 being less than the second capacitor voltage VC2. Isolation in the switching control circuit of the control circuit is based on the control output voltage signal VO to control the first depletion-mode FET Q1 and the second depletion-mode FET Q2 to achieve capacitor voltage equalization during normal operation.

[0026] Figure 1D The first isolation circuit 133 includes a first opto-isolator chip or optocoupler (labeled U1) with an input diode, wherein the cathode of the input diode is coupled to the output of the regulator 138 to receive a control output voltage signal VO, and its anode is coupled to the power supply output 141 via a resistor to receive a positive power supply voltage VCCVP. The first opto-isolator chip 133 includes an output bipolar transistor having an emitter, a base that operates according to the current flowing through the diode, and a collector coupled to the source of a first depletion-type FET Q1.

[0027] A first switch control circuit 131 is coupled to a first depletion-type FET Q1 and disconnects the first depletion-type FET Q1 based on a control output voltage signal VO responding to a first capacitor voltage VC1 being less than or equal to a second capacitor voltage VC2. In this example, the first switch control circuit 131 operates to disconnect the first depletion-type FET Q1 in response to the control output voltage signal VO having a zero or negative amplitude. The first switch control circuit 131 includes first and second input terminals coupled to corresponding collector and emitter outputs of a first isolation circuit 133, wherein a resistor is coupled between the first input terminal and the source of the first depletion-type FET Q1. The first switch control circuit 131 includes a first discharge circuit branch comprising a first NPN bipolar transistor T1 coupled between the source of the first depletion-type FET Q1 and an intermediate node 121 and a first discharge resistor. Additionally, the first switch control circuit 131 includes a resistor coupled between the source of the first depletion-type FET Q1 and the intermediate node 121.

[0028] During normal power supply operation of system 101, in response to a positive amplitude control output voltage signal VO, the first switch control circuit 131 controls the gate-source voltage to exceed the negative threshold voltage of the first depletion-type FET Q1, and controls the positive amplitude of the output voltage signal VO to turn on the first NPN bipolar transistor T1 to provide a discharge path for conducting a first discharge current ID1 from the source of the first depletion-type FET Q1, thereby providing controlled discharge of the first bus capacitor C1. The conduction of the first discharge current ID1 causes the first capacitor voltage VC1 to decrease relative to the second capacitor voltage VC2 and tends to make the first capacitor voltage VC1 and the second capacitor voltage VC2 equal. Additionally, when power supply 140 is turned off or when the power supply voltage is below the corresponding threshold voltage of either VCCVP or VCCVN, the depletion-type transistor Q1 remains on to allow any voltage in the first bus capacitor C1 to discharge rapidly.

[0029] The second isolation circuit 134 and the second switch control circuit 132 are in Figure 1D The configuration is similar to that in the example. Figure 1D The second isolation circuit 134 includes a second opto-isolator chip or optocoupler (labeled U2) with an input diode, wherein the anode of the input diode is coupled to the output of the regulator 138 to receive a control output voltage signal VO, and its cathode is coupled to the second power supply output 142 via a resistor to receive a negative power supply voltage VCCVN. The second opto-isolator chip 134 includes an output bipolar transistor having an emitter, a base that operates according to the current flowing through the diode, and a collector coupled to the source of the second depletion-type FET Q2.

[0030] The second switch control circuit 132 is coupled to the second depletion-type FET Q2 and disconnects the second depletion-type FET Q2 in response to the first capacitor voltage VC1 being greater than or equal to the second capacitor voltage VC2. In this example, the second switch control circuit 132 operates to disconnect the second depletion-type FET Q2 in response to the control output voltage signal VO having zero or positive amplitude. The second switch control circuit 132 includes first and second input terminals coupled to corresponding collector and emitter outputs of the second isolation circuit 134, wherein a resistor is coupled between the first terminal and the source of the second depletion-type FET Q2. The second switch control circuit 132 includes a second discharge circuit branch, which includes a second NPN bipolar transistor T2 coupled between the source of the second depletion-type FET Q2 and the intermediate node 121, and a second discharge resistor. Additionally, the second switch control circuit 132 includes a resistor coupled between the source of the second depletion-type FET Q2 and the second bus terminal 112.

[0031] During normal power supply operation of system 101, in response to a negative amplitude control output voltage signal VO, the second switch control circuit 132 controls the gate-source voltage to exceed the negative threshold voltage of the second depletion-type FET Q2, and controls the negative amplitude of the output voltage signal VO to turn on the second NPN bipolar transistor T2 to provide a second discharge path for conducting the second discharge current ID2 from the source of the second depletion-type FET Q2 to the second bus terminal 112. This provides controlled discharge of the second bus capacitor C2. The conduction of the second discharge current ID2 causes the second capacitor voltage VC2 to decrease relative to the first capacitor voltage VC1 and tends to make the second capacitor voltage VC1 and the second capacitor voltage VC2 equal. Additionally, when power supply 140 is turned off or when one or both of the power supply voltages VCCVP or VCCVN are below the corresponding threshold, the depletion-type transistor Q2 remains on to allow any voltage of the second bus capacitor C2 to discharge rapidly.

[0032] Also refer to Figure 2 In one example, bus balancing and discharge control circuitry 130 implements method 200 for rapidly discharging DC bus capacitors C1 and C2 when system 101 is powered down, and additionally provides energy-efficient and cost-effective DC bus voltage balancing during operation of system 101. Furthermore, the use of depletion-mode FETs for discharge and voltage balancing facilitates very rapid discharge, for example, allowing maintenance personnel to perform maintenance on system 101 without having to wait for extended periods. In the illustrated example, the depletion-mode FETs are controlled as active current sinks to balance the DC bus voltage at high DC bus levels and to rapidly discharge DC bus circuitry 120 when no control voltage is present (or the control voltage is low).

[0033] Method 200 includes determining at 202 whether power supply 140 (SMPS) is off or has an output voltage below a corresponding threshold (e.g., supply voltage VCCVP or VCCVN). If the power supply is off or has an output voltage below the corresponding threshold (yes at 202), the first depletion-type transistor Q1 and the second depletion-type transistor Q2 of the bus equalization and discharge control circuit 130 remain on at 204 to allow bus capacitors C1 and C2 to discharge rapidly. Otherwise, if power supply 140 is on and provides sufficient supply voltage (no at 202), method 200 includes selectively operating depletion-type transistors Q1 and Q2 according to a control output voltage signal VO from regulator 138.

[0034] Example method 200 includes determining at 206 whether the control output voltage signal VO is zero, and if the output voltage signal VO is zero (yes at 206), the first capacitor voltage VC1 and the second capacitor voltage VC2 are equalized, and the bus equalization and discharge control circuit 130 disconnects Q1 and Q2 at 208. If the control output voltage signal VO is not zero (no at 206), the bus equalization and discharge control circuit 130 determines at 210 whether the control output voltage signal VO is greater than zero (e.g., positive, indicating VC1 is greater than VC2). If the control output voltage signal VO is greater than zero (yes at 210), the bus equalization and discharge control circuit 130 keeps the second depletion-type transistor Q2 off and turns on the first depletion-type transistor Q1 to discharge the first bus capacitor C1. In one example, the first switch control circuit 131 controls the gate-source voltage of Q1 based on the positive amplitude of the control output voltage signal VO to control the first discharge current ( Figure 1D The amplitude of ID1 in the data.

[0035] Otherwise, the control output voltage signal VO is less than zero (e.g., negative, indicating that VC1 is less than VC2), such as... Figure 2 As indicated at point 214, the bus equalization and discharge control circuit 130 keeps the first depletion-type transistor Q1 off and turns on the second depletion-type transistor Q2 to discharge the second bus capacitor C2. In this example, the second switch control circuit 132 controls the gate-source voltage of Q2 based on the negative amplitude of the control output voltage signal VO to control the second discharge current. Figure 1D The amplitude of ID2 in the data.

[0036] Method 200 returns to 202 as described above and operates continuously to equalize capacitor voltages VC1 and VC2 during normal power supply system operation, and to rapidly discharge the bus capacitors in response to power supply 140 being shut down or having one or more power supply output voltages (VCCVP or VCCVN) below their respective thresholds. Bus capacitor voltage equalization is useful in motor drives or other power conversion systems with high-voltage DC bus circuits, for example, using electrolytic capacitors with insulation resistance that can vary based on applied voltage, temperature, aging, design and manufacturing tolerances, resulting in leakage current. In the absence of capacitor voltage equalization, the equivalent insulation resistance ratio between each column of bus capacitors C1 and C2 connected in series across DC bus terminals 111 and 112 controls capacitor voltages VC1 and VC2.

[0037] For the first bus capacitor C1, if VO > 0, the input current of the first isolation circuit 133 will decrease, its output will be turned off, transistor T1 will turn on, the first discharge current ID1 will increase, and the first depletion-type FET Q1 will turn on to discharge capacitor C1. If VO = 0, the input current of the first isolation circuit 133 will be large enough to turn on the output of the first isolation circuit 133, transistor T1 will turn off, and Q1 will turn off. If VO < 0, the input current of the first isolation circuit 133 will increase, its output will turn on, transistor T1 will turn off, and Q1 will turn off. For the second bus capacitor C2, if VO < 0, the input current of the second isolation circuit 134 will decrease, its output will be turned off, transistor T2 will turn on, the second discharge current ID2 will increase, and the second depletion-type FET Q2 will turn on to discharge capacitor C2. If VO = 0, the input current of the second isolation circuit 134 will be large enough to turn on the output of the second isolation circuit 134, transistor T2 will turn off, and Q2 will turn off. If VO > 0, the input current of the second isolation circuit 134 will increase, then its output will be turned on, transistor T2 will be turned off, and Q2 will be turned off.

[0038] The described examples and other implementations facilitate uniform voltage sharing among each column of capacitors connected in series across the DC bus 120 through the closed-loop operation of regulator 138, and also provide rapid discharge of charge stored in the DC bus capacitors at lower voltage levels when control power is unavailable. The described depletion-type FET balancing and discharging circuit offers advantages over simple external balancing circuits using balancing resistors connected in parallel with each column, which require sufficiently small resistance values ​​to provide voltage balancing in the worst case and are therefore not energy-efficient and dissipate a large amount of unnecessary heat, which is necessarily large and expensive. Furthermore, the parallel discharge capacitors require a long time to discharge the bus capacitors to a safe DC voltage level.

[0039] Figure 3 and Figure 4 The DC bus voltage discharge performance is shown in comparison. Figure 3 Figure 300 shows DC bus voltage curve 301, illustrating the performance of a system using a parallel discharge resistor starting from an initial DC bus voltage of 150V. In this example, the costly, inefficient resistor discharge circuit takes a long time to discharge the DC bus to a safe voltage level, with the bus voltage remaining above 50V after 80 seconds and above 25V after 100 seconds of system shutdown. In this example, maintenance personnel must wait a considerable amount of time (e.g., two minutes or more) before servicing the equipment. Figures 400 and... Figure 4 This is DC bus voltage profile 401, which illustrates the DC bus voltage discharge operation of the aforementioned bus balancing and discharge control circuit 130 using depletion-type FETs Q1 and Q2. In this implementation, the DC bus voltage discharges rapidly and reaches 0V within seconds, thus allowing for quick access by warranty personnel after power-off.

[0040] In the described example, depletion-mode FETs Q1 and Q2 are controlled to conduct only when capacitor voltage equalization is required and when the required minimum current is present, thus providing energy-efficient operation as well as low cost and small form factor advantages. Additionally, as... Figure 3 and Figure 4 As shown, the described example offers a significant advantage in the rapid discharge of DC bus capacitors C1 and C2, particularly at low DC voltage levels when the sink current of the depletion-type FET reaches high or maximum values ​​without the presence of a control supply voltage. Therefore, compared to existing solutions, the described example demonstrates better energy efficiency, lower heat dissipation, faster DC bus discharge time, lower cost, smaller footprint, and better mechanical / reliability performance.

[0041] Various embodiments have been described with reference to the accompanying drawings. Modifications and alterations can be made to these embodiments, and other embodiments can be implemented without departing from the broader scope of the invention as set forth in the appended claims. Therefore, the specification and drawings are to be considered illustrative rather than restrictive. The examples above are merely examples illustrating several possible embodiments of various aspects of this disclosure, wherein equivalent changes and / or modifications will occur to those skilled in the art upon reading and understanding this specification and drawings. Furthermore, although a particular feature of this disclosure may be disclosed only with respect to one of several implementations, such features may be combined as desired and advantageously for any given or particular application with one or more other features of other implementations. Moreover, to a certain extent, the terms “comprising,” “including,” “containing,” “having,” “with,” or variations thereof are used in the detailed description and / or in the claims, such terms are intended to be inclusive in a manner similar to the term “comprising.”

Claims

1. A power conversion system, comprising: The DC bus circuit has a first bus terminal, a second bus terminal, a first bus capacitor and a second bus capacitor. The first bus capacitor and the second bus capacitor are connected in series between the first bus terminal and the second bus terminal, and the first bus capacitor and the second bus capacitor are connected to each other at an intermediate node. A first depletion-type field-effect transistor (FET) coupled between the first bus capacitor and the first switch control circuit; A second depletion-type FET coupled between the second bus capacitor and the second switch control circuit; as well as The control circuit is configured to control the first depletion-mode FET and the second depletion-mode FET to balance the first capacitor voltage of the first bus capacitor and the second capacitor voltage of the second bus capacitor. The control output voltage signal is provided to the corresponding first switch control circuit and second switch control circuit through the first isolation circuit and the second isolation circuit to operate the first depletion FET and the second depletion FET during normal operation.

2. The power conversion system according to claim 1, wherein, The first depletion-mode FET and the second depletion-mode FET are configured to discharge the corresponding first bus capacitor and second bus capacitor in response to the power supply being turned off or to an output voltage less than a threshold.

3. The power conversion system according to claim 2, wherein, The control circuit includes: A voltage sensing circuit is configured to sense the voltage of the first capacitor and the voltage of the second capacitor, and to provide a sensor voltage signal based on the voltage of the first capacitor and the voltage of the second capacitor; and The regulator is configured to control the first depletion-type FET and the second depletion-type FET based on the sensor voltage signal.

4. The power conversion system according to claim 3, wherein, The regulator is a proportional-integral (PI) regulator.

5. The power conversion system according to claim 3, wherein, The regulator is configured to provide the control output voltage signal based on the sensor voltage signal, the control output voltage signal having a zero amplitude in response to the first capacitor voltage and the second capacitor voltage being equal; In response to the first capacitor voltage being greater than the positive amplitude of the second capacitor voltage; And in response to the first capacitor voltage being less than the negative amplitude of the second capacitor voltage.

6. The power conversion system according to claim 5, wherein: The control circuit is configured to control the first depletion-type FET and the second depletion-type FET based on the control output voltage signal; The first switch control circuit is coupled to the first depletion-type FET and is configured to disconnect the first depletion-type FET in response to the control output voltage signal having zero or negative amplitude. as well as The second switch control circuit is coupled to the second depletion-type FET and is configured to disconnect the second depletion-type FET in response to the control output voltage signal having zero amplitude or positive amplitude.

7. The power conversion system according to claim 6, wherein: The drain of the first depletion-type FET is coupled to the first bus terminal; The first switch control circuit includes a first discharge circuit branch coupled between the source of the first depletion-type FET and the intermediate node; The drain of the second depletion-type FET is coupled to the intermediate node; as well as The second switching control circuit includes a second discharge circuit branch coupled between the source of the second depletion-type FET and the second bus terminal.

8. The power conversion system according to claim 7, wherein: The first discharge circuit branch includes a first bipolar transistor coupled between the source of the first depletion-type FET and the intermediate node; as well as The second discharge circuit branch includes a second bipolar transistor coupled between the source of the second depletion-type FET and the second bus terminal.

9. The power conversion system according to claim 2, wherein: The first switch control circuit is configured to disconnect the first depletion-type FET in response to the first capacitor voltage being less than or equal to the second capacitor voltage when the power supply is turned on and the output voltage is greater than or equal to the threshold. as well as The second switch control circuit is configured to disconnect the second depletion-type FET in response to the first capacitor voltage being greater than or equal to the second capacitor voltage when the power supply is turned on and the output voltage is greater than or equal to the threshold.

10. The power conversion system according to claim 1, wherein: The first switch control circuit is configured to disconnect the first depletion-type FET in response to the first capacitor voltage being less than or equal to the second capacitor voltage; as well as The second switch control circuit is configured to disconnect the second depletion-type FET in response to the first capacitor voltage being greater than or equal to the second capacitor voltage.

11. The power conversion system according to claim 10, wherein: The drain of the first depletion-type FET is coupled to the first bus terminal; The first switch control circuit includes a first discharge circuit branch coupled between the source of the first depletion-type FET and the intermediate node; The drain of the second depletion-type FET is coupled to the intermediate node; as well as The second switching control circuit includes a second discharge circuit branch coupled between the source of the second depletion-type FET and the second bus terminal.

12. The power conversion system according to claim 11, wherein: The first discharge circuit branch includes a first bipolar transistor coupled between the source of the first depletion-type FET and the intermediate node; as well as The second discharge circuit branch includes a second bipolar transistor coupled between the source of the second depletion-type FET and the second bus terminal.

13. The power conversion system according to claim 1, wherein, The control circuit includes: A voltage sensing circuit is configured to sense a first capacitor voltage of the first bus capacitor and a second capacitor voltage of the second bus capacitor, and to provide a sensor voltage signal based on the first capacitor voltage and the second capacitor voltage; and The regulator is configured to control the first depletion-type FET and the second depletion-type FET based on the sensor voltage signal.

14. The power conversion system according to claim 13, wherein, The regulator is configured to provide the control output voltage signal based on the sensor voltage signal, the control output voltage signal having a zero amplitude in response to the first capacitor voltage and the second capacitor voltage being equal; In response to the first capacitor voltage being greater than the positive amplitude of the second capacitor voltage; And in response to the first capacitor voltage being less than the negative amplitude of the second capacitor voltage.

15. The power conversion system according to claim 14, wherein: The first switch control circuit is coupled to the first depletion-type FET and is configured to disconnect the first depletion-type FET in response to the control output voltage signal having zero or negative amplitude. as well as The second switch control circuit is coupled to the second depletion-type FET and is configured to disconnect the second depletion-type FET in response to the control output voltage signal having zero amplitude or positive amplitude.

16. A power conversion system, comprising: A DC bus circuit has a first bus terminal, a second bus terminal, an intermediate node, a first bus capacitor, and a second bus capacitor. The first bus capacitor has a first terminal coupled to the first bus terminal and a second terminal coupled to the intermediate node. The second bus capacitor has a first terminal coupled to the intermediate node and a second terminal coupled to the second bus terminal. A first depletion-type field-effect transistor (FET) has a drain coupled to the first bus terminal, a source coupled to the intermediate node, and a gate. The second depletion-type FET has a drain coupled to the intermediate node, a source coupled to the second bus terminal, and a gate. A voltage sensing circuit is configured to sense a first capacitor voltage of the first bus capacitor and a second capacitor voltage of the second bus capacitor; A first switch control circuit is configured to disconnect the first depletion-type FET in response to the first capacitor voltage being less than or equal to the second capacitor voltage. as well as A second switching control circuit is configured to disconnect the second depletion-type FET in response to the first capacitor voltage being greater than or equal to the second capacitor voltage. The control output voltage signal is provided to the corresponding first switch control circuit and second switch control circuit through the first isolation circuit and the second isolation circuit to operate the first depletion FET and the second depletion FET during normal operation.

17. The power conversion system according to claim 16, wherein: The first switch control circuit includes a first discharge circuit branch coupled between the source of the first depletion-type FET and the intermediate node; as well as The second switching control circuit includes a second discharge circuit branch coupled between the source of the second depletion-type FET and the second bus terminal.

18. The power conversion system according to claim 17, wherein: The first discharge circuit branch includes a first bipolar transistor coupled between the source of the first depletion-type FET and the intermediate node; as well as The second discharge circuit branch includes a second bipolar transistor coupled between the source of the second depletion-type FET and the second bus terminal.

19. The power conversion system according to claim 16, wherein, The first depletion-mode FET and the second depletion-mode FET are configured to discharge the corresponding first bus capacitor and the corresponding second bus capacitor in response to the power supply being turned off or to an output voltage less than a threshold.

20. A motor drive device, comprising: A rectifier with output; The DC bus circuit has a first bus terminal coupled to the output of the rectifier, a second bus terminal coupled to the output of the rectifier, a first bus capacitor and a second bus capacitor, the first bus capacitor and the second bus capacitor being connected in series between the first bus terminal and the second bus terminal, and the first bus capacitor and the second bus capacitor being coupled to each other at an intermediate node. An inverter having an input coupled to the first bus terminal and the second bus terminal and an output configured to drive a motor load; A first depletion-type field-effect transistor (FET) coupled between the first bus capacitor and the first switch control circuit; A second depletion-type FET coupled between the second bus capacitor and the second switch control circuit; as well as The control circuit is configured to control the first depletion-mode FET and the second depletion-mode FET to balance the first capacitor voltage of the first bus capacitor and the second capacitor voltage of the second bus capacitor. The control output voltage signal is provided to the corresponding first switch control circuit and second switch control circuit through the first isolation circuit and the second isolation circuit to operate the first depletion FET and the second depletion FET during normal operation.

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