A circuit and method for smoothing and stabilizing the reference voltage in soft-start of a voltage converter.

Abstract

A circuit for smoothing and stabilizing the soft-start reference voltage of a voltage converter is characterized by comprising a soft-start voltage generation unit, a pre-stage reference voltage generation unit, and a step elimination unit. The soft-start voltage generation unit, based on a soft-start capacitor, achieves a smooth rise in the soft-start voltage. The pre-stage reference voltage generation unit, connected to the soft-start voltage generation unit, receives the soft-start voltage from the soft-start voltage generation unit and generates a pre-stage reference voltage based on the soft-start voltage. The step elimination unit, connected to the pre-stage reference voltage generation unit, is used to conduct after the pre-stage reference voltage is output, thereby eliminating the step in the pre-stage reference voltage and outputting the reference voltage. This invention can also effectively overcome the influence of process corners during chip manufacturing, expand the range of component selection, and improve the smoothness of the reference voltage.

Description

Technical Field

[0001] This invention relates to the field of integrated circuits, and more specifically, to a circuit and method for smoothing and stabilizing the reference voltage during the soft-start process of a voltage converter. Background Technology

[0002] With the increasing demand for power, voltage converter circuits are widely used in various integrated circuits, such as power chips for electronic devices, everyday lighting, and household appliances. The operating modes of voltage converters can be categorized based on the state of the current in the magnetizing inductor into continuous conduction mode (CCM), boundary conduction mode (BCM), and discontinuous conduction mode. With the development of voltage converter circuits, existing technologies have developed circuits that switch between multiple conduction modes based on different load conditions or other parameters.

[0003] In existing technologies, a soft-start method for smooth output voltage startup has been introduced to mitigate overshoot and surge phenomena during the startup process. During soft-start, the feedback voltage rises slowly and smoothly in sync with the reference voltage, thereby stabilizing the circuit output. Therefore, a smooth startup of the reference voltage is crucial for the stability of the circuit output.

[0004] However, most current soft-start circuits do not address the startup process of the reference voltage, leading to a step-like rise in the reference voltage, which in turn causes a step-like rise in the output voltage. Additionally, some existing technologies use a soft-start voltage to achieve a smooth rise in the reference voltage; however, this method suffers from a threshold voltage inherent in the switching transistor receiving the soft-start voltage, causing the reference voltage to jump directly from 0V to above the switching transistor's threshold voltage during the initial soft-start phase.

[0005] To solve the above problems, there is an urgent need for a circuit that provides a smooth and stable soft-start reference voltage for voltage converters. Summary of the Invention

[0006] To address the shortcomings of existing technologies, the present invention aims to provide a circuit for smoothing and stabilizing the soft-start reference voltage of a voltage converter. This is achieved by continuously adding two NMOS transistors after the switch receiving the soft-start voltage, thereby eliminating the step of the reference voltage.

[0007] The present invention adopts the following technical solution.

[0008] In a first aspect, the present invention relates to a circuit for smoothing and stabilizing a soft-start reference voltage in a voltage converter, wherein the circuit includes a soft-start voltage generation unit, a pre-stage reference voltage generation unit, and a step elimination unit; the soft-start voltage generation unit, based on a soft-start capacitor, achieves a smooth rise in the soft-start voltage; the pre-stage reference voltage generation unit, connected to the soft-start voltage generation unit, receives the soft-start voltage from the soft-start voltage generation unit and generates a pre-stage reference voltage based on the soft-start voltage; the step elimination unit, connected to the pre-stage reference voltage generation unit, is used to turn on after the pre-stage reference voltage is output, thereby eliminating the step of the pre-stage reference voltage and outputting the reference voltage.

[0009] Preferably, the soft-start voltage generation unit includes a charging current source and a soft-start capacitor; wherein, one end of the charging current source Icharge is connected to the power supply voltage Vdd, and the other end is connected to the soft-start voltage terminal SS; the soft-start capacitor has one end connected to the soft-start voltage terminal SS, and the other end grounded.

[0010] Preferably, the front-end reference voltage generation unit includes a bias current source Ibias, a PMOS transistor PM1, a first resistor R1, a second resistor R2, an NMOS transistor NM2, and a voltage regulator capacitor C1. One end of the bias current source Ibias is connected to the power supply voltage Vdd, and the other end is connected to the source of the PMOS transistor PM1. The gate of the PMOS transistor PM1 is connected to the soft-start voltage terminal SS, and its drain is grounded through the first resistor R1. The gate of the NMOS transistor NM2 is connected to the other end of the bias current source Ibias and the source of the PMOS transistor PM1. Its drain is connected to the power supply voltage Vdd through the second resistor R2, and its source serves as the output terminal of the front-end reference voltage generation unit, and is grounded after passing through the voltage regulator capacitor C1.

[0011] Preferably, the step elimination unit includes an NMOS transistor NM3 and a voltage regulator capacitor C2; wherein, the gate of the NMOS transistor NM3 is connected to the output terminal of the preceding reference voltage generation unit, the source serves as the output terminal of the reference voltage Vref, and is grounded through the voltage regulator capacitor C2, and the drain of the NMOS transistor NM3 is connected to the reference voltage source REF.

[0012] Preferably, when the sum of the soft-start voltage and the gate-source voltage difference of PMOS transistor PM1 does not reach the threshold turn-on voltage of NMOS transistor NM2, NM2 is turned off and the circuit does not output the front-end reference voltage; when the sum of the soft-start voltage and the gate-source voltage difference of PMOS transistor PM1 reaches the threshold turn-on voltage of NMOS transistor NM2, NM2 is turned on and the circuit outputs the front-end reference voltage.

[0013] Preferably, when NM2 is turned on and the preceding stage reference voltage is less than the threshold opening voltage of NM3, NM3 is turned off and the circuit does not output a reference voltage; when NM2 is turned on and the preceding stage reference voltage is greater than the threshold opening voltage of NM3, NM3 is turned on and the circuit outputs a reference voltage.

[0014] Preferably, the magnitude of the reference voltage is linearly related to the magnitude of the soft-start voltage, and the increments are equal.

[0015] Preferably, the soft-start voltage is V. ref =V ss +|V gs1 |-V gs2 -V gs3 Among them, V ss This is the soft-start voltage, V gs1 V gs2 and V gs3 The gate-source voltages of PM1, NM2, and NM3 are respectively equal to the threshold turn-on voltages V of PM1, NM2, and NM3. th1 V th2 and V th3 .

[0016] Preferably, the circuit still satisfies V despite the influence of process angle. th2 <|V th1 |<V th2 +V th3 and V gs2 <|V gs1 |<V gs2 +V gs3 .

[0017] In a second aspect of the present invention, a method for smoothing and stabilizing a reference voltage during soft-start of a voltage converter is provided, wherein the method is implemented using a circuit for smoothing and stabilizing a reference voltage during soft-start of a voltage converter as described in the first aspect of the present invention.

[0018] The beneficial effects of this invention are that, compared with the prior art, the circuit for smoothing and stabilizing the soft-start reference voltage of a voltage converter in this invention can eliminate the reference voltage step by continuously adding two NMOS transistors after the switching transistor receiving the soft-start voltage. This allows the reference voltage to accurately follow the increase of the soft-start voltage and increase smoothly, providing a good reference for the voltage converter. In addition, this invention can also effectively overcome the influence of process corners in chip manufacturing, expand the range of component selection, and improve the smoothness of the reference voltage. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of the structure of a BUCK circuit in the prior art;

[0020] Figure 2 This is a schematic diagram showing the timing changes of inductor current and MOSFET voltage in a BUCK circuit operating in CCM state in the prior art.

[0021] Figure 3 This is a schematic diagram of the current feedback unit in a BUCK circuit in the prior art.

[0022] Figure 4 This is a schematic diagram of a voltage converter soft-start reference voltage generation circuit in the prior art.

[0023] Figure 5 This is a schematic diagram illustrating the time-varying reference voltage generated by a voltage converter soft-start reference voltage generation circuit in the prior art.

[0024] Figure 6 This is a schematic diagram of the circuit for smoothing and stabilizing the soft-start reference voltage of a voltage converter according to the present invention;

[0025] Figure 7 This is a schematic diagram illustrating the time-varying reference voltage generated by a circuit that smoothly stabilizes the soft-start reference voltage of a voltage converter according to the present invention. Detailed Implementation

[0026] The present application will be further described below with reference to the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solutions of the present invention, and should not be construed as limiting the scope of protection of the present application.

[0027] Figure 1 This is a schematic diagram of a BUCK (step-down voltage converter) circuit in the prior art of this invention. Figure 1 As shown, a BUCK circuit includes an upper transistor S1 and a lower transistor S2 that switch between on and off modes, as well as an inductor L, a capacitor Cout, and a resistor Rout. As the two transistors switch continuously, the circuit generates an output voltage Vout and an inductor current I. L . Figure 1 In this context, FB is the feedback voltage achieved by the two voltage divider resistors Rup and Rdown, and its function is to... Figure 3 This will be explained together.

[0028] Figure 2 This is a schematic diagram illustrating the timing changes of inductor current and MOSFET voltage in a BUCK circuit operating in CCM (Continuous Conduction Mode) mode, according to the prior art of this invention. When the circuit is in CCM mode, the circuit continuously conducts, the inductor current continuously increases and decreases, and the upper and lower transistors also sequentially turn on and off without interval.

[0029] Figure 3This is a schematic diagram of the current control unit in a BUCK circuit according to the prior art of this invention. Figure 3 As shown, when the circuit operates in a common peak current control mode, it includes a current control unit, which may include an error amplifier, a PWM unit, etc. The error amplifier generates an error amplification signal based on the magnitudes of the reference voltage Vref and the feedback voltage Vfb. By comparing this signal with the inductor current from the inductor feedback, this unit enables feedback control of the BUCK circuit. Specifically, the difference between the reference voltage Vref and the feedback voltage Vfb positively influences the magnitude of the peak inductor current Ipeak.

[0030] Figure 4 This is a schematic diagram of a soft-start reference voltage generation circuit for a voltage converter in the prior art. Figure 4 As shown, in the prior art, in order for the voltage converter to have a smoothly rising output voltage during the soft-start process, the reference voltage Vref should also be able to rise smoothly during the soft-start process.

[0031] In existing technologies, the soft-start voltage terminal is typically connected to the gate of PM1 transistor, allowing PM1 to conduct based on the gradually increasing soft-start current generated by capacitor Css at point SS. Since the source and drain of PM1 are connected to the bias current source and the first resistor, respectively, PM1 can be in a critical conduction state with a stable small current and drain voltage. When PM1 is stable, its gate-source voltage difference is approximately equal to its threshold voltage. Because NM2 is also in a critical conduction state based on appropriate device selection, it will also conduct with a small current after PM1 is turned on. The capacitor at its source stabilizes the current and voltage output by NM2. REF can serve as a stable reference voltage source, providing a reference for the generation of the Vref voltage.

[0032] During soft-start operation, the current flowing through the source and drain of PM1 and NM2 is very small. This ensures that the source-drain voltage of PM1 and NM2 remains approximately equal to their threshold voltages during conduction. To ensure that the circuit can output a reference voltage when the soft-start voltage is very small, and that the output reference voltage Vref does not experience a step, it is generally advisable to set the threshold voltages of PM1 and NM2 to be equal, or the threshold voltage of NM2 to be slightly less than that of PM1, during equipment selection. If the threshold voltage of NM2 is greater than that of PM1, NM2 may only conduct when SS is very large, resulting in a high step for Vref.

[0033] However, due to the influence of chip process technology, it is difficult to ensure that the threshold turn-on voltages of NM2 and PM1 are exactly equal during chip manufacturing. A situation may occur where, for example, when the threshold turn-on voltage of PM1 is 0V, the threshold turn-on voltage of NM2 is approximately 0.3V. Figure 5 This is a schematic diagram illustrating the time-varying reference voltage generated by a soft-start reference voltage generation circuit for a voltage converter, as described in the prior art. Figure 5 The reference voltage is V when both transistors are conducting. ss +V gs1 -V gs2 That is, V ss -0.3V. Therefore, NM2 will only be turned on when Vss reaches the threshold turn-on voltage of NM2, which is 0.3V or higher, causing a sudden increase in Vref output by NM2, resulting in a step voltage jump. To prevent this problem, this invention provides a new circuit for smoothing and stabilizing the soft-start reference voltage of a voltage converter, which can effectively overcome the influence of process corners during chip manufacturing, expand the range of component selection, and improve the smoothness of the reference voltage.

[0034] Figure 6 This is a schematic diagram of the circuit structure for smoothing and stabilizing the soft-start reference voltage of a voltage converter according to the present invention. Figure 6 As shown, a circuit for smoothing and stabilizing the soft-start reference voltage of a voltage converter is disclosed. The circuit includes a soft-start voltage generation unit, a pre-stage reference voltage generation unit, and a step elimination unit. The soft-start voltage generation unit, based on a soft-start capacitor, achieves a smooth rise in the soft-start voltage. The pre-stage reference voltage generation unit, connected to the soft-start voltage generation unit, receives the soft-start voltage from the soft-start voltage generation unit and generates the pre-stage reference voltage based on the soft-start voltage. The step elimination unit, connected to the pre-stage reference voltage generation unit, is used to conduct after the pre-stage reference voltage is output, thereby eliminating the step of the pre-stage reference voltage and outputting the reference voltage.

[0035] In the method of this invention, the soft-start reference voltage stabilization circuit of the voltage converter includes not only a soft-start voltage generation unit and a front-stage reference voltage generation unit, but also a step elimination unit. This step elimination unit, based on existing technology, fully recognizes the problem that component selection in existing technologies cannot achieve an ideal state under the influence of process angles, and improves the circuit so that the reference voltage is slowly output only after PM1 is fully turned on, and gradually increases from 0V.

[0036] Preferably, the soft-start voltage generation unit includes a charging current source and a soft-start capacitor; wherein, one end of the charging current source Icharge is connected to the power supply voltage Vdd, and the other end is connected to the soft-start voltage terminal SS; the soft-start capacitor has one end connected to the soft-start voltage terminal SS, and the other end grounded.

[0037] The soft-start voltage generation unit of the present invention includes a charging current source for charging a soft-start capacitor. This current source can be a built-in current source Icharge in the voltage converter. Furthermore, the capacitance value of the soft-start capacitor can be designed to be relatively large, enabling the capacitor to achieve a stable and gradual increase in the soft-start voltage.

[0038] Preferably, the front-end reference voltage generation unit includes a bias current source Ibias, a PMOS transistor PM1, a first resistor R1, a second resistor R2, an NMOS transistor NM2, and a voltage regulator capacitor C1. One end of the bias current source Ibias is connected to the power supply voltage Vdd, and the other end is connected to the source of the PMOS transistor PM1. The gate of the PMOS transistor PM1 is connected to the soft-start voltage terminal SS, and its drain is grounded through the first resistor R1. The gate of the NMOS transistor NM2 is connected to the other end of the bias current source Ibias and the source of the PMOS transistor PM1. Its drain is connected to the power supply voltage Vdd through the second resistor R2, and its source serves as the output terminal of the front-end reference voltage generation unit, and is grounded after passing through the voltage regulator capacitor C1.

[0039] In this invention, the front-end reference voltage generation unit can output the soft-start voltage through the common function of PM1 and NM2. Additionally, the bias current source and the first capacitor stabilize the states of PM1 and NM2 at the critical conduction state, ensuring their threshold turn-on voltage is sufficiently small. Specifically, the threshold turn-on voltage of PM1 is sufficiently small because the bias current source Ibias is set sufficiently small, and the voltage division of R1 is essentially constant. Therefore, the source-drain current of PMOS transistor PM1 is small, resulting in a small threshold turn-on voltage for PM1.

[0040] In addition, since the slow charging current of the first capacitor C1 is also very small, the threshold turn-on voltage of NM2 is also small enough.

[0041] In addition, the first resistor R1 and the second resistor R2 can limit the current to prevent damage to the internal components of the chip when electrostatic discharge occurs.

[0042] Preferably, the step elimination unit includes an NMOS transistor NM3 and a voltage regulator capacitor C2; wherein, the gate of the NMOS transistor NM3 is connected to the output terminal of the preceding reference voltage generation unit, the source serves as the output terminal of the reference voltage Vref, and is grounded through the voltage regulator capacitor C2, and the drain of the NMOS transistor NM3 is connected to the reference voltage source REF.

[0043] It is understood that the step elimination unit in this invention is actually an additional NMOS transistor and a second capacitor to stabilize the transistor.

[0044] Having described the main structure of the circuit above, the following section explains its operating principle.

[0045] Preferably, when the sum of the soft-start voltage and the gate-source voltage difference of PMOS transistor PM1 does not reach the threshold turn-on voltage of NMOS transistor NM2, NM2 is turned off and the circuit does not output the front-end reference voltage; when the sum of the soft-start voltage and the gate-source voltage difference of PMOS transistor PM1 reaches the threshold turn-on voltage, NM2 is turned on and the circuit outputs the front-end reference voltage.

[0046] Understandably, as mentioned above, in order to prevent the front-end reference voltage from stepping once it is output due to the final conduction of PM1 caused by process corner deviation, in this invention, PMOS transistor PM1 can be set to the critical conduction state. After PM1 is turned on and the gate voltage of NM2 gradually increases, NM2 will turn on and output a front-end reference voltage that gradually increases from 0.

[0047] Preferably, when NM2 is turned on and the preceding stage reference voltage is less than the threshold opening voltage of NM3, NM3 is turned off and the circuit does not output a reference voltage; when NM2 is turned on and the preceding stage reference voltage is greater than the threshold opening voltage of NM3, NM3 is turned on and the circuit outputs a reference voltage.

[0048] Continuing the analysis, if the current stage reference voltage can be output, Vss may still be insufficient to turn on NM3. Therefore, even if NM2 turns on, NM3 will still not output Vref. However, when Vss continues to increase until NM3 turns on, Vref can be output.

[0049] Preferably, the magnitude of the reference voltage is linearly related to the magnitude of the soft-start voltage, and the increments are equal.

[0050] Although the reference voltage and the soft-start voltage are not necessarily exactly the same, the reference voltage output in this invention changes with the soft-start voltage.

[0051] Preferably, the soft-start voltage is V. ref =V ss +|V gs1 |-V gs2 -V gs3 Among them, V ss This is the soft-start voltage, V gs1 V gs2 and V gs3 Let V be the gate-source voltages of PM1, NM2, and NM3, respectively, and approximately equal to the threshold turn-on voltages V of PM1, NM2, and NM3, respectively. th1 V th2 and V th3 .

[0052] according to Figure 6As can be seen from the circuit diagram, the soft-start voltage can be calculated based on the threshold turn-on voltages of the three MOSFETs in a basically stable state. In this invention, the gate-source voltages V of the three MOSFETs... gs1 V gs2 and V gs3 The threshold turn-on voltage V of PM1, NM2 and NM3 th1 V th2 and V th3 The approximate equality is due to the fact that during the process of the three MOS transistors being turned on and outputting the reference voltage, the source and drain currents of the three transistors are very small, and the threshold voltage is also very small, due to the effect of the bias current source Ibias, the first capacitor C1, and the second capacitor C2 in the circuit mentioned above. Under these circumstances, the gate-source voltage of the transistors is approximately equal to the threshold voltage.

[0053] Preferably, the circuit still satisfies V despite the influence of process angle. th2 <|V th1 |<V th2 +V th3 and V gs2 <|V gs1 |<V gs2 +V gs3 If the above component parameters are set in accordance with V... th2 <|V th1 |<V th2 +V th3 This ensures that even if NM3 only turns on when Vss increases to a high level, Vref will still gradually increase from 0V at the instant NM3 turns on. In other words, during soft-start, when PM1, NM2, and NM3 are in a low-current conduction state, Vref always changes with Vss, but Vref is always less than Vss, and the difference between the two is just enough to turn on all three MOSFETs. This is because the gate-source voltage of the three MOSFETs during operation and the three threshold turn-on voltages V0... th1 V th2 and V th3 Since their sizes are basically equal, V can be approximated. gs2 <|V gs1 |<V gs2 +V gs3 .

[0054] Figure 7 This is a schematic diagram illustrating the time-varying reference voltage generated by the circuit of the present invention, which uses a soft-start reference voltage smoothing and stabilization method for a voltage converter. (Comparison) Figure 5 and Figure 7 It can be clearly seen that Figure 5The 0.3V step at the beginning of the process is completely eliminated. Vref starts from 0V and rises steadily and smoothly, overcoming the Vref step caused by the influence of process angle on the turn-on threshold voltage of the MOSFET.

[0055] A second aspect of the present invention relates to a method for smoothing and stabilizing a reference voltage during soft-start of a voltage converter. This method is implemented using a circuit for smoothing and stabilizing a reference voltage during soft-start of a voltage converter as described in the first aspect of the present invention.

[0056] The beneficial effects of this invention are that, compared with the prior art, the circuit for smoothing and stabilizing the soft-start reference voltage of a voltage converter in this invention can eliminate the reference voltage step by continuously adding two NMOS transistors after the switching transistor receiving the soft-start voltage. This allows the reference voltage to accurately follow the increase of the soft-start voltage and increase smoothly, providing a good reference for the voltage converter. In addition, this invention can also effectively overcome the influence of process corners in chip manufacturing, expand the range of component selection, and improve the smoothness of the reference voltage.

[0057] The applicant of this invention has provided a detailed description of the embodiments of the invention in conjunction with the accompanying drawings. However, those skilled in the art should understand that the above embodiments are merely preferred embodiments of the invention. The detailed description is only intended to help readers better understand the spirit of the invention and is not intended to limit the scope of protection of the invention. On the contrary, any improvements or modifications made based on the inventive spirit of the invention should fall within the scope of protection of the invention.

Claims

1. A circuit for smoothing and stabilizing the reference voltage in soft-start of a voltage converter, characterized in that: The circuit includes a soft-start voltage generation unit, a pre-stage reference voltage generation unit, and a step cancellation unit; wherein... The soft-start voltage generation unit, based on the soft-start capacitor, achieves a smooth rise in the soft-start voltage; The front-end reference voltage generation unit is connected to the soft-start voltage generation unit, receives the soft-start voltage from the soft-start voltage generation unit, and generates the front-end reference voltage based on the soft-start voltage. The step elimination unit is connected to the front-stage reference voltage generation unit and is used to turn on after the front-stage reference voltage is output, thereby eliminating the step of the front-stage reference voltage and outputting the reference voltage. The step cancellation unit includes an NMOS transistor NM3 and a voltage regulator capacitor C2; wherein, the gate of the NMOS transistor NM3 is connected to the output terminal of the front-end reference voltage generation unit, the source serves as the output terminal of the reference voltage Vref, and is grounded through the voltage regulator capacitor C2, and the drain of the NMOS transistor NM3 is connected to the reference voltage source REF.

2. The circuit for smoothing and stabilizing the reference voltage in the soft-start of a voltage converter according to claim 1, characterized in that: The soft-start voltage generation unit includes a charging current source and a soft-start capacitor; wherein... One end of the charging current source Icharge is connected to the power supply voltage Vdd, and the other end is connected to the soft-start voltage terminal SS. One end of the soft-start capacitor is connected to the soft-start voltage terminal SS, and the other end is grounded.

3. The circuit for smoothing and stabilizing the reference voltage in the soft-start of a voltage converter according to claim 2, characterized in that: The front-end reference voltage generation unit includes a bias current source Ibias, a PMOS transistor PM1, a first resistor R1, a second resistor R2, an NMOS transistor NM2, and a voltage-regulating capacitor C1; wherein... One end of the bias current source Ibias is connected to the power supply voltage Vdd, and the other end is connected to the source of the PMOS transistor PM1. The gate of the PMOS transistor PM1 is connected to the soft-start voltage terminal SS, and the drain is grounded through the first resistor R1. The gate of the NMOS transistor NM2 is connected to the other end of the bias current source Ibias and the source of the PMOS transistor PM1. The drain is connected to the power supply voltage Vdd through the second resistor R2. The source serves as the output terminal of the front-end reference voltage generation unit and is grounded after passing through the voltage regulating capacitor C1.

4. The circuit for smoothing and stabilizing the reference voltage in the soft-start of a voltage converter according to claim 3, characterized in that: When the sum of the soft-start voltage and the gate-source voltage difference of the PMOS transistor PM1 does not reach the threshold turn-on voltage of the NMOS transistor NM2, the NM2 is turned off, and the circuit does not output the front-end reference voltage. When the sum of the soft-start voltage and the gate-source voltage difference of the PMOS transistor PM1 reaches the threshold turn-on voltage of the NMOS transistor NM2, the NM2 is turned on, and the circuit outputs the front-end reference voltage.

5. The circuit for smoothing and stabilizing the reference voltage in the soft-start of a voltage converter according to claim 4, characterized in that: When NM2 is turned on and the front-end reference voltage is less than the threshold turn-on voltage of NM3, NM3 is turned off and the circuit does not output a reference voltage. When NM2 is turned on and the preceding reference voltage is greater than the threshold voltage of NM3, NM3 is turned on and the circuit outputs a reference voltage.

6. The circuit for smoothing and stabilizing the reference voltage in soft-start of a voltage converter according to claim 5, characterized in that: The magnitude of the reference voltage is linearly related to the magnitude of the soft-start voltage, and the increments are equal.

7. The circuit for smoothing and stabilizing the reference voltage in soft-start of a voltage converter according to claim 6, characterized in that: The reference voltage is ; wherein, The soft-start voltage is... , and The gate-source voltages of PM1, NM2, and NM3 are respectively equal to the threshold turn-on voltages of PM1, NM2, and NM3. , and .

8. The circuit for smoothing and stabilizing the reference voltage in soft-start of a voltage converter according to claim 7, characterized in that: Despite the influence of process corners, the circuit still satisfies and .

9. A method for smoothing and stabilizing a reference voltage during soft-start of a voltage converter, characterized in that: The method is implemented using a circuit that smoothly stabilizes the reference voltage during the soft-start process of a voltage converter, as described in any one of claims 1-8.

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