Dual output dc-dc boost converter with reduced output leakage

Abstract

The present disclosure relates to a dual output DC-DC boost converter with reduced output leakage. The DC-DC boost converter includes an inductor coupled between an input voltage and an input node, a first path coupled between the input node and a first output node generating a first output voltage, and a second path coupled between the input node and a second output node generating a second output voltage. The DC-DC boost converter operates in a first operating phase in which the first path boosts the first output voltage and in which the second path is prevented from boosting the second output voltage by the second path being coupled to the first path, and the DC-DC boost converter operates in a second operating phase in which the second path boosts the second output voltage and in which the first path is prevented from boosting the first output voltage by the second path being uncoupled from the first path.

Description

Technical Field

[0001] This invention relates to the field of DC-DC boost converters, and more specifically, to a dual-output DC-DC boost converter that utilizes clamping between output lines to reduce output leakage. Background Technology

[0002] DC-DC boost converters are used to increase the input voltage (while decreasing the input current) to generate a high-voltage output. One of the many applications of DC-DC boost converters is in driving piezoelectrically actuated microelectromechanical systems (MEMS) mirror devices. Devices incorporating MEMS mirror devices can utilize two such MEMS mirror devices to scan an incident beam over a target area with a desired two-dimensional scanning pattern.

[0003] Figure 1 The diagram illustrates a known example DC-DC boost converter 1 used in a system for driving a pair of MEMS mirror devices (e.g., a pair of MEMS mirror devices operating at the same or different frequencies). The DC-DC boost converter 1 receives an input voltage Vin via an input inductor L connected to node Nn, generating a voltage SW at node Nn during operation. A first diode D1 is connected between node Nn and a first output capacitor C1, generating a first boost output voltage VBOOSTL across the first output capacitor C1. A first switch S1 is connected between node Nn and ground. The first switch S1 is operated by a drive main control signal Drive_Main_SW. A second diode D2 is connected between node Nn and a second output capacitor C2 via a switch S2 (e.g., an NMOS transistor). A second boost output voltage VBOOSTR (e.g., which may be lower than the first boost output voltage VBOOSTL) is generated across the second output capacitor C2. The NMOS transistor S2 is operated by a drive line control signal Drive_Line_SW.

[0004] Now refer to another source Figure 2 The operation is described, where circuit 1 alternates between the boost voltage VBOOSTL and boost voltage VBOOSTR phases. At the beginning of the VBOOSTL phase, as... Figure 2 As shown, the switch control signal Drive_Main_SW is asserted to close switch S1, thereby grounding node Nn.

[0005] When the switch control signal Drive_Main_SW is deasserted to open switch S1, a boost voltage SW is generated at node Nn, such as... Figure 2 As can be seen, current is transferred to the charging capacitor C1, increasing the voltage VBOOSTL stored on capacitor C1. This is the intention during the VBOOSTL phase.

[0006] At the start of the VBOOSTR phase, the assertion switch control signal Drive_Main_SW closes switch S1, thereby grounding node Nn. The drive line control signal Drive_Line_SW remains asserted throughout the VBOOSTR phase. When the assertion switch control signal Drive_Main_SW opens switch S1, a boost voltage SW is generated at node Nn, as shown below. Figure 2 As can be seen, current is supplied to the charging capacitor C2, increasing the voltage VBOOSTR stored on capacitor C2.

[0007] The problem is that during the VBOOSTL phase, the gate of NMOS transistor S2 is coupled to voltage SW through the parasitic capacitance across the junction of diode D2 and through the parasitic drain-gate capacitance in NMOS transistor S2. As a result, the voltage Vline at the cathode of diode D2 also increases with increasing voltage SW. This increases the voltage seen from the gate of S2, regardless of the drive line control signal Drive_Line_SW, causing S2 to conduct weakly and current to flow into capacitor C2, thus increasing voltage VBOOSTR. This is undesirable because the current flowing into capacitor C2 reduces the current flowing into capacitor C1, and the VBOOSTL phase is designed to charge capacitor C1 to boost VBOOSTL.

[0008] One approach to this problem is to add a second NMOS transistor in series with S2, since the current through S2 charging from its parasitic drain-gate capacitance will be insufficient to charge the parasitic drain-gate capacitance of the added NMOS transistor. However, this increases system complexity, increases the resistance of the path between diode D2 and capacitor C2 during the VBOOSTR phase when the NMOS transistor is on, and increases area consumption. Therefore, further development of the DC-DC boost converter is needed. Summary of the Invention

[0009] This document discloses a device including a DC-DC boost converter. The DC-DC boost converter includes an inductor coupled between an input voltage and an input node, a first path coupled between the input node and a first output node to generate a first output voltage, a second path coupled between the input node and a second output node to generate a second output voltage, and a first switch selectively coupling the second path to the first path in response to a first control signal. The DC-DC boost converter is configured to: operate in the first operating phase, in which the first path boosts the first output voltage, and in the first operating phase, prevent the second path from boosting the second output voltage by asserting the first control signal to cause the first switch to couple the second path to the first path; and operate in the second operating phase, in which the second path boosts the second output voltage, and in the second operating phase, prevent the first path from boosting the first output voltage.

[0010] The first path may include a first diode and a first capacitor, the first diode having an anode coupled to an input node and a cathode coupled to a first output node, the first capacitor being coupled between the first output node and ground, wherein a first output voltage is generated across the first capacitor.

[0011] The second path may include: a second diode having an anode coupled to an input node and a cathode coupled to an intermediate node; a second switch coupled between the intermediate node and the second output node, the second switch being controlled by a second control signal; and a second capacitor coupled between the second output node and ground, wherein a second output voltage is generated across the second capacitor. During a first operating phase, the first switch can selectively couple the intermediate node to the cathode of the first diode, and the second control signal can be asserted during a second operating phase to cause the second switch to selectively couple the intermediate node to the second output node.

[0012] An auxiliary switch can be coupled between the input node and ground. The auxiliary switch is controlled by an auxiliary control signal, which is asserted to close the auxiliary switch during the first portion of the first operating phase and deasserted to open the auxiliary switch during the second portion of the first operating phase. Additionally, the auxiliary control signal can be asserted to close the auxiliary switch during the first portion of the second operating phase and deasserted to open the auxiliary switch during the second portion of the second operating phase.

[0013] The second switch can be an NMOS transistor with its drain coupled to the intermediate node, its source coupled to the second output node, and its gate coupled to receive the second control signal.

[0014] The first switch may be a PMOS transistor, with its source coupled to a first output node, its drain coupled to an intermediate node, and its gate coupled to receive a first control signal.

[0015] A first feedback circuit can be coupled to a first output node, generating a first feedback voltage. A second feedback circuit can be coupled to a second output node, generating a second feedback voltage. The controller can be configured to generate first and second control signals based on the first and second feedback voltages.

[0016] The first driving circuit device can be powered by a first output voltage, and the first micromirror can be driven by the first driving circuit device. The second driving circuit device can be powered by a second output voltage, and the second micromirror can be driven by the second driving circuit device.

[0017] This document also discloses a DC-DC boost converter, comprising a first diode coupled between an input node and a first output node, wherein a first capacitor is coupled between the first output node and ground, such that a first output voltage is generated across the first capacitor. The DC-DC boost converter further includes a first switch coupled between the input node and ground, the first switch being operated by a first control signal; a second diode coupled between the input node and an intermediate node; a second switch coupled between the intermediate node and a second output node, the second switch being operated by a second control signal; wherein a second capacitor is coupled between the output node and ground, such that a second output voltage is generated across the second capacitor. A third switch coupled between the intermediate node and the first output node, the third switch being operated by a third control signal. The controller is configured to generate the first control signal, the second control signal, and the third control signal to: in a first operation phase, close the first switch during a first portion of the first operation phase and open the first switch during a second portion of the first operation phase, open the second switch during the first operation phase, and close the third switch during the first operation phase; and in a second operation phase, close the first switch during a first portion of the second operation phase and open the first switch during a second portion of the second operation phase, close the second switch during the second operation phase, and open the third switch during the second operation phase.

[0018] The second switch can be an NMOS transistor with its drain coupled to the intermediate node, its source coupled to the second output node, and its gate coupled to receive the second control signal.

[0019] The third switch can be a PMOS transistor, with its source coupled to the first output node, its drain coupled to the intermediate node, and its gate coupled to receive a third control signal.

[0020] A first feedback circuit can be coupled to a first output node, generating a first feedback voltage. A second feedback circuit can be coupled to a second output node, generating a second feedback voltage. The controller can be configured to generate first, second, and third control signals based on the first and second feedback voltages.

[0021] The method described herein includes: operating a DC-DC boost controller in a first operating phase, wherein a first path boosts an input voltage to generate a first output voltage, and wherein a second path is prevented from boosting a second output voltage by clamping a second path to the first path; and operating the DC-DC boost controller in a second operating phase, wherein the second path boosts the second output voltage and wherein the first path is prevented from boosting the first output voltage, wherein the second path is not clamped to the first path during the second operating phase.

[0022] The method further includes: charging an inductor coupled to the input voltage during a first portion of the first operation phase, and allowing the inductor to discharge during a second portion of the first operation phase.

[0023] The method further includes: charging the inductor during a first portion of the second operation phase and allowing the inductor to discharge during a second portion of the second operation phase. Attached Figure Description

[0024] Figure 1 This is a schematic diagram of an existing DC-DC boost converter.

[0025] Figure 2 It is shown Figure 1 The graph shows the signal of the DC-DC boost converter during operation.

[0026] Figure 3 This is a block diagram of the driving system for a pair of MEMS mirror devices as disclosed in this paper.

[0027] Figure 4 yes Figure 3 A schematic block diagram of a DC-DC boost converter.

[0028] Figure 5 It is shown Figure 4 The graph shows the signal of the DC-DC boost converter during operation. Detailed Implementation

[0029] The following disclosure enables those skilled in the art to make and use the subject matter disclosed herein. The general principles described herein can be applied to embodiments and applications other than those detailed above without departing from the spirit and scope of this disclosure. This disclosure is not intended to be limited to the embodiments shown, but is consistent with the widest scope of the principles and features disclosed or suggested herein. Note that in the following description, any described resistor or resistor is a discrete device unless otherwise stated, and is not simply an electrical lead between two points. Therefore, any such resistor or resistor coupled between two points has a greater resistance than a lead between those two points, and such resistor or resistor cannot be interpreted as a lead. Similarly, any described capacitor or capacitor is a discrete device unless otherwise stated, and is not parasitic. Furthermore, any described inductor or inductor is a discrete device unless otherwise stated, and is not parasitic.

[0030] Figure 3 The diagram illustrates a drive system 10 for a pair of MEMS mirror devices 14 (e.g., a first MEMS mirror 14a and a second MEMS mirror 14b operating at the same or different frequencies). The drive system 10 can be integrated into a picoprojector, a headset, or a depth sensing system.

[0031] The drive system 10 includes a DC-DC boost converter 11 that receives an input voltage Vin and boosts it to generate two output voltages, VBOOSTL and VBOOSTR. Vin can be in the range of 3.3V, while VBOOSTL can be in the range of 19V to 45V, and VBOOSTR can be in the range of 14V to 40V. The voltage VBOOSTR is fed as input to a low-dropout (LDO) voltage regulator 12a, which provides an output power supply voltage to the driver circuit 13a. The driver circuit 13a uses the power supply voltage generated by the LDO voltage regulator 12a and, under the control of the low-voltage drive control signal LV_Drive_Signal1, generates a high-voltage drive signal HV_Drive_Signal1 for driving the MEMS mirror 14a (e.g., at resonance). The voltage VBOOSTL is fed as input to the low-dropout (LDO) voltage regulator 12b, which provides the output power supply voltage to the driver circuit 13b. The driver circuit 13b uses the power supply voltage generated by the LDO voltage regulator 12b and, under the control of the low-voltage drive control signal LV_Drive_Signal2, generates a high-voltage drive signal HV_Drive_Signal2 (e.g., in a linear manner) to drive the MEMS mirror 14b.

[0032] Now refer to Figure 4 Describes a DC-DC boost converter 11. The DC-DC boost converter 11 receives an input voltage Vin through an input inductor L connected to node Nn, generating a voltage SW at node Nn during operation. The anode of a first diode D1 is connected to node Nn, and its cathode is connected to the first terminal of a first output capacitor C1, generating a first boost output voltage VBOOSTL across the first output capacitor C1. The second terminal of the first output capacitor C1 is grounded. The first terminal of the first output capacitor C1 is grounded through resistors R1 and R2 connected in series, with node N1 being the tap between resistors R1 and R2. A first feedback voltage Fbk1 is generated at node N1.

[0033] The first switch S1 is connected between node Nn and ground. The first switch S1 can be a transistor, such as an NMOS transistor, and is operated by the drive main control signal Drive_Main_SW.

[0034] The anode of the second diode D2 is connected to node Nn, and its cathode is connected to the drain of the second switch S2 (e.g., an NMOS transistor). The source of the NMOS transistor S2 is connected to the first terminal of the second output capacitor C2, and its gate is connected to the drive line control signal Drive_Line_SW. The second terminal of the second output capacitor C2 is grounded. A second boost output voltage VBOOSTR is generated across the second output capacitor C2. The first terminal of the second output capacitor C2 is grounded through resistors R3 and R4 connected in series, with node N2 being the tap between resistors R3 and R4. A second feedback voltage Fbk2 is generated at node N2.

[0035] The source of the third switch S3 (e.g., a PMOS transistor) is connected to the first terminal of the first output capacitor C1, its drain is connected to the cathode of diode D2 and the drain of NMOS transistor S2, and its gate is connected to the drive line SW. Alternatively, S3 can be an NMOS transistor with its drain connected to the first terminal of the first output capacitor C1, its source connected to the cathode of diode D2 and the drain of NMOS transistor S2, and its gate connected to Drive_Neg_Line_SW, where Drive_Neg_Line is the logical inversion of Drive_Line_SW in this example. Control loop 21 has inputs connected to nodes N1 and N2, thereby receiving feedback voltages FBk1 and FBk2 as inputs. Control loop circuit 21 has outputs that generate the drive main control signal Drive_Main_SW and the drive line switch control signal Drive_Line_SW. Control loop 21 generates its outputs based on its inputs to generate the required VBOOSTL and VBOOSTR voltages.

[0036] Now refer to another source Figure 5 The operation is described, in which circuit 11 alternates between the boost voltage VBOOSTL and boost voltage VBOOSTR phases. At the beginning of the VBOOSTL phase, as... Figure 5 As can be seen, asserting Drive_Main_SW closes switch S1, grounding node Nn. This results in a rapid upward surge of current through inductor L, generating a magnetic field and storing energy in inductor L. When Drive_Main_SW is deasserted to open switch S1, the current into inductor L decreases, and the magnetic field strength collapses as the stored energy is converted into current to attempt to sustain the output current from inductor L. Consequently, the left side of inductor L becomes positive, meaning the voltage across inductor L is in series with the input voltage Vin, thus providing a boost voltage SW on the right side of inductor L (node ​​Nin). Figure 5 As can be seen, when switch S1 is open, the voltage SW rises during the VBOOSTL phase. The rise in voltage SW causes diode D1 to become forward biased (because VBOOSTL is already sufficiently tilted downward) and conducts forward current, so current is supplied to charge capacitor C1, increasing the voltage VBOOSTL stored on capacitor C1.

[0037] The drive line switch control signal Drive_Line_SW is deasserted during the VBOOSTL phase. As a result, NMOS transistor S2 remains off, while PMOS transistor S3 is on. The on of transistor S3 clamps the drain of NMOS transistor S2 (and therefore the voltage Vline) to VBOOSTL during the VBOOSTL phase. This prevents diode D2 from becoming forward biased and prevents voltage SW from coupling to the gate of NMOS transistor S2 through the parasitic drain-gate capacitance of S2, thereby keeping NMOS transistor S2 off.

[0038] Therefore, note that in Figure 5 In this configuration, the voltage Vline remains asserted throughout the VBOOSTL phase, the drive line switch control signal Drive_Line_SW remains deasserted throughout the VBOOSTL phase, and VBOOSTR does not boost during the VBOOSTL phase. Therefore, clamping the voltage Vline to the voltage VBOOSTL during the VBOOSTL phase eliminates the capacitive coupling from the voltage SW to the gate of the NMOS transistor S2 present in the prior art. This also has the benefit of virtually eliminating concerns about power-consuming leakage current. Furthermore, it has the benefit of not increasing parasitic resistance, as occurs in prior art designs.

[0039] At the beginning of the VBOOSTR phase, as Figure 5 As can be seen, asserting Drive_Main_SW closes switch S1, grounding node Nn. This results in a rapid upward surge of current through inductor L, generating a magnetic field and storing energy in inductor L. When Drive_Main_SW is deasserted to open switch S1, the current into inductor L decreases, and the magnetic field strength collapses as the stored energy is converted into current to attempt to sustain the output current from inductor L. Consequently, the left side of inductor L becomes positive, meaning the voltage across inductor L is in series with the input voltage Vin, thus providing a boost voltage SW on the right side of inductor L (node ​​Nin). Figure 5 As can be seen, the voltage SW rises during the VBOOSTL phase when switch S1 is open. However, the rise in voltage SW does not cause diode D1 to become forward biased because VBOOSTL has not yet dropped sufficiently for this to happen; therefore, VBOOSTL continues to slope down during the VBOOSTR phase.

[0040] The drive line control signal Drive_Line_SW is asserted during the VBOOSTR phase. As a result, NMOS transistor S2 turns on, and current is supplied to capacitor C2, boosting VBOOSTR during the VBOOSTR phase, as shown. Figure 5 As shown. Since diode D1 does not become forward biased, as mentioned above, VBOOSTL is not boosted during the VBOOSTR stage.

[0041] Finally, it is clear that modifications and changes may be made to the content described and shown herein without departing from the scope of this disclosure as defined by the appended claims.

[0042] Although the invention has been described with respect to a limited number of embodiments, those skilled in the art to which this invention pertains will understand that other embodiments may be conceived without departing from the scope of the invention disclosed herein. Therefore, the scope of this disclosure will be limited only by the appended claims.

Claims

1. A DC-DC boost converter, comprising: A first diode is coupled between an input node and a first output node, wherein a first capacitor is coupled between the first output node and ground, such that a first output voltage is generated across the first capacitor; A first switch is coupled between the input node and ground, and the first switch is operated by a first control signal; A second diode is coupled between the input node and the intermediate node; A second switch is coupled between the intermediate node and the second output node. The second switch is operated by a second control signal. A second capacitor is coupled between the second output node and ground, such that a second output voltage is generated across the second capacitor. A third switch is coupled between the intermediate node and the first output node, and the third switch is operated by a third control signal; The controller is configured to generate the first control signal, the second control signal, and the third control signal so as to: In the first operation phase, the first switch is closed during the first part of the first operation phase and opened during the second part of the first operation phase, the second switch is opened during the first operation phase, and the third switch is closed during the first operation phase. as well as In the second operation phase, the first switch is closed during the first part of the second operation phase and opened during the second part of the second operation phase, the second switch is closed during the second operation phase, and the third switch is opened during the second operation phase.

2. The DC-DC boost converter of claim 1, wherein the second switch comprises an NMOS transistor having a drain coupled to the intermediate node, a source coupled to the second output node, and a gate coupled to receive the second control signal.

3. The DC-DC boost converter of claim 1, wherein the third switch comprises a PMOS transistor having a source coupled to the first output node, a drain coupled to the intermediate node, and a gate coupled to receive the third control signal.

4. The DC-DC boost converter according to claim 1, further comprising: A first feedback circuit is coupled to the first output node, and the first feedback circuit generates a first feedback voltage. as well as The second feedback circuit is coupled to the second output node, and the second feedback circuit generates a second feedback voltage. The controller is configured to generate the first control signal, the second control signal, and the third control signal based on the first feedback voltage and the second feedback voltage.

5. A method for operating a DC-DC boost controller, wherein the DC-DC boost controller is a DC-DC boost converter according to claim 1, the method comprising: The DC-DC boost controller is operated in the first operation phase, in which the first path boosts the input voltage to generate the first output voltage, and in the first operation phase, the second path is prevented from boosting the second output voltage by clamping the second path to the first path. as well as The DC-DC boost controller is operated in the second operation phase, in which the second path boosts the second output voltage, and in which the first path is prevented from boosting the first output voltage, wherein the second path is not clamped to the first path during the second operation phase.

6. The method for operating a DC-DC boost controller according to claim 5, further comprising: In the first operation phase, the inductor coupled to the input voltage is charged during a first portion of the first operation phase, and the inductor is allowed to discharge during a second portion of the first operation phase.

7. The method for operating a DC-DC boost controller according to claim 6, further comprising: In the second operation phase, the inductor is charged during the first part of the second operation phase and the inductor is allowed to discharge during the second part of the second operation phase.

8. A device including a DC-DC boost controller, wherein, The DC-DC boost controller is the DC-DC boost converter according to claim 1.

9. The device of claim 8, further comprising an additional switch coupled between the input node and ground, the additional switch being controlled by an additional control signal, wherein the additional control signal is asserted to close the additional switch during a first portion of the first operation phase and deasserted to open the additional switch during a second portion of the first operation phase, and wherein the additional control signal is asserted to close the additional switch during a first portion of the second operation phase and deasserted to open the additional switch during a second portion of the second operation phase.

10. The device of claim 8, further comprising a first driving circuit device powered by the first output voltage and a first micromirror driven by the first driving circuit device; and a second driving circuit device powered by the second output voltage and a second micromirror driven by the second driving circuit device.

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