Semiconductor structure and manufacturing method

Abstract

This disclosure relates to the semiconductor field, providing a semiconductor structure and a method for manufacturing the same. The method includes: providing a first substrate; forming a conductive layer on the first substrate; forming a filling layer on the conductive layer; forming a capacitor hole penetrating the filling layer in the filling layer, the capacitor hole exposing a portion of the surface of the conductive layer; forming a second electrode layer, a dielectric layer, and a first electrode layer sequentially stacked within the capacitor hole, the first electrode layer, the dielectric layer, and the second electrode layer constituting a capacitor structure; providing a second substrate, the surface of the second substrate having a contact structure, the position of the contact structure corresponding to the position of the first electrode layer; aligning the first substrate and the second substrate so that the first electrode layer is aligned and in contact with the contact structure, and bonding the first substrate and the second substrate; and removing the first substrate. The semiconductor structure and manufacturing method provided by this disclosure at least improve the performance of the semiconductor structure.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductors, and in particular to a semiconductor structure and a method for manufacturing the same. Background Technology

[0002] Memory is a storage component used to store programs and various data information. Random Access Memory (RAM) used in general computer systems can be divided into two types: Dynamic Random Access Memory (DRAM) and Static Random Access Memory (SRAM). DRAM is a commonly used semiconductor storage device in computers, consisting of many repeating storage cells.

[0003] A memory cell typically includes a capacitor and a transistor. The drain of the transistor is connected to the bit line structure, and the source is connected to the capacitor. The capacitor includes a capacitor contact structure and a capacitor. The word line structure of the memory cell can control the opening or closing of the transistor's channel region, thereby reading data information stored in the capacitor through the bit line structure, or writing data information into the capacitor for storage through the bit line structure. Summary of the Invention

[0004] This disclosure provides a semiconductor structure and a method for manufacturing the same, which at least helps to improve the performance of the semiconductor structure.

[0005] According to some embodiments of this disclosure, one aspect of this disclosure provides a method for manufacturing a semiconductor structure, comprising: providing a first substrate; forming a conductive layer on the first substrate; forming a filling layer on the conductive layer; forming a capacitor hole penetrating the filling layer in the filling layer, the capacitor hole exposing a portion of the surface of the conductive layer; forming a second electrode layer, a dielectric layer, and a first electrode layer sequentially stacked within the capacitor hole, the second electrode layer covering the inner wall of the capacitor hole and the surface of the filling layer; the dielectric layer covering the surface of the second electrode layer; the first electrode layer covering the surface of the dielectric layer and filling the capacitor hole, the first electrode layer, the dielectric layer, and the second electrode layer constituting a capacitor structure; providing a second substrate, the surface of the second substrate having a contact structure, the position of the contact structure corresponding to the position of the first electrode layer; aligning the first substrate and the second substrate so that the first electrode layer is aligned with and in contact with the contact structure, and bonding the first substrate and the second substrate; and removing the first substrate.

[0006] In some embodiments, providing a first substrate includes: providing a first substrate; forming a buffer layer on the first substrate; and forming a conductive layer on the first substrate includes: forming a conductive layer on the buffer layer.

[0007] In some embodiments, forming a capacitor hole through the fill layer in the fill layer includes: patterning the fill layer to form the capacitor hole, wherein a conductive layer serves as an etch stop layer when forming the capacitor hole.

[0008] In some embodiments, the filling layer material includes at least one of doped polycrystalline silicon, germanium silicon, tungsten, platinum nickelate, titanium, tantalum, cobalt, tantalum nitride, titanium nitride, and ruthenium; and / or the conductive layer material includes a metallic material that can bond with the material of the second electrode layer.

[0009] In some embodiments, the material of the filling layer is the same as the material of the second electrode layer, so that the filling layer is used as the second electrode layer; forming a capacitor structure includes: forming a dielectric layer and a first electrode layer stacked sequentially in a capacitor hole, the dielectric layer covering the inner wall of the capacitor hole and the surface of the filling layer; the first electrode layer covering the surface of the dielectric layer and filling the capacitor hole, the first electrode layer, the dielectric layer and the filling layer constituting a capacitor structure.

[0010] In some embodiments, after forming the capacitor structure and before bonding the first substrate and the second substrate, the method further includes: planarizing the surface of the first electrode layer away from the first substrate so that the top surface of the first electrode layer is flush with the top surface of the dielectric layer.

[0011] In some embodiments, after bonding the first substrate and the second substrate, an annealing process is further included, wherein the annealing process conditions include: an annealing time of 3 to 8 minutes and an annealing temperature of 250 to 350°C.

[0012] In some embodiments, the second substrate includes a second substrate on which transistors, word lines, and bit lines are disposed. The gate of the transistor is electrically connected to the word line, one of the source or drain of the transistor is electrically connected to the bit line, and the other of the source or drain of the transistor is electrically connected to a contact structure.

[0013] According to some embodiments of this disclosure, another aspect of this disclosure provides a semiconductor structure, including: a second substrate having a contact structure on its surface; a capacitor structure disposed on the second substrate, the capacitor structure including a first electrode layer, a dielectric layer, and a second electrode layer stacked sequentially, the first electrode layer extending along the thickness direction of the second substrate, and the bottom surface of the first electrode layer contacting the top surface of the contact structure; the dielectric layer covering the surface of the first electrode layer and the surface of the second substrate between the first electrode layers; the second electrode layer covering the surface of the dielectric layer; a filling layer filling the gap between adjacent capacitor structures; and a conductive layer covering the top surface of the filling layer and the top surface of the second electrode layer.

[0014] In some embodiments, the filling layer material includes at least one of doped polycrystalline silicon, germanium silicon, tungsten, platinum nickelate, titanium, tantalum, cobalt, tantalum nitride, titanium nitride, and ruthenium; and / or the conductive layer material includes a metallic material that can bond with the material of the second electrode layer.

[0015] The technical solutions provided in this disclosure have at least the following advantages:

[0016] The semiconductor structure and manufacturing method disclosed herein first form a conductive layer and a filling layer on a first substrate, and then form capacitor holes within the filling layer. The capacitor holes are then filled to form a capacitor structure. This allows the filling layer to fully fill the spaces between the capacitor structures. Since the filling layer is a single unit, the capacitor holes within it can have a high aspect ratio, resulting in a capacitor structure with a large aspect ratio after the holes are filled. Therefore, the capacitor structure can have a high charge storage capacity. Furthermore, by first forming the capacitor structure on the first substrate and then bonding the first substrate (e.g., performing the capacitor structure fabrication process on the first substrate) to a second substrate (e.g., performing front-end processes on the second substrate, including transistor formation, word line formation, bit line formation, capacitor contact structure formation, and bonding pad formation), the structures on the first and second substrates can be fabricated simultaneously. These structures are then bonded together to form a complete memory cell, significantly simplifying the process and improving the manufacturing efficiency of the semiconductor structure. Attached Figure Description

[0017] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or the conventional technology, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figures 1 to 11 This is a schematic diagram of the various steps in a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure. Detailed Implementation

[0019] Analysis reveals that as the size of semiconductor structures continues to shrink, capacitor structures require larger aspect ratios to accommodate higher charge storage capacities. Typically, capacitor structures are vertically oriented cylindrical shapes with high aspect ratios to maximize surface area. A capacitor structure consists of a bottom electrode layer, a dielectric layer, and a top electrode layer stacked sequentially. To improve the stability of the capacitor structure, support layers are needed between the layers to prevent it from collapsing due to excessive height.

[0020] In addition, a filler layer is needed between multiple capacitor structures to serve as a connection layer between the capacitor structure and the metal wiring layer formed in the subsequent process, and the filler layer also stabilizes the capacitor structure. Since the dielectric layer in the capacitor structure is greatly affected by the thermal budget, if the filler layer uses a high-temperature process, it will cause the dielectric layer to become too crystallized, increasing its conductivity and causing leakage current.

[0021] To reduce the resistance of the filler layer and improve the performance of the semiconductor structure, doped polysilicon is typically used as the filler layer. However, to reduce the resistance of the filler layer to the required value, the concentration of dopant ions needs to be increased. Increasing the concentration of dopant ions will cause the deposition rate to be too fast, resulting in premature sealing of the filler layer. This leads to the formation of air gaps within the filler layer between capacitor structures, thus affecting the performance of the semiconductor structure.

[0022] According to some embodiments of this disclosure, one embodiment of this disclosure provides a method for manufacturing a semiconductor structure, which at least helps to improve the performance of the semiconductor structure.

[0023] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this disclosure to facilitate a better understanding of the disclosure. However, the technical solutions claimed in this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0024] Figures 1 to 11 This is a schematic diagram of the various steps in a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure, wherein... Figure 5 for Figure 4 A cross-sectional view along the AA1 direction is shown below. The manufacturing method of the semiconductor structure provided in this embodiment will be described in detail below with reference to the accompanying drawings:

[0025] refer to Figures 1 to 11 A method for manufacturing a semiconductor structure, including:

[0026] refer to Figure 1 Provides a first substrate 100.

[0027] In some embodiments, the first substrate 100 may include a substrate, wherein the substrate may include a basic semiconductor, a compound semiconductor, or an alloy semiconductor. For example, basic semiconductors include silicon and germanium (Ge); compound semiconductors include silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, and / or group III-V semiconductor materials; alloy semiconductors include silicon germanium (SiGe), silicon germanium carbide, germanium tin, silicon germanium tin, gallium arsenide phosphide, gallium indium phosphide, gallium indium arsenide, indium gallium arsenide, aluminum indium arsenide, and / or aluminum gallium arsenide. In some embodiments, the first substrate 100 may also be a silicon-on-insulator structure, a germanium-silicon-on-insulator structure, a germanium-on-insulator structure, or a combination thereof.

[0028] refer to Figure 2 A conductive layer 101 is formed on the first substrate 100.

[0029] In some embodiments, the material of the conductive layer 101 includes tungsten.

[0030] In some embodiments, reference Figure 3 Providing a first substrate 100 includes: providing a first substrate 110; forming a buffer layer 120 on the first substrate 110; and forming a conductive layer 101 on the first substrate 100 includes: forming a conductive layer 101 on the buffer layer 120. This allows the conductive layer 101 and the first substrate 110 to transition between each other via the buffer layer 120, preventing diffusion between elements in the conductive layer 101 and the first substrate 110, thereby improving the stability of the semiconductor structure.

[0031] In some embodiments, the material of the first substrate 110 may be a semiconductor material, such as, but not limited to, silicon. In some embodiments, the first substrate 110 may include a silicon substrate (e.g., a wafer). In some embodiments, the first substrate 110 may include: a basic semiconductor, a compound semiconductor, or an alloy semiconductor. For example, basic semiconductors include germanium (Ge); compound semiconductors include silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, and / or group III-V semiconductor materials; alloy semiconductors include silicon germanium (SiGe), silicon germanium carbide, germanium tin, silicon germanium tin, gallium arsenide phosphide, gallium indium phosphide, gallium indium arsenide, indium gallium arsenide, aluminum indium arsenide, and / or aluminum gallium arsenide.

[0032] In some embodiments, the material of the buffer layer 120 includes silicon oxide, silicon nitride, or silicon oxynitride.

[0033] refer to Figure 4 A filling layer 102 is formed on the conductive layer 101; a capacitor hole 103 is formed in the filling layer 102, and the capacitor hole 103 exposes part of the surface of the conductive layer 101.

[0034] It should be noted that, in Figure 4 In this example, taking the direction of the capacitor hole 103 penetrating the filling layer 102 as perpendicular to the surface of the first substrate 100, that is, the angle between the extension direction of the capacitor hole 103 and the surface of the first substrate 100 is 90°, which does not constitute a limitation on the extension direction of the capacitor hole 103. In some embodiments, the extension direction of the capacitor hole may be at an angle of 30°, 60° or 45° with the surface of the first substrate, etc.

[0035] In some embodiments, reference Figure 5 The number of capacitor holes 103 formed in the filling layer 102 is multiple. The multiple capacitor holes 103 can be arranged in an array along the first direction X and the second direction Y in the filling layer 102. The first direction X and the second direction Y are both parallel to the surface of the first substrate 100. This can increase the arrangement density of the capacitor holes 103, which is beneficial to the subsequent formation of multiple closely arranged capacitor structures and improve the space utilization of the semiconductor structure.

[0036] It should be noted that, in Figure 5 Taking a 90° angle between the first direction X and the second direction Y as an example, the resulting capacitor structure can be arranged in a square close-packed configuration. In some embodiments, the first and second directions can be at a 60° angle, so that the resulting capacitor structure is arranged in a hexagonal close-packed configuration. The square or hexagonal close-packed capacitor structure can improve the space utilization of the capacitor structure, thereby increasing the integration density of the semiconductor structure.

[0037] In addition, Figure 5 In this example, the capacitor hole 103 is described with a circular cross-section. The resulting capacitor structure is cylindrical, but this does not limit the shape of the capacitor hole 103. In some embodiments, the cross-section of the capacitor hole 103 can also be rectangular, square, or triangular. It is understood that a cylindrical capacitor structure can have a smooth surface to avoid tip discharge. When the capacitor hole is rectangular, square, or triangular, the tip can be chamfered to make the surface of the subsequently formed capacitor structure smooth.

[0038] In some embodiments, the thickness of the filling layer 102 in the direction perpendicular to the surface of the first substrate 100 is greater than or equal to 1 μm. For example, the thickness of the filling layer 102 can be 1 μm, 1.5 μm, 2 μm, or 3 μm. It is understood that the thickness of the filling layer 102 determines the depth of the capacitor hole 103, which corresponds to the length of the capacitor structure in the direction perpendicular to the surface of the first substrate 100. The thicker the filling layer 102, the longer the corresponding capacitor structure, which is more conducive to forming a capacitor structure with a larger aspect ratio and improving the charge storage capacity of the capacitor structure.

[0039] In some embodiments, the material of the filler layer 102 includes at least one selected from doped polycrystalline silicon, germanium silicon, tungsten, platinum nickelide, titanium, tantalum, cobalt, tantalum nitride, titanium nitride, and ruthenium. This allows the filler layer 102 to possess better conductivity, which helps reduce the resistance of the subsequently formed capacitor structure and improves the electrical transport performance between the capacitor structure and other devices.

[0040] In some embodiments, forming a capacitor hole 103 penetrating the fill layer 102 in the fill layer 102 includes: patterning the fill layer to form the capacitor hole 103, wherein the conductive layer 101 serves as an etching stop layer during the formation of the capacitor hole 103. This avoids the fill layer 102 from being exposed to the etching environment for extended periods, which could lead to poor morphology of the capacitor hole 103 or excessive etching that could damage the surface of the contacting conductive layer 101.

[0041] In some embodiments, reference Figure 6 The material of the conductive layer 101 can be the same as the material of the filler layer 102. Thus, the formation of the conductive layer 101 on the first substrate 100 and the formation of the filler layer 102 on the conductive layer 101 can be performed in the same process step, thereby improving the manufacturing efficiency of the semiconductor structure.

[0042] refer to Figure 7 A second electrode layer 133, a dielectric layer 123, and a first electrode layer 113 are formed sequentially within the capacitor hole 103. The second electrode layer 133 covers the bottom surface and sidewalls of the capacitor hole 103 and the surface of the filling layer 102. The dielectric layer 123 covers the surface of the second electrode layer 133. The first electrode layer 113 covers the surface of the dielectric layer 123 and fills the capacitor hole 103. The first electrode layer 113, the dielectric layer 123, and the second electrode layer 133 constitute a capacitor structure 203.

[0043] In some embodiments, the resistance of the material of the filling layer 102 is less than or equal to the resistance of the material of the second electrode layer 133. This allows the second electrode layers 133 of multiple capacitor structures 203 to be electrically connected to each other via the filling layer 102, while simultaneously reducing the resistance of the multiple capacitor structures 203 and improving the electrical transmission efficiency between the capacitor structures 203 and other devices.

[0044] In some embodiments, reference Figure 8The filling layer 102 is made of the same material as the second electrode layer 133, so that the filling layer 102 serves as the second electrode layer 133. Forming the capacitor structure 203 includes: forming a dielectric layer 123 and a first electrode layer 113 sequentially stacked within the capacitor hole 103. The dielectric layer 123 covers the inner wall (including the bottom and sidewalls) of the capacitor hole 103 and the surface of the filling layer 102; the first electrode layer 113 covers the surface of the dielectric layer 123 and fills the capacitor hole 103. The first electrode layer 113, the dielectric layer 123, and the filling layer 102 constitute the capacitor structure. Thus, the filling layer 102 and the second electrode layer 133 can be formed in the same process step, or the fabrication process steps of the second electrode layer 133 can be reduced, thereby improving the manufacturing efficiency of the semiconductor structure.

[0045] In some embodiments, the material of the conductive layer 101 includes a metallic material that can be bonded to the material of the second electrode layer 133. This allows for good ohmic contact between the conductive layer 101 and the second electrode layer 133, preventing excessive contact resistance and improving the performance of the semiconductor structure.

[0046] In some embodiments, the materials of the first electrode layer 113 and the second electrode layer 133 both include at least one of platinum nickel, titanium, tantalum, cobalt, polycrystalline silicon, copper, tungsten, tantalum nitride, titanium nitride, or ruthenium.

[0047] In some embodiments, the dielectric layer 123 is made of high dielectric constant materials such as silicon oxide, tantalum oxide, hafnium oxide, zirconium oxide, niobium oxide, titanium oxide, barium oxide, strontium oxide, yttrium oxide, lanthanum oxide, praseodymium oxide, or barium strontium titanate. High dielectric constant materials are beneficial for improving the charge storage capacity of the capacitor structure.

[0048] In some embodiments, the filling layer 102 is made of germanium-silicon, the conductive layer 101 is made of tungsten, and the first electrode layer 113 and the second electrode layer 133 are made of titanium nitride.

[0049] refer to Figure 9 A second substrate 200 is provided, the surface of which has a contact structure 201, the position of which corresponds to the position of the first electrode layer 113. (Reference) Figure 10 The first substrate 100 and the second substrate 200 are aligned so that the first electrode layer 113 is aligned with and in contact with the contact structure 201, and the first substrate 100 and the second substrate 200 are bonded together. (Reference) Figure 11Remove the first substrate 100. Thus, in the capacitor structure 203 retained on the second substrate 200, the first electrode layer 113 that contacts the contact structure 201 serves as the lower electrode layer of the capacitor structure 203, the dielectric layer 123 serves as the capacitor dielectric layer of the capacitor structure 203, and the second electrode layer 133 serves as the upper electrode layer of the capacitor structure 203.

[0050] In some embodiments, the second substrate 200 may include a basic semiconductor, a compound semiconductor, or an alloy semiconductor. For example, basic semiconductors include silicon and germanium (Ge); compound semiconductors include silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, and / or group III-V semiconductor materials; alloy semiconductors include silicon germanium (SiGe), silicon germanium carbide, germanium tin, silicon germanium tin, gallium arsenide phosphide arsenide, gallium arsenide indium phosphide, indium gallium arsenide phosphide, aluminum indium arsenide, and / or aluminum gallium arsenide. In some embodiments, the second substrate 200 may also be a silicon-on-insulator structure, a germanium-silicon-on-insulator structure, a germanium-on-insulator structure, or a combination thereof.

[0051] In some embodiments, the material of the contact structure 201 includes copper, silver, gold, tungsten, tin, or lead.

[0052] In some embodiments, the second substrate includes a second substrate on which transistors, word lines, and bit lines are disposed. The gate of the transistor is electrically connected to the word line, one of the source or drain of the transistor is electrically connected to the bit line, and the other of the source or drain of the transistor is electrically connected to a contact structure. Thus, the transistor can be electrically connected to a corresponding capacitor structure through the contact structure. The transistor and the corresponding capacitor structure constitute a memory cell, and the corresponding word line and bit line enable the storage or retrieval of the memory cell.

[0053] In some embodiments, the material of the second substrate may be a semiconductor material, such as, but not limited to, silicon. In some embodiments, the second substrate may include a crystalline silicon substrate (e.g., a wafer). In some embodiments, the second substrate may include: a basic semiconductor, a compound semiconductor, or an alloy semiconductor. For example, basic semiconductors include germanium (Ge); compound semiconductors include silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, and / or group III-V semiconductor materials; alloy semiconductors include silicon germanium (SiGe), silicon germanium carbide, germanium tin, silicon germanium tin, gallium arsenide phosphide arsenide, gallium arsenide indium phosphide, indium gallium arsenide, aluminum indium arsenide, and / or aluminum gallium arsenide. In some embodiments, the second substrate may also be a silicon-on-insulator structure, a germanium-silicon-on-insulator structure, a germanium-on-insulator structure, or a combination thereof.

[0054] In some embodiments, the material of the word line includes at least one of polycrystalline silicon, titanium nitride, titanium aluminide, tantalum nitride, nickel silicide, cobalt silicide, tantalum, aluminum, lanthanum, titanium, or tungsten.

[0055] In some embodiments, the material of the bit line includes at least one of metal silicide, titanium nitride, or tungsten. In some embodiments, the material forming the bit line can be a single metal, a metal compound, or an alloy. The single metal can be aluminum, tungsten, gold, or silver; the metal compound can be tungsten nitride, tantalum nitride, or titanium nitride; and the alloy can be an alloy material composed of at least two of aluminum, tungsten, gold, or silver.

[0056] In some embodiments, after forming the capacitor structure and before bonding the first substrate 100 and the second substrate 200, the method further includes: planarizing the surface of the first electrode layer 113 away from the first substrate 100, so that the top surface of the first electrode layer 113 is flush with the top surface of the dielectric layer 123. Planarizing the top surface of the first electrode layer 113 to be flush with the top surface of the dielectric layer 123 facilitates subsequent bonding of the first substrate 100 and the second substrate 200, avoiding poor contact between the contact structure 201 and the first electrode layer 113. Furthermore, by planarizing the surface of the first electrode layer 113 away from the first substrate 100, the top surface of the dielectric layer 123 is exposed. After subsequent bonding with the second substrate, the dielectric layer 123 and the adjacent contact structures 201 are in contact with the surfaces of the second substrate 200, and the different capacitor structures 203 can be insulated from each other, preventing leakage between adjacent capacitor structures 203.

[0057] In some embodiments, the process conditions for bonding the first substrate 100 and the second substrate 200 include: a bonding temperature of 20–25°C and a bonding time of 5 seconds or more. For example, the bonding temperature can be 20°C, 22°C, 24.5°C, or 25°C, etc.; the bonding time can be 5 seconds, 8 seconds, or 10 seconds, etc.

[0058] In some embodiments, after bonding the first substrate 100 and the second substrate 200, an annealing process is further included. The annealing process conditions include an annealing time of 3 to 8 minutes and an annealing temperature of 250 to 350°C. The annealing process can improve the ohmic contact between the first electrode layer 113 and the contact structure 201.

[0059] In some embodiments, the annealing time can be 3 minutes, 4 minutes, 5 minutes, 6.5 minutes or 8 minutes, etc.; the annealing temperature can be 250°C, 275°C, 290°C, 314°C, 328°C or 350°C.

[0060] The semiconductor structure manufacturing method provided in this embodiment first forms a conductive layer 101 and a filling layer 102 on a first substrate 100, and forms a capacitor hole 103 in the filling layer 102. Then, the capacitor hole 103 is filled to form a capacitor structure 203. In this way, the filling layer 102 can fully fill the space between the capacitor structures 203. Since the filling layer 102 is a whole, the capacitor hole 103 in the filling layer 102 can have a high aspect ratio. As a result, the capacitor structure 203 formed after filling the capacitor hole 103 can also have a large aspect ratio. Therefore, the capacitor structure 203 can have a high charge storage capacity. Furthermore, by first forming a capacitor structure 203 on the first substrate 100, and then bonding the first substrate 100 (e.g., performing a capacitor structure fabrication process on the first substrate) with the second substrate 200 (e.g., performing front-end processes on the second substrate, including transistor formation, word line formation, bit line formation, capacitor contact structure formation, and landing pad formation), the structures on the first substrate 100 and the second substrate 200 can be fabricated simultaneously, and then a complete memory cell can be formed by bonding. This can significantly simplify the process and improve the manufacturing efficiency of semiconductor structures.

[0061] Compared to forming multiple independent capacitor structures first and then filling the gaps between them with a filler layer, the method provided in this disclosure, which involves forming the capacitor structure on a first substrate and then bonding it to a second substrate, avoids the problem of gaps forming between capacitor structures due to an excessively rapid formation rate of the filler layer, thereby improving the performance of the semiconductor structure. Furthermore, compared to forming multiple independent capacitor structures first, this disclosure provides a capacitor hole within the filler layer. The filler layer itself, as a whole, can have high support strength, effectively preventing the capacitor structure from collapsing due to an excessively large aspect ratio.

[0062] According to some embodiments of this disclosure, another embodiment of this disclosure provides a semiconductor structure that can be formed using the above-described semiconductor structure manufacturing method to improve the performance of the semiconductor structure. It should be noted that the parts that are the same as or corresponding to those in the above embodiments can be referred to the corresponding descriptions of the foregoing embodiments, and will not be described in detail below.

[0063] The semiconductor structure provided in this embodiment will be described in detail below with reference to the accompanying drawings, as follows:

[0064] refer to Figure 11The semiconductor structure includes: a second substrate 200, the surface of which has a contact structure 201; a capacitor structure 203 disposed on the second substrate, the capacitor structure 203 including a first electrode layer 113, a dielectric layer 123 and a second electrode layer 133 stacked sequentially, the first electrode layer 113 extending along the thickness direction of the second substrate 200, and the bottom surface of the first electrode layer 113 contacting the top surface of the contact structure 201; the dielectric layer 123 covering the surface of the first electrode layer 113 and the surface of the second substrate 200 between the first electrode layers 113; the second electrode layer 133 covering the surface of the dielectric layer 123; a filling layer 102 filling the gap between adjacent capacitor structures 203; and a conductive layer 101 covering the top surface of the filling layer 102 and the top surface of the second electrode layer 133.

[0065] The semiconductor structure provided in this embodiment is formed by the above-described semiconductor structure manufacturing method. The filling layer 102 can be fully filled between the capacitor structures 203, and the filling layer 102 can serve as a support structure between the capacitor structures 203, so that the capacitor structure 203 has a large aspect ratio and sufficient strength to prevent the capacitor structure 203 from collapsing.

[0066] In some embodiments, the resistance of the material of the conductive layer 101 is less than the resistance of the material of the filler layer 102. It is understood that the filler layer 102 is used to interconnect the second electrode layers 133 of the multiple capacitor structures 203. Even if the upper electrode layers of the multiple capacitor structures 203 share the same control terminal, the conductive layer 101 can electrically connect the multiple capacitor structures 203 to the metal wiring layer in subsequent process steps, enabling the capacitor structures 203 to transmit signals with other devices. The fact that the resistance of the material of the conductive layer 101 is less than the resistance of the material of the filler layer 102 can help reduce the contact resistance between the capacitor structures 203 and other devices, thereby improving signal transmission efficiency.

[0067] In some embodiments, the material of the filler layer 102 includes at least one selected from doped polycrystalline silicon, germanium silicon, tungsten, platinum nickelide, titanium, tantalum, cobalt, tantalum nitride, titanium nitride, and ruthenium. This allows the filler layer 102 to possess better conductivity, which helps reduce the resistance of the subsequently formed capacitor structure and improves the electrical transport performance between the capacitor structure and other devices.

[0068] In some embodiments, the material of the conductive layer 101 includes a metallic material that can be bonded to the material of the second electrode layer 133. This allows for good ohmic contact between the conductive layer 101 and the second electrode layer 133, preventing excessive contact resistance and improving the performance of the semiconductor structure.

[0069] In some embodiments, the filling layer 102 is made of germanium-silicon, the conductive layer 101 is made of tungsten, and the first electrode layer 113 and the second electrode layer 133 are made of titanium nitride.

[0070] Those skilled in the art will understand that the above embodiments are specific examples of implementing this disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of this disclosure.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that, include: Provide the first base; A conductive layer is formed on the first substrate; A filling layer is formed on the conductive layer; A capacitor hole is formed in the filling layer, exposing a portion of the surface of the conductive layer. A second electrode layer, a dielectric layer, and a first electrode layer are formed sequentially within the capacitor hole. The second electrode layer covers the inner wall of the capacitor hole and the surface of the filling layer. The dielectric layer covers the surface of the second electrode layer. The first electrode layer covers the surface of the dielectric layer and fills the capacitor hole. The first electrode layer, the dielectric layer, and the second electrode layer constitute a capacitor structure. A second substrate is provided, the surface of which has a contact structure, the position of which corresponds to the position of the first electrode layer; The first substrate and the second substrate are aligned so that the first electrode layer is aligned with and in contact with the contact structure, and the first substrate and the second substrate are bonded together. Remove the first substrate; The filling layer is made of the same material as the second electrode layer, so that the filling layer is used as the second electrode layer; Forming the capacitor structure includes: The dielectric layer and the first electrode layer are formed sequentially in the capacitor hole, and the dielectric layer covers the inner wall of the capacitor hole and the surface of the filling layer. The first electrode layer covers the surface of the dielectric layer and fills the capacitor hole. The first electrode layer, the dielectric layer, and the filling layer constitute a capacitor structure.

2. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, Providing a first substrate includes: providing a first substrate; forming a buffer layer on the first substrate; and forming a conductive layer on the first substrate includes: forming the conductive layer on the buffer layer.

3. The method for manufacturing a semiconductor structure according to claim 2, characterized in that, The method of forming a capacitor hole penetrating the filling layer in the filling layer includes: The filling layer is patterned to form the capacitor aperture, wherein the conductive layer serves as an etch stop layer during the formation of the capacitor aperture.

4. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, The materials of the filling layer and the second electrode layer both include at least one of platinum nickelate, titanium, tantalum, cobalt, polycrystalline silicon, copper, tungsten, tantalum nitride, titanium nitride, or ruthenium; and / or the material of the conductive layer includes a metallic material that can bond with the material of the second electrode layer.

5. The method for manufacturing a semiconductor structure according to any one of claims 1-4, characterized in that, After forming the capacitor structure and before bonding the first substrate and the second substrate, the method further includes: planarizing the surface of the first electrode layer away from the first substrate so that the top surface of the first electrode layer is flush with the top surface of the dielectric layer.

6. The method for manufacturing a semiconductor structure according to any one of claims 1-4, characterized in that, After bonding the first substrate and the second substrate, an annealing process is further included. The annealing process conditions include: an annealing time of 3 to 8 minutes and an annealing temperature of 250 to 350°C.

7. The method for manufacturing a semiconductor structure according to any one of claims 1-4, characterized in that, The second substrate includes a second substrate on which transistors, word lines, and bit lines are disposed. The gate of the transistor is electrically connected to the word line, one of the source or drain of the transistor is electrically connected to the bit line, and the other of the source or drain of the transistor is electrically connected to the contact structure.

8. A semiconductor structure, characterized in that, Prepared by the semiconductor structure manufacturing method according to any one of claims 1-7, comprising: A second substrate, the surface of which has a contact structure; The capacitor structure disposed on the second substrate includes a first electrode layer, a dielectric layer and a second electrode layer stacked sequentially. The first electrode layer extends along the thickness direction of the second substrate, and the bottom surface of the first electrode layer contacts the top surface of the contact structure. The dielectric layer covers the surface of the first electrode layer and the surface of the second substrate between the first electrode layers; The second electrode layer covers the surface of the dielectric layer; A filling layer that fills the gaps between adjacent capacitor structures; A conductive layer, the conductive layer covering the top surface of the filler layer and the top surface of the second electrode layer; The filling layer is made of the same material as the second electrode layer, such that the filling layer serves as the second electrode layer; forming the capacitor structure includes: The dielectric layer and the first electrode layer are formed sequentially in the capacitor hole, and the dielectric layer covers the inner wall of the capacitor hole and the surface of the filling layer. The first electrode layer covers the surface of the dielectric layer and fills the capacitor hole. The first electrode layer, the dielectric layer, and the filling layer constitute a capacitor structure.

9. The semiconductor structure according to claim 8, characterized in that, The materials of the filling layer and the second electrode layer both include at least one of platinum nickelate, titanium, tantalum, cobalt, polycrystalline silicon, copper, tungsten, tantalum nitride, titanium nitride, or ruthenium; and / or the material of the conductive layer includes a metallic material that can bond with the material of the second electrode layer.

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