Organic light-emitting display devices and thin-film transistor array substrates

Abstract

An organic light-emitting display device and a thin-film transistor array substrate are disclosed. This organic light-emitting display device can reduce the size of the thin-film transistors disposed in the sub-pixels to achieve a high-resolution organic light-emitting display device. The conductive and non-conductive regions are combined in each of the source and drain regions, thereby increasing the channel size, for example, significantly. Therefore, a high-resolution organic light-emitting display device can be realized. Furthermore, the s-factor value of the driving thin-film transistors is increased, and the operating speed of switching the thin-film transistors is increased.

Description

[0001] This application claims the benefit of Korean Patent Application No. 10-2021-0180748, filed on December 16, 2021, which is incorporated herein by reference as fully set forth herein. Technical Field

[0002] This disclosure relates to organic light-emitting display devices, and more particularly, to organic light-emitting display devices including hybrid thin-film transistors, wherein different types of semiconductor materials are used to form a plurality of thin-film transistors constituting a pixel circuit portion of a sub-pixel and a plurality of thin-film transistors constituting a GIP circuit portion, and wherein the organic light-emitting display device is capable of reducing the size of the thin-film transistors, for example, minimizing the size of the thin-film transistors, to achieve a high-definition display device. Background Technology

[0003] Unlike backlit liquid crystal displays (LCDs), organic light-emitting diode (OLED) displays, which use self-emissive elements, have a smaller thickness and exhibit high image quality. Therefore, OLED displays are a focus of widespread attention in the display industry.

[0004] In particular, because light-emitting elements can be formed on flexible substrates, organic light-emitting display devices enable the creation of screens in various forms, such as flexible and foldable screens. Furthermore, due to their small thickness, organic light-emitting display devices are suitable for small electronic products, such as smartwatches.

[0005] Furthermore, for applications in display devices that frequently display still images, such as smartwatches, there is a need for light-emitting display devices that include novel pixel circuitry sections capable of preventing leakage current when displaying still images.

[0006] Thin-film transistors using oxide semiconductors as the active layer have been proposed to achieve improved leakage current blocking effect. Summary of the Invention

[0007] However, display devices using hybrid thin-film transistors employ different types of semiconductor layers, such as polycrystalline semiconductor layers and oxide semiconductor layers. Therefore, the processes for forming the polycrystalline semiconductor layer and the oxide semiconductor layer are performed separately, complicating the manufacturing process. Furthermore, the polycrystalline semiconductor layer and the oxide semiconductor layer have different properties relative to chemical gases, further complicating the manufacturing process.

[0008] In particular, compared to oxide semiconductor layers, polycrystalline semiconductor layers are characterized by the high-speed movement of charge carriers, such as electrons or holes, and are therefore suitable for driving thin-film transistors that require high-speed operation. Thus, polycrystalline semiconductor layers are commonly used to form driving thin-film transistors.

[0009] However, while driving thin-film transistors using polycrystalline semiconductor layers operates at relatively high speeds, it is disadvantageous in terms of low grayscale value representation due to the high current fluctuation rate caused by current stress. Therefore, one object of this disclosure is to form the driving thin-film transistors using oxide semiconductors and to provide pixel circuit portions with low current fluctuation rate caused by current stress and a large s-factor value. Another object of this disclosure is to provide a structure capable of reducing (e.g., minimizing) the size of multiple thin-film transistors disposed in sub-pixels, in accordance with recent trends toward high-definition display devices.

[0010] To achieve the above and other objectives, the organic light-emitting display device according to this disclosure includes: a substrate comprising a display area and a non-display area; and at least one thin-film transistor comprising a semiconductor pattern including a source region and a drain region. Each of the source region and the drain region includes conductive and non-conductive regions alternately disposed on the substrate.

[0011] Semiconductor patterns can be oxide semiconductor patterns.

[0012] At least one thin-film transistor may include: a gate electrode overlapping a semiconductor pattern; and a source electrode and a drain electrode electrically connected to a source region and a drain region, respectively. A conductive region may include a first conductive region contacting the source electrode or drain electrode, and a second conductive region disposed between the source electrode or drain electrode and the gate electrode.

[0013] The first conductive region can be made conductive by contacting it with ions, and the second conductive region can be made conductive by injecting ions into it.

[0014] The gate electrode can be located in a layer above the source and drain electrodes.

[0015] The gate electrode can be disposed on the same layer as the source and drain electrodes.

[0016] At least one thin-film transistor may include a driving thin-film transistor and at least one switching thin-film transistor. The driving thin-film transistor may include a first light-blocking pattern disposed below a semiconductor pattern and connected to a source electrode.

[0017] A driving thin-film transistor may include: a first semiconductor pattern; a first gate electrode overlapping the first semiconductor pattern; and a first source electrode and a first drain electrode connected to the first semiconductor pattern. A switching thin-film transistor may include: a second semiconductor pattern; a second gate electrode overlapping the second semiconductor pattern; and a second source electrode and a second drain electrode connected to the second semiconductor pattern. The first source electrode, the first drain electrode, the second source electrode, and the second drain electrode may be disposed on the same layer.

[0018] The first gate electrode and the second gate electrode can be disposed on the same layer. The first gate electrode and the second gate electrode can be disposed on a layer located above the first source electrode, the first drain electrode, the second source electrode, and the second drain electrode.

[0019] The first gate electrode and the second gate electrode can be disposed on the same layer as the first source electrode, the first drain electrode, the second source electrode, and the second drain electrode.

[0020] The first gate electrode and the second gate electrode can be disposed on different layers. The vertical distance between the first gate electrode and the first semiconductor pattern can be longer than the vertical distance between the second gate electrode and the second semiconductor pattern.

[0021] The switching thin-film transistor may include a second photoblocking pattern. The vertical distance between the second semiconductor pattern and the second photoblocking pattern may be longer than the vertical distance between the first semiconductor pattern and the first photoblocking pattern.

[0022] The driving thin-film transistor can be disposed in the display area, and the switching thin-film transistor can be disposed in at least one of the display area and the non-display area.

[0023] The thin-film transistor array substrate according to this disclosure includes: at least one thin-film transistor comprising a semiconductor pattern, the semiconductor pattern including a source region, a drain region, and a channel region disposed between the source region and the drain region. Each of the source region and the drain region includes at least two conductive regions and a non-conductive region disposed between the at least two conductive regions.

[0024] The conductive and non-conductive regions can be alternated in each of the source and drain regions.

[0025] The conductive region may include a first conductive region spaced apart from the channel region and a second conductive region disposed adjacent to the channel region.

[0026] The first conductive region can be made conductive by contacting it with ions, and the second conductive region can be made conductive by injecting ions into it.

[0027] The thin-film transistor array substrate according to this disclosure may further include: a source electrode and a drain electrode respectively connected to the source region and the drain region; and a light-blocking pattern disposed below the semiconductor pattern and connected to the source electrode.

[0028] Semiconductor patterns can be oxide semiconductor patterns.

[0029] At least one thin-film transistor can be at least one of a driving thin-film transistor and a switching thin-film transistor. Attached Figure Description

[0030] The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. In the drawings:

[0031] Figure 1 This is a schematic diagram of a display device according to an embodiment of the present disclosure;

[0032] Figure 2 This is a circuit diagram illustrating a pixel circuit for driving pixels in a display device according to an embodiment of the present disclosure;

[0033] Figure 3 According to embodiments of this disclosure, the thin-film transistor disposed in the non-display area and the pixel circuit portion and light-emitting element portion disposed in the pixel area are along the edge of the thin-film transistor disposed in the non-display area. Figure 1 A cross-sectional view of line I-I' in the diagram;

[0034] Figure 4 It is shown in detail Figure 3 Cross-sectional view of the driving thin-film transistor and the switching thin-film transistor in the pixel area;

[0035] Figure 5A and Figure 5B They are shown respectively Figure 4 Cross-sectional and planar views of a portion of one of the thin-film transistors shown;

[0036] Figure 6 This is a cross-sectional view of a driving thin-film transistor and a switching thin-film transistor in a pixel region according to another embodiment of the present disclosure;

[0037] Figure 7 This is a cross-sectional view of a driving thin-film transistor and a switching thin-film transistor in a pixel region according to yet another embodiment of the present disclosure.

[0038] Figure 8A It shows Figure 7 A cross-sectional view showing the relationship between the parasitic capacitances generated in the driving thin-film transistor;

[0039] Figure 8B yes Figure 8A The circuit diagram; and

[0040] Figure 9A and Figure 9B It is a cross-sectional view used to illustrate the main parts of the manufacturing process according to the embodiments of this disclosure. Detailed Implementation

[0041] The advantages and features of this disclosure, as well as the methods for achieving these advantages and features, will become clear from the embodiments described in detail below with reference to the accompanying drawings. However, this disclosure may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of this disclosure to those skilled in the art.

[0042] In the accompanying drawings used to illustrate exemplary embodiments of this disclosure, shapes, dimensions, ratios, angles, and numbers are shown by way of example and are therefore not limited to the scope of this disclosure. Throughout this specification, the same reference numerals denote the same constituent elements. Furthermore, in the following description of this disclosure, detailed descriptions of known functions and configurations incorporated herein will be omitted where such detailed descriptions might make the subject matter of this disclosure considerably unclear.

[0043] The terms “comprising,” “including,” and / or “having” as used in this specification do not exclude the presence or addition of other elements unless used with the term “only.” Unless the context clearly indicates otherwise, the singular form is intended to include the plural form as well.

[0044] In interpreting the constituent elements included in the various embodiments of this disclosure, even if not explicitly described, the constituent elements are to be interpreted as including a range of error.

[0045] In describing various embodiments of this disclosure, when describing positional relationships, for example, when using terms such as "on," "above," "below," or "beside" to describe the positional relationship between two parts, one or more other parts may be located between the two parts unless the terms "directly" or "immediately" are used.

[0046] For example, spatial relative terms such as “below,” “under,” “down,” “above,” and “above” can be used herein to describe the relationship between one element or component and another element or component as shown in the figures. It should be understood that, in addition to the orientations depicted in the figures, spatial relative terms are intended to cover different orientations of the device in use or operation. For example, if the device in the figure is flipped, an element described as “below” or “under” other elements will be oriented “above” other elements. Therefore, the exemplary terms “below” or “under” can cover both the above and below orientations. Similarly, the exemplary terms “above” or “above” can cover both the above and below orientations.

[0047] When describing various embodiments of this disclosure, when describing temporal relationships, for example, when using terms such as "after," "following," "next," "before," etc. to describe the temporal relationship between two actions, the actions may not occur consecutively unless the terms "directly" or "immediately after" are used with them.

[0048] It is understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements are not limited by these terms. These terms are used only to distinguish one element from another. Therefore, in this specification, an element indicated by “first” may be the same as an element indicated by “second,” without exceeding the technical scope of this disclosure, unless otherwise stated.

[0049] The term "at least one" should be understood to include all possible combinations that can be obtained from one or more related items. For example, "at least one of the first, second, or third items" can mean each of the first, second, or third items, and can also mean all possible combinations that can be obtained from two or more of the first, second, and third items.

[0050] The various features of the various embodiments of this disclosure can be coupled and combined with each other in whole or in part, and various technical connections and operating modes are possible. These various embodiments can be implemented independently of each other or can be implemented in conjunction with each other.

[0051] It should be noted that when reference numerals are assigned to elements in a drawing, the same or similar elements are represented by the same reference numerals, even when they are depicted in different drawings.

[0052] In embodiments of this disclosure, for ease of explanation, the source electrode and drain electrode are distinguished from each other. However, the source electrode and drain electrode are interchangeable. The source electrode can be the drain electrode, and the drain electrode can be the source electrode. Furthermore, the source electrode in any embodiment can be the drain electrode in another embodiment, and vice versa.

[0053] In one or more embodiments of this disclosure, for ease of explanation, the source region is distinguished from the source electrode, and the drain region is distinguished from the drain electrode. However, embodiments of this disclosure are not limited thereto. For example, the source region may be the source electrode, and the drain region may be the drain electrode. Furthermore, the source region may be the drain electrode, and the drain region may be the source electrode.

[0054] The various features of the various embodiments of this disclosure may be partially or wholly coupled and combined with each other, and may be interlocked and operated in various technical ways, as will be fully understood by those skilled in the art, and the embodiments may be performed independently or in association with each other.

[0055] In the following, various embodiments of this disclosure will be described in detail with reference to the accompanying drawings.

[0056] Figure 1 This is a plan view of a display device 100 according to an embodiment of the present disclosure.

[0057] The display panel 102 includes a display area AA and a non-display area NA disposed adjacent to the display area AA, and the display area AA and the non-display area NA are disposed in a substrate 101. For example, the substrate 101 may be formed of a flexible plastic material so that it is bendable. For example, the substrate 101 may be formed of polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polycarbonate (PC), polyethersulfone (PES), polyacrylate (PAR), polysulfone (PSF), or cyclic olefin copolymer (COC). However, glass is not excluded as a substrate material.

[0058] The sub-pixels in the display area AA include thin-film transistors that use oxide semiconductor materials as the active layer.

[0059] At least one of the data driving unit 104 and the gate driving unit 103 can be disposed in the non-display area NA. In addition, the non-display area NA may also include a bending region BA in which the substrate 101 can be bent.

[0060] The gate driving unit 103 can be formed directly on the substrate 101 using a thin-film transistor (TFT) that uses a polycrystalline semiconductor material as the active layer. Alternatively, the gate driving unit 103 may include a TFT that uses a polycrystalline semiconductor material as the active layer and a TFT that uses an oxide semiconductor material as the active layer.

[0061] Thin-film transistors with oxide semiconductor layers and thin-film transistors with polycrystalline semiconductor layers have high electron mobility in the channel and are therefore able to exhibit high resolution and be driven at low power.

[0062] Multiple data lines and multiple gate lines can be set in the display area AA. For example, multiple data lines can be set in rows or columns, and multiple gate lines can be set in columns or rows. In addition, sub-pixels PX can be set in the area defined by the data lines and gate lines.

[0063] A gate driving unit 103, including a gate driving circuit, can be disposed in the non-display area NA. The gate driving circuit of the gate driving unit 103 sequentially supplies scan signals to multiple gate lines GL, thereby sequentially driving each pixel row in the display area. Here, the gate driving circuit can also be referred to as a scan driving circuit. Furthermore, a pixel row refers to a row formed by pixels connected to a single gate line.

[0064] The gate drive circuit can be composed of a thin-film transistor with a polycrystalline semiconductor layer, a thin-film transistor with an oxide semiconductor layer, or both. When the same semiconductor material is used in the thin-film transistors positioned in the non-display area NA and the display area AA, the thin-film transistors can be formed simultaneously through the same process.

[0065] The gate drive circuit may include a shift register and a level shifter.

[0066] In the display device according to the embodiments of the present disclosure, the gate driving circuit can be implemented as a gate in panel (GIP) type and can be directly disposed on the substrate 101.

[0067] The gate driving unit 103, which includes a gate driving circuit, sequentially supplies scan signals with on-state voltage or off-state voltage to multiple gate lines.

[0068] The display device 100 according to embodiments of this disclosure may further include a data driving circuit. When a specific gate line is turned on by a gate driving unit 103 including a gate driving circuit, the data driving circuit converts image data into analog data voltage (e.g., Figure 2 The data voltage Vdata is shown, and the analog data voltage is supplied to multiple data lines.

[0069] The multiple gate lines GL disposed on the substrate 101 may include multiple scan lines and multiple emitter control lines. The multiple scan lines and multiple emitter control lines are wiring that transmits different types of gate signals (scan signals and emitter control signals) to the gate nodes of different types of transistors (scan transistors and emitter control transistors).

[0070] The gate driving unit 103, including the gate driving circuit, may include: a scan driving circuit that drives a scan signal (e.g., Figure 2 The scan signals Scan 1[n], Scan 2[n], Scan 3[n], and Scan 3[n+1] shown are output to multiple scan lines, which are gate lines GL; and an emitter drive circuit that outputs emitter control signals (e.g., Figure 2 The transmit control signal EM shown is output to multiple transmit control lines, which are another type of gate line GL.

[0071] Data cables DL can be configured to pass through the bend area BA. Each data cable DL can be configured to connect to the data pad PAD. Figure 1 (Not shown in the image).

[0072] The bending region BA can be the area where the substrate 101 can be bent. The substrate 101 can remain flat in areas other than the bending region BA.

[0073] Figure 2 This is a pixel circuit diagram of a sub-pixel according to an embodiment of this disclosure. A pixel circuit diagram is given by way of example, comprising seven thin-film transistors T2, T3, T4, T5, T6, T7 and a D-TFT and a single storage capacitor Cst. One of the seven thin-film transistors (e.g., the D-TFT) may be a driving thin-film transistor, and the remaining thin-film transistors may be switching thin-film transistors for internal compensation. Figure 2 As shown, the anode of the OLED is electrically connected to the thin-film transistor T6, and the cathode of the OLED is electrically connected to the low power supply voltage V. SSEL One electrode of the storage capacitor Cst is electrically connected to the gate electrode of the thin-film transistor D-TFT, and the other electrode of the storage capacitor Cst is electrically connected to the high supply voltage V. DDEL Here, Vin is the voltage that resets the thin-film transistor D-TFT, and VAR is the voltage that resets the anode of the light-emitting element OLED.

[0074] The following description of embodiments of this disclosure is given under the following assumptions: the driving thin-film transistor D-TFT uses an oxide semiconductor pattern as the active layer, and the T3 thin-film transistor positioned adjacent to the driving thin-film transistor D-TFT uses an oxide semiconductor pattern as the active layer. Furthermore, at least one of the remaining switching thin-film transistors used for internal compensation may use a polycrystalline semiconductor pattern as the active layer. However, this disclosure is not limited to... Figure 2 The example shown is applicable to any internal compensation circuit with various configurations. For instance, all thin-film transistors included in the pixel circuitry of a sub-pixel can be configured to use oxide semiconductors as active layers. Furthermore, thin-film transistors constituting the gate drive circuit portion can also be configured to use oxide semiconductors as active layers.

[0075] In the following text, reference will be made to Figures 3 to 5B This invention describes an organic light-emitting display device according to a first embodiment of the present disclosure.

[0076] Figure 3 The following is a cross-sectional view of a configuration that includes a first gate driving thin-film transistor GT disposed in the non-display area NA. Specifically, in the gate driving unit, a polycrystalline semiconductor pattern is used as the active layer. The configuration also includes a single driving thin-film transistor DT, a single switching thin-film transistor ST, and a single storage capacitor Cst disposed in the sub-pixel PX. Figure 4 It shows more details Figure 3 The diagram shows a cross-sectional view of the driving thin-film transistor DT and the switching thin-film transistor ST. Figure 5A yes Figure 4 The cross-sectional view of the switching thin-film transistor ST shown is shown, and Figure 5B yes Figure 4 The diagram shows a plan view of the components of the switching thin-film transistor ST.

[0077] In brief, a sub-pixel PX includes: a pixel circuit portion 370 disposed on a substrate 101; and a light-emitting element portion 380 electrically connected to the pixel circuit portion 370. The pixel circuit portion 370 and the light-emitting element portion 380 are electrically insulated from each other by planarization layers PLN1 and PLN2.

[0078] Here, pixel circuit section 370 refers to an array section including a driving thin-film transistor DT, a switching thin-film transistor ST, and a storage capacitor Cst to drive a sub-pixel PX. Furthermore, light-emitting element section 380 refers to an array section including an anode 323, a cathode 327, and a light-emitting layer 325 disposed between the anode 323 and the cathode 327 to emit light.

[0079] Although the pixel circuit section 370 is in Figure 3 The example is shown by way of example as including a single driving thin-film transistor DT, a single switching thin-film transistor ST, and a single storage capacitor Cst, but the present disclosure is not limited thereto.

[0080] In particular, in one embodiment of this disclosure, each of the driving thin-film transistor DT and at least one switching thin-film transistor ST uses an oxide semiconductor pattern as the active layer.

[0081] Thin-film transistors using oxide semiconductor materials as the active layer exhibit improved leakage current blocking effect and offer relatively lower manufacturing costs compared to thin-film transistors using polycrystalline semiconductor materials as the active layer. Therefore, to reduce power consumption and manufacturing costs, according to one embodiment of this disclosure, oxide semiconductor materials are used not only to manufacture driving thin-film transistors but also to manufacture at least one switching thin-film transistor.

[0082] Oxide semiconductors can be made of oxides of metals such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), or titanium (Ti), or combinations of such metals and their oxides. More specifically, oxide semiconductors can include zinc oxide (ZnO), zinc tin oxide (ZTO), zinc indium oxide (ZIO), indium oxide (InO), titanium oxide (TiO), indium gallium zinc oxide (IGZO), or indium zinc tin oxide (IZTO).

[0083] In the pixel circuit portion that constitutes a sub-pixel, oxide semiconductor materials can be used to form all thin-film transistors, or can be used to form at least one switching thin-film transistor.

[0084] It is difficult to ensure the reliability of thin-film transistors using oxide semiconductor materials, while thin-film transistors using polycrystalline semiconductor materials exhibit high operating speeds and improved reliability. Therefore, the following assumptions will be used to describe... Figure 3 The embodiments of this disclosure shown herein include: oxide semiconductor materials used to fabricate one of a switching thin-film transistor and a driving thin-film transistor (DT), and polycrystalline semiconductor materials used to fabricate the thin-film transistor constituting the gate driving unit. However, this disclosure is not limited to... Figure 3 The embodiment shown herein. That is, all thin-film transistors constituting a sub-pixel can be configured to use oxide semiconductor as the active layer, and all thin-film transistors constituting a gate driving unit can be configured to use oxide semiconductor as the active layer. Alternatively, thin-film transistors using oxide semiconductor as the active layer and thin-film transistors using polycrystalline semiconductor as the active layer can be combined to constitute a gate driving unit.

[0085] In line with the recent trend toward high-definition display devices with a relatively large number of subpixels per unit area, one embodiment of this disclosure aims to reduce the size of thin-film transistors (TFTs), which are the main components of subpixels (e.g., to minimize their size). To reduce the size of TFTs (e.g., to minimize their size), it is crucial to reduce the size of the semiconductor pattern, including the channel region.

[0086] Reducing the size of a semiconductor pattern refers to reducing the size of the conductive region, which can be the channel region, source region, and drain region that constitute the semiconductor pattern.

[0087] However, if the size of the channel region of the semiconductor pattern, especially the oxide semiconductor pattern, is reduced, the threshold voltage Vth becomes negative, which undesirably limits the operation of the thin-film transistor. Furthermore, if the size of the channel region of the driving thin-film transistor DT, which uses an oxide semiconductor pattern as the active layer, is reduced, the s-factor value decreases, and therefore the driving voltage range of the driving thin-film transistor DT is reduced.

[0088] Therefore, this disclosure proposes a thin-film transistor that uses an oxide semiconductor pattern as the active layer and is able to achieve high resolution and increase the s-factor value while preventing the Vth value from turning negative.

[0089] The substrate 101 can be configured as a multilayer substrate in which organic films and inorganic films are stacked alternately. For example, the substrate 101 can be formed by alternating stacking of organic films such as polyimide and inorganic films such as silicon oxide (SiO2).

[0090] A lower buffer layer 301 is formed on the substrate 101. The lower buffer layer 301 is used to block the entry of moisture and other external factors. The lower buffer layer 301 can be formed by stacking multiple layers of silicon oxide (SiO2) films.

[0091] A second buffer layer (not shown) may be further formed on the lower buffer layer 301 to more reliably protect the thin-film transistors disposed in the pixel circuit section 370 from moisture.

[0092] A first thin-film transistor GT is formed on substrate 101 and in the non-display area NA. The first thin-film transistor may use a polycrystalline semiconductor pattern as the active layer. The first thin-film transistor GT includes a first polycrystalline semiconductor pattern 303, which includes a channel through which electrons or holes move, a first gate electrode 306, a first source electrode 317S, and a first drain electrode 317D.

[0093] The first polycrystalline semiconductor pattern 303 is formed of a polycrystalline semiconductor material. The first polycrystalline semiconductor pattern 303 includes a first channel region 303C disposed therein, and also includes a first source region 303S and a first drain region 303D, wherein the first source region 303S and the first drain region 303D are disposed between the first channel region 303C and the first source region 303S and the first drain region 303D.

[0094] The first source region 303S and the first drain region 303D are conductive regions obtained by doping an intrinsic polycrystalline semiconductor pattern with a predetermined concentration of group V or group III impurity ions, such as phosphorus (P) or boron (B).

[0095] The first channel region 303C retains the intrinsic state of the polycrystalline semiconductor material and provides a path for electrons or holes to move along it.

[0096] The first thin-film transistor GT includes a first gate electrode 306, which overlaps with a first channel region 303C of a first polycrystalline semiconductor pattern 303. A first gate insulating layer 302 is located between the first gate electrode 306 and the first polycrystalline semiconductor pattern 303.

[0097] According to an embodiment of this disclosure, the first thin-film transistor GT has a top-gate type, wherein the first gate electrode 306 is located above the first polycrystalline semiconductor pattern 303. Therefore, the first storage capacitor electrode 305 and the second light-blocking pattern 304, formed from the first gate electrode material, can be formed by a single masking process, thereby reducing the number of masking processes.

[0098] The first gate electrode 306 is made of a metallic material. For example, the first gate electrode 306 may be in the form of a single layer or multiple layers made of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), or alloys thereof. However, this disclosure is not limited thereto.

[0099] A first interlayer insulating layer 307 is deposited on the first gate electrode 306. The first interlayer insulating layer 307 may be formed of silicon nitride (SiNx). In particular, the first interlayer insulating layer 307 formed of silicon nitride (SiNx) may contain hydrogen particles. During a heat treatment process performed after forming the first channel region 303C and depositing the first interlayer insulating layer 307 thereon, the hydrogen particles contained in the first interlayer insulating layer 307 permeate the first source region 303S and the first drain region 303D, thereby making the polycrystalline semiconductor material conductive. This can be referred to as a hydrogenation process, which is a process of making the source and drain regions conductive through a contact method.

[0100] The first thin-film transistor GT may further include an upper buffer layer 310 and a second gate insulating layer 313 sequentially formed on the first interlayer insulating layer 307. The first source electrode 317S and the first drain electrode 317D may be formed on the second gate insulating layer 313 and may be connected to the first source region 303S and the first drain region 303D, respectively.

[0101] The upper buffer layer 310 isolates the first polycrystalline semiconductor pattern 303 from the first oxide semiconductor pattern 311 formed of oxide semiconductor material for the driving thin-film transistor DT and the second oxide semiconductor pattern 312 formed of oxide semiconductor material for the first switching thin-film transistor ST. Furthermore, the upper buffer layer 310 provides the basis for forming the first oxide semiconductor pattern 311 and the second oxide semiconductor pattern 312.

[0102] The second gate insulating layer 313 is an insulating layer covering the first oxide semiconductor pattern 311 of the driving thin film transistor DT and the second oxide semiconductor pattern 312 of the first switching thin film transistor ST. Since the second gate insulating layer 313 is formed on the first oxide semiconductor pattern 311 and the second oxide semiconductor pattern 312, the second gate insulating layer 313 can be configured as an inorganic film that does not contain hydrogen particles.

[0103] Each of the first source electrode 317S and the first drain electrode 317D may be in the form of a single layer or multiple layers made of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), or alloys thereof. However, this disclosure is not limited thereto.

[0104] A driving thin-film transistor DT is formed on the upper buffer layer 310.

[0105] According to embodiments of this disclosure, the driving thin-film transistor DT includes a first oxide semiconductor pattern 311.

[0106] In conventional driving thin-film transistors (TFTs), polycrystalline semiconductor patterns, which are advantageous for high-speed operation, are used as the active layer. However, conventional driving TFTs including polycrystalline semiconductor patterns have the problem of generating leakage current in the off state, thus consuming a large amount of power. Therefore, embodiments of this disclosure propose a driving TFT DT that uses oxide semiconductor patterns, which are advantageous for preventing leakage current generation, as the active layer.

[0107] However, in thin-film transistors using oxide semiconductor patterns as the active layer, the current fluctuation relative to a unit voltage fluctuation is large due to the characteristics of oxide semiconductor materials, and therefore defects often occur in low grayscale regions where precise current control is required. Therefore, embodiments of this disclosure provide driving thin-film transistors in which current fluctuations in the active layer are relatively insensitive to fluctuations in the voltage applied to the gate electrode. Furthermore, embodiments of this disclosure provide driving thin-film transistors with a relatively small channel region and a relatively high S-factor value to achieve high resolution.

[0108] Reference Figure 4 , Figure 5A and Figure 5B The driving thin-film transistor DT includes a first oxide semiconductor pattern 311 formed on the upper buffer layer 310, and further includes: a second source electrode 319S and a second drain electrode 319D, the second source electrode 319S and the second drain electrode 319D being electrically connected to the first oxide semiconductor pattern 311; and a second gate electrode 314, which overlaps with the first oxide semiconductor pattern 311.

[0109] The second gate insulating layer 313 is located between the first oxide semiconductor pattern 311 and each of the second source electrode 319S and the second drain electrode 319D. That is, the second gate insulating layer 313 covers the first oxide semiconductor pattern 311, and the second source electrode 319S and the second drain electrode 319D are disposed on the second gate insulating layer 313.

[0110] Furthermore, in one embodiment of this disclosure, the second gate electrode 314 is formed on a second interlayer insulating layer 316 covering the second source electrode 319S and the second drain electrode 319D, and overlaps with the first oxide semiconductor pattern 311. Therefore, the second gate insulating layer 313 and the second interlayer insulating layer 316 are located between the second gate electrode 314 and the first oxide semiconductor pattern 311. Additionally, the second gate electrode 314 is disposed on an insulating layer located on the second source electrode 319S and the second drain electrode 319D.

[0111] The first oxide semiconductor pattern 311 includes a second channel region 311CH through which charge carriers move, and also includes a second source region 311S and a second drain region 311D, wherein the second source region 311S and the second drain region 311D are configured such that the second channel region 311CH is located between the second source region 311S and the second drain region 311D.

[0112] The second channel region 311CH is the region where the first oxide semiconductor pattern 311 overlaps with the second gate electrode 314. Therefore, in order to reduce the size of the driving thin-film transistor DT, the width of the second channel region 311CH needs to be reduced by reducing the linewidth of the second gate electrode 314.

[0113] The second source region 311S has multiple conductive regions 311b and 311c. These regions become conductive by implanting impurity ions into them. Similarly, the second drain region 311D has multiple conductive regions 311f and 311e. These regions also become conductive by implanting impurity ions into them. Furthermore, non-conductive regions 311a and 311d, which are not implanted with impurity ions, are respectively located between conductive regions 311b and 311c and between conductive regions 311f and 311e.

[0114] Conductive and non-conductive regions can be alternately set. Note that, as seen above, in this article, "non-conductive region" can refer to a region with a lower conductivity than the conductive region. For example, a non-conductive region can be an undoped intrinsic region.

[0115] Specifically, the second source region 311S can be formed such that the non-conductive region 311a, the first conductive region 311b, the non-conductive region 311a, and the second conductive region 311c are sequentially adjacent to each other. Similarly, the second drain region 311D can be formed such that the non-conductive region 311d, the first conductive region 311e, the non-conductive region 311d, and the second conductive region 311f are sequentially adjacent to each other. Furthermore, the second conductive regions 311c and 311f are adjacent to the second channel region 311CH.

[0116] The non-conductive regions 311a and 311d included in the second source region 311S and the second drain region 311D are used as channel regions, thereby exhibiting the effect of significantly increasing the length of the second channel region 311CH.

[0117] Therefore, in the driving thin film transistor DT according to the embodiments of the present disclosure, since the non-conductive regions 311a and 311d included in the second source region 311S and the second drain region 311D are used as channel regions, a driving thin film transistor DT with a smaller size can be realized by reducing the length of the second channel region 311CH.

[0118] Reference Figure 5BThe first conductive region 311b of the second source region 311S can be the region in contact with the second source electrode 319S. The first conductive region 311e of the second drain region 311D can be the region in contact with the second drain electrode 319D. The areas of the first conductive regions 311b and 311e may be larger than the contact area between the second source electrode 319S and the second source region 311S, and the contact area between the second drain electrode 319D and the second drain region 311D, respectively. This is because by bringing the second source region 311S and the second drain region 311D into contact with impurity ions, the first conductive regions 311b and 311e become conductive, at which point the impurity ions diffuse within specific portions of the second source region 311S and the second drain region 311D. Therefore, the areas of the first conductive regions 311b and 311e may be larger than the contact area between the second source electrode 319S and the second source region 311S, and the contact area between the second drain electrode 319D and the second drain region 311D, respectively.

[0119] In the following text, reference will be made to Figure 9A The process of forming the first conductive regions 311b and 311e according to embodiments of the present disclosure is described in more detail.

[0120] A first oxide semiconductor pattern 311 is formed on the upper buffer layer 310, and then a second gate insulating layer 313 that electrically insulates the first oxide semiconductor pattern 311 is deposited on the first oxide semiconductor pattern 311. If the first oxide semiconductor pattern 311 comes into contact with hydrogen particles, the oxygen vacancies contained in the first oxide semiconductor pattern 311 combine with the hydrogen particles, and thus the first oxide semiconductor pattern 311 becomes conductive. Therefore, the second gate insulating layer 313 can be formed of silicon oxide (SiO2) that does not contain hydrogen particles.

[0121] A fifth contact hole CH5 and a sixth contact hole CH6 are formed in the second gate insulating layer 313 to expose the second source region 311S and the second drain region 311D, respectively.

[0122] In addition to the fifth contact hole CH5 and the sixth contact hole CH6, a seventh contact hole CH7, a third contact hole CH3, a fourth contact hole CH4, a first contact hole CH1, and a second contact hole CH2 are simultaneously formed. The seventh contact hole CH7 exposes the upper surface of the first light-blocking pattern 308, which is disposed below the first oxide semiconductor pattern 311 to protect the first oxide semiconductor pattern 311 from light. The third contact hole CH3 and the fourth contact hole CH4 expose a portion of the third source region 312S and a portion of the third drain region 312D of the second oxide semiconductor pattern 312, respectively. The first contact hole CH1 and the second contact hole CH2 expose a portion of the first source region 303S and a portion of the first drain region 303D of the first thin-film transistor GT disposed in the non-display area NA, respectively. In this case, hydrogen particles are generated in the first interlayer insulating layer 302 and the second sub-buffer layer 310b. The first interlayer insulating layer 302 is formed on the first polycrystalline semiconductor pattern 303 and contains hydrogen particles, and the second sub-buffer layer 310b is formed on the first light-blocking pattern 308 and contains hydrogen particles. The generated hydrogen particles come into contact with the first oxide semiconductor pattern 311, thereby forming the first conductive regions 311b and 311e.

[0123] The second conductive region 311c of the second source region 311S may be the portion of the second source region 311S located between the second gate electrode 314 and the second source electrode 319S. Furthermore, the second conductive region 311f of the second drain region 311D may be the portion of the second drain region 311D located between the second gate electrode 314 and the second drain electrode 319D. Therefore, the ends of the second source electrode 319S and the second drain electrode 319D may be spaced apart from the corresponding ends of the second gate electrode 314.

[0124] In the following text, reference will be made to Figure 9B Describe the process of forming the second conductive regions 311c and 311f.

[0125] After forming the second source electrode 319S and the second drain electrode 319D, a second interlayer insulating layer 316 is formed to cover the second source electrode 319S and the second drain electrode 319D. The second gate electrode 314 is formed on the second interlayer insulating layer 316.

[0126] The second gate electrode 314 is configured to overlap with the first oxide semiconductor pattern 311, and the overlapping region of the first oxide semiconductor pattern 311 becomes the second channel region 311CH.

[0127] like Figure 5B As shown, the second gate electrode 314 and the second source electrode 319S are spaced apart by a predetermined distance. Furthermore, as... Figure 5BAs shown, the second gate electrode 314 and the second drain electrode 319D are spaced apart by a predetermined distance. Impurity ions, such as Group III or Group V ions, such as boron (B) or phosphorus (P), are implanted via ion implantation. At this time, the second gate electrode 314, the second source electrode 319S, and the second drain electrode 319D serve as a mask for the implanted ions, thereby forming the second conductive regions 311c and 311f. Therefore, unlike the first conductive regions 311b and 311e, the second conductive regions 311c and 311f are formed by ion implantation.

[0128] In addition, the driving thin film transistor DT also includes a first light blocking pattern 308, which is inserted into the upper buffer layer 310 to overlap with the first oxide semiconductor pattern 311.

[0129] Basically, the first light-blocking pattern 308 can be inserted into the upper buffer layer 310. In one embodiment of this disclosure, multiple sub-upper buffer layers are provided. That is, in the upper buffer layer 310, a second sub-upper buffer layer 310b and a third sub-upper buffer layer 310c can be stacked sequentially. Alternatively, in the upper buffer layer 310, a first sub-upper buffer layer ( Figure 3 (not shown in the image), second sub-buffer layer 310b and third sub-buffer layer 310c.

[0130] Reference Figure 3 A first light-blocking pattern 308 is disposed on a first interlayer insulating layer 307. In addition, a second sub-buffer layer 310b completely covers the top of the first light-blocking pattern 308, and a third sub-buffer layer 310c is formed on the second sub-buffer layer 310b.

[0131] The first sub-buffer layer and the third sub-buffer layer 310c can be formed of silicon oxide (SiO2).

[0132] The first and third sub-buffer layers 310c are made of silicon oxide (SiO2) that does not contain hydrogen particles, thereby protecting the oxide semiconductor pattern whose reliability may be degraded due to the infiltration of hydrogen particles during the heat treatment process.

[0133] The second sub-buffer layer 310b can be made of silicon nitride (SiNx), thus possessing excellent hydrogen particle trapping capabilities. The second sub-buffer layer 310b can be formed on a portion of the first sub-buffer layer to cover both the upper and side surfaces of the first light-blocking pattern 308, thereby completely sealing the first light-blocking pattern 308. Alternatively, the second sub-buffer layer 310b can be formed on the entire surface of the first sub-buffer layer on which the first light-blocking pattern 308 is formed. Silicon nitride (SiNx) has a better ability to trap hydrogen particles than silicon oxide (SiO2). That is, when a hydrogenation process is performed to introduce hydrogen particles into the first polycrystalline semiconductor pattern 303 of the first thin-film transistor GT, the second sub-buffer layer 310b, including silicon nitride, traps the hydrogen particles generated in the first interlayer insulating layer 307, thereby protecting the oxide semiconductor pattern formed thereon from the effects of hydrogen particles. When hydrogen particles permeate the oxide semiconductor pattern, the following problem arises: depending on its formation location, the oxide semiconductor has different threshold voltages or different channel conductivities.

[0134] In particular, ensuring the reliability of driving thin-film transistors is important, as driving thin-film transistors directly contributes to the operation of light-emitting elements.

[0135] Therefore, in embodiments of this disclosure, since the second sub-buffer layer 310b is formed to cover the first light-blocking pattern 308, the reliability of the driving thin-film transistor DT can be prevented from deteriorating due to hydrogen particles.

[0136] Furthermore, in embodiments of this disclosure, the first light-blocking pattern 308 can be formed as a metal layer comprising titanium (Ti), a material with excellent ability to capture hydrogen particles. For example, the metal layer can be a single layer of titanium, a multilayer of molybdenum (Mo) and titanium (Ti), or an alloy of molybdenum (Mo) and titanium (Ti). However, this disclosure is not limited to these, and any other metal layer comprising titanium (Ti) can be used.

[0137] Titanium (Ti) traps hydrogen particles diffusing in the upper buffer layer 310 to prevent them from reaching the first oxide semiconductor pattern 311. Therefore, in the driving thin-film transistor DT according to an embodiment of this disclosure, the first light-blocking pattern 308 is formed as a layer of a metal such as titanium capable of trapping hydrogen particles, and covered with a silicon nitride (SiNx) layer capable of trapping hydrogen particles, thereby mitigating the problem of the oxide semiconductor pattern's reliability being degraded due to hydrogen particles.

[0138] The second sub-buffer layer 310b, which includes silicon nitride (SiNx), can selectively cover only the first light-blocking pattern 308.

[0139] The second sub-buffer layer 310b is formed of a material different from that of the first sub-buffer layer. That is, the second sub-buffer layer 310b is formed as a silicon nitride (SiNx) film. Therefore, when the second sub-buffer layer 310b is deposited over the entire surface of the display area, film lifting may occur. To solve this problem, the second sub-buffer layer 310b can be selectively formed only on the necessary portions, i.e., only at the locations where the first light-blocking pattern 308 is formed.

[0140] Functionally, the first light-blocking pattern 308 and the second sub-buffer layer 310b are preferably formed vertically below the first oxide semiconductor pattern 311 to overlap with it. Furthermore, the first light-blocking pattern 308 can be formed larger than the first oxide semiconductor pattern 311 to completely overlap it.

[0141] The second source electrode 319S that drives the thin-film transistor DT can be electrically connected to the first light-blocking pattern 308.

[0142] As described above, when the first light-blocking pattern 308 is inserted into the upper buffer layer 310 and the second source electrode 319S is electrically connected to the first light-blocking pattern 308, the following additional effects can be obtained.

[0143] This will refer to Figure 8A and Figure 8B Describe it.

[0144] Figure 8A Is Figure 3 A cross-sectional view of the driving thin-film transistor DT in the component shown. Figure 8B This is a circuit diagram showing the relationship between the parasitic capacitance generated in the driving thin-film transistor DT and the voltage applied to it.

[0145] Reference Figure 8A Because the second source region 311S and the second drain region 311D become conductive, a parasitic capacitance C is generated inside the first oxide semiconductor pattern 311. act A parasitic capacitance C is generated between the second gate electrode 314 and the first oxide semiconductor pattern 311. gi Furthermore, a parasitic capacitance C is generated between the first light-blocking pattern 308 and the first oxide semiconductor pattern 311, which are electrically connected to the second source electrode 319S. buf .

[0146] The first oxide semiconductor pattern 311 and the first light-blocking pattern 308 are electrically connected to each other via the second source electrode 319S, and therefore have a parasitic capacitance C. act and parasitic capacitance Cbuf They are connected in parallel and have a parasitic capacitance C. act and parasitic capacitance C gi They are connected in series. Additionally, when V... gat (ΔV gat When the gate voltage of ) is applied to the second gate electrode 314, the effective voltage V actually applied to the first oxide semiconductor pattern 311 is eff (ΔV) satisfies the following equation 1.

[0147] [Equation 1]

[0148] ΔV=Cgi / (Cgi+Cact+Cbuf)×ΔVgat

[0149] Therefore, the effective voltage applied to the channel of the first oxide semiconductor pattern 311 is related to the parasitic capacitance C. buf It is inversely proportional, and therefore can be adjusted by regulating the parasitic capacitance C. buf To adjust the effective voltage applied to the first oxide semiconductor pattern 311.

[0150] In other words, when the first light-blocking pattern 308 is positioned close to the first oxide semiconductor pattern 311 to increase the parasitic capacitance C buf At that time, the actual value of the current flowing through the first oxide semiconductor pattern 311 may decrease.

[0151] The reduction in the effective value of the current flowing through the first oxide semiconductor pattern 311 means that the voltage V actually applied to the second gate electrode 314 can be used. gat The range of control for driving thin-film transistors (DTs) has been expanded.

[0152] The effective voltage Veff can be adjusted by the ratio of parasitic capacitance Cbuf to parasitic capacitance Cgi. Therefore, in Figure 3 In the embodiment of this disclosure shown, by positioning the first light-blocking pattern 308 relatively close to the first oxide semiconductor pattern 311, the parasitic capacitance Cbuf is greater than the parasitic capacitance Cgi, thereby expanding the range of grayscale values ​​in which the driving thin-film transistor DT can perform control. Therefore, even at low grayscale values, the light-emitting element can be precisely controlled, and thus the problem of uneven brightness that often occurs at low grayscale values ​​can be solved.

[0153] The first switching thin-film transistor ST includes: a second oxide semiconductor pattern 312 formed on an upper buffer layer 310; a second gate insulating layer 313 covering the second oxide semiconductor pattern 312; a third source electrode 318S and a third drain electrode 318D formed on the second gate insulating layer 313; a second interlayer insulating layer 316 formed on the third source electrode 318S and the third drain electrode 318D; and a third gate electrode 315 formed on the second interlayer insulating layer 316.

[0154] The first switching thin-film transistor ST according to an embodiment of this disclosure has a configuration that is generally similar to that of the driving thin-film transistor DT. However, the first switching thin-film transistor ST has a smaller size than the driving thin-film transistor DT. For example, the driving thin-film transistor DT may have a channel length of 7 μm, and the first switching thin-film transistor ST may have a channel length of 3 μm.

[0155] As the channel size of the switching thin-film transistor (ST) decreases, the electrical power consumed decreases. When the components of this disclosure, namely the source and drain regions, are configured such that conductive and non-conductive regions alternate, the effective length of the channel of the switching thin-film transistor (ST) can be increased, even though the actual channel size remains constant. Therefore, when embodiments of this disclosure are designed to consume the same electrical power as conventional devices, the channel length can be reduced.

[0156] The second oxide semiconductor pattern 312 includes a third channel region 312CH through which charge carriers move, and also includes a third source region 312S and a third drain region 312D, wherein the third source region 312S and the third drain region 312D are provided when the third channel region 312CH is located between the third source region 312S and the third drain region 312D.

[0157] The third channel region 312CH is the region where the second oxide semiconductor pattern 312 overlaps with the third gate electrode 315. Therefore, in order to reduce the size of the first switching thin-film transistor ST, the width of the third channel region 312CH needs to be reduced by reducing the linewidth of the third gate electrode 315.

[0158] The third source region 312S is provided with a plurality of conductive regions 312b and 312c that become conductive by implanting impurity ions therein, and the third drain region 312D is provided with a plurality of conductive regions 312f and 312e that become conductive by implanting impurity ions therein. Furthermore, non-conductive regions 312a and 312d that are not implanted with impurity ions are respectively provided between conductive regions 312b and 312c and between conductive regions 312f and 312e.

[0159] Conductive and non-conductive areas can be set alternately.

[0160] Specifically, the third source region 312S can be formed such that the non-conductive region 312a, the third conductive region 312b, the non-conductive region 312a, and the fourth conductive region 312c are arranged adjacent to each other in sequence. Similarly, the third drain region 312D can be formed such that the non-conductive region 312d, the third conductive region 312e, the non-conductive region 312d, and the fourth conductive region 312f are arranged adjacent to each other in sequence. Furthermore, the fourth conductive regions 312c and 312f are arranged adjacent to the third channel region 312CH.

[0161] The non-conductive regions 312a and 312d included in the third source region 312S and the third drain region 312D are used as channel regions, thus exhibiting the effect of greatly increasing the length of the third channel region 312CH.

[0162] Therefore, in the first switching thin-film transistor ST according to the embodiments of the present disclosure, since the non-conductive regions 312a and 312d included in the third source region 312S and the third drain region 312D are used as channel regions, the first switching thin-film transistor ST with a smaller size can be achieved by reducing the length of the third channel region 312CH.

[0163] Figure 5B The configuration of the driving thin-film transistor DT shown is essentially the same as that of the first switching thin-film transistor ST.

[0164] The first switching thin-film transistor ST may further include a second light-blocking pattern 304 disposed below and overlapping the second oxide semiconductor pattern 312. Specifically, the second light-blocking pattern 304 may be made of the same material as the first gate electrode 306 and may be formed on the upper surface of the first gate insulating layer 302. The second light-blocking pattern 304 may not be a necessary component. That is, in some cases, the second light-blocking pattern 304 can be omitted from the first switching thin-film transistor ST.

[0165] Alternatively, the second light-blocking pattern 304 can be formed on the same layer as the second storage capacitor electrode 309 and made of the same material as the second storage capacitor electrode 309, instead of being formed on the same layer as the first gate electrode 306 and made of the same material as the first gate electrode 306. That is, when a sub-pixel PX is provided with multiple switching thin-film transistors, the multiple switching thin-film transistors can each have the second light-blocking pattern 304 formed in different layers, thereby increasing design freedom.

[0166] Although the second light-blocking pattern 304 is in Figure 3 The first switching thin-film transistor ST is shown without electrical connection to the third gate electrode 315, but the second light-blocking pattern 304 can be electrically connected to the third gate electrode 315 to form a dual-gate structure. Because the first switching thin-film transistor ST has a dual-gate structure, the flow of current through the third channel region 312CH can be more precisely controlled, thereby reducing the overall size of the display device and achieving a high-definition display.

[0167] The second oxide semiconductor pattern 312 is made of oxide semiconductor material and includes: a third channel region 312CH, which maintains the intrinsic state of the oxide semiconductor material rather than being doped with impurities; and a third source region 312S and a third drain region 312D, wherein a conductive region implanted with impurities and a non-conductive region not implanted with impurities are combined.

[0168] Similar to the first source electrode 317S and the first drain electrode 317D, as well as the second source electrode 319S and the second drain electrode 319D, each of the third source electrode 318S and the third drain electrode 318D may be in the form of a single layer or multiple layers made of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), or alloys thereof.

[0169] The third source electrode 318S and the third drain electrode 318D are formed on the second gate insulating layer 313 simultaneously with the first source electrode 317S and the first drain electrode 317D, as well as the second source electrode 319S and the second drain electrode 319D, and are made of the same material as the first source electrode 317S and the first drain electrode 317D, as well as the second source electrode 319S and the second drain electrode 319D. Therefore, the number of masking processes can be reduced.

[0170] Among them, reference Figure 3 The pixel circuit portion 370 according to an embodiment of the present disclosure also includes a storage capacitor Cst.

[0171] The storage capacitor Cst stores the data voltage applied to it via the data line during a specified time period, and then supplies the data voltage to the light-emitting element.

[0172] The storage capacitor Cst includes two corresponding electrodes and a dielectric disposed between them. The storage capacitor Cst includes: a first storage capacitor electrode 305, which is made of the same material as the first gate electrode 306 and disposed on the same layer as the first gate electrode 306; and a second storage capacitor electrode 309, which is made of the same material as the first light-blocking pattern 308 and disposed on the same layer as the first light-blocking pattern 308.

[0173] The first interlayer insulating layer 307 is located between the first storage capacitor electrode 305 and the second storage capacitor electrode 309.

[0174] The second storage capacitor electrode 309 of the storage capacitor Cst can be electrically connected to the second source electrode 319S.

[0175] Next, we will refer to Figure 6 An organic light-emitting display device according to a second embodiment of this disclosure is described. Except for the second gate electrode 314 and the third gate electrode 315, the components of the second embodiment of this disclosure are the same as those of the first embodiment.

[0176] Reference Figure 6 In the second embodiment, the second gate electrode 314 and the third gate electrode 315 are formed on the same layer as the second source electrode 319S and the second drain electrode 319D. The second gate electrode 314 is disposed between the second source electrode 319S and the second drain electrode 319D. The third source electrode 318S and the third drain electrode 318D are disposed on the same layer as the second gate electrode 314 and the third gate electrode 315.

[0177] The second gate electrode 314 and the third gate electrode 315 are formed simultaneously with each other using the same material. However, the second gate electrode 314 and the third gate electrode 315 may be formed of the same material as the second source electrode 319S and the third source electrode 318S or a different material.

[0178] Since the second gate electrode 314, the second source electrode 319S, and the third source electrode 318S are disposed on the same layer, the gate line 338 that applies the gate voltage to the second gate electrode 314 and the data lines (not shown) that apply the source voltage to the second source electrodes 319S and the third source electrodes 318S need to be located in different layers. The gate lines and data lines are arranged to intersect each other to define sub-pixels, and therefore need to be formed in different layers to prevent short circuits when the gate lines and data lines intersect each other. Therefore, in Figure 6 In the second embodiment of the present disclosure shown, the gate line 338 may be disposed on the second interlayer insulating layer 316 and may be connected to the second gate electrode 314 and the third gate electrode 315 through the contact hole CHG.

[0179] When the gate line 338 is formed on the second interlayer insulating layer 316, the gate line 338 can be covered by the third interlayer insulating layer 317 to electrically insulate the gate line 338 from the outside.

[0180] In the second embodiment, the upper buffer layer 310 is shown as having a three-layer structure. That is, the upper buffer layer 310 can be formed such that a first sub-upper buffer layer 310a, a second sub-upper buffer layer 310b, and a third sub-upper buffer layer 310c are stacked sequentially. In particular, the second sub-upper buffer layer 310b may comprise a silicon nitride (SiNx) with excellent ability to capture hydrogen particles. The first sub-upper buffer layer 310a and the third sub-upper buffer layer 310c may be silicon oxide (SiO2) layers that do not contain hydrogen particles.

[0181] The first light-blocking pattern 308 is disposed on the second sub-buffer layer 310b.

[0182] Although the upper buffer layer 310 is described in the second embodiment as having a structure with three sub-upper buffer layers stacked, this structure of the upper buffer layer 310 is also applicable to the first embodiment.

[0183] Next, we will refer to Figure 7 A third embodiment of the present disclosure is described.

[0184] The third embodiment is the same as the first embodiment, except for the positions of the second gate electrode 314, the third gate electrode 315, and the first light blocking pattern 308.

[0185] As described above, referring to Equation 1 and Figure 8A As the distance from the first oxide semiconductor pattern 311 to the first light-blocking pattern 308 (e.g., the vertical distance in the direction perpendicular to the surface of the substrate 101) decreases, C buf The value increases, and the effective voltage V eff The value of (ΔV) decreases.

[0186] [Equation 1]

[0187] ΔV=Cgi / (Cgi+Cact+Cbuf)×ΔVgat

[0188] As the distance from the first oxide semiconductor pattern 311 to the second gate electrode 314 (e.g., the vertical distance in a direction perpendicular to the surface of the substrate 101) increases, C gi The value decreases, and the effective voltage V eff The value of decreases. That is, when C... buf The value increases and C gi When the value decreases, V eff The value may decrease significantly. Decrease V eff The value implies an increase in the range of voltages that can actually be applied to the gate electrode to control it. In other words, the s-factor value of the thin-film transistor DT can be increased.

[0189] The first switching thin-film transistor ST needs to have a high operating speed. To increase the operating speed of the first switching thin-film transistor ST, it is necessary to reduce the distance between the second oxide semiconductor pattern 312 and the third gate electrode 315 (e.g., the vertical distance in the direction perpendicular to the surface of the substrate 101). Therefore, in the third embodiment of this disclosure, the second gate electrode 314 is disposed on the second interlayer insulating layer 316, the third gate electrode 315 is disposed on the second gate insulating layer 313, and the first light-blocking pattern 308 is disposed on the second sub-buffer layer 310b. Therefore, the s-factor value of the driving thin-film transistor DT increases, and the operating speed of the first switching thin-film transistor ST increases, thereby realizing a highly efficient pixel circuit portion of the sub-pixel.

[0190] Additionally, refer to Figure 3 A first planarization layer PLN1 and a second planarization layer PLN2 can be sequentially formed on the pixel circuit portion 370 to planarize the upper end of the pixel circuit portion 370. The light-emitting element portion 380 includes: a first electrode 323, which is an anode; a second electrode 327, which is a cathode corresponding to the first electrode 323; and a light-emitting layer 325, which is located between the first electrode 323 and the second electrode 327. The first electrode 323 is formed in each sub-pixel.

[0191] The light-emitting element portion 380 is connected to the pixel circuit portion 370 via a connection electrode 321, which is formed on the first planarization layer PLN1. Specifically, the first electrode 323 of the light-emitting element portion 380 and the second drain electrode 319D of the driving thin-film transistor DT constituting the pixel circuit portion 370 are connected to each other via the connection electrode 321.

[0192] The first electrode 323 is connected to the connecting electrode 321, which is exposed through a contact hole CH9 formed through the second planarization layer PLN2. Furthermore, the connecting electrode 321 is connected to the second drain electrode 319D, which is exposed through a contact hole CH8 formed through the first planarization layer PLN1.

[0193] The first electrode 323 can be formed as a multilayer structure, comprising a transparent conductive film and an opaque conductive film with high reflectivity. The transparent conductive film can be formed of a material with a relatively high work function, such as indium tin oxide (ITO) or indium zinc oxide (IZO), and the opaque conductive film can be formed as a single layer or multilayer structure comprising Al, Ag, Cu, Pb, Mo, Ti, or alloys thereof. For example, the first electrode 323 can be formed such that the transparent conductive film, the opaque conductive film, and the transparent conductive film are stacked sequentially, or that the transparent conductive film and the opaque conductive film are stacked sequentially.

[0194] The light-emitting layer 325 is formed by stacking the hole-related layer, the organic light-emitting layer, and the electron-related layer on the first electrode 323 in either the order of the hole-related layer, the organic light-emitting layer, and the electron-related layer or in the reverse order.

[0195] The dam layer 324 is a pixel-defining film that exposes the first electrode 323 of each sub-pixel. The dam layer 324 may be formed of an opaque material (e.g., a black material) to prevent optical interference between adjacent sub-pixels. In this case, the dam layer 324 includes a light-blocking material, which includes at least one of a coloring pigment, organic black, or carbon. A spacer 326 may also be disposed on the dam layer 324.

[0196] A second electrode 327, serving as a cathode, is formed on the upper and side surfaces of the light-emitting layer 325, facing the first electrode 323, wherein the light-emitting layer 325 is located between the second electrode 327 and the first electrode 323. The second electrode 327 can be integrally formed on the entire surface of the active region. When the second electrode 327 is applied to a top-emitting organic light-emitting display device, the second electrode 327 can be formed as a transparent conductive film made of, for example, indium tin oxide (ITO) or indium zinc oxide (IZO).

[0197] The encapsulation portion 390 for preventing moisture penetration can also be provided on the second electrode 327.

[0198] The encapsulation portion 390 may include a first inorganic encapsulation layer 328a, a second organic encapsulation layer 328b, and a third inorganic encapsulation layer 328c stacked sequentially.

[0199] The first inorganic encapsulation layer 328a and the third inorganic encapsulation layer 328c can be formed of inorganic materials such as silicon oxide (SiOx). The second organic encapsulation layer 328b can be formed of organic materials, such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0200] As is apparent from the above description, in some embodiments of the organic light-emitting display device according to this disclosure, each of the driving thin-film transistors and the switching thin-film transistors includes an oxide semiconductor pattern, thereby reducing power consumption. Additionally, a thin-film transistor capable of efficient operation at low grayscale values ​​is provided. Furthermore, since each of the source and drain regions includes both conductive and non-conductive regions, an increased (e.g., significantly increased) channel length can be achieved. Therefore, this disclosure is applicable to high-definition organic light-emitting display devices in which a relatively large number of pixels are disposed per unit area.

[0201] It will be understood that the technical spirit of this disclosure has been described herein with reference to the foregoing description and accompanying drawings for illustrative purposes only, and that components may be combined, separated, substituted, and modified by those skilled in the art without departing from the scope and spirit of this disclosure. Therefore, exemplary embodiments of this disclosure are provided for illustrative purposes only, and these exemplary embodiments are not intended to limit the technical spirit of this disclosure. The scope of the technical spirit of this disclosure is not limited thereto. The scope of protection of this disclosure should be interpreted based on the appended claims, and it should be understood that all technical spirit falling within the scope of equivalents to the claims is included within the scope of protection of this disclosure.

Claims

1. An organic light-emitting display device, comprising: The substrate includes both the display area and the non-display area; as well as At least one thin-film transistor comprising a semiconductor pattern, said semiconductor pattern including a source region, a drain region, and a channel region disposed between said source region and said drain region. Each of the source region and the drain region includes conductive and non-conductive regions alternately disposed on the substrate. The conductive region includes a first conductive region spaced apart from the channel region and a second conductive region disposed adjacent to the channel region.

2. The organic light-emitting display device according to claim 1, wherein, The semiconductor pattern is an oxide semiconductor pattern.

3. The organic light-emitting display device according to claim 1, wherein, The at least one thin-film transistor includes: Gate electrode overlapping the semiconductor pattern; and The source and drain electrodes are respectively electrically connected to the source region and the drain region, and The first conductive region contacts the source electrode or the drain electrode, and the second conductive region is disposed between the source electrode or the drain electrode and the gate electrode.

4. The organic light-emitting display device according to claim 3, wherein, The first conductive region becomes conductive by contacting it with ions, and The second conductive region becomes conductive by injecting ions into it.

5. The organic light-emitting display device according to claim 3, wherein, The gate electrode is disposed in a layer located above the source electrode and the drain electrode.

6. The organic light-emitting display device according to claim 3, wherein, The gate electrode is disposed on the same layer as the source electrode and the drain electrode.

7. The organic light-emitting display device according to claim 3, wherein, The at least one thin-film transistor includes a driving thin-film transistor and at least one switching thin-film transistor, and The driving thin-film transistor includes a first light-blocking pattern disposed below the semiconductor pattern and connected to the source electrode.

8. The organic light-emitting display device according to claim 7, wherein, The driving thin-film transistor includes: First semiconductor pattern; The first gate electrode overlapping the first semiconductor pattern; and The first source electrode and the first drain electrode are connected to the first semiconductor pattern. The switching thin-film transistor includes: Second semiconductor pattern; The second gate electrode overlapping the second semiconductor pattern; and The second source electrode and the second drain electrode are connected to the second semiconductor pattern, and The first source electrode, the first drain electrode, the second source electrode, and the second drain electrode are disposed on the same layer.

9. The organic light-emitting display device according to claim 8, wherein, The first gate electrode and the second gate electrode are disposed on the same layer, and wherein the first gate electrode and the second gate electrode are disposed on a layer located above the first source electrode.

10. The organic light-emitting display device according to claim 8, wherein, The first gate electrode and the second gate electrode are disposed on the same layer as the first source electrode.

11. The organic light-emitting display device according to claim 8, wherein, The first gate electrode and the second gate electrode are disposed on different layers from each other, and Wherein, the vertical distance between the first gate electrode and the first semiconductor pattern is longer than the vertical distance between the second gate electrode and the second semiconductor pattern.

12. The organic light-emitting display device according to claim 11, wherein, The switching thin-film transistor includes a second light-blocking pattern, and The vertical distance between the second semiconductor pattern and the second light-blocking pattern is longer than the vertical distance between the first semiconductor pattern and the first light-blocking pattern.

13. The organic light-emitting display device according to claim 7, wherein, The driving thin-film transistor is disposed in the display area, and The switching thin-film transistor is disposed in at least one of the display area and the non-display area.

14. The organic light-emitting display device according to claim 12, wherein, The second light-blocking pattern is electrically connected to the second gate electrode.

15. A thin-film transistor array substrate, comprising: At least one thin-film transistor comprising a semiconductor pattern, said semiconductor pattern including a source region, a drain region, and a channel region disposed between said source region and said drain region. Each of the source region and the drain region includes at least two conductive regions and a non-conductive region disposed between the at least two conductive regions. The at least two conductive regions include a first conductive region spaced apart from the channel region and a second conductive region disposed adjacent to the channel region.

16. The thin-film transistor array substrate according to claim 15, wherein, The conductive region and the non-conductive region are alternately arranged in each of the source region and the drain region.

17. The thin-film transistor array substrate according to claim 15, wherein, The first conductive region becomes conductive by contacting it with ions, and The second conductive region becomes conductive by injecting ions into it.

18. The thin-film transistor array substrate according to claim 15, further comprising: The source electrode and drain electrode are respectively connected to the source region and the drain region; as well as A light-blocking pattern is disposed below the semiconductor pattern and connected to the source electrode.

19. The thin-film transistor array substrate according to claim 15, wherein, The semiconductor pattern is an oxide semiconductor pattern.

20. The thin-film transistor array substrate according to claim 15, wherein, The at least one thin-film transistor is at least one of a driving thin-film transistor and a switching thin-film transistor.

21. An organic light-emitting display device comprising a thin-film transistor array substrate according to any one of claims 15 to 20.

Images