Organic light emitting diode display device including low level lines

Abstract

An organic light emitting diode display device including a low level line includes a substrate having a plurality of sub-pixels, a driving transistor in each of the plurality of sub-pixels on the substrate, an organic light emitting diode on the driving transistor in each of the plurality of sub-pixels, and a low level line between the driving transistor and the organic light emitting diode in each of the plurality of sub-pixels.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2021-0184946, filed on December 22, 2021, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present invention relates to an organic light-emitting diode (OLED) display device, and more specifically, to an OLED display device including a low-level line, wherein coupling between the anode and the gate is minimized by providing a low-level line between the anode and the gate of adjacent sub-pixels. Background Technology

[0004] Recently, with the advent of the information-oriented society, the increasing attention paid to information displays for processing and displaying large amounts of information, and the growing demand for portable information media, the display field has developed rapidly. Consequently, various thin and light flat panel display devices have been developed and have attracted attention.

[0005] Among various flat panel display devices, organic light-emitting diode (OLED) displays are self-emissive devices, lacking the backlight unit used in non-emissive devices such as liquid crystal displays (LCDs). As a result, OLED displays offer advantages in viewing angle, contrast ratio, and power consumption, making them suitable for various applications.

[0006] In OLED displays, red, green, and blue light-emitting diodes emit red, green, and blue light, respectively, to display images. Shorter wavelengths of light have higher energy. As a result, when red, green, and blue subpixels have the same area, the lifetime of the blue emissive layer in the blue subpixel becomes shorter than the lifetime of the red and green emissive layers in the red and green subpixels.

[0007] To address the aforementioned issues, a technique was proposed to form the blue emitting layer of the blue sub-pixel with an area larger than that of the red and green emitting layers of the red and green sub-pixels. However, since the positions of the emitting layer of each sub-pixel and the pixel circuitry below it do not overlap, degradation such as crosstalk due to coupling occurs.

[0008] Specifically, when the blue emitting layer of the blue sub-pixel with the largest area is configured to overlap with the pixel circuit of the green sub-pixel, the anode of the blue sub-pixel and the gate of the driving transistor of the green sub-pixel overlap each other, resulting in coupling. As a result, the voltage of the gate of the driving transistor of the green sub-pixel changes due to the voltage of the anode of the blue sub-pixel, and the green sub-pixel does not display the predetermined brightness due to the blue sub-pixel. Summary of the Invention

[0009] Therefore, the present invention aims to provide an organic light-emitting diode display device that substantially overcomes one or more problems caused by the limitations and disadvantages of related technologies.

[0010] One object of the present invention is to provide an organic light-emitting diode display device including a low-level line, wherein by setting a low-level line between the anode and the gate in adjacent sub-pixels, the coupling between the anode and the gate in adjacent sub-pixels is minimized, the linewidth of the low-level line in the non-light-emitting area is reduced, and high-speed driving and narrow bezel are achieved.

[0011] Another object of the present invention is to provide an organic light-emitting diode display device that minimizes the coupling between the anode and the gate in adjacent sub-pixels by forming the storage electrode as a cover gate, preventing degradation such as crosstalk, and achieving high-speed driving.

[0012] Additional features and advantages of the invention will be set forth in the description which follows, will be apparent in part from the description, or may be learned by practice of the invention. These and other advantages of the invention will be realized and obtained by means of the structures specifically pointed out in the written description, the claims, and the drawings.

[0013] To achieve these and other advantages and in accordance with the intent of the invention, as embodied and broadly described herein, an organic light-emitting diode (OLED) display device includes: a substrate having a plurality of sub-pixels; a driving transistor in each of the plurality of sub-pixels on the substrate; a light-emitting diode located on the driving transistor in each of the plurality of sub-pixels; and a low-level line located between the driving transistor and the light-emitting diode in each of the plurality of sub-pixels.

[0014] In another aspect, an organic light-emitting diode (OLED) display device includes: a substrate having a first sub-pixel and a second sub-pixel; a driving transistor in each of the first and second sub-pixels on the substrate; a light-emitting diode located on the driving transistor in each of the first and second sub-pixels; and a low-level line located between the gate of the driving transistor of the first sub-pixel and the anode of the light-emitting diode of the second sub-pixel.

[0015] It will be understood that the foregoing general description and the following detailed description are illustrative and intended to provide further explanation of the claimed invention. Attached Figure Description

[0016] The accompanying drawings, which provide a further understanding of the invention and are incorporated in and form a part of this application, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. In the drawings:

[0017] Figure 1 This is a plan view illustrating an organic light-emitting diode display device including a low-level line according to an embodiment of the present invention;

[0018] Figure 2 This is a circuit diagram showing a sub-pixel of an organic light-emitting diode display device according to an embodiment of the present invention;

[0019] Figure 3 This is a view showing multiple signals used in a sub-pixel of an organic light-emitting diode display device according to an embodiment of the present invention;

[0020] Figure 4 This is a plan view showing three adjacent sub-pixels of an organic light-emitting diode display device according to an embodiment of the present invention;

[0021] Figure 5A It is along Figure 4 A sectional view taken by line Va-Va';

[0022] Figure 5B It is along Figure 4 A cross-sectional view taken by line Vb-Vb';

[0023] Figure 5C It is along Figure 4 A cross-sectional view taken by line Vc-Vc';

[0024] Figure 6 This is a view showing the parasitic capacitance of each sub-pixel of an organic light-emitting diode display device according to an embodiment of the present invention. Detailed Implementation

[0025] The advantages and features of the present invention, as well as its implementation methods, will become clear from the exemplary embodiments described below with reference to the accompanying drawings. However, the present invention can be implemented in different forms and should not be construed as limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided so that the disclosure of the present invention is thorough and complete and helps those skilled in the art to fully understand the scope of the invention. Furthermore, the present invention is defined only by the scope of the claims.

[0026] The shapes, dimensions, ratios, angles, and quantities disclosed in the drawings for the purpose of describing embodiments of the invention are merely examples. Therefore, the invention is not limited to the details illustrated. Similar reference numerals refer to similar elements throughout the application. In the following description, detailed descriptions of known functions or constructions may be omitted where it is determined that such detailed descriptions would unnecessarily obscure the focus of the invention. Where the terms "comprising," "having," and "including" are used in the description herein, additional terms may be added unless more restrictive terms such as "only" are used.

[0027] When interpreting an element, even if there is no explicit statement about the range of error or tolerance, the element should be interpreted as including such a range of error or tolerance.

[0028] When describing positional relationships, for example, when the positional relationship between two parts is described as “on top of,” “above,” “below,” and “after,” one or more additional parts may be placed between the two parts, unless more restrictive terms such as “exactly” or “directly” are used.

[0029] It will be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are merely used to distinguish one element from another. For example, without departing from the scope of the invention, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0030] Those skilled in the art will fully understand that the features of the various embodiments of the present invention can be combined or integrated with each other, either partially or entirely, and can be technically interoperable and driven in various ways. The embodiments of the present invention can be implemented independently of each other, or implemented together in an interdependent relationship.

[0031] The organic light-emitting diode display device including a low-level line according to embodiments of the present invention will be described in detail below with reference to the accompanying drawings. In the following description, the same reference numerals refer to the same elements throughout. Detailed descriptions of well-known functions or constructions relevant herein will be omitted or will be provided briefly when it is determined that such detailed descriptions would unnecessarily obscure the essential points of the inventive concept.

[0032] Figure 1 This is a plan view illustrating an organic light-emitting diode display device including a low-level line according to an embodiment of the present invention.

[0033] exist Figure 1 In this invention, an organic light-emitting diode (OLED) display device 110 includes a display area DA having a plurality of sub-pixels and a non-display area NDA having a plurality of link lines.

[0034] For example, the display area DA can be disposed in the central portion of the OLED display device 110, and the non-display area NDA can be disposed in the edge portion adjacent to the two long sides of the OLED display device 110.

[0035] Multiple sub-pixels may include a red sub-pixel SPr, a green sub-pixel SPg, and a blue sub-pixel SPb, and multiple connections may include: transmitting a high-level voltage VDD to multiple sub-pixels (see...). Figure 2The high-level connection (not shown); transmits a low-level voltage VSS (see) to multiple sub-pixels. Figure 2 The low-level connection 180; transmits data voltage Vdata to multiple sub-pixels (see...) Figure 2 The data connection (not shown); transmits the first gate voltage Scan1 (see) to multiple sub-pixels. Figure 2 ) and the second gate voltage Scan2 (see Figure 2 The gate interconnects of the sub-pixels; and the transmission of the light-emitting voltage EM to multiple sub-pixels (see Figure 2 The luminous connection of )

[0036] When the OLED display device 110 has a gate in panel (GIP) type in which the gate driving unit is formed in the display panel by the same process as the multiple sub-pixels, the gate interconnects and light-emitting interconnects of the non-display area NDA can be omitted.

[0037] A low-level line 164 corresponding to each of the multiple sub-pixels is provided in the display area DA. The low-level line 164 is connected to the low-level connection 180 of the non-display area NDA to transmit a low-level voltage VSS to the multiple sub-pixels, and can be configured to be parallel to the short side of the OLED display device 110.

[0038] Low-level line 164 and low-level connection 180 may have the same layer and the same material as each other.

[0039] The operation of the subpixels and OLED display device 110 will be described with reference to the accompanying drawings.

[0040] Figure 2 This is a circuit diagram illustrating a sub-pixel of an organic light-emitting diode display device according to an embodiment of the present invention. Figure 3 This is a view illustrating multiple signals used in a sub-pixel of an organic light-emitting diode display device according to an embodiment of the present invention.

[0041] exist Figure 2 In the OLED display device 110 according to an embodiment of the present invention, each of the red sub-pixel SPr, the green sub-pixel SPg, and the blue sub-pixel SPb includes a first to a sixth transistor T1 to T6, a storage capacitor Cst, and a light-emitting diode D.

[0042] For example, the first to sixth transistors T1 to T6 can be positive (P) type.

[0043] The first transistor T1, acting as a switching transistor, performs switching operations according to the first gate voltage Scan1. The gate of the first transistor T1 is connected to the first gate voltage Scan1, the source of the first transistor T1 is connected to the first capacitor electrode of the storage capacitor Cst and the source of the fourth transistor T4, and the drain of the first transistor T1 is connected to the data voltage Vdata.

[0044] The second transistor T2, acting as the driving transistor, switches on and off according to the voltage at the second capacitor electrode of the storage capacitor Cst. The gate of the second transistor T2 is connected to the second capacitor electrode of the storage capacitor Cst and the drain of the third transistor T3. The source of the second transistor T2 is connected to the high-level voltage VDD, and the drain of the second transistor T2 is connected to the source of the third transistor T3 and the source of the fifth transistor T5.

[0045] The third transistor T3 is switched on and off according to the second gate voltage Scan2. The gate of the third transistor T3 is connected to the second gate voltage Scan2, the source of the third transistor T3 is connected to the drain of the second transistor T2 and the source of the fifth transistor T5, and the drain of the third transistor T3 is connected to the gate of the second transistor T2 and the second capacitor electrode of the storage capacitor Cst.

[0046] Although the third transistor T3 is in Figure 2 In one embodiment, the transistor T3 has a dual-gate configuration, but in other embodiments, the third transistor T3 may have a single-gate configuration.

[0047] The fourth transistor T4 switches on and off according to the light-emitting voltage EM. The gate of the fourth transistor T4 is connected to the light-emitting voltage EM, the source of the fourth transistor T4 is connected to the source of the first transistor T1 and the first capacitor electrode of the storage capacitor Cst, and the drain of the fourth transistor T4 is connected to the drain of the sixth transistor T6 and the reference voltage Vref.

[0048] The fifth transistor T5, acting as a light-emitting transistor, switches on and off according to the light-emitting voltage EM. The gate of the fifth transistor T5 is connected to the light-emitting voltage EM, the source of the fifth transistor T5 is connected to the drain of the second transistor T2 and the source of the third transistor T3, and the drain of the fifth transistor T5 is connected to the source of the sixth transistor T6 and the anode of the light-emitting diode D.

[0049] The sixth transistor T6 switches according to the second gate voltage Scan2. The gate of the sixth transistor T6 is connected to the second gate voltage Scan2, the source of the sixth transistor T6 is connected to the drain of the fifth transistor T5 and the anode of the light-emitting diode D, and the drain of the sixth transistor T6 is connected to the drain of the fourth transistor T4 and the reference voltage Vref.

[0050] The storage capacitor Cst stores the data voltage Vdata and the threshold voltage Vth. The first capacitor electrode of the storage capacitor Cst is connected to the source of the first transistor T1 and the source of the fourth transistor T4, and the second capacitor electrode of the storage capacitor Cst is connected to the gate of the second transistor T2 and the drain of the third transistor T3.

[0051] An LED D is connected between the fifth transistor T5, the sixth transistor T6, and a low-level voltage VSS, and emits light with a brightness proportional to the current of the second transistor T2. The anode of the LED D is connected to the drain of the fifth transistor T5 and the source of the sixth transistor T6, and the cathode of the LED D is connected to the low-level voltage VSS.

[0052] exist Figure 3 During the first time period TP1, which serves as the initialization period, the first gate voltage Scan1 and the light-emitting voltage EM have a low-level voltage V1, and the second gate voltage Scan2 has a high-level voltage Vh. This causes the first transistor T1, the fourth transistor T4, and the fifth transistor T5 to be turned on, while the sixth transistor T6 is turned off. Consequently, the first capacitor electrode of the storage capacitor Cst has a first reference voltage Vref, thus initializing the gate of the second transistor T2.

[0053] During the second time period TP2, which serves as the sensing period, the first gate voltage Scan1 and the second gate voltage Scan2 have a low-level voltage V1, and the light-emitting voltage EM has a high-level voltage Vh. This causes the first transistor T1, the third transistor T3, and the sixth transistor T6 to be turned on, while the fourth transistor T4 and the fifth transistor T5 are turned off. As a result, the first capacitor electrode of the storage capacitor Cst has a data voltage Vdata, and the second capacitor electrode of the storage capacitor Cst has the sum of the difference between the data voltage Vdata and the reference voltage Vref (Vdata-Vref) and the threshold voltage Vth (Vdata-Vref+Vth), thereby storing the threshold voltage Vth in the storage capacitor Cst.

[0054] During the third time period TP3, which serves as the hold period, the first gate voltage Scan1, the second gate voltage Scan2, and the light-emitting voltage EM have a high-level voltage Vh, thereby turning off the first transistor T1, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6. As a result, the first capacitor electrode of the storage capacitor Cst has a data voltage Vdata, and the second capacitor electrode of the storage capacitor Cst has the sum of the difference between the data voltage Vdata and the reference voltage Vref (Vdata-Vref) and the threshold voltage Vth (Vdata-Vref+Vth).

[0055] During the fourth time period TP4, which is the light-emitting period, the first gate voltage Scan1 and the second gate voltage Scan2 have a high-level voltage Vh, and the light-emitting voltage EM has a low-level voltage V1. As a result, the first transistor T1, the third transistor T3, and the sixth transistor T6 are turned off, while the fourth transistor T4 and the fifth transistor T5 are turned on. Consequently, a current proportional to the square of the value obtained by subtracting the threshold voltage Vth from the gate-source voltage Vgs ((Vdata-Vref+Vth-VDD)-Vth=Vdata-Vref-VDD) flows into the second transistor T2, causing the light-emitting diode to emit light with a brightness corresponding to the current flowing into the second transistor T2.

[0056] In the OLED display device 110 according to an embodiment of the present invention, the light-emitting diode D emits light according to the operation of the first to sixth transistors T1 to T6 and the storage capacitor Cst to display an image. Shifts in the threshold voltage or degradation of the light-emitting diode D caused by the operation time can be compensated for by the sub-pixel SP, and the brightness can be adjusted by driving the light-emitting diode D according to the duty cycle corresponding to the emission time.

[0057] In the OLED display device 110, the light-emitting layers of multiple sub-pixels can have different areas based on the lifetime of the light-emitting layers of the multiple sub-pixels.

[0058] Figure 4 This is a plan view showing three adjacent sub-pixels of an organic light-emitting diode display device according to an embodiment of the present invention. Figure 5A It is along Figure 4 A cross-sectional view taken by line Va-Va'. Figure 5B It is along Figure 4 A cross-sectional view taken by line Vb-Vb'. Figure 5C It is along Figure 4 A sectional view taken by line Vc-Vc'.

[0059] exist Figure 4 According to an embodiment of the present invention, an OLED display device 110 includes: a plurality of first gate lines 136 for transmitting a first gate voltage Scan1; a plurality of second gate lines 138 for transmitting a second gate voltage Scan2; a plurality of light-emitting lines 140 for transmitting a light-emitting voltage EM; a plurality of reference lines 154 for transmitting a reference voltage Vref; a plurality of low-level lines 164 for transmitting a low-level voltage VSS; a plurality of high-level lines 156 for transmitting a high-level voltage VDD; and a plurality of data lines 158 for transmitting a data voltage Vdata. The low-level lines 164 may be located between a driving transistor T2 and a light-emitting diode D in each of the plurality of sub-pixels.

[0060] Multiple first gate lines 136, multiple second gate lines 138, and multiple light-emitting lines 140 are arranged in a horizontal direction parallel to the long side of the OLED display device 110, while multiple reference lines 154, multiple low-level lines 164, multiple high-level lines 156, and multiple data lines 158 are arranged in a vertical direction parallel to the short side of the OLED display device 110. The second gate lines 138 and light-emitting lines 140 intersect with the reference lines 154 and data lines 158 to define each of the multiple sub-pixels.

[0061] For example, in each of the red sub-pixel SPr, the green sub-pixel SPg, and the blue sub-pixel SPb, the second gate line 138, the light-emitting line 140, the first gate line 136, and the light-emitting line 140 may be arranged sequentially along the vertical direction, and the reference line 154, the low-level line 164, the high-level line 156, and the data line 158 may be arranged sequentially along the horizontal direction.

[0062] Each of the red sub-pixel SPr, the green sub-pixel SPg, and the blue sub-pixel SPb includes first to sixth transistors T1 to T6, a storage capacitor Cst, and a light-emitting diode D.

[0063] To compensate for the relatively short lifespan of the blue LED D, the blue LED D is formed to have a larger area than each of the red and green LEDs D. As a result, the anode 170 of the red LED D is disposed in the red sub-pixel SPr, the anode 170 of the green LED D is disposed in both the red and green sub-pixels SPr and SPg, and the anode 170 of the blue LED D is disposed in both the green and blue sub-pixels SPg and SPb.

[0064] Because the anode 170 of the light-emitting diode D of the blue sub-pixel SPb overlaps with the gate 134 of the second transistor T2, which is the driving transistor of the green sub-pixel SPg, coupling occurs between the anode of the blue sub-pixel SPb and the gate 134 of the green sub-pixel SPg, causing the green sub-pixel SPg to display abnormal brightness.

[0065] In the OLED display device 110 according to an embodiment of the present invention, since a low-level line 164 to which a low-level voltage VSS is applied is provided between the anode 170 of the light-emitting diode D of the blue sub-pixel SPb and the gate 134 of the second transistor T2 of the green sub-pixel SPg, the coupling between the anode 170 of the blue sub-pixel SPb and the gate 134 of the green sub-pixel SPg is minimized.

[0066] Furthermore, since the storage electrode 144 completely covers the gate 134 so that the gate 134 is not exposed to the outside of the storage electrode 144, the coupling between the anode 170 of the blue sub-pixel SPb and the gate 134 of the green sub-pixel SPg is further minimized.

[0067] exist Figures 5A to 5C In the first buffer layer 122, a first buffer layer 122 is disposed on the entire substrate 120, and a light-shielding layer 124 is disposed in the region of the second transistor T2 on the first buffer layer 122.

[0068] The substrate 120 may include glass or polyimide (PI), the first buffer layer 122 may have a double layer of inorganic insulating material such as silicon nitride (SiNx) or silicon oxide (SiO2), and the light-shielding layer 124 may contain an opaque metallic material such as molybdenum (Mo).

[0069] The first buffer layer 122 can block moisture that seeps in from below, and the light-shielding layer 124 can block light incident from below and collect the charge accumulated in the lower part.

[0070] The light-shielding layer 124 can be connected to the gate 134 to receive the gate voltage.

[0071] The second buffer layer 126 is disposed on the entire light-shielding layer 124, and the semiconductor layer 130 is disposed in the region of each of the first to sixth transistors T1 to T6.

[0072] The second buffer layer 126 may contain an inorganic insulating material such as silicon oxide (SiO2), and the semiconductor layer 130 may contain a semiconductor material such as silicon or an oxide semiconductor material. When the semiconductor layer 130 contains polysilicon, the semiconductor layer 130 may have an active region located in the central portion and a source-drain region located in the side portion.

[0073] A gate insulating layer 132 is disposed on the entire semiconductor layer 130, and a gate 134 is disposed on the gate insulating layer 132 above the semiconductor layer 130.

[0074] The gate insulating layer 132 may contain an inorganic insulating material such as silicon oxide (SiO2), and the gate 134 may contain a metallic material such as molybdenum (Mo).

[0075] The gate 134 may be located in the region corresponding to the first to sixth transistors T1 to T6 and the storage capacitor Cst.

[0076] The first gate line 136, the second gate line 138, and the light-emitting line 140 are disposed on the gate insulating layer 132. The first gate line 136, the second gate line 138, and the light-emitting line 140 may have the same layer and the same material as the gate 134.

[0077] A first interlayer insulating layer 142 is disposed over the entire gate 134, for example, over the gate 134 of the second transistor T2. A storage electrode 144 is disposed in the region of the storage capacitor Cst on the first interlayer insulating layer 142. The storage electrode 144 may be configured on the first interlayer insulating layer 142 to correspond to the gate 134 of the second transistor T2. The gate 134 in the region of the storage capacitor Cst may be the gate 134 of the second transistor T2 or an extension thereof.

[0078] The first interlayer insulating layer 142 may contain an inorganic insulating material such as silicon nitride (SiNx), and the storage electrode 144 may contain a metallic material such as molybdenum (Mo).

[0079] The gate 134, serving as the first capacitor electrode, the first interlayer insulating layer 142, and the storage electrode 144, serving as the second capacitor electrode, constitute the storage capacitor Cst. The storage electrode 144 has a larger area than the gate 134, such that the storage electrode 144 completely covers the gate 134 and the gate 134 is not exposed outside the storage electrode 144. The storage capacitor Cst can be connected to the driving transistor T2 in each of the plurality of sub-pixels.

[0080] Figure 5C The gate 134, the first interlayer insulating layer 142, and the storage electrode 144 of the storage capacitor Cst of the green sub-pixel SPg are shown.

[0081] The second interlayer insulating layer 146 is disposed on the entire storage electrode 144, and the source 150 and drain 152 are disposed in the regions of the first to sixth transistors T1 to T6 on the second interlayer insulating layer 146. For example, the drain 152 of the third transistor T3, which is connected to the gate 134 of the second transistor T2, may be disposed on the second interlayer insulating layer 146.

[0082] The second interlayer insulation layer may be a double layer of inorganic insulating material such as silicon nitride (SiNx) or silicon oxide (SiO2), and the source 150 and drain 152 may be a triple layer of metallic material such as titanium (Ti) and aluminum (Al).

[0083] The source 150 and drain 152 are connected to the side portion of the semiconductor layer 130 via contact holes in the gate insulating layer 132, the first interlayer insulating layer 142, and the second interlayer insulating layer 146, respectively. The semiconductor layer 130, gate 134, source 150, and drain 152 constitute each of the first to sixth transistors T1 to T6.

[0084] The drain 152 of the third transistor T3 is connected to the gate 134 of the second transistor T2 via contact holes of the first interlayer insulating layer 142 and the second interlayer insulating layer 146.

[0085] Figure 5A The semiconductor layer 130, gate 134, source 150, and drain 152 of the fifth transistor T5 of the blue sub-pixel SPb are shown. Figure 5B The drain 152 of the third transistor T3 and the gate 134 of the second transistor T2 are shown.

[0086] The reference line 154, the high-level line 156, and the data line 158 are disposed on the second interlayer insulating layer. The reference line 154, the high-level line 156, and the data line 158 may include the same layer and the same material as the source 150 and the drain 152.

[0087] The first planarization layer 160 is disposed on the entire source 150 and drain 152, and the connecting electrode 162 and the low-level line 164 are disposed in the region of the light-emitting diode D on the first planarization layer 160. The first planarization layer 160 may be disposed on the drain 152 of the third transistor T3.

[0088] The first planarization layer 160 may include an organic insulating material such as photoacryl, and the connecting electrode 162 and the low-level line 164 may include three layers of metallic materials such as titanium (Ti) and aluminum (Al).

[0089] The connection electrode 162 is connected to the drain 152 of the fifth transistor T5 via a contact hole in the first planarization layer 160. The low-level line 164 completely covers the drain 152 of the third transistor T3 and the gate 134 of the second transistor T2 of the green sub-pixel SPg, so that the drain 152 and the gate 134 are not exposed outside the low-level line 164. The fifth transistor T5 can be connected to the light-emitting diode D via the connection electrode 162. The low-level line 164 can be configured on the first planarization layer 160 to correspond to the gate 134 of the second transistor T2.

[0090] The connecting electrode 162 and the low-level line 164 may comprise the same layers and the same materials.

[0091] The second planarization layer 166 is disposed on the entire connecting electrode 162 and the low-level line 164, and the anode 170 is disposed in the region of the light-emitting diode D on the second planarization layer 166.

[0092] The second planarization layer 166 may include an organic insulating material such as optical acrylic, and the anode 170 may have three layers of a transparent conductive material such as indium tin oxide (ITO) and a metallic material such as a silver-palladium-copper (AgPdCu) ​​alloy.

[0093] The anode 170 is connected to the connection electrode 162 via a contact hole in the second planarization layer 166. The anode 170 may be disposed on the second planarization layer 166 corresponding to the low-level line 164.

[0094] A dam layer 172 is disposed on the edge portion of the anode 170, and a light-emitting layer 176 is disposed on the anode 170 exposed through the opening of the dam layer 172.

[0095] The dam layer 172 may include an organic insulating material such as polyimide (PI), and the light-emitting layer 176 may emit red light, green light, and blue light in the red sub-pixel SPr, the green sub-pixel SPg, and the blue sub-pixel SPb, respectively.

[0096] Spacer 174 is disposed on dam 172, and cathode 178 is disposed on the entire spacer 174.

[0097] Spacer 174 may include an organic insulating material such as polyimide (PI).

[0098] Cathode 178 can be connected to low-level line 164 in the non-display area NDA to receive low-level voltage VSS. Alternatively, the low-level voltage VSS supplied to cathode 178 can be applied to low-level line 164.

[0099] An anode 170, a light-emitting layer 176, and a cathode 178 constitute a light-emitting diode D. The light-emitting diode D can be disposed on a driving transistor T2 in each of multiple sub-pixels. Although in Figures 5A to 5C In one embodiment, the anode 170 is configured as the lower layer and the cathode 178 as the upper layer; however, in other embodiments, the anode may be configured as the upper layer and the cathode may be configured as the lower layer.

[0100] exist Figure 5B In the blue sub-pixel SPb, the anode 170 of the light-emitting diode D is configured to overlap with the gate 134 of the second transistor T2, which is the driving transistor for the green sub-pixel SPg.

[0101] As a result, due to the parasitic capacitance Cpara coupling between the anode 170 of the LED D of the blue sub-pixel SPb and the gate 134 of the second transistor T2 of the green sub-pixel SPg, and due to the voltage applied to the anode 170 of the LED D of the blue sub-pixel SPb, the voltage of the gate 134 of the second transistor T2 of the green sub-pixel SPg changes, causing the green sub-pixel SPg to display abnormal brightness.

[0102] In the OLED display device 110 according to an embodiment of the present invention, since a low-level line 164 having a low-level voltage is provided between the anode 170 of the light-emitting diode D of the blue sub-pixel SPb and the gate 134 of the second transistor T2 of the green sub-pixel SPg, the parasitic capacitance Cpara between the anode 170 of the light-emitting diode D of the blue sub-pixel SPb and the gate 134 of the second transistor T2 of the green sub-pixel SPg is minimized. As a result, coupling is minimized, and abnormal brightness display of the green sub-pixel SPg is prevented.

[0103] Furthermore, since the parasitic capacitance Cpara is minimized, the capacitance of the storage capacitor Cst, which is used to block the effects of the parasitic capacitance Cpara, is reduced. Because the load on signals such as gate voltage and data voltage is minimized, high-speed driving such as approximately 120Hz can be easily achieved.

[0104] Furthermore, by setting a low-level line 164 in each of the red sub-pixels SPr, SPg, and SPb, the low-level line on the edge portion of the short side is omitted or its width is reduced, thus minimizing the non-display area NDA to achieve a narrow bezel.

[0105] exist Figure 5C In the green sub-pixel SPg, the storage electrode 144 of the storage capacitor Cst completely covers the gate 134 (or its extension) of the second transistor T2, so that the gate 134 of the second transistor T2 is not exposed to the outside of the storage electrode 144.

[0106] The storage electrode 144 of the storage capacitor Cst of the green sub-pixel SPg overlaps with the anode 170 of the light-emitting diode D of the blue sub-pixel SPb. As a result, when the storage electrode 144 of the storage capacitor Cst of the green sub-pixel SPg exposes the gate 134 of the second transistor T2, coupling occurs between the gate 134 of the second transistor T2 of the green sub-pixel SPg and the anode 170 of the light-emitting diode D of the blue sub-pixel SPb, thereby allowing the green sub-pixel SPg to display abnormal brightness.

[0107] In the OLED display device 110 according to an embodiment of the present invention, since the storage electrode 144 of the storage capacitor Cst of the green sub-pixel SPg connected to the first transistor T1 and the fourth transistor T4 completely covers the gate 134 of the second transistor T2 and the gate 134 is not exposed outside the storage electrode 144 of the storage capacitor Cst of the green sub-pixel SPg, the parasitic capacitance Cpara between the anode 170 of the light-emitting diode D of the blue sub-pixel SPb and the gate 134 of the second transistor of the green sub-pixel SPg is further minimized, and the coupling is further minimized. As a result, abnormal brightness display of the green sub-pixel SPg is prevented.

[0108] Furthermore, since the parasitic capacitance Cpara is further minimized, the capacitance of the storage capacitor Cst, which is used to block the effects of the parasitic capacitance Cpara, is reduced. As a result, the load on signals such as gate voltage and data voltage is minimized, and high-speed driving such as approximately 120Hz can be easily achieved.

[0109] The minimization of parasitic capacitance will be explained with reference to the accompanying drawings.

[0110] Figure 6 This is a view showing the parasitic capacitance of each sub-pixel of an organic light-emitting diode display device according to an embodiment of the present invention.

[0111] exist Figure 6 In the comparative example (where the low-level line 164 is not positioned between the anode 170 of the LED D of the blue sub-pixel SPb and the gate 134 of the second transistor T2 of the green sub-pixel SPg), a total capacitance Ctot of approximately 238 fF and a parasitic capacitance Cpara of approximately 3.46 fF are present. The total capacitance Ctot is the sum of the gate-source capacitance, the capacitance of the storage capacitor Cst, and the parasitic capacitance Cpara connected to the gate 134 of the second transistor T2. The ratio of the parasitic capacitance Cpara to the total capacitance Ctot in the comparative example is approximately 1.46%.

[0112] An embodiment of the present invention (in which a low-level line 164 is disposed between the anode 170 of the light-emitting diode D of the blue sub-pixel SPb and the gate 134 of the second transistor T2 of the green sub-pixel SPg) has a total capacitance Ctot of approximately 242 fF and a parasitic capacitance Cpara of approximately 0.299 fF. The total capacitance Ctot is the sum of the gate-source capacitance, the capacitance of the storage capacitor Cst, and the parasitic capacitance Cpara connected to the gate 134 of the second transistor T2. The ratio of the parasitic capacitance Cpara to the total capacitance Ctot in this embodiment is approximately 0.12%.

[0113] In embodiments of the present invention, a substrate having a first sub-pixel and a second sub-pixel may be included. The first sub-pixel may be a green sub-pixel SPg, and the second sub-pixel may be a blue sub-pixel SPb. In this case, due to the low-level line 164 provided between the anode 170 of the light-emitting diode D of the blue sub-pixel SPb and the gate 134 of the second transistor T2 of the green sub-pixel SPg, the parasitic capacitance Cpara is reduced. As a result, coupling is reduced, and abnormal brightness display of the green sub-pixel SPg is prevented.

[0114] Furthermore, in embodiments of the present invention, the parasitic capacitance Cpara relative to the total capacitance Ctot is reduced, and the capacitance of the storage capacitor Cst constituting the total capacitance Ctot is reduced. As a result, the load on each sub-pixel relative to a signal such as data voltage is minimized, making it easier to achieve high-speed driving such as approximately 120Hz.

[0115] Therefore, in the OLED display device 110 according to an embodiment of the present invention, since a low-level line is provided between the anode and gate of a sub-pixel, the coupling between the anode and gate of adjacent sub-pixels is minimized, and the width of the low-level line in the non-display area is reduced. As a result, high-speed driving and narrow bezels are achieved.

[0116] Furthermore, since the storage electrode completely covers the gate and does not expose the gate, the coupling between the gate and anode of adjacent sub-pixels is minimized. As a result, degradation such as crosstalk is prevented, and high-speed driving is achieved.

[0117] Various modifications and variations may be made to this invention without departing from its scope, as will be apparent to those skilled in the art. Therefore, this invention is intended to cover any modifications and variations that fall within the scope of the appended claims and their equivalents.

Claims

1. An organic light-emitting diode (OLED) display device, comprising: A substrate with multiple sub-pixels; A driving transistor in each of the plurality of sub-pixels on the substrate; A light-emitting diode located on the driving transistor in each of the plurality of sub-pixels; as well as The low-level line in each of the plurality of sub-pixels, The low-level line is positioned between the gate electrode of the driving transistor and the anode of the light-emitting diode in adjacent sub-pixels that overlap.

2. The organic light-emitting diode display device according to claim 1, wherein the plurality of sub-pixels includes red sub-pixels, green sub-pixels, and blue sub-pixels. in, The anode of the light-emitting diode of the blue sub-pixel is configured to overlap with the gate electrode of the driving transistor of the green sub-pixel, and The low-level line is positioned between the gate of the driving transistor of the green sub-pixel and the anode of the light-emitting diode of the blue sub-pixel.

3. The organic light-emitting diode display device according to claim 2, wherein the anode of the light-emitting diode of the red sub-pixel is disposed in the red sub-pixel. The anode of the light-emitting diode in the green sub-pixel is disposed in both the red sub-pixel and the green sub-pixel. The anode of the blue sub-pixel is disposed in both the green sub-pixel and the blue sub-pixel.

4. The organic light-emitting diode display device according to claim 1, wherein a low-level voltage supplied to the cathode of the light-emitting diode is applied to the low-level line.

5. The organic light-emitting diode display device according to claim 1, further comprising a storage capacitor connected to a driving transistor in each of the plurality of sub-pixels. The storage capacitor includes a storage electrode that covers the gate of the corresponding driving transistor.

6. The organic light-emitting diode display device according to claim 1, wherein each of the plurality of sub-pixels comprises: A first transistor is connected to a data line and switches on and off according to a first gate voltage; A storage capacitor, the storage capacitor being connected to the first transistor and including a first capacitor electrode and a second capacitor electrode; As the second transistor of the driving transistor, the second transistor is connected to the high-level line and performs switching operation according to the voltage of the second capacitor electrode of the storage capacitor; A third transistor is connected to the storage capacitor and the second transistor and is switched on and off according to a second gate voltage; A fourth transistor is connected to the storage capacitor and the reference line and switches on and off according to the emission voltage; A fifth transistor, which is connected to the second transistor and the light-emitting diode and switches on and off according to the light-emitting voltage; as well as A sixth transistor is connected to the light-emitting diode and the reference line and performs switching operations according to the second gate voltage.

7. The organic light-emitting diode display device according to claim 6, wherein the fifth transistor is connected to the light-emitting diode via a connection electrode. The connecting electrode has the same layer and the same material as the low-level line.

8. The organic light-emitting diode display device according to claim 6, wherein a first interlayer insulating layer is disposed on the gate of the second transistor. A storage electrode is disposed on the first interlayer insulating layer corresponding to the gate of the second transistor. A second interlayer insulating layer is provided on the storage electrode. The drain of the third transistor, which is connected to the gate of the second transistor, is disposed on the second interlayer insulating layer. A first planarization layer is provided on the drain of the third transistor. The low-level line is disposed on the first planarization layer corresponding to the gate of the second transistor. A second planarization layer is provided on the low-level line. The anode of the light-emitting diode is disposed on a second planarization layer corresponding to the low-level line.

9. The organic light-emitting diode display device of claim 6, wherein the third transistor is further connected to the fifth transistor, the third transistor having a dual-gate configuration, and the second gate voltage is applied to both gates of the third transistor.

10. The organic light-emitting diode display device according to claim 6, wherein during the initialization period, the first gate voltage and the light-emitting voltage have a low-level voltage, and the second gate voltage has a high-level voltage. During the sensing period following the initialization period, the first gate voltage and the second gate voltage have the low-level voltage, and the light-emitting voltage has the high-level voltage. During the hold period following the sensing period, the first gate voltage, the second gate voltage, and the light-emitting voltage have the high-level voltage. During the light emission period following the holding period, the first gate voltage and the second gate voltage have the high-level voltage, and the light emission voltage has the low-level voltage.

11. The organic light-emitting diode display device according to claim 6, further comprising a first gate line for transmitting the first gate voltage, a second gate line for transmitting the second gate voltage, and a light-emitting line for transmitting the light-emitting voltage. The first gate line, the second gate line, and the light-emitting line are arranged in a horizontal direction parallel to the long side of the organic light-emitting diode display device, and the reference line, the low-level line, the high-level line, and the data line are arranged in a vertical direction parallel to the short side of the organic light-emitting diode display device.

12. The organic light-emitting diode display device according to claim 11, wherein the second gate line, the light-emitting line, the second gate line, the first gate line and the light-emitting line are arranged sequentially along the vertical direction, and the reference line, the low-level line, the high-level line and the data line are arranged sequentially along the horizontal direction.

13. The organic light-emitting diode display device of claim 5, wherein the storage electrode completely covers the gate such that the gate is not exposed to the outside of the storage electrode.

14. The organic light-emitting diode display device of claim 8, wherein the low-level line completely covers the drain of the third transistor and the gate of the second transistor, such that the drain of the third transistor and the gate of the second transistor are not exposed outside the low-level line.

15. The organic light-emitting diode display device of claim 1, further comprising a storage capacitor connected to a driving transistor in each of the plurality of sub-pixels. The first interlayer insulating layer, the second interlayer insulating layer, and the first planarization layer are disposed between the gate electrode of the driving transistor and the low-level line. The second planarization layer is disposed between the low-level line and the anode of the light-emitting diode, and The storage electrode of the storage capacitor is disposed between the first interlayer insulating layer and the second interlayer insulating layer, and covers the gate of the driving transistor.

16. The organic light-emitting diode display device according to claim 1, wherein the low-level line is configured to be parallel to the short side of the organic light-emitting diode display device.

17. An organic light-emitting diode display device, comprising: A substrate having adjacent first and second sub-pixels; The driving transistor in each of the first and second sub-pixels on the substrate; A light-emitting diode located on the driving transistor in each of the first sub-pixel and the second sub-pixel; as well as The low-level line located between the gate of the driving transistor of the first sub-pixel and the anode of the light-emitting diode of the second sub-pixel. Wherein, the anode of the light-emitting diode of the second sub-pixel is configured to overlap with the gate electrode of the driving transistor of the first sub-pixel.

18. The organic light-emitting diode display device of claim 17, further comprising a storage capacitor connected to a driving transistor in each of the first sub-pixel and the second sub-pixel. The storage capacitor includes a storage electrode that covers the gate of the corresponding driving transistor.

19. The organic light-emitting diode display device of claim 18, wherein the storage electrode completely covers the gate electrode such that the gate electrode is not disposed outside the storage electrode.

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