A display panel and display device

Abstract

This application provides a display panel and display device, including a display area and a non-display area. The non-display area surrounds at least a portion of the display area and includes a fan-shaped wiring area. The fan-shaped wiring area and the display area are arranged along a first direction. The display area includes multiple first signal lines, multiple adapter lines, and an edge area and a middle area arranged along a second direction. The first signal lines extend along the first direction, and the multiple first signal lines are arranged along the second direction, intersecting the first and second directions. The adapter lines are electrically connected to the first signal lines located in the edge area and extend from the edge area to the middle area. The fan-shaped wiring area includes multiple second signal lines, and the first signal lines and adapter lines located in the middle area are correspondingly connected to the second signal lines. This application can reduce the bezel width of the display panel at the fan-shaped wiring area without needing to increase the width of the peripheral scanning circuit, which is beneficial for achieving a multi-sided narrow bezel of the display panel.

Description

[Technical Field]

[0001] This application relates to the field of display technology, and in particular to a display panel and display device. [Background Technology]

[0002] In recent years, large-size display panels have become increasingly popular with users and have become a key research focus for major manufacturers. In large-size display panels, in order to reduce the bottom bezel, the bonding area used for bonding driver chips is usually bent to the back of the display panel. At this time, fan-shaped traces are used to connect the display area signal lines to the bonding area so as to electrically connect the display area signal lines to the driver chip.

[0003] To further reduce the width of the bottom bezel of the display panel, the existing method is to reduce the number of fan-shaped traces by connecting a multiplexer between the fan-shaped traces and the display area signal lines. However, the use of a multiplexer will compress the time for the fan-shaped traces to transmit data to the display area signal lines. In order to ensure the data writing time, it is usually necessary to increase the channel width of the transistor that outputs the scan signal in the peripheral scanning circuit so that the scan signal is not delayed too much and affects the data writing time.

[0004] However, increasing the channel width of the transistor that outputs the scanning signal will inevitably lead to an increase in the width of the peripheral scanning circuit, which is not conducive to the realization of multi-sided narrow bezels on the display panel.

[0005] [Application Content]

[0006] In view of this, embodiments of this application provide a display panel and a display device to solve the above problems.

[0007] In a first aspect, embodiments of this application provide a display panel, including a display area and a non-display area. The non-display area surrounds at least a portion of the display area and includes a fan-shaped wiring area. The fan-shaped wiring area and the display area are arranged along a first direction. The display area includes multiple first signal lines, multiple adapter lines, and an edge area and a middle area arranged along a second direction. The first signal lines extend along the first direction, and the multiple first signal lines are arranged along the second direction, with the first direction intersecting the second direction. The adapter lines are electrically connected to the first signal lines located in the edge area and extend from the edge area to the middle area. The fan-shaped wiring area includes multiple second signal lines, and the first signal lines and adapter lines located in the middle area are connected to the second signal lines.

[0008] In one implementation of the first aspect, the display area further includes a transition area located between the edge area and the middle area, and the fan-shaped trace area further includes multiple demultiplexers; wherein the input terminal of the demultiplexer is electrically connected to the corresponding second signal line, and the output terminal is electrically connected to the corresponding first signal line located in the transition area.

[0009] In one implementation of the first aspect, the adapter cable and the first signal line are located on different film layers.

[0010] In one implementation of the first aspect, the film layer containing the first signal line is located on the side of the film layer containing the adapter line facing the light-emitting surface of the display panel.

[0011] In one implementation of the first aspect, the display panel includes a transistor array layer located on the side of the film layer containing the adapter cable away from the light-emitting surface of the display panel.

[0012] In one implementation of the first aspect, the display area further includes a first trace located in the edge region and the transition region.

[0013] In one implementation of the first aspect, the first trace is a virtual trace.

[0014] In one implementation of the first aspect, the first trace is a first power supply voltage signal line.

[0015] In one implementation of the first aspect, the first trace and the adapter are set on the same layer.

[0016] In one implementation of the first aspect, the adapter cable includes a first part and a second part that are electrically connected to each other, the first part extending along a first direction and the second part extending along a second direction; the first trace includes a third part and a fourth part, the third part extending along the first direction and the fourth part extending along the second direction; wherein the third part of the first trace is disconnected at the second part of the adapter cable.

[0017] In one implementation of the first aspect, the length of the first part of the adapter cable is L1, where 0 < L1 ≤ 30 mm.

[0018] In one implementation of the first aspect, the multiplexer includes an input terminal and at least two output terminals. The input terminal is electrically connected to a second signal line, and the different output terminals are electrically connected to different first signal lines in the transition region, respectively; wherein the different output terminals output signals at different time periods.

[0019] In one implementation of the first aspect, the plurality of demultiplexers includes a first type of demultiplexer and a second type of demultiplexer. The first type of demultiplexer is electrically connected to a first signal line near the middle region of the transition region, and the second type of demultiplexer is electrically connected to a first signal line near the edge region of the transition region. The number of output terminals included in the first type of demultiplexer is less than the number of output terminals included in the second type of demultiplexer.

[0020] In one implementation of the first aspect, the demultiplexer includes at least two transistors, the first terminal of each transistor being electrically connected to the input terminal of the demultiplexer, and the second terminal being electrically connected to the output terminal of the demultiplexer; along the direction from the edge region to the middle region, the channel width-to-length ratio of the transistors in the demultiplexer electrically connected to the first signal lines in the transition region gradually increases.

[0021] In one implementation of the first aspect, the non-display area includes a first driving area and a second driving area disposed opposite to each other along a second direction. The first driving area includes a first gate driving circuit, and the second driving area includes a second gate driving circuit. The display area includes a plurality of first gate lines extending along the second direction, and the plurality of first gate lines are arranged along the first direction. The same first gate line is electrically connected to the first gate driving circuit and the second gate driving circuit.

[0022] Secondly, embodiments of this application provide a display device, including a display panel as provided in the first aspect.

[0023] In this embodiment, the first signal line located in the edge region is electrically connected to the second signal line through an adapter line extending to the middle region. Therefore, the second signal line located in the fan-shaped trace area does not need to be tilted towards the edge region of the display area, which helps to reduce the width of the fan-shaped trace area in the first direction, thereby helping to reduce the bezel width of the display panel at the position of the fan-shaped trace area.

[0024] Furthermore, by directly connecting the first signal line and the adapter line located in the middle area to the second signal line, the transmission time of the second signal line to the first signal line and the adapter line in the middle area will not be compressed. Even if the scanning signal output by the first gate line is delayed in the middle area, it will not significantly affect the time for the signal on the first signal line to be written into the pixel circuit. Therefore, there is no need to increase the width of the peripheral scanning circuit, which is beneficial for achieving a multi-sided narrow bezel of the display panel. [Attached Image Description]

[0025] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1 A schematic diagram of a display panel provided in an embodiment of this application;

[0027] Figure 2 This is a schematic diagram of a multiplexer provided in an embodiment of this application;

[0028] Figure 3 for Figure 2The following is a timing diagram of a multiplexer;

[0029] Figure 4 This is a schematic diagram of the structure of a display panel provided in an embodiment of this application;

[0030] Figure 5 A schematic diagram of yet another display panel provided in an embodiment of this application;

[0031] Figure 6 This application provides a schematic diagram of the wiring of a display area according to an embodiment of the present application.

[0032] Figure 7 A schematic diagram of yet another display panel provided in an embodiment of this application;

[0033] Figure 8 A schematic diagram of a pixel circuit provided in an embodiment of this application;

[0034] Figure 9 A schematic diagram of yet another display panel provided in an embodiment of this application;

[0035] Figure 10 This is a schematic diagram showing a gradient of the aspect ratio of a transistor channel related to this application;

[0036] Figure 11 A schematic diagram of yet another display panel provided in an embodiment of this application;

[0037] Figure 12 This is another schematic diagram of the wiring of a display area provided in an embodiment of this application;

[0038] Figure 13 This is a schematic diagram of a display device provided in an embodiment of this application.

Detailed Implementation Methods

[0039] To better understand the technical solution of this application, the embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0040] It should be understood that the described embodiments are merely some, not all, of the embodiments in this application. All other embodiments obtained by those skilled in the art based on the embodiments in this application without inventive effort are within the scope of protection of this application.

[0041] The terminology used in the embodiments of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application. The singular forms “a,” “the,” and “the” used in the embodiments of this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0042] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0043] In the description of this specification, it should be understood that the terms "substantially", "approximately", "about", "about", "generally", "largely" used in the claims and embodiments of this application refer to values ​​that can be generally agreed upon within a reasonable range of process operations or tolerances, rather than a precise value.

[0044] It should be understood that although terms such as "first," "second," etc., may be used to describe directions, signal lines, etc., in the embodiments of this application, these directions, signal lines, etc., should not be limited to these terms. These terms are only used to distinguish directions, signal lines, etc., from each other. For example, without departing from the scope of the embodiments of this application, a first direction may also be referred to as a second direction, and similarly, a second direction may also be referred to as a first direction.

[0045] Through meticulous and in-depth research, the applicant in this case has provided a solution to the problems existing in the prior art.

[0046] Figure 1 This is a schematic diagram of a display panel provided in an embodiment of this application.

[0047] This application embodiment provides a display panel 01, such as Figure 1 As shown, the display panel 01 includes a display area AA and a non-display area FA, with the non-display area FA surrounding at least a portion of the display area AA.

[0048] Optionally, such as Figure 1 As shown, the display area AA is completely surrounded by the non-display area FA.

[0049] The non-display area FA includes a fan-shaped trace area FA1, which is arranged along the first direction Y with the display area AA. The fan-shaped trace area FA1 can be located at the lower edge of the display panel 01. The signal for display transmitted by the driver chip enters the display area AA through the fan-shaped trace area FA1.

[0050] It should be noted that the display panel 01 may include a top border, a bottom border, a left border, and a right border. Here, "top", "bottom", "left", and "right" can be the orientation determined when the user is facing the display panel 01.

[0051] The display area AA includes multiple pixel circuits 10 and multiple first signal lines DL1. The first signal lines DL1 are electrically connected to the pixel circuits 10. The first signal lines DL1 extend along a first direction Y, and the multiple first signal lines DL1 are arranged along a second direction X, where the first direction Y intersects with the second direction X. The multiple pixel circuits 10 arranged along the first direction Y can be electrically connected to the same first signal line DL1.

[0052] Optionally, the first direction Y is the column direction in the display panel 01, and the second direction X is the row direction in the display panel 01.

[0053] Optionally, the first signal line DL1 is a data signal line, and the first signal line DL1 is used to transmit data signals to the pixel circuit 10.

[0054] The display area AA also includes an edge region A1 and a middle region A2 arranged along the second direction X. In the second direction X, the edge region A1 is closer to the edge of the display panel 01 than the middle region A2. Since the display panel 01 includes two opposing edges in the second direction X, as... Figure 1 As shown, the display area AA may include two edge areas A1 and a middle area A2, with the two edge areas A1 located on both sides of the middle area A2.

[0055] Please continue to refer to this. Figure 1 The display area AA also includes multiple adapter cables DLZ. The adapter cables DLZ are electrically connected to the first signal line DL1 located in the edge area A1. The adapter cables DLZ extend from the edge area A1 to the middle area A2. The first signal line DL1 located in the edge area A1 can receive signals through the adapter cables DLZ extending to the middle area A2.

[0056] The sector-shaped wiring area FA1 includes multiple second signal lines DL2. The first signal line DL1 and the adapter cable DLZ located in the middle area A2 are connected to the second signal lines DL2. This connection can mean that the first signal line DL1 and the adapter cable DLZ located in the middle area A2 are directly electrically connected to the second signal lines DL2.

[0057] The second signal line DL2 can be used to electrically connect to the bonding pin of the driver chip, and to transmit the output signal of the driver chip to the first signal line DL1.

[0058] like Figure 1 As shown, the display area AA also includes multiple first gate lines SL1. The first gate lines SL1 extend along the second direction X, and the multiple first gate lines SL1 are arranged along the first direction Y. The first gate lines SL1 are electrically connected to the pixel circuit 10 to provide scanning signals to the pixel circuit 10. Moreover, the pixel circuit 10 arranged along the second direction X can be electrically connected to the same first gate line SL1.

[0059] When a frame is displayed on the display panel 01, multiple first gate lines SL1 sequentially output valid scan signals to the pixel circuit 10, and at the same time, the first signal line DL1 transmits data signals to the pixel circuit 10 of the corresponding row.

[0060] Optionally, the display panel 01 provided in this application embodiment is a dual-sided driven display panel.

[0061] Understandably, the scan signal output from the first gate line SL1 can be provided by the peripheral scan circuit located in the non-display area FA, and the data signal transmitted by the first signal line DL1 can be provided by the driver chip. Moreover, along the direction from the edge region A1 to the middle region A2, the scan signal output from the first gate line SL1 will typically experience a delay.

[0062] In this embodiment, the first signal line DL1 located in the edge region A1 is electrically connected to the second signal line DL2 through the adapter line DLZ extending to the middle region A2. Therefore, the second signal line DL2 located in the fan-shaped trace area FA1 does not need to be tilted towards the edge region A1 of the display area AA, which is beneficial to reduce the width of the fan-shaped trace area FA1 in the first direction Y, thereby reducing the bezel width of the display panel 01 at the position of the fan-shaped trace area FA1.

[0063] Furthermore, by directly connecting the first signal line DL1 and the adapter line DLZ located in the middle region A2 to the second signal line DL2, the transmission time of the second signal line DL2 to the first signal line DL1 and the adapter line DLZ in the middle region A2 will not be compressed. Even if the scanning signal output by the first gate line SL1 is delayed in the middle region A2, it will not significantly affect the time for the signal on the first signal line DL1 to be written into the pixel circuit 10. Therefore, there is no need to increase the width of the peripheral scanning circuit, which is beneficial for realizing the polygonal narrow bezel of the display panel 01.

[0064] Figure 2 This is a schematic diagram of a multiplexer provided in an embodiment of this application. Figure 3 for Figure 2 The diagram shows a timing diagram of a multiplexer.

[0065] Please continue to refer to this. Figure 1 In one embodiment of this application, the display area AA further includes a transition area A3 located between the edge area A1 and the middle area A2. Of course, the transition area A3 is arranged along the second direction X with the edge area A1 and the middle area A2. The delay of the scan signal output on the first gate line SL1 in the transition area A3 is less than the delay in the middle area A2.

[0066] Given that the display area AA can include two edge areas A1 and one middle area A2, it can be concluded that the display area AA can include two transition areas A3, which are located on both sides of the middle area A2.

[0067] The sector-shaped trace area FA1 also includes multiple demultiplexers 11. The input terminal Q1 of the demultiplexer 11 is electrically connected to the second signal line DL2, and the output terminal Q2 is electrically connected to the first signal line DL1 located in the transition area A3.

[0068] Specifically, in combination Figure 2 and Figure 3 As shown, the demultiplexer 11 includes one input terminal Q1 and at least two output terminals Q2. The input terminal Q1 is electrically connected to the second signal line DL2, and the different output terminals Q2 are respectively electrically connected to different first signal lines DL1 in the transition region A3. The different output terminals Q2 output signals at different time periods, allowing the demultiplexer 11 to transmit the signal on the second signal line DL2 to different first signal lines DL1 in a time-division manner.

[0069] It should be noted that, Figure 1 and Figure 2 This only illustrates the case where the multiplexer 11 includes two output terminals Q2.

[0070] In this embodiment, the demultiplexer 11 reduces the number of second signal lines DL2 in the sectoral wiring area FA1, which helps to further reduce the width of the sectoral wiring area FA1 in the first direction Y. Furthermore, although the demultiplexer 11 compresses the signal transmission time from the second signal line DL2 to the first signal line DL1 in the transition region A3 to some extent, the delay of the scan signal output by the first gate line SL1 in the transition region A3 is small, and it will not significantly affect the time for the signal on the first signal line DL1 in the transition region A3 to be written into the pixel circuit 10. This helps to ensure that the width of the peripheral scanning circuit is not too large, thereby facilitating the realization of a multi-sided narrow bezel on the display panel 01.

[0071] Figure 4 This is a schematic diagram of the structure of a display panel provided in an embodiment of this application.

[0072] In one embodiment of this application, such as Figure 4 As shown, the adapter cable DLZ and the first signal line DL1 are located on different film layers, and an insulating layer is provided between the adapter cable DLZ and the first signal line DL1.

[0073] The embodiments of this application can reduce the routing difficulty of the adapter cable DLZ and the first signal line DL1, which helps to avoid the problem of short circuit caused by the small distance between the adapter cable DLZ and the first signal line DL1.

[0074] Please continue to refer to this. Figure 4 In one embodiment of this application, the display panel 01 includes a substrate 20 and a pixel definition layer 21. Along the thickness direction Z of the display panel 01, the pixel definition layer 21 is located on the side of the substrate 20 facing the light-emitting surface of the display panel 01, and the pixel definition layer 21 includes a light-emitting device (not shown in the figure).

[0075] The first signal line DL1 is located in film layer 22 and the adapter line DLZ is located in film layer 23 between substrate 20 and pixel definition layer 21. The first signal line DL1 is located in film layer 22 on the side of the adapter line DLZ facing the light-emitting surface of display panel 01.

[0076] Furthermore, the display panel 01 also includes a transistor array layer 24, which is located on the side of the film layer 23 containing the adapter cable DLZ that faces away from the light-emitting surface of the display panel 01. That is, the transistor array layer 24 can be located on the side of the film layer 23 containing the adapter cable DLZ that faces the substrate 10.

[0077] In this embodiment, the number of first signal lines DL1 is relatively large. Placing the first signal lines DL1 on the side away from the transistor array layer 30 is beneficial to increasing the distance between the first signal lines DL1 and the traces in the transistor array layer 30, reducing the parasitic capacitance of the first signal lines DL1, thereby reducing the impedance of the first signal lines DL1 and improving the accuracy of the signals transmitted by the first signal lines DL1.

[0078] Figure 5 This is a schematic diagram of another display panel provided in an embodiment of this application.

[0079] In one embodiment of this application, such as Figure 5 As shown, the display area AA also includes a first trace XL, which is located in the edge area A1 and the transition area A3.

[0080] It should be noted that the first trace XL can be set in the middle area A2 where no adapter cable DLZ is set.

[0081] Optionally, the first trace XL is a virtual trace, meaning that the first trace XL may not be used to transmit electrical signals.

[0082] Optionally, the first trace XL and the adapter line DLZ are set in the same layer, that is, the first trace XL and the adapter line DLZ can be located in the same film layer.

[0083] In this embodiment, a first trace XL is provided at a position in the display area AA where no adapter cable DLZ is provided. This helps to ensure the uniformity of the trace density in the display area AA, thereby helping to ensure the consistency of the transmission signal delay of the first signal line DL1 at different positions, and further helping to ensure the uniformity of brightness at different positions of the display panel 01.

[0084] In one embodiment of this application, the first trace XL is a first power supply voltage signal line, which transmits the voltage signal PVEE. This helps to achieve uniformity of the first power supply voltage signal line in the display area AA and reduces the difference in the voltage signal PVEE at different locations in the display area AA.

[0085] It should be noted that in some other embodiments, the first power supply voltage signal line can also transmit the voltage signal PVDD.

[0086] Figure 6 This is a schematic diagram of the wiring of a display area provided in an embodiment of this application.

[0087] In one embodiment of this application, such as Figure 6 As shown, the adapter cable DLZ includes a first part DLZ1 and a second part DLZ2 that are electrically connected to each other. The first part DLZ1 extends along a first direction Y, and the second part DLZ2 extends along a second direction X.

[0088] The first trace XL includes a third part XL1 and a fourth part XL2 that are electrically connected to each other, and the third part XL1 and the fourth part XL2 can be distributed in a mesh pattern. The third part XL1 extends along the first direction Y, and the fourth part XL2 extends along the second direction X. The fourth part XL2 can be used to transmit electrical signals to the third part XL1.

[0089] In addition, multiple third parts XL1 can be arranged along the second direction X, and multiple fourth parts XL2 can be arranged along the first direction Y.

[0090] Among them, the third part XL1 of the first trace XL is disconnected at the second part DLZ2 of the adapter DLZ.

[0091] In this embodiment, the third part XL1 of the first trace XL is disconnected at the second part DLZ2 of the adapter cable DLZ, which can reduce the design difficulty of the first trace XL and the adapter cable DLZ and help avoid short circuit between the first trace XL and the adapter cable DLZ.

[0092] Furthermore, when the first trace XL is used to transmit electrical signals, even if the third part XL1 of the first trace XL is disconnected, the fourth part XL2 extending along the second direction X will transmit electrical signals to the disconnected third part XL1, and the electrical signals will not be disconnected.

[0093] Please continue to refer to this. Figure 6 In one embodiment of this application, the length of the first part DLZ1 of the adapter cable DLZ is L1, where 0 < L1 ≤ 30 mm.

[0094] In this embodiment of the application, by setting the length of the first part DLZ1 of the adapter cable DLZ within a certain range, the length of the adapter cable DLZ in the first direction Y can be limited, which is beneficial to reduce the total length of the adapter cable DLZ, thereby reducing the signal loss of the adapter cable DLZ in transmitting signals to the first signal line DL1 in the edge region A1 and improving the accuracy of the first signal line DL1 in the edge region A1 in receiving signals.

[0095] Figure 7 This is a schematic diagram of another display panel provided in an embodiment of this application.

[0096] In one embodiment of this application, such as Figure 7 As shown, the non-display area FA also includes a first driving area FA2 and a second driving area FA3 disposed opposite to each other along the second direction X. The first driving area FA2 may be located on the left edge of the display panel 01, and the second driving area FA3 may be located on the right edge of the display panel 01. The first driving area FA2 includes a first gate driving circuit 12, and the second driving area FA3 includes a second gate driving circuit 13.

[0097] The display area AA includes multiple first gate lines SL1 extending along the second direction X. The first gate lines SL1 are electrically connected to the pixel circuit 10 and are used to transmit scan signals to the pixel circuit 10. Furthermore, the multiple first gate lines SL1 are arranged along the first direction Y. The same first gate line SL1 is electrically connected to the first gate driving circuit 12 and the second gate driving circuit 13. The first gate driving circuit 12 and the second gate driving circuit 13 together provide scan signals to the first gate line SL1.

[0098] In other words, the display area AA is driven using a dual-side driving method.

[0099] When a frame is displayed on the display panel 01, multiple first gate lines SL1 sequentially output valid scan signals to the pixel circuit 10, and at the same time, the first signal line DL1 transmits data signals to the pixel circuit 10 of the corresponding row.

[0100] It is understood that the first gate driving circuit 12 and the second gate driving circuit 13 can be the peripheral scanning circuits described in the above embodiments.

[0101] In this embodiment, the driving mode of the display area AA is set to dual-sided driving, which ensures that the delay of the scanning signal transmitted by the first gate line SL1 in the two transition regions A3 is approximately the same, and the delay in the two transition regions A3 is less than the delay in the middle region A2. This helps to ensure that when the first signal line DL1 in the two transition regions A3 is connected to the second signal line DL2 through the demultiplexer 11, the influence of the demultiplexer 11 on the signal transmission time will not have too much impact on the time when the signals on the first signal line DL1 in the two transition regions A3 are written to the corresponding pixel circuits 10, which helps to ensure that the width of the first gate driving circuit 12 and the second gate driving circuit 13 is not too large, and thus helps to ensure the realization of the multi-sided narrow bezel of the display panel 01.

[0102] Figure 8 This is a schematic diagram of a pixel circuit provided in an embodiment of this application.

[0103] To illustrate the technical solution of this application more clearly, the following will use... Figure 8 The process of writing signals from the first signal line DL1 into the pixel circuit 10 will be explained using the pixel circuit shown as an example. The first signal line DL1 can be used to transmit the data signal Vdata.

[0104] like Figure 8 As shown, the pixel circuit 10 includes a driving transistor Md, a data writing transistor M1, and a threshold grabbing transistor M2. The driving transistor Md is used to generate a light-emitting driving current. The first terminal of the data writing transistor M1 is electrically connected to a first signal line DL1, the second terminal is electrically connected to the first terminal of the driving transistor Md, and the gate is electrically connected to a first gate line SL1. The first terminal of the threshold grabbing transistor M2 is electrically connected to the second terminal of the driving transistor Md, the second terminal is electrically connected to the gate of the driving transistor Md, and the gate is electrically connected to the first gate line SL1. The first gate line SL1 transmits a signal to control the switching states of the data writing transistor M1 and the threshold grabbing transistor M2 to be the same. The first terminal of the driving transistor Md can be its source and the second terminal can be its drain.

[0105] When the first gate line SL1 transmits the valid scan signal to control the data writing transistor M1 and the threshold grabbing transistor M2 to be turned on, the data signal Vdata on the first signal line DL1 is transmitted to the gate of the driving transistor Md through the turned-on data writing transistor M1 and threshold grabbing transistor M2, thus completing the writing of the data signal Vdata.

[0106] In addition, the pixel circuit 10 also includes a first reset transistor M3, a second reset transistor M4, a power supply voltage writing transistor M5, a light emission control transistor M6, and a first capacitor C1.

[0107] The first terminal of the first reset transistor M3 receives the reset voltage Vref, the second terminal is electrically connected to the gate of the driving transistor Md, and the gate is electrically connected to the second gate line SL2. When the second gate line SL2 transmits a valid scan signal to control the first reset transistor M3 to turn on, the reset voltage Vref is transmitted to the gate of the driving transistor Md through the turned-on first reset transistor M3, completing the reset of the gate of the driving transistor Md.

[0108] The second reset transistor M4 receives the reset voltage Vref at its first terminal, is electrically connected to the first terminal of the light-emitting device FG at its second terminal, and is electrically connected to the first gate line SL1 at its gate. The second reset transistor M4 is used to reset the first terminal of the light-emitting device FG. The second terminal of the light-emitting device FG can be electrically connected to the voltage signal PVEE.

[0109] The first terminal of the power supply voltage writing transistor M5 receives the voltage signal PVDD, the second terminal is electrically connected to the first terminal of the driving transistor Md, and the gate is electrically connected to the light-emitting control signal line EM. The first terminal of the light-emitting control transistor M6 is electrically connected to the second terminal of the driving transistor Md, the second terminal is electrically connected to the first terminal of the light-emitting device FG, and the gate is electrically connected to the light-emitting control signal line EM. The signal transmitted by the light-emitting control signal line EM controls the switching states of the power supply voltage writing transistor M5 and the light-emitting control transistor M6 in the same way.

[0110] One plate of the first capacitor C1 receives the voltage signal PVDD, and the other plate is electrically connected to the gate of the driving transistor Md to stabilize the gate potential of the driving transistor Md.

[0111] In one working cycle of the pixel circuit 10, the gate of the driving transistor Md is first reset, then a data signal is written to the gate of the driving transistor Md, and finally the driving transistor Md is controlled to generate a light-emitting driving current and transmit it to the light-emitting device FG, driving the light-emitting device FG to emit light.

[0112] It should be noted that, as Figure 8 As shown, the data writing transistor M1, threshold grabbing transistor M2, first reset transistor M3, second reset transistor M4, power supply voltage writing transistor M5, and light-emitting control transistor M6 can all be P-type transistors. Of course, any one of these transistors can also be an N-type transistor.

[0113] Figure 9 This is a schematic diagram of yet another display panel provided in an embodiment of this application. Figure 10 This is a schematic diagram showing a gradient of the aspect ratio of a transistor channel related to this application.

[0114] In one embodiment of this application, please continue to refer to Figure 2 The multiplexer 11 includes at least two transistors T, with the first terminal of each transistor T electrically connected to the input terminal Q1 of the multiplexer 11 and the second terminal of each transistor T electrically connected to the output terminal Q2 of the multiplexer 11.

[0115] In other words, the first terminals of each transistor T can be electrically connected together and electrically connected to the input terminal Q1 of the multiplexer 11. The second terminal of each transistor T is electrically connected to one of the output terminals Q2 of the multiplexer 11. Of course, the output terminals Q2 electrically connected to the second terminal of each transistor T are different.

[0116] It should be noted that, Figure 2 This only illustrates the case where a multiplexer 11 includes two transistors T.

[0117] In addition, combined Figure 2 and Figure 3 As shown, in the same multiplexer 11, the gate of each transistor T is electrically connected to a different control line CK. The control line CK transmits an effective signal (such as a low-level signal) to control the transistor T to turn on for different periods.

[0118] For example, such as Figure 2 As shown, the two transistors T included in the multiplexer 11 can be a first transistor T1 and a second transistor T2, respectively. The gate of the first transistor T1 is electrically connected to the control line CK1, and the gate of the second transistor T2 is electrically connected to the control line CK2. Of course, in the display panel 01, the gates of the first transistors T1 in different multiplexers 11 can be electrically connected to the same control line CK1, and the gates of the second transistors T2 in different multiplexers 11 can be electrically connected to the same control line CK2.

[0119] Along the direction from the edge region A1 to the middle region A2, the channel width-to-length ratio of the transistor T in the multiplexer 11, which is electrically connected to the first signal line DL1 in the transition region A3, gradually increases.

[0120] For example, combining Figure 9 and Figure 2 As shown, the multiplexer 11 electrically connected to the first signal line DL1 in the transition region A3 includes an adjacent first multiplexer 111 and a second multiplexer 112. The first multiplexer 111 is electrically connected to the first signal line DL1 near the edge region A1 in the transition region A3, and the second multiplexer 112 is electrically connected to the first signal line DL1 near the middle region A2 in the transition region A3. That is, the first signal line DL1 electrically connected to the second multiplexer 112 is closer to the middle region A2 than the first signal line DL1 electrically connected to the first multiplexer 111.

[0121] In the first multiplexer 111, the channel width-to-length ratio of transistor T is smaller than that of transistor T in the second multiplexer 112. Of course, the channel width-to-length ratio of transistor T in the same multiplexer 11 can be the same.

[0122] Optionally, such as Figure 10 As shown, the channel length L1 of transistor T in the first multiplexer 111 is the same as the channel length L2 of transistor T in the second multiplexer 112, and the channel width W1 of transistor T in the first multiplexer 111 is smaller than the channel width W2 of transistor T in the second multiplexer 112. That is, L1 = L2, W1 < W2. This results in the channel width-to-length ratio W1 / L1 of transistor T in the first multiplexer 111 being smaller than the channel width-to-length ratio W2 / L2 of transistor T in the second multiplexer 112.

[0123] It is understandable that the larger the channel width-to-length ratio of transistor T, the better the transistor T can turn on or off, that is, the smaller the delay in turning on or off.

[0124] In this embodiment, the channel width-to-length ratio of the transistor T in the multiplexer 11, which is electrically connected to the first signal line DL1 in the transition region A3, gradually increases along the direction from the edge region A1 to the middle region A2. This increases the effective time for the first signal line DL1 in the transition region A3, which is close to the middle region A2, to receive electrical signals. This ensures that the time for the signals on each first signal line DL1 in the transition region A3 to be written into the corresponding pixel circuit 10 meets the requirements, thus eliminating the need to increase the width of the peripheral scanning circuit. This further helps to ensure the realization of the multi-sided narrow bezel of the display panel 01.

[0125] Figure 11 This is a schematic diagram of another display panel provided in an embodiment of this application.

[0126] In one embodiment of this application, such as Figure 11 As shown, the multiple demultiplexers 11 include a first type demultiplexer 11A and a second type demultiplexer 11B. The first type demultiplexer 11A is electrically connected to a first signal line DL1 near the middle region A2 in the transition region A3, and the second type demultiplexer 11B is electrically connected to a first signal line DL1 near the edge region A1 in the transition region A3. That is, the first signal line DL1 electrically connected to the first type demultiplexer 11A is closer to the middle region A2 than the first signal line DL1 electrically connected to the second type demultiplexer 11B.

[0127] The number of output terminals Q2 included in the first type of multiplexer 11A is less than the number of output terminals Q2 included in the second type of multiplexer 11B.

[0128] It is understandable that the more output terminals Q2 included in the multiplexer 11, the less time each output terminal Q2 in the multiplexer 11 will output a valid signal.

[0129] In this embodiment, the number of output terminals Q2 included in the first type of demultiplexer 11A is less than the number of output terminals Q2 included in the second type of demultiplexer 11B. This increases the effective time of the output signals of each output terminal Q2 in the first type of demultiplexer 11A, so that the time for the signals on each first signal line DL1 in the transition region A3 to be written into the corresponding pixel circuit 10 can meet the requirements. Therefore, there is no need to increase the width of the peripheral scanning circuit, which is beneficial to further ensure the realization of the multi-sided narrow bezel of the display panel 01.

[0130] Figure 12 This is a schematic diagram of the wiring of another display area provided in an embodiment of this application.

[0131] In one embodiment of this application, such as Figure 12 As shown, in the display area AA, the width K1 of the first signal line DL1 located in the middle area A2 is greater than the width K2 of the first signal line DL1 located in the edge area A1, and is also greater than the width K3 of the first signal line DL1 located in the transition area A3.

[0132] In this embodiment, by setting the width K1 of the first signal line DL1 located in the middle region A2 to be larger, the resistance of the first signal line DL1 located in the middle region A2 can be reduced, which is beneficial to reduce the signal loss of the first signal line DL1 located in the middle region A2. This is beneficial to further ensure the time for the signal on the first signal line DL1 located in the middle region A2 to be written into the pixel circuit 10, and further ensures that there is no need to increase the width of the peripheral scanning circuit, thus realizing the multi-sided narrow bezel of the display panel 01.

[0133] Figure 13 This is a schematic diagram of a display device provided in an embodiment of this application.

[0134] This application provides a display device 02, such as... Figure 13 As shown, the display device 02 includes the display panel 01 provided in the above embodiments. Exemplarily, the display device 02 provided in the embodiments of this application can be an electronic device such as a mobile phone, computer, television, or vehicle display, and this application does not make any specific limitations.

[0135] In the display device 02, the first signal line DL1 located in the edge region A1 is electrically connected to the second signal line DL2 through the adapter line DLZ extending to the middle region A2. Then, the second signal line DL2 located in the fan-shaped trace area FA1 does not need to be tilted towards the edge region A1 of the display area AA, which is beneficial to reduce the width of the fan-shaped trace area FA1 in the first direction Y, thereby reducing the bezel width of the display panel 01 at the position of the fan-shaped trace area FA1.

[0136] Furthermore, by directly connecting the first signal line DL1 and the adapter line DLZ located in the middle region A2 to the second signal line DL2, the transmission time of the second signal line DL2 to the first signal line DL1 and the adapter line DLZ in the middle region A2 will not be compressed. Even if the scanning signal output by the first gate line SL1 is delayed in the middle region A2, it will not significantly affect the time for the signal on the first signal line DL1 to be written into the pixel circuit 10. Therefore, there is no need to increase the width of the peripheral scanning circuit, which is beneficial for realizing the polygonal narrow bezel of the display panel 01.

[0137] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A display panel, characterized in that, The display panel includes a display area and a non-display area, the non-display area surrounding at least a portion of the display area, the non-display area including a fan-shaped wiring area, the fan-shaped wiring area and the display area being arranged along a first direction, the display area including: Multiple first signal lines, the first signal lines extending along the first direction, and the multiple first signal lines arranged along the second direction, the first direction intersecting the second direction; The edge region and the middle region arranged along the second direction; Multiple adapter cables are electrically connected to a first signal line located in the edge region, and the adapter cables extend from the edge region to the middle region. The fan-shaped trace area includes multiple second signal lines, and the first signal line located in the middle area and the adapter line are connected to the second signal lines accordingly. The display area also includes a transition area located between the edge area and the middle area, and the fan-shaped wiring area also includes multiple multiplexers; The input terminal of the multiplexer is electrically connected to the second signal line, and the output terminal is electrically connected to the first signal line located in the transition region. in, The plurality of multiplexers includes a first type of multiplexer and a second type of multiplexer. The first type of multiplexer is electrically connected to the first signal line in the transition region near the middle region, and the second type of multiplexer is electrically connected to the first signal line in the transition region near the edge region. The number of output terminals included in the first type of multiplexer is less than the number of output terminals included in the second type of multiplexer. or, The multiplexer includes at least two transistors, with the first terminal of each transistor electrically connected to the input terminal of the multiplexer and the second terminal correspondingly electrically connected to the output terminal of the multiplexer; along the direction from the edge region to the middle region, the channel width-to-length ratio of the transistors in the multiplexer electrically connected to the first signal lines in the transition region gradually increases.

2. The display panel according to claim 1, characterized in that, The adapter cable and the first signal line are located on different film layers.

3. The display panel according to claim 2, characterized in that, The film layer containing the first signal line is located on the side of the film layer containing the adapter line that faces the light-emitting surface of the display panel.

4. The display panel according to claim 3, characterized in that, The display panel includes a transistor array layer, which is located on the side of the film layer containing the adapter cable that faces away from the light-emitting surface of the display panel.

5. The display panel according to claim 1, characterized in that, The display area also includes a first trace, which is located in the edge region and the transition region.

6. The display panel according to claim 5, characterized in that, The first trace is a virtual trace.

7. The display panel according to claim 5, characterized in that, The first trace is the first power supply voltage signal line.

8. The display panel according to claim 5, characterized in that, The first trace is installed on the same layer as the adapter cable.

9. The display panel according to claim 8, characterized in that, The adapter cable includes a first part and a second part that are electrically connected to each other, the first part extending along the first direction and the second part extending along the second direction; The first trace includes a third part and a fourth part, wherein the third part extends along the first direction and the fourth part extends along the second direction; The third part of the first trace is disconnected at the second part of the adapter cable.

10. The display panel according to claim 9, characterized in that, The length of the first part of the adapter cable is L1, where 0 < L1 ≤ 30 mm.

11. The display panel according to claim 1, characterized in that, The multiplexer includes an input terminal and at least two output terminals. The input terminal is electrically connected to the second signal line, and different output terminals are respectively electrically connected to different first signal lines in the transition region. The time periods for the output signals from different output terminals are different.

12. The display panel according to claim 1, characterized in that, The non-display area includes a first driving area and a second driving area disposed opposite to each other along the second direction. The first driving area includes a first gate driving circuit, and the second driving area includes a second gate driving circuit. The display area includes multiple first gate lines extending along the second direction, and the multiple first gate lines are arranged along the first direction. The same first gate line is electrically connected to the first gate driving circuit and the second gate driving circuit.

13. A display device, characterized in that, Includes the display panel as described in any one of claims 1-12.

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