Hdp sacrificial carbon gap fill

Abstract

Methods of filling a substrate feature with carbon gap fill while leaving voids are described. The methods include the steps of flowing a process gas into a high-density plasma chemical vapor deposition (HDP-CVD) chamber, the chamber housing a substrate having at least one feature, the process gas comprising a hydrocarbon reactant; generating a plasma; and depositing a carbon film.

Description

Technical Field

[0001] The embodiments of this disclosure generally relate to methods for filling substrate features. More specifically, embodiments of this disclosure relate to methods for filling features with carbon using a high-density plasma chemical vapor deposition (HDP CVD) chamber. Background Technology

[0002] In microelectronic device fabrication, many applications require the non-porous filling of narrow trenches with an aspect ratio (AR) greater than 10:1. One application is shallow trench isolation (STI). For this application, the film needs to have high quality throughout the trench (e.g., a wet etch rate ratio of less than 2) and very low leakage. One method that has been successful in the past is flowable CVD. In this method, oligomers are carefully formed in a gas phase, which condenses on a surface and then “flows” into the trench. However, the quality of the deposited film is very poor and requires processing steps such as vapor annealing and UV curing.

[0003] Ultra-high density memory devices can be manufactured using three-dimensional (3D) stacked memory structures. For example, a 3D NAND stacked memory device can be formed from an array of alternating conductive and dielectric layers. Memory vias are formed through the memory layers, and NAND strings are formed by filling the memory vias with appropriate materials. As the structure size decreases and the aspect ratio increases, post-curing methods for the deposited film become more difficult.

[0004] Both logic and memory applications require carbon interstitial filling processes. Carbon materials can be removed using plasma etching without affecting the underlying material. In multilayer 3D NAND production, sacrificial memory via plugging processes are needed to protect the underlying memory vias and deposit the upper layer on top of the underlying layer. Such processes need to meet requirements for throughput, dry etch removability, and high-temperature (approximately 850°C) stability. Current amorphous silicon (aSi) sacrificial filling methods present several integration challenges. Therefore, there is a need for interstitial filling processes using amorphous carbon materials that are stable at high temperatures. Summary of the Invention

[0005] One or more embodiments of this disclosure relate to a method for forming a film. The method includes the steps of: infusing a process gas into a high-density plasma chemical vapor deposition (HDP-CVD) chamber, the chamber containing a substrate having at least one feature, the process gas comprising a hydrocarbon reactant with a hydrogen-to-carbon ratio (H:C) less than or equal to 2:1, and one or more of hydrogen (H2), helium (He), and argon (Ar); treating the substrate at a temperature in the range of about 400°C to about 650°C and a pressure less than about 50 mTorr; generating plasma via a source RF; accelerating ions by biasing the RF and depositing a carbon film in the at least one feature, the carbon film having pores in the at least one feature. RF energy is inductively coupled into the chamber via a coil and generates a high-density plasma.

[0006] Another embodiment of this disclosure relates to a method for forming a film. The method includes the steps of: flowing a process gas into a high-density plasma chemical vapor deposition (HDP-CVD) chamber, the chamber containing a substrate having a substrate surface, the process gas comprising a hydrocarbon reactant with a hydrogen-to-carbon ratio (H:C) less than or equal to 2:1, and one or more of hydrogen (H2), helium (He), and argon (Ar); generating plasma from a source RF; accelerating ions by biasing the RF; and depositing a carbon film on the substrate surface, the substrate surface having at least one feature extending from the substrate surface to a feature depth to a bottom surface, the at least one feature having a width defined by a first sidewall and a second sidewall, wherein a first film is deposited on the substrate surface and the first sidewall, second sidewall, and bottom surface of the at least one feature, the carbon film having pores located within the width of the feature at a first distance from the bottom surface of the feature.

[0007] Other embodiments of this disclosure relate to a method of manufacturing a memory device. In one or more embodiments, the method includes the steps of: forming a film stack on a substrate, the film stack comprising a plurality of alternating layers of a first material and a second material, and the film stack having a stack thickness; etching the film stack to form a memory aperture opening extending from a top surface of the film stack to a bottom surface, the memory aperture opening having a width defined by a first sidewall and a second sidewall; loading the substrate into a high-density plasma chemical vapor deposition (HDP-CVD) chamber; allowing a process gas to flow into the HDP-CVD chamber, the process gas comprising a hydrocarbon reactant with a hydrogen-to-carbon ratio (H:C) less than or equal to 2:1, and one or more of hydrogen (H2), helium (He), and argon (Ar), the film stack being at a temperature in the range of about 400°C to about 650°C and a pressure less than about 50 mTorr; and depositing a carbon film on the surface of the film stack and on the first sidewall, the second sidewall, and the bottom surface of the memory aperture opening, the carbon film having pores located within the width of the memory aperture opening at a first distance from the bottom surface of the memory aperture opening. Attached Figure Description

[0008] To gain a more detailed understanding of the features described above, a more specific description of the disclosure can be obtained by referring to the embodiments, some of which are illustrated in the accompanying drawings. However, it should be noted that the drawings illustrate only typical embodiments of the disclosure and should not therefore be considered as limiting the scope of the disclosure, as other equally effective embodiments are permissible.

[0009] Figures 1A to 1D A cross-sectional view of a substrate according to one or more embodiments of the present disclosure is illustrated;

[0010] Figures 2A to 2E A cross-sectional view of a substrate according to one or more embodiments of the present disclosure is illustrated;

[0011] Figure 3 The illustration shows a process flow according to one or more embodiments of the present disclosure.

[0012] Figure 4A The illustration depicts a high-density plasma chemical vapor deposition (HDP-CVD) system according to one or more embodiments; and

[0013] Figure 4B The diagram shows that it can be used Figure 4B A cross-sectional view of the gas ring used in high-density plasma chemical vapor deposition (HDP-CVD). Detailed Implementation

[0014] Before describing several exemplary embodiments of this disclosure, it should be understood that this disclosure is not limited to the details of the construction or process steps set forth in the following description. This disclosure can be used in other embodiments and can be practiced or carried out in various ways.

[0015] As used herein, the term “about” means approximately or close to, and in the context of the numerical value or range described, it means a variation of the value by ±15% or less. For example, values ​​differing by ±14%, ±10%, ±5%, ±2%, or ±1% would satisfy the definition of about.

[0016] As used in this specification and the appended claims, the terms "substrate" and "wafer" are used interchangeably, both referring to a surface or part thereof on which a process is performed. Those skilled in the art will also understand that, unless the context clearly indicates otherwise, reference to substrate may also refer only to a portion of the substrate. Furthermore, the reference to deposition on a substrate may mean both a bare substrate and a substrate on which one or more films or features are deposited or formed.

[0017] As used herein, “substrate” refers to any substrate or material surface formed on a substrate, on which a film treatment is performed during a manufacturing process. For example, depending on the application, substrate surfaces on which treatments can be performed include materials such as silicon, silicon dioxide, strained silicon, silicon-on-insulator (SOI), carbon-doped silicon oxide, silicon nitride, doped silicon, germanium, gallium arsenide, glass, sapphire, and any other materials such as metals, metal nitrides, metal alloys, and other conductive materials. Substrates include, but are not limited to, semiconductor wafers. Substrates may be exposed to pretreatment processes to grind, etch, reduce, oxidize, hydroxylate (or otherwise generate or graft target chemical moieties to impart chemical functionality), anneal, and / or bake the substrate surface. In addition to film treatments performed directly on the surface of the substrate itself, any step of the film treatment steps disclosed in this disclosure may also be performed on an underlayer formed on the substrate, as disclosed in more detail below, and the term “substrate surface” is intended to include such an underlayer as indicated by the context. Thus, for example, where a film / layer or a portion of a film / layer has already been deposited onto the substrate surface, the exposed surface of the newly deposited film / layer becomes the substrate surface. What a given substrate surface contains will depend on what film will be deposited and the specific chemicals used.

[0018] V-NAND, or 3D-NAND, structures are used for flash memory applications. A V-NAND device is a vertically stacked NAND structure with a large number of cells arranged in a block. As used herein, the term "3D-NAND" refers to a type of electronic (solid-state) non-volatile computer memory in which memory cells are stacked in multiple layers. 3D NAND memory typically includes multiple memory cells containing floating-gate transistors. Traditionally, a 3D NAND memory cell comprises multiple NAND memory structures arranged in a three-dimensional manner around bit lines.

[0019] A key step in 3D NAND technology is the ability to vertically deposit additional layers to enhance capability. In multilayer 3D NAND production, a sacrificial memory via plugging process is required to protect the underlying memory vias. Before subsequent processes, the memory vias need to be filled and planarized with specific materials. Such processes must meet requirements for throughput, dry etch removability, and high-temperature (e.g., 850°C) stability.

[0020] Other methods include processes based on amorphous silicon or other amorphous carbon. Amorphous silicon materials require wet removal processes, which can have a detrimental effect on oxide / nitride stacking. Other amorphous carbon materials suffer from low deposition rates, slow throughput, and instability at high temperatures.

[0021] Embodiments of this disclosure provide methods for depositing films (e.g., amorphous carbon (aC)) in high aspect ratio (Ar) features with small dimensions using a high-density plasma chemical vapor deposition (HDP-CVD) chamber. Some embodiments advantageously provide sacrificial carbon films to fill high AR trenches with small dimensions while leaving porosity in the trenches / features. The sacrificial carbon films of one or more embodiments exhibit high thermal stability at annealing temperatures.

[0022] This document provides a method for filling gaps using high-density plasma chemical vapor deposition (HDP CVD). According to various embodiments, a carbon-containing film (such as an amorphous carbon film) is deposited onto a substrate via HDP CVD to fill gaps. In one or more embodiments, the method may include using a low-hydrogen-content process gas during HDP CVD deposition to provide gap filling. The amorphous carbon material in one or more embodiments can be readily removed via oxygen (O2) plasma, thereby eliminating its effect on oxide / nitride stacking.

[0023] In one or more embodiments, the feature is selected from trenches, vias, word line slits, and memory holes. In a particular embodiment, the feature is a memory hole. In a very specific embodiment, the feature is a memory hole in a NAND device. In one or more embodiments, a filling feature, i.e., gap filling, is used. In some embodiments, gap filling is performed by HDP CVD.

[0024] High-density plasma chemical vapor deposition (HDP CVD) is a directional CVD process that involves guiding charged precursor materials onto a substrate. As used herein, HDP-CVD differs from plasma-enhanced chemical vapor deposition (also known as PECVD). HDP-CVD reactors typically employ inductively coupled plasma, while PECVD reactors typically employ capacitively coupled plasma. HDP-CVD process conditions and the resulting films differ from those of PECVD processes. For example, the various HDP reactors described herein operate at pressures less than about 50 mTorr, where the plasma density is greater than 10. 17 ions / m 3 For example, 10 17 ions / m 3 Up to 10 19 ions / m 3 Conversely, PECVD processes operate at much higher pressures and much lower plasma densities, such as 10⁻⁶. 14 ions / m 3 Up to 10 16 ions / m 3 .

[0025] For coils, HDP reactors can ignite plasma at a plasma frequency of 2 MHz, while for wafer-mounted substrates, they can ignite plasma at a frequency of 13.56 MHz. Conversely, in capacitively coupled plasma reactors, a plasma frequency of 13.56 MHz is used to generate plasma for application to the nozzle or substrate, while 2 MHz is used for the nozzle or substrate. Ion energies in HDP reactors can be higher than those in PECVD reactors. Therefore, the composition and properties of films deposited in HDP-CVD reactors differ from those deposited in PECVD reactors. For carbon-based interstitial filling, the lower plasma density in PECVD typically fails to generate sufficient dissociation to achieve high throughput.

[0026] In one or more embodiments, the substrate temperature during processing may be in the range of about 400°C to about 650°C, or in the range of about 510°C to about 650°C. In one or more embodiments, the chamber pressure is maintained at a value below 50 mTorr, or below 40 mTorr, or below 30 mTorr, or below 20 mTorr, or below 10 mTorr. In one or more embodiments, the substrate temperature is controlled by the density, pressure, and bias power of the ionic material.

[0027] In one or more embodiments, a high-frequency RF power supply or other power source may be used to bias the substrate. During the deposition operation, the substrate is typically biased to guide charged material downwards to the bottom of features, such as memory vias. In one or more embodiments, the bias power during HDP-CVD ranges from about 0 to 9500 W, scaling with the substrate surface area. In one or more embodiments, the bias power and pressure are critical for designing the via size and location.

[0028] Figure 1A A partial cross-sectional view of an electronic device 100 according to one or more embodiments is illustrated. In some embodiments, a substrate 102 having feature 106 is provided for processing in an HDP-CVD processing chamber 101. As used in this specification and the appended claims, the term “provided” means that the substrate is available for processing (e.g., placed within the processing chamber). For illustrative purposes, the figures show a substrate having a single feature; however, those skilled in the art will understand that more than one feature may be present. The shape of feature 106 can be any suitable shape, including but not limited to trenches and cylindrical through-holes. As used in this regard, the term “feature” means any intentional surface irregularity. Suitable examples of features include, but are not limited to, trenches having a top, two sidewalls, and a bottom, word line slits, and memory holes having peaks with a top and two sidewalls. Features may have any suitable aspect ratio (the ratio of the depth of the feature to the width of the feature). In some embodiments, the aspect ratio is greater than or equal to about 5:1, 10:1, 15:1, 20:1, 25:1, 30:1, 35:1, 40:1, or 45:1, or 50:1, or 55:1, or 60:1, or 65:1, or 70:1, or 75:1, or 80:1, or 85:1, or 90:1, or 95:1, or 100:1.

[0029] In one or more embodiments, substrate 102 has substrate surface 120. At least one feature 106 forms an opening in substrate surface 120. At least one feature 106 extends from substrate surface 120 to a feature depth D. f To the bottom surface 112. In one or more embodiments, the depth D of at least one feature f In the range of approximately 50 nm to approximately 10,000 nm.

[0030] At least one feature 106 has a first sidewall 114 and a second sidewall 116, the first sidewall 114 and the second sidewall 116 defining the width W of the at least one feature 106. The opening region formed by the sidewalls 114, 116 and the bottom surface 112 is also referred to as a gap. In one or more embodiments, the width W extends along the depth D of the at least one feature 106. fIt is uniform. In other embodiments, the width W at the top of at least one feature 106 is greater than the width W at the bottom surface 112 of at least one feature 106.

[0031] In one or more embodiments, at least one feature 106 includes a memory hole or word line slit. Therefore, in one or more embodiments, the substrate 102 includes a memory device or logic device, such as NAND, VNAND, DRAM, etc.

[0032] refer to Figures 1B to 1D In one or more embodiments, a carbon film 108 is formed on the substrate surface 120, and on the walls 114, 116 and bottom 112 of at least one feature 106. Figures 1B to 1D As shown, in one or more embodiments, the carbon film 108 has pores 122 located within the width W of at least one feature 106.

[0033] In some embodiments, the carbon film 108 is a continuous film. As used herein, the term "continuous" means a layer that covers the entire exposed surface without gaps or bare spots of material exposed beneath the deposited layer. A continuous layer may have gaps or bare spots having a surface area smaller than about 1% of the total surface area of ​​the film.

[0034] In one or more embodiments, a substrate 102 having at least one feature 106 formed thereon is placed in an HDP-CVD chamber 101 for processing. Reference Figure 1B In one or more embodiments, a carbon film 108 is formed on the substrate surface 120 and on the walls 114, 116 and bottom 112 of at least one feature 106.

[0035] In one or more embodiments, the carbon film 108 is formed by flowing process gas into a high-density plasma chemical vapor deposition (HDP-CVD) chamber 101. In one or more embodiments, the process gas comprises a hydrocarbon reactant with a hydrogen-to-carbon ratio (H:C) less than or equal to 2:1, and one or more of hydrogen (H2), helium (He), and argon (Ar). In some embodiments, the process gas comprises a hydrocarbon reactant with a hydrogen-to-carbon ratio (H:C) less than or equal to 1:1.

[0036] In some embodiments, the hydrocarbon reactants comprise one or more of olefins and alkynes. As used herein, the term "olefin" refers to a hydrocarbon containing a carbon-carbon double bond. An olefin is an acyclic hydrocarbon with only one double bond. As used herein, the term "alkyne" refers to an unsaturated hydrocarbon containing at least one carbon-carbon triple bond. In one or more embodiments, the hydrocarbon reactants are selected from the group consisting of acetylene (C2H2), propylene (C3H6), ethylene (C2H4), and methylacetylene (C3H4).

[0037] Non-limiting examples of hydrocarbon process gases used for depositing carbon films include acetylene (C2H2) / hydrogen (H2) / helium (He) / argon (Ar), propylene (C3H6) / hydrogen (H2) / helium (He) / argon (Ar), ethylene (C2H4) / hydrogen (H2) / helium (He) / argon (Ar), and methylacetylene (C3H4) / hydrogen (H2) / helium (He) / argon (Ar).

[0038] A carbon film 108 is then deposited into feature 106 and formed on sidewalls 114, 116 and bottom 112, but leaving pores 122 in at least one feature 106. According to various embodiments, filling the pores can be performed by a single deposition or multiple depositions.

[0039] In one or more embodiments, gap filling can be provided by using hydrocarbon process gases in HDP CVD deposition. This... Figures 1A to 1D The diagram illustrates that, Figures 1A to 1D A cross-sectional view is depicted of feature 106 filled with a carbon film 108 during the deposition stage. As deposition proceeds, redeposition and preferential growth form a tip 110. This causes the top of feature 106 to close, thereby creating pores 122.

[0040] The pore 122 is illustrated as a rectangular opening in the carbon film 108. However, those skilled in the art will understand that this is merely for illustrative purposes. The shape and size of the pore 122 can vary.

[0041] In one or more embodiments, hydrocarbon process gas flows into the HDP-CVD processing chamber at a flow rate ranging from about 10 sccm to about 150 sccm (including about 15 sccm to about 135 sccm). Standard cubic centimeters per minute (sccm) is a unit of flow rate measurement, representing cubic centimeters per minute (cm³ / min) under standard conditions of temperature and pressure for a given fluid (typically a gas). 3 / min).

[0042] In one or more embodiments, argon (Ar) is introduced / flowed into the HDP-CVD chamber at a flow rate ranging from about 40 sccm to about 60 sccm. In one or more embodiments, hydrogen (H2) is introduced / flowed into the HDP-CVD chamber at a flow rate ranging from about 0 sccm to about 500 sccm (including the ranges from about 0 sccm to about 300 sccm and from about 0 sccm to about 200 sccm). In one or more embodiments, helium (He) is introduced / flowed into the HDP-CVD chamber at a flow rate ranging from about 0 sccm to about 500 sccm and from about 0 sccm to about 300 sccm.

[0043] In one or more embodiments, the substrate is processed at a temperature ranging from about 400°C to about 650°C and a pressure of less than about 50 millitors. In some embodiments, the pressure is less than about 40 millitors, or less than about 30 millitors, or less than about 20 millitors, or less than about 10 millitors.

[0044] After the process gas flows into the HDP-CVD chamber, plasma is generated to form a carbon film 108 on at least one feature 106 and the substrate surface 122.

[0045] In one or more embodiments, the carbon film 108 exhibits excellent thermal stability. After annealing at a temperature greater than or equal to 800°C for 1 hour, the shrinkage rate of the carbon film 108 is less than 15%. In some embodiments, the shrinkage rate of the carbon film 108 is less than 10%.

[0046] Figures 2A to 2E A partial cross-sectional view of a memory device 200 (e.g., a NAND device) according to one or more embodiments is illustrated. In some embodiments, a substrate 202 having a feature 214 is provided for processing in an HDP-CVD processing chamber 201. The feature 214 may be of any suitable shape, including but not limited to trenches and cylindrical through-holes. As used in this context, the term "feature" means any intentional surface irregularity. Suitable examples of features include, but are not limited to, trenches having a top, two sidewalls, and a bottom, word line slits, and memory holes having peaks at the top and two sidewalls. The feature may have any suitable aspect ratio (the ratio of the feature's depth to its width). In some embodiments, the aspect ratio is greater than or equal to about 5:1, 10:1, 15:1, 20:1, 25:1, 30:1, 35:1, 40:1, 45:1, 50:1, 55:1, 60:1, 65:1, 70:1, 75:1, 80:1, 85:1, 90:1, 95:1, or 100:1. In one or more embodiments, feature 214 includes a memory hole.

[0047] In one or more embodiments, the substrate 202 has a substrate surface 222. At least one feature 214 forms an opening in the substrate surface 222. The at least one feature 214 extends from the substrate surface 222 to a feature depth D. m To the bottom surface 220. At least one feature 214 has a first sidewall 216 and a second sidewall 218, the first sidewall 216 and the second sidewall 218 defining the width W of the at least one feature 214. m In one or more embodiments, the width W m Along at least one feature 214 at depth D m It is uniform. In other embodiments, the width W at the top of at least one feature 214 is... mWidth W at the bottom surface 220 of at least one feature 214 is greater than the width of the feature 214. m .

[0048] In one or more embodiments, at least one feature 214 includes a memory hole or word line slit. Therefore, in one or more embodiments, the device 200 includes a memory device or a logic device, such as NAND, VNAND, DRAM, etc.

[0049] In one or more embodiments, the device 200 includes a film stack comprising a plurality of alternating layers of a first material 210 and a second material 212 deposited on a semiconductor substrate 202. In one or more embodiments, the first material 210 and the second material 212 independently comprise one or more of an oxide material, a nitride material, and a polycrystalline silicon material. In a particular embodiment, the first material 210 is a nitride material, and the second material 212 is an oxide material 212 deposited on the semiconductor substrate 202.

[0050] Semiconductor substrate 202 can be any suitable substrate material. In one or more embodiments, semiconductor substrate 202 comprises semiconductor materials such as silicon (Si), carbon (C), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium phosphate (InP), indium gallium arsenide (InGaAs), indium aluminum arsenide (InAlAs), germanium (Ge), silicon germanium (SiGe), copper indium gallium selenide (CIGS), other semiconductor materials, or any combination thereof. In one or more embodiments, semiconductor substrate 102 comprises one or more of silicon (Si), germanium (Ge), gallium (Ga), arsenic (As), indium (In), phosphorus (P), copper (Cu), or selenium (Se). Although some examples of materials that can form substrate 202 are described herein, any material that can be used as a base on which passive and active electronic devices (e.g., transistors, memories, capacitors, inductors, resistors, switches, integrated circuits, amplifiers, optoelectronic devices, or any other electronic devices) can be constructed falls within the spirit and scope of this disclosure.

[0051] Figures 2A to 2C A partial cross-sectional view of a memory device 200 processed according to one or more embodiments is illustrated. Figure 3 The illustration shows a process flow diagram of a processing method 300 according to one or more embodiments of the present disclosure. Reference Figures 2A to 2C and Figure 3In one or more embodiments, at least one feature 214 is formed on substrate 202. In some embodiments, substrate 202 is provided for processing prior to operation 302. In one or more embodiments, at least one feature 214 has already been formed on substrate 202. In other embodiments, at operation 302, at least one feature 214 is formed on substrate 202. In one or more embodiments, at least one feature extends from substrate surface 222 to a feature depth D. m To the bottom surface 220, at least one feature has a width W defined by the first sidewall 216 and the second sidewall 218. m .

[0052] In one or more embodiments, at operation 304, a substrate 202 having a film stack 204 formed thereon is placed in an HDP-CVD chamber 201 for processing. (See reference) Figure 2B In one or more embodiments, a carbon film 208 is formed on the substrate surface 222 and on the walls 216, 218 and bottom 220 of at least one feature 214.

[0053] In one or more embodiments, the carbon film 208 is formed by flowing process gas into a high-density plasma chemical vapor deposition (HDP-CVD) chamber 101. In one or more embodiments, the process gas comprises a hydrocarbon reactant with a hydrogen-to-carbon ratio (H:C) less than or equal to 2:1, and one or more of hydrogen (H2), helium (He), and argon (Ar). In some embodiments, the process gas comprises a hydrocarbon reactant with a hydrogen-to-carbon ratio (H:C) less than or equal to 1:1.

[0054] In some embodiments, the hydrocarbon reactants comprise one or more of olefins and alkynes. As used herein, the term "olefin" refers to a hydrocarbon containing a carbon-carbon double bond. An olefin is an acyclic hydrocarbon with only one double bond. As used herein, the term "alkyne" refers to an unsaturated hydrocarbon containing at least one carbon-carbon triple bond. In one or more embodiments, the hydrocarbon reactants are selected from the group consisting of acetylene (C2H2), propylene (C3H6), ethylene (C2H4), and methylacetylene (C3H4).

[0055] Non-limiting examples of hydrocarbon process gases used for depositing carbon films include acetylene (C2H2) / hydrogen (H2) / helium (He) / argon (Ar), propylene (C3H6) / hydrogen (H2) / helium (He) / argon (Ar), ethylene (C2H4) / hydrogen (H2) / helium (He) / argon (Ar), and methylacetylene (C3H4) / hydrogen (H2) / helium (He) / argon (Ar).

[0056] A carbon film 208 is then deposited in the memory aperture 214 and formed on the sidewalls 216, 218 and the bottom 220, but leaving pores 240 in the memory aperture 214. According to various embodiments, filling the gaps can be performed by a single deposition or multiple depositions.

[0057] Pore ​​240 in Figure 2C The image shows a rectangular opening in the carbon film 208. However, those skilled in the art will understand that this is merely for illustrative purposes. The shape and size of the pores 240 can vary.

[0058] In one or more embodiments, gap filling can be provided by using hydrocarbon process gases in HDP CVD deposition. This... Figures 2A to 2C The diagram illustrates that, Figures 2A to 2C A cross-sectional view is depicted of feature 214 filled with a carbon film 208 during the deposition stage using HDP-CVD. As deposition proceeds, reference... Figure 2B A tip 206 is formed. This causes the top of the memory aperture 214 to close, thus creating a pore 240. The memory aperture 214 is intentionally filled and the pore 240 is intentionally formed, without being constrained by theory, to facilitate the removal of the carbon film 208 later during NAND device fabrication. The memory aperture has a high aspect ratio, where the depth is much greater than its width. If the memory aperture 214 is completely filled with the carbon film 208, removing the film would take a very long time and could potentially damage the device during removal. If the carbon film 208 is only located at the top of the memory aperture 214, there is a pore 240 below, into which solvents or plasma can penetrate to make the carbon film 208 easier to remove.

[0059] In one or more embodiments, hydrocarbons flow into the HDP-CVD processing chamber at a rate ranging from about 10 sccm to about 150 sccm (including about 15 sccm to about 135 sccm). Standard cubic centimeters per minute (sccm) is a unit of flow rate measurement that indicates the flow rate in cubic centimeters per minute (cm³) under standard conditions of temperature and pressure for a given fluid (typically a gas). 3 / min).

[0060] In one or more embodiments, argon (Ar) is introduced / flowed into the HDP-CVD chamber at a flow rate ranging from about 40 sccm to about 60 sccm. In one or more embodiments, hydrogen (H2) is introduced / flowed into the HDP-CVD chamber at a flow rate ranging from about 0 sccm to about 500 sccm (including the ranges from about 0 sccm to about 300 sccm and from about 0 sccm to about 200 sccm). In one or more embodiments, helium (He) is introduced / flowed into the HDP-CVD chamber at flow rates ranging from about 0 sccm to about 500 sccm and from about 0 sccm to about 300 sccm.

[0061] In one or more embodiments, the apparatus 200 is processed at a temperature ranging from about 400°C to about 650°C and a pressure of less than about 50 mTorr. In some embodiments, the pressure is less than about 40 mTorr, or less than about 30 mTorr, or less than about 20 mTorr, or less than about 10 mTorr.

[0062] In one or more embodiments, the carbon film 208 exhibits excellent thermal stability. After annealing at a temperature greater than or equal to 800°C for 1 hour, the shrinkage rate of the carbon film 208 is less than 20%. In some embodiments, the shrinkage rate of the carbon film 208 is less than 15%. In some embodiments, the shrinkage rate of the carbon film 208 is less than 10%.

[0063] like Figure 2C As shown, in one or more embodiments, the carbon film 208 has a width W located at at least one feature 214. m The internal porosity is 240.

[0064] At decision point 310, it is determined whether the desired film properties of the carbon film 208 have been achieved. If the desired properties have been achieved, the apparatus 200 is provided at operation 312 for further processing. If the desired properties have not been achieved, the process returns to operation 306, in which the substrate is exposed to hydrocarbon processing gases again.

[0065] Figure 2D and Figure 2E A partial cross-sectional view of a memory device 200 according to one or more embodiments is illustrated. At operation 312, the device 200 may undergo various post-processing methods. For example, refer to... Figure 2D The carbon film 208 is etched or planarized such that the carbon film 208 is substantially coplanar with the top surface 222 of the device 200. The carbon film 208 can be etched or planarized using any suitable process known to those skilled in the art, including but not limited to chemical mechanical polishing (CMP), wet etching, plasma-based sputtering etching, chemical etching, etc. Etching, reactive ion etching (RIE), high-density plasma (HDP) etching, etc. In some embodiments, the step of etching the carbon film 208 includes exposing the carbon film 208 to an etching chemical comprising one or more of NF3, CL2, HBR, C4F6, C2F4, H2, Ar, He, or N2. In one or more embodiments, the carbon film 208 is planarized by chemical mechanical polishing (CMP).

[0066] refer to Figure 2EA film 232 is deposited on the top surface 222 and the top surface of the carbon film 208. In one or more embodiments, the film 232 may be composed of any suitable material. In some embodiments, the film 232 comprises silicon nitride (SiN) or silicon oxide (SiO2). X One or more of the following. In one or more embodiments, film 232 is formed by atomic layer deposition or plasma-enhanced chemical vapor deposition (PECVD). In one or more embodiments, film 232 covers the gap-filled carbon film 208 and reduces the shrinkage of the underlying gap-filled carbon film 208 during annealing. In one or more embodiments, film 232 may be removed after annealing.

[0067] According to one or more embodiments, the apparatus 200 undergoes processing before and / or after the formation of the layer. This processing may be performed in the same chamber or in one or more separate processing chambers.

[0068] One or more embodiments of the method can be implemented in an HDP-CVD reactor. Such reactors can take many different forms. Typically, the apparatus will include one or more chambers or “reactors” (sometimes including multiple stations) that house one or more substrates and are suitable for substrate processing. Each chamber can house one or more substrates for processing. The one or more chambers hold the substrates in one or more defined positions (with or without movement, such as rotation, vibration, or other agitation). In the process, each substrate is held in place by a base, a vacuum chuck, and / or an electrostatic chuck. For certain operations requiring heating of the substrates, the apparatus may include heaters, such as heating plates. A suitable reactor example is the CENTURA, available from Applied Materials, Santa Clara, California. HDP-CVD chamber / system.

[0069] Combined with the following Figure 4A and Figure 4B Provides an overview of the HDP-CVD chamber / system. Figure 4A The structure of such an HDP-CVD system 610 in one embodiment is schematically illustrated. System 610 includes a chamber 613, a vacuum system 670, a source plasma system 680A, a substrate bias plasma system 680B, a gas delivery system 633, and a remote plasma cleaning system 650.

[0070] The upper part of the chamber 613 includes a dome 614, which is made of a ceramic dielectric material (such as alumina or aluminum nitride). The dome 614 defines the upper boundary of the plasma processing region 616. The plasma processing region 616 is defined at the bottom by the upper surface of the substrate 617 and the substrate support member 618.

[0071] A heating plate 623 and a cooling plate 624 are located above and thermally coupled to the dome 614. The heating plate 623 and cooling plate 624 allow the dome temperature to be controlled within approximately ±10°C of the range of approximately 400°C to approximately 650°C. This allows for optimization of the dome temperature for various processes. For example, in cleaning or etching processes, it may be desirable to maintain the dome at a higher temperature compared to deposition processes. Precise control of the dome temperature also reduces the number of debris or particles in the chamber and improves the adhesion between the deposited layer and the substrate.

[0072] The lower portion of chamber 613 includes a main body member 622, which connects the chamber to a vacuum system. The bottom 621 of a substrate support member 618 is mounted on the main body member 622 and forms a continuous inner surface with the main body member 622. A substrate is moved into and out of chamber 613 via a robot blade (not shown) through an insertion / removal opening (not shown) on the side of chamber 613. A lifting rod (not shown) is raised and then lowered under the control of a motor (also not shown) to move the substrate from the robot blade at an upper loading position 657 to a lower processing position 656, where the substrate is placed on a substrate receiving portion 619 of the substrate support member 618. The substrate receiving portion 619 includes an electrostatic chuck 620 that holds the substrate to the substrate support member 618 during substrate processing. In a particular embodiment, the substrate support member 618 is made of alumina or alumina-ceramic material.

[0073] Vacuum system 670 includes a throttle body 625 that houses a two-lobe throttle valve 626 and is attached to a gate valve 627 and a turbomolecular pump 628. It should be noted that the throttle body 625 provides minimal resistance to airflow and allows for symmetrical pumping. The gate valve 627 isolates the pump 628 from the throttle body 625 and controls chamber pressure by limiting exhaust flow when the throttle valve 626 is fully open. The arrangement of the throttle valve, gate valve, and turbomolecular pump allows for precise and stable control of chamber pressures from approximately 1 mTorr to approximately 2 Torr.

[0074] The source plasma system 680A includes a top coil 629 and a side coil 630 mounted on a dome 614. A symmetrically grounded shield (not shown) reduces electrical coupling between the coils. The top coil 629 is powered by a top-source RF (SRF) generator 631A, while the side coil 630 is powered by a side SRF generator 631B, allowing for independent power levels and operating frequencies for each coil. This dual-coil system allows for control of the radial ion density in chamber 613, thereby improving plasma homogeneity. The side coil 630 and top coil 629 are typically inductively driven, which eliminates the need for auxiliary electrodes. In a particular embodiment, the top-source RF generator 631A provides up to 10,000 watts of RF power at a nominal 2 MHz, and the side-source RF generator 631B provides up to 10,500 watts of RF power at a nominal 2 MHz. The operating frequencies of the top and side RF generators can be deviated from the nominal operating frequency (e.g., to 1.7–1.9 MHz and 1.9–2.1 MHz, respectively) to improve plasma generation efficiency.

[0075] The substrate biased plasma system 680B includes a biased RF (“BRF”) generator 631C and a bias matching network 632C. The biased plasma system 680B capacitively couples a substrate portion 617 to a body member 622, with the substrate portion 617 and the body member 622 serving as complementary electrodes. The biased plasma system 680B is used to enhance the transport of plasma material (e.g., ions) generated by the source plasma system 680A to the substrate surface. In a particular embodiment, the substrate biased RF generator provides up to 10,000 watts of RF power at a frequency of approximately 13.56 MHz.

[0076] RF generators 631A and 631B include a digitally controlled synthesizer. Each generator includes RF control circuitry (not shown) that measures the reflected power returning from the chamber and coils to the generator and adjusts the operating frequency to obtain the lowest reflected power, as understood by one of ordinary skill in the art. RF generators are typically designed to operate with a load having a characteristic impedance of 50 ohms. RF power can be reflected from a load having a different characteristic impedance than the generator. This can reduce the power transmitted to the load. Furthermore, power reflected back to the generator from the load can overload and damage the generator. Since the impedance of the plasma can range from less than 5 ohms to greater than 900 ohms, depending on factors such as plasma ion density, and the reflected power can be a function of frequency, adjusting the generator frequency according to the reflected power can increase the power transmitted from the RF generator to the plasma and protect the generator. Another method to reduce reflected power and improve efficiency is to use a matching network.

[0077] Matching networks 632A and 632B match the output impedances of generators 631A and 631B to their respective coils 629 and 630. The RF control circuitry can tune the two matching networks by changing the values ​​of the capacitors within them to match the generator to the load as the load changes. The RF control circuitry can also tune the matching networks when the power reflected back to the generator from the load exceeds a certain limit. One method to provide constant matching and effectively prevent the RF control circuitry from tuning the matching networks is to set the reflected power limit above any expected value. This can help stabilize the plasma under certain conditions by keeping the matching networks constant in their most recent state.

[0078] Other measures may also help stabilize the plasma. For example, RF control circuitry can be used to determine the power delivered to the load (plasma) and can increase or decrease the generator output power to keep the delivered power substantially constant during layer deposition.

[0079] Gas delivery system 633 delivers gas from several sources 634A to 634E to a chamber for processing the substrate via gas delivery lines 638 (some of which are shown only). As those skilled in the art will understand, the actual sources for sources 634A to 634E and the actual connections of delivery lines 638 to chamber 613 vary depending on the deposition and cleaning processes performed within chamber 613. Gas is introduced into chamber 613 through gas ring 637 and / or top nozzle 645. Figure 4B This is a simplified partial cross-sectional view of chamber 613, illustrating additional details of the gas ring 637.

[0080] In one embodiment, a first gas source 634A and a second gas source 634B, along with a first gas flow controller 635A' and a second gas flow controller 635B', supply gas to the annular inflation booster 636 in the gas ring 637 via gas delivery lines 638 (only some are illustrated). The gas ring 637 has a plurality of source gas nozzles 639 (only one is illustrated for illustrative purposes), which provide a uniform airflow on the substrate. The nozzle length and nozzle angle can be varied to allow for tailoring of uniformity profiles and gas utilization efficiency for a specific process within a single chamber. In a particular embodiment, the gas ring 637 has 12 source gas nozzles made of alumina ceramic.

[0081] The gas ring 637 also has a plurality of oxidant gas nozzles 640 (only one is shown). In one embodiment, the plurality of oxidant gas nozzles 640 are coplanar with and shorter than the source gas nozzle 639, and in one embodiment, receive gas from the main body pressurization section 641. In some embodiments, it is desirable not to mix the source gas and the oxidant gas before injecting gas into the chamber 613. In other embodiments, the oxidant gas and the source gas can be mixed by providing an orifice (not shown) between the main body pressurization section 641 and the gas ring pressurization section 636 before injecting gas into the chamber 613. In one embodiment, a third gas source 634C, a fourth gas source 634D, and a fifth gas source 634D', as well as a third gas flow controller 635C and a fourth gas flow controller 635D', supply gas to the main body pressurization section via a gas delivery line 638. Additional valves (such as 643B (other valves not shown)) can shut off the gas from the flow controller to the chamber. In some embodiments of the invention, source 634A includes a hydrocarbon source, source 634B includes a molecular hydrogen (H2) source, source 634C includes a helium (He) source, and source 634D includes an argon (Ar) source.

[0082] In embodiments using flammable, toxic, or corrosive gases, it may be necessary to eliminate residual gas in the gas delivery line after deposition. This can be achieved, for example, by using a three-way valve (such as valve 643B) to isolate chamber 613 from delivery line 638A and venting delivery line 638A to vacuum pre-line 644. Figure 4A As shown, other similar valves (such as 643A and 643C) can be integrated into other gas delivery lines. Such three-way valves can be placed as close as possible to chamber 613 to minimize the volume of unvented gas delivery lines (between the three-way valve and the chamber). Additionally, a two-way (on / off) valve (not shown) can be placed between the mass flow controller (“MFC”) and the chamber or between the gas source and the MFC.

[0083] Refer again Figure 4AThe chamber 613 also includes a top nozzle 645 and a top vent 646. The top nozzle 645 and top vent 646 allow independent control of the top and side flow of gas, which improves membrane uniformity and allows for fine-tuning of membrane deposition and doping parameters. The top vent 646 is an annular opening around the top nozzle 645. In one embodiment, a first gas source 634A supplies source gas to source gas nozzle 639 and top nozzle 645. Source nozzle MFC 635A' controls the amount of gas delivered to source gas nozzle 639, and top nozzle MFC 635A controls the amount of gas delivered to top gas nozzle 645. Similarly, two MFCs 635B and 635B' can be used to control the oxygen flow from a single oxygen source (such as source 634B) to top vent 646 and oxidant gas nozzle 640. In some embodiments, oxygen is not supplied to the chamber from any side nozzle. The gas supplied to the top nozzle 645 and top vent 646 before flowing into chamber 613 can be kept separate, or the gas can be mixed in the top inflation booster 648 before flowing into chamber 613. Separate sources of the same gas can be used to supply different parts of the chamber.

[0084] A plasma cleaning system 650 that generates remote microwaves is provided for periodically cleaning deposited residues on chamber components. The cleaning system includes a remote microwave generator 651 that generates plasma from a cleaning gas source 634E (e.g., molecular fluorine, nitrogen trifluoride, other fluorocarbons, or equivalents) within a reactor chamber 653. Reactive material generated from this plasma is delivered to the chamber 613 via an applicator tube 655 and a cleaning gas inlet 654. The materials used to contain the cleaning plasma (e.g., chamber 653 and applicator tube 655) must be resistant to plasma erosion. The distance between the reactor chamber 653 and the inlet 654 should be kept as short as possible, as the ideal plasma material concentration may decrease with distance from the reactor chamber 653. Generating cleaning plasma in a remote chamber allows for the use of a highly efficient microwave generator and avoids bombardment of chamber components by temperature, radiation, or glow discharges that may exist in in-situ formed plasma. Therefore, relatively sensitive components (such as the electrostatic chuck 620) do not require dummy wafer covering or other protection as required by in-situ plasma cleaning processes. Figure 4A In this configuration, the plasma cleaning system 650 is positioned above the chamber 613, although other locations may be used alternatively.

[0085] A baffle 661 may be provided near the top nozzle to guide the source gas flow supplied via the top nozzle into the chamber and to guide the remotely generated plasma flow. The source gas supplied via the top nozzle 645 is guided into the chamber through the central channel 662, while the remotely generated plasma material supplied via the purge gas inlet 654 is guided to the side of the chamber 613 through the baffle 661.

[0086] Example

[0087] Example 1:

[0088] A substrate with stacked oxide / nitride films containing memory vias is placed in an HDP CVD processing chamber. Process gases He / Ar / C₂H₂ flow into the chamber. The substrate is maintained at 500°C and 3 mTorr. Plasma is generated using an RF source. An amorphous carbon (aC) layer is formed in the memory vias on the substrate. Pores are left in the memory vias. The substrate is annealed at 800°C for 1 hour. The carbon film withstands annealing at 800°C with a shrinkage rate ≥25%.

[0089] Example 2:

[0090] A substrate with stacked oxide / nitride films containing memory vias was placed in an HDP CVD processing chamber. Process gases He / Ar / C₂H₂ flowed into the chamber. The substrate was maintained at 550°C and 10 mTorr. Plasma was generated using an RF source. An amorphous carbon (aC) layer was formed in the memory vias on the substrate. Pores were left in the memory vias. The substrate was annealed at 800°C for 1 hour. The carbon film underwent annealing at 800°C, with a shrinkage rate of 15.5%.

[0091] Example 3:

[0092] A substrate with stacked oxide / nitride films containing memory vias was placed in an HDP CVD processing chamber. Process gases H2 / He / Ar / C2H2 flowed into the chamber. The substrate was maintained at 592°C and 4.2 mTorr. Plasma was generated using an RF source. An amorphous carbon (aC) layer was formed on the substrate with the memory vias. Pores were left in the memory vias. The substrate was annealed at 800°C for 1 hour. The carbon film withstood the 800°C annealing with a shrinkage rate of <10%.

[0093] In terms of stress, gap filling, and thermal stability, the process of Example 3 has more process margin than the processes of Example 1 and Example 2. The carbon film formed in Example 3 exhibits a shrinkage rate of <10% after annealing at 800°C for 1 hour.

[0094] As shown in the figures, for ease of description, spatially relative terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein to describe the relationship of one element or feature to another (or more) elements or features. It should be understood that, in addition to the orientations depicted in the figures, the spatially relative terms are intended to encompass different orientations of the device being used or operated. For example, if the device in the figures were flipped, an element described as “below other elements or features” or “below other elements or features” would be oriented “above other elements or features.” Thus, the exemplary term “below” can include orientations above and below both. The device may be oriented in other ways (rotated 90 degrees or in other orientations) and the spatially relative descriptive terms used herein may be interpreted accordingly.

[0095] In the context of describing the materials and methods discussed herein (especially in the context of the appended claims), the terms “a” and “an”, as well as “described” and similar designations, should be interpreted as including both the singular and plural, unless otherwise stated herein or contradicted by the obvious context. Unless otherwise stated herein, descriptions of numerical ranges herein are intended only as a way of abbreviating each individual numerical value falling within the range, and each individual numerical value is incorporated into this specification as if it were described separately herein. Unless otherwise stated herein or by the obvious contradiction of the context, all methods described herein may be performed in any suitable order. The use of any and all example or exemplary language provided herein (e.g., “such as”) is intended only to better illustrate the materials and methods and does not constitute a limitation on the scope, unless otherwise stated. No language in the specification should be construed as indicating that any unclaimed element is essential to the practice of the disclosed materials and methods.

[0096] Throughout this specification, references to "an embodiment," "some embodiments," "one or more embodiments," or "embodiment" mean that a particular feature, structure, material, or characteristic described in connection with an embodiment is included in at least one embodiment of this disclosure. Therefore, phrases such as "in one or more embodiments," "in some embodiments," "in one embodiment," or "in an embodiment" appearing in various places in this specification do not necessarily refer to the same embodiment of this disclosure. In one or more embodiments, a particular feature, structure, material, or characteristic is combined in any suitable manner.

[0097] Although the disclosure herein has been described with reference to specific embodiments, it should be understood that these embodiments are merely illustrative of the principles and applications of this disclosure. It will be apparent to those skilled in the art that various modifications and variations can be made to the methods and apparatus of this disclosure without departing from the spirit and scope of this disclosure. Therefore, this disclosure is intended to cover modifications and variations falling within the scope of the appended claims and their equivalents.

Claims

1. A method for forming a membrane, the method comprising the following steps: Process gas is introduced into a high-density plasma chemical vapor deposition (HDP-CVD) chamber, the chamber containing a substrate having a substrate surface and at least one feature, the process gas comprising hydrocarbon reactants with a hydrogen-to-carbon ratio (H:C) less than or equal to 2:1, and one or more of hydrogen (H2), helium (He) and argon (Ar), the substrate being processed at a temperature in the range of 400°C to 650°C and a pressure of less than 50 mTorr; plasma is generated; A carbon film is deposited in at least one of the features, the carbon film having pores in the at least one feature; The carbon film is etched or planarized such that the carbon film is coplanar with the surface of the substrate, and a second film is deposited on the surface of the substrate and the top surface of the carbon film. as well as The substrate is annealed, wherein the second film reduces the shrinkage of the carbon film during annealing.

2. The method of claim 1, wherein the hydrocarbon reactant comprises one or more of olefins and alkynes.

3. The method of claim 2, wherein the hydrocarbon reactant is selected from the group consisting of: acetylene (C2H2), propylene (C3H6), ethylene (C2H4), and methylacetylene (C3H4).

4. The method of claim 1, wherein the carbon film comprises an amorphous carbon (aC) film.

5. The method of claim 1, wherein the at least one feature is selected from one or more of a trench, a through hole, a word line slit, and a memory hole.

6. The method of claim 5, wherein the at least one feature has an aspect ratio greater than or equal to 50:

1.

7. The method of claim 5, wherein the at least one feature extends from the top surface of the substrate to a feature depth to the bottom surface and has a width defined by a first sidewall and a second sidewall, wherein the carbon film is deposited on the top surface, the first sidewall, the second sidewall, and the bottom surface, and the pore is located within the width of the at least one feature at a first distance from the bottom surface of the feature.

8. A method for forming a membrane, the method comprising the following steps: Process gas is introduced into a high-density plasma chemical vapor deposition (HDP-CVD) chamber, which contains a substrate having a substrate surface. The process gas contains hydrocarbon reactants with a hydrogen-to-carbon ratio (H:C) less than or equal to 2:1, and one or more of hydrogen (H2), helium (He) and argon (Ar). plasma is generated; A carbon film is deposited on the surface of the substrate, the surface of the substrate having at least one feature extending a depth from the surface of the substrate to a bottom surface, the at least one feature having a width defined by a first sidewall and a second sidewall, wherein the carbon film is deposited on the surface of the substrate, the first sidewall, the second sidewall and the bottom surface of the at least one feature, the carbon film having pores located within the width of the feature at a first distance from the bottom surface of the feature; The carbon film is etched or planarized such that the carbon film is coplanar with the surface of the substrate, and a second film is deposited on the surface of the substrate and the top surface of the carbon film. as well as The substrate is annealed, wherein the second film reduces the shrinkage of the carbon film during annealing.

9. The method of claim 8, wherein the second film comprises silicon nitride (SiN) or silicon oxide (SiO). X One or more of them.

10. The method of claim 8, wherein the substrate is processed at a temperature in the range of 400°C to 640°C and a pressure of less than 50 millitor.

11. The method of claim 8, wherein the hydrocarbon reactant is selected from the group consisting of acetylene (C2H2), propylene (C3H6), ethylene (C2H4), and methylacetylene (C3H4).

12. The method of claim 8, wherein the carbon film comprises an amorphous carbon (aC) film.

13. The method of claim 8, wherein the feature has an aspect ratio greater than or equal to 10:

1.

14. The method of claim 8, wherein the depth of the at least one feature is in the range of 50 nm to 10000 nm.

15. A method of manufacturing a memory device, the method comprising the following steps: A film stack is formed on a substrate, the film stack comprising multiple alternating layers of a first material and a second material, and the film stack having a stack thickness; The film stack is etched to form a memory aperture opening that extends from the top surface of the film stack to the bottom surface and has a width defined by a first sidewall and a second sidewall. The substrate is placed into a high-density plasma chemical vapor deposition (HDP-CVD) chamber; Process gas is introduced into the high-density plasma chemical vapor deposition (HDP-CVD) chamber, the process gas containing hydrocarbon reactants with a hydrogen-to-carbon ratio (H:C) less than or equal to 2:1, and one or more of hydrogen (H2), helium (He) and argon (Ar), the film stacked at a temperature in the range of 400°C to 650°C and a pressure of less than 50 mTorr; A carbon film is deposited on the top surface of the film stack, and on the first sidewall, the second sidewall, and the bottom surface of the memory aperture opening. The carbon film has pores located within the width of the memory aperture and at a first distance from the bottom surface of the memory aperture opening. The carbon film is etched or planarized such that the carbon film is coplanar with the top surface of the film stack, and a second film is deposited on the top surface of the film stack and the top surface of the carbon film. as well as The substrate is annealed, wherein the second film reduces the shrinkage of the carbon film during annealing.

16. The method of claim 15, wherein the hydrocarbon reactant is selected from the group consisting of acetylene (C2H2), propylene (C3H6), ethylene (C2H4), and methylacetylene (C3H4).

17. The method of claim 15, wherein the second film comprises silicon nitride (SiN) or silicon oxide (SiO). X One or more of them.

18. The method of claim 15, wherein the first material and the second material independently comprise one or more of an oxide material, a nitride material, and a polycrystalline silicon material.

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