Metal-insulator-metal (MIM) capacitors and thin film resistors (TFRs) formed in integrated circuit structures

Abstract

An integrated circuit structure includes a metal-insulator-metal (MIM) capacitor and a thin film resistor (TFR) formed concurrently using components of a shared material layer. A first metal layer can be patterned to form lower components of an interconnect structure, the MIM capacitor, and the TFR, and a second metal layer can be patterned to form upper components of the interconnect structure, the MIM capacitor, and the TFR. A via layer can be deposited to form interconnect vias, a cup-shaped bottom electrode component of the MIM capacitor, and a pair of TFR contact vias of the TFR. An insulator layer can be patterned to form an insulator of the MIM capacitor and an insulator cap on the TFR element.

Description

[0001] Related patent applications

[0002] This application claims priority to jointly owned U.S. Provisional Patent Application No. 63 / 161,492, filed March 16, 2021, the entire contents of which are incorporated herein by reference for all purposes. Technical Field

[0003] This disclosure relates to analog components formed in integrated circuit devices, and more specifically to metal-insulator-metal (MIM) capacitors and thin-film resistors (TFRs) formed simultaneously in integrated circuit structures. Background Technology

[0004] Capacitors and resistors that are monolithically formed in integrated circuit devices are called integrated capacitors and resistors. Integrated capacitors and resistors are common components in many integrated circuit devices. For example, various analog, mixed-signal, and RF-CMOS (Radio Frequency Complementary Metal-Oxide-Semiconductor) integrated circuit devices use these two components individually or in combination with each other, i.e., integrated capacitors and resistors. Integrated capacitors and resistors offer various advantages over their discrete counterparts (i.e., off-chip capacitors and resistors). For example, integrated capacitors and resistors can generally be manufactured at a lower cost compared to typical discrete (off-chip) capacitors and resistors; on-chip system devices that include integrated capacitors and resistors can have a reduced pin count (which provides improved ease of use and form factor); and can exhibit reduced parasitic capacitance.

[0005] One type of integrated capacitor is the metal-insulator-metal (MIM) capacitor, which is constructed of a metal top plate, a metal base plate, and an insulator (dielectric material) sandwiched between the metal top plate and the metal base plate. MIM capacitors typically offer better performance than alternatives such as POP (polysilicon-oxide-polysilicon) capacitors and MOM (metal-oxide-metal) capacitors due to lower resistance, better matching to analog circuits (e.g., matching device characteristics such as resistance and capacitance), and / or a better signal-to-noise ratio.

[0006] One type of integrated resistor is the thin-film resistor (TFR), which comprises a pair of TFR heads connected by a TFR element or a TFR film. TFR elements are typically formed from materials such as SiCr (silicon-chromium), SiCCr (silicon-chromium carbide), TaN (tantalum nitride), NiCr (nickel-chromium), AlNiCr (aluminum-doped nickel-chromium), or TiNiCr (titanium-nickel-chromium). TFRs generally offer better performance than polycrystalline resistors, such as better control over the resistance value and a better (closer to zero) temperature coefficient of resistance (TCR) characteristic than polycrystalline silicon (polycrystalline) resistors.

[0007] The construction cost of MIM capacitors and TFRs is generally higher than that of other integrated capacitors and resistors. For example, the process for forming a MIM capacitor or TFR typically involves at least one additional mask layer compared to other types of integrated capacitors and resistors. Furthermore, MIM capacitors and TFRs are often constructed independently of each other, which further increases the number of additional mask layers involved in the manufacturing process.

[0008] There is a need to build integrated capacitors and resistors, especially to construct MIM capacitors and TFRs together (simultaneously) efficiently and at low cost. Summary of the Invention

[0009] Embodiments of this disclosure provide an integrated circuit structure comprising a simultaneously formed three-dimensional (3D) MIM capacitor and a thin-film resistor (TFR), as well as a method for forming such an integrated circuit structure. In some embodiments, the MIM capacitor and TFR can be formed using only a single added mask layer, compared to background integrated circuit manufacturing processes.

[0010] In some implementations, the MIM capacitor and TFR can be formed simultaneously with the interconnect structure, for example, using components sharing a common material layer. For example, (a) a first common metal layer can be patterned to form the lower interconnect, the bottom electrode plate of the MIM capacitor, and a pair of TFR heads; (b) a common via layer can be deposited to form interconnect vias, the cup-shaped bottom electrode component of the MIM capacitor, and a pair of TFR contact vias on which TFR elements are formed; (c) a common insulating layer can be patterned to form the insulator of the MIM capacitor and the insulating cap (protective layer) on the TFR elements; and (d) a second common metal layer can be patterned to form the upper interconnect, the top electrode of the MIM capacitor, and the metal TFR cap.

[0011] One aspect provides an integrated circuit structure including a MIM capacitor and a TFR resistor. The MIM capacitor includes a MIM bottom electrode, a MIM top electrode, and a MIM insulator. The MIM bottom electrode includes a bottom electrode plate formed in a first metal layer; and a bottom electrode cup including a laterally extending bottom electrode cup base and a plurality of vertically extending bottom electrode cup sidewalls extending upward from the bottom electrode cup base. The MIM top electrode is formed in a second metal layer above the first metal layer. The MIM insulator includes an insulator base disposed between the MIM top electrode and the bottom electrode cup base; and a plurality of vertically extending insulator sidewalls, each insulator sidewall disposed between the MIM top electrode and a corresponding bottom electrode cup sidewall. The TFR includes a pair of TFR heads formed in the first metal layer and a TFR element connected to each TFR head via a TFR contact via.

[0012] In one implementation, the MIM insulator is cup-shaped.

[0013] In one embodiment, the TFR contact via and the vertically extending bottom electrode cup sidewall are formed in the dielectric region between the first metal layer and the second metal layer.

[0014] In one embodiment, the TFR includes a TFR insulator cap (protective layer) formed on the TFR element, and the TFR insulator cap and the MIM insulator are formed in the insulator layer.

[0015] In one embodiment, the integrated circuit structure further includes an interconnect structure comprising a lower interconnect formed in a first metal layer and an upper interconnect formed in a second metal layer and connected to the lower interconnect through at least one interconnect via.

[0016] In one embodiment, the MIM capacitor further includes a bottom electrode connection pad connected to the bottom electrode plate through at least one through-hole, and the bottom electrode connection pad is formed in a second metal layer above the first metal layer.

[0017] In one embodiment, the TFR contact through-hole for connecting the TFR membrane to each TFR head has a width in a first transverse direction and a length in a second transverse direction that is at least five times the width in the first transverse direction.

[0018] In some embodiments, the first metal layer is an interconnect layer comprising copper or aluminum, and the second metal layer comprises aluminum. In other embodiments, the first metal layer is a silicided polysilicon layer comprising metal silicide regions formed on each of a plurality of polysilicon regions.

[0019] On the other hand, an integrated circuit structure is provided, which includes (a) an interconnect structure, (b) a MIM capacitor, and (c) a TFR. The interconnect structure includes a lower interconnect and an upper interconnect connected to the lower interconnect. The MIM capacitor includes a bottom electrode plate, a top MIM electrode, and a MIM insulator disposed between the top MIM electrode and the bottom MIM electrode plate. The TFR includes a pair of TFR headers and a TFR element connected to the pair of TFR headers. The lower interconnect, the bottom electrode plate, and the pair of TFR headers are formed in a first metal layer, and the upper interconnect and the top MIM electrode are formed in a second metal layer above the first metal layer.

[0020] In one embodiment, the MIM capacitor further includes a bottom electrode connection pad formed in the second metal layer and connected to the bottom electrode plate through a through-hole.

[0021] In one embodiment, the MIM capacitor includes a bottom electrode cup formed on a bottom electrode plate, wherein the bottom electrode cup includes a laterally extending bottom electrode cup base formed on the bottom electrode plate, and a plurality of vertically extending bottom electrode cup sidewalls. The MIM insulator and the MIM top electrode are at least partially located within the internal volume of the bottom electrode cup.

[0022] On the other hand, a method for forming an integrated circuit structure is provided, the integrated circuit structure including a MIM capacitor and a TFR. The integrated circuit structure includes a MIM capacitor and a TFR. A plurality of first conductive elements, including a MIM bottom electrode plate and a first TFR head and a second TFR head, are formed in a first metal layer. The TFR elements are formed to be conductively connected to both the first TFR head and the second TFR head. An insulating layer is formed over the first metal layer to define a MIM insulator and a TFR insulator cap on the TFR elements. A plurality of second conductive elements are formed in a second metal layer over the first metal layer, the plurality of second conductive elements including a MIM top electrode. A MIM insulator is formed between the MIM bottom electrode plate and the MIM top electrode.

[0023] In one embodiment, the method further includes forming a plurality of vertically extending MIM bottom electrode cup sidewalls above the MIM bottom electrode plate, wherein the MIM insulator includes a plurality of vertically extending insulator sidewalls, each vertically extending insulator sidewall being formed adjacent to a corresponding vertically extending MIM bottom electrode cup sidewall.

[0024] In one embodiment, the method further includes forming, after forming a plurality of conductive elements in the first metal layer and before forming the TFR elements, simultaneously forming: (a) a vertically extending MIM bottom electrode cup sidewall above the MIM bottom electrode plate, and (b) a first TFR contact via conductively connected to a first TFR head and a second TFR contact via conductively connected to a second TFR head. The TFR elements are conductively connected to the first TFR head through the first TFR contact via and conductively connected to the second TFR head through the second TFR contact via.

[0025] In one embodiment, the plurality of second conductive elements further include a MIM bottom electrode connection pad connected to the MIM bottom electrode plate via at least one MIM bottom electrode connection pad via.

[0026] In one embodiment, the method further includes forming, after forming a plurality of conductive elements in the first metal layer and before forming the TFR elements, simultaneously forming: (a) a vertically extending MIM bottom electrode cup sidewall above the MIM bottom electrode plate, (b) a first TFR contact via electrically connected to a first TFR head and a second TFR contact via electrically connected to a second TFR head, and (c) at least one MIM bottom electrode connection pad via.

[0027] In one embodiment, the method further includes forming a MIM bottom electrode cup on a MIM bottom electrode plate, the MIM bottom electrode cup including a laterally extending bottom electrode cup base formed on the MIM bottom electrode plate and a plurality of vertically extending MIM bottom electrode cup sidewalls. The MIM insulator and the MIM top electrode are at least partially formed within the internal volume of the MIM bottom electrode cup.

[0028] In one embodiment, the plurality of first conductive elements further include a lower interconnect line, and the plurality of second conductive elements further include an upper interconnect line connected to the lower interconnect line through at least one interconnect via.

[0029] In one embodiment, forming a TFR element includes forming and patterning a TFR layer to form (a) the TFR element and (b) a TFR layer region above the bottom electrode plate of the MIM. An MIM insulator is then formed on the TFR layer region above the bottom electrode plate of the MIM. Attached Figure Description

[0030] Example aspects of this disclosure are described below with reference to the accompanying drawings, in which:

[0031] Figure 1 A cross-sectional view is shown of an exemplary integrated circuit structure according to an exemplary embodiment, including interconnect structures, MIM capacitors, and TFRs formed simultaneously using a shared material layer;

[0032] Figures 2 to 9 This illustrates a method for forming according to an exemplary embodiment. Figure 1 The exemplary process of the exemplary integrated circuit structure shown; and

[0033] Figure 10 An example embodiment similar to that shown is illustrated. Figure 1 The exemplary integrated circuit structure shown is a cross-sectional side view, wherein the selected lower elements of the interconnect structure, MIM capacitor and TFR are formed as polysilicon silicon elements.

[0034] It should be understood that reference numerals for any illustrated element appearing in multiple different figures have the same meaning in all figures, and any illustrated element mentioned or discussed herein in the context of any particular figure also applies to every other figure (if any) in which the same illustrated element is shown. Detailed Implementation

[0035] Embodiments of this disclosure provide an integrated circuit (IC) structure comprising a simultaneously formed three-dimensional (3D) MIM capacitor and a thin-film resistor (TFR), and a method for forming such an IC structure. In some embodiments, the MIM capacitor and TFR are formed simultaneously with interconnect structures, for example, using components sharing a common material layer. For example, a first common metal layer may be patterned to form selected lower components of the interconnect structure, MIM capacitor, and TFR, and a second common metal layer may be patterned to form selected upper components of the interconnect structure, MIM capacitor, and TFR. A common via layer may be deposited to form interconnect vias, a cup-shaped component for the bottom electrode of the MIM capacitor, and a pair of TFR contact vias for the TFR, and a common insulating layer may be patterned to form the insulator of the MIM capacitor and the insulating cap on the TFR element.

[0036] Figure 1 A cross-sectional view of an exemplary IC structure 100 according to an exemplary embodiment is shown, the IC structure including (a) an interconnect structure 102, (b) a MIM capacitor 104 and (c) a TFR 106 formed simultaneously using a shared material layer.

[0037] Interconnection structure 102 may include a first metal layer M x The lower interconnect 110 in the middle, and the second metal layer M formed therein x+1 And through the formation in the through-hole layer V x At least one interconnect via 114 is connected to the upper interconnect 112 of the lower interconnect 110, for example, an interconnect bonding pad. Second metal layer M x+1 Formed in the first metal layer M x Above.

[0038] MIM capacitor 104 includes a MIM bottom electrode 120, a MIM top electrode 122, and a MIM insulator 124 sandwiched between the MIM bottom electrode 120 and the MIM top electrode 122. MIM bottom electrode 120 includes (a) formed in a first metal layer M x(a) A bottom electrode plate 126 and (b) a bottom electrode cup 128 formed on the bottom electrode plate 126. The bottom electrode cup 128 includes a laterally extending bottom electrode cup base 130 and a plurality of vertically extending bottom electrode cup sidewalls 132 extending upward from the laterally extending bottom electrode cup base 130. The bottom electrode cup base 130 may have a rectangular perimeter (e.g., having a square or non-square rectangular shape), which defines four lateral sides when viewed from above, wherein four vertically extending bottom electrode cup sidewalls 132 extend upward from the four lateral sides of the rectangular perimeter, as discussed below. Figures 5A to 5B As better illustrated in the diagram. As another example, the bottom electrode cup 128 may include two vertically extending bottom electrode cup sidewalls 132 extending upward from two opposing lateral sides of the bottom electrode cup base 130, for example in... Figure 1 Two bottom electrode cup sidewalls 132 are visible in the image. The bottom electrode cup 128 may include any other number of vertically extending bottom electrode cup sidewalls 132 extending upward from the bottom electrode cup base 130.

[0039] A laterally extending bottom electrode cup base 130 and a vertically extending bottom electrode cup sidewall 132 define an internal volume 136 of the bottom electrode cup 128. As shown, a MIM insulator 124 may be formed on the bottom electrode cup 128 and extend into the internal volume 136 of the bottom electrode cup 128, such that the MIM insulator 124 is also cup-shaped. The cup-shaped MIM insulator 124 includes a laterally extending insulator cup base 140 formed on the bottom electrode cup base 130 and a plurality of vertically extending insulator sidewalls 142 extending upward from the laterally extending insulator cup base 140, each vertically extending insulator sidewall 142 being formed on a corresponding bottom electrode cup base sidewall 132 (e.g., laterally adjacent to the corresponding bottom electrode cup base sidewall). As shown, the cup-shaped MIM insulator 124 may also include an insulator top flange 144 that extends laterally from each vertically extending insulator sidewall 142 and over the top (far end) 146 of the corresponding vertically extending bottom electrode cup sidewall 132.

[0040] The top electrode 122 of the MIM can be formed on the cup-shaped MIM insulator 124 with a second metal layer M x+1 In the middle, and extending downward into the internal volume 136 of the bottom electrode cup 128, such that the top electrode 122 of the MIM covers the insulator cup base 140 of the cup-shaped MIM insulator 124, a plurality of vertically extending insulator sidewalls 142 and insulator top flange 144.

[0041] As shown in the figure, a TFR layer region 148 may be formed between the bottom electrode cup 128 and the cup-shaped MIM insulator 124. The TFR layer region 148 may be formed from a material layer common to the TFR element 172 of the TFR 106, for example by depositing and patterning the TFR layer 171 to simultaneously define the TFR layer region 148 and the TFR element 172, as referenced below. Figure 6 and 7A to Figure 7B The TFR layer 171 discussed may contain, for example, SiCCr (silicon chromium carbide), SiCr (silicon chromium), TaN (tantalum nitride), NiCr (nickel chromium), AlNiCr (aluminum-doped nickel chromium), or TiNiCr (titanium nickel chromium).

[0042] The MIM capacitor 104 also includes a second metal layer M x+1 It is connected to the bottom electrode connection pad 160 of the bottom electrode plate 126 through at least one bottom plate contact through hole 162.

[0043] The MIM top electrode 122 is capacitively coupled to both the bottom electrode cup base 130 and the bottom electrode cup sidewall 132 of the bottom electrode cup 128 (which is conductively coupled to the bottom electrode plate 126). Compared to conventional designs, this defines a significantly larger capacitive coupling area between the MIM top electrode 122 and the MIM bottom electrode 120. Specifically, the MIM capacitor 104 defines the following capacitive coupling between the MIM top electrode 122 and the MIM bottom electrode 120:

[0044] (a) Capacitive coupling between the top electrode 122 and the bottom electrode 120 of the MIM via a displacement current path through the insulator cup base 140 and through the bottom electrode cup base 130, as indicated by arrow 150.

[0045] (b) Capacitive coupling between the MIM top electrode 122 and the MIM bottom electrode 120 via a displacement current path passing through each vertically extending insulator sidewall 142 and through the corresponding vertically extending bottom electrode cup sidewall 132, as indicated by arrow 152; and

[0046] (c) Capacitive coupling between the MIM top electrode 122 and the MIM bottom electrode 120 via a displacement current path passing through the top (far) end 146 of each insulator top flange 144 and through the corresponding bottom electrode cup sidewall 132, as indicated by arrow 154.

[0047] The laterally extending insulator cup base 140 effectively defines a parallel-plate capacitor, wherein the top and bottom plates extend horizontally (xy plane), and each vertically extending insulator sidewall 142 effectively defines an additional parallel-plate capacitor, wherein the top and bottom plates extend vertically (xz plane or yz plane). Therefore, the MIM capacitor 104 can be referred to as a "three-dimensional" or "3D" MIM capacitor. For example, compared to a conventional MIM capacitor, the MIM capacitor 104 defines a significantly increased capacitive coupling area between the MIM top electrode 122 and the MIM bottom electrode 120.

[0048] Now let's turn to TFR 106, which includes the first metal layer M. x A pair of TFR heads 170 formed therein and a TFR element 172 connected to each TFR head 170 via a TFR contact via 174 (or alternatively via a plurality of TFR contact vias 174). See below for reference. Figures 5A to 5B As discussed, each TFR contact via 174 can be formed as an elongated via, particularly elongated in the direction extending into the page, to provide a predictable and consistent contact area between each lateral end of the TFR element 172 and the corresponding TFR contact via 174.

[0049] A TFR insulator cap 176 may be formed on the TFR element 172 to protect the TFR element from damage during TFR formation. The TFR insulator cap 176 may be formed from a material layer common to the MIM insulator 124, for example by depositing, patterning, and etching the insulator layer 123 to simultaneously define the MIM insulator 124 and the TFR insulator cap 176, as referenced below. Figure 6 and Figures 7A to 7B As discussed, as shown in the figure, a second metal layer M can be formed on the TFR insulator cap 176, with the TFR metal cap 178 being a second metal layer M. x+1 middle.

[0050] As shown in the figure, the lower interconnect 110, the bottom electrode plate 126, and the pair of TFR heads 170 may each include components simultaneously formed in the first metal layer M. x For example, conductive elements 180 in a metal interconnect layer. A barrier layer 183 (e.g., SiN, SiC, or a low-k dielectric material) may be formed in the first metal layer M. xThe conductive element 180 may be a metal element comprising copper, aluminum, or other metals. For example, the conductive element 180 may include copper damascene elements, each formed on a barrier layer 182 (e.g., a tantalum / tantalum nitride (Ta / TaN) bilayer) in a corresponding trench. As another example, the conductive element 180 may be formed by depositing, patterning, and etching a metal layer (e.g., copper or aluminum). As another example, see the reference below. Figure 10 The first metal layer M discussed x It may be a polysilicon silicide layer, wherein each conductive element 180 (including a lower interconnect 110, a bottom electrode plate 126, and a TFR head 170) includes a metal silicide region formed on the corresponding polysilicon region.

[0051] Furthermore, the upper interconnect 112, the MIM top electrode 122, the bottom electrode connection pad 160, and the TFR metal cap 178 may each include components simultaneously formed in the second metal layer M. x+1 The conductive element 184 may comprise copper, aluminum, or other conductive metals. For example, the conductive element 184 may comprise an aluminum element formed in an aluminum bonding pad layer. As another example, the conductive element 184 may comprise a copper or aluminum element formed in an interconnect layer at any depth in the integrated circuit structure 100. A passivation layer 186 (e.g., comprising the deposition of a 1.1 μm thick silicon oxide film formed by a high-density plasma (HDP) chemical vapor deposition process, followed by the deposition of a 1 μm thick silicon oxynitride (SiON) film formed by a plasma-enhanced chemical vapor deposition (PECVD) process) may be formed over the conductive element 184 and etched to expose an upper interconnect 112, for example, wherein the upper interconnect 112 is formed as a bonding pad.

[0052] Furthermore, interconnect vias 114, bottom electrode cups 128, base contact vias 162, and TFR contact vias 174 can be simultaneously formed in an intermetallic dielectric (IMD) region 190 comprising, for example, silicon dioxide (SiO2) or, for example, a low-k dielectric material having a dielectric constant less than 3.6. For example, interconnect vias 114, bottom electrode cups 128, base contact vias 162, and TFR contact vias 174 can be formed by depositing a common via layer into various openings formed in the IMD region 190, as described below. Figures 5A to 5B The subject of discussion.

[0053] Figures 2 to 9 It shows the method for forming Figure 1The illustrated example process of an integrated circuit (IC) structure 100 includes an interconnect structure 102, a MIM capacitor 104, and a TFR 106. As discussed below, the interconnect structure 102, the MIM capacitor 104, and the TFR 106 may utilize a common layer (e.g., a metal layer M). x and metal layer M x+1 Simultaneously, components are formed to form interconnect structure 102, MIM capacitor 104 and TFR 106.

[0054] First, such as Figure 2 As shown, the conductive element 180 can be simultaneously formed in the metal layer M in the dielectric region 181. x In the middle. Conductive element 180 may define (a) the lower interconnect 110 of the interconnect structure 102 under construction, (b) the bottom electrode plate 126 of the MIM capacitor 104 under construction, and (c) a pair of TFR heads 170 of the TFR 106 under construction. Metal layer M x It may contain copper, aluminum, or other suitable metals. For some applications of integrated circuit structure 100, such as radio frequency (RF) devices, the metal layer M... x It is the top layer of copper interconnect, which may be desirable for building MIM capacitors 104 in the top metal layer (i.e., away from the silicon substrate of the wafer) to reduce noise.

[0055] Each conductive element 180 may be formed on a barrier layer 182 (e.g., a Ta / TaN bilayer) deposited in a corresponding trench opening. For example, the conductive element 180 may be a trench element formed by a Cu damascene process, in which the barrier layer 182, followed by Cu, is deposited on a dielectric region 181 and extends downward into a trench opening formed in the dielectric region 181, followed by a chemical mechanical planarization (CMP) process to remove excess Cu at the top of the structure. The dielectric region 181 may include one or more dielectric materials, such as silicon oxide, fluorosilicate glass (FSG), organosilicon glass (OSG), porous OSG, or at least one of other low-k dielectric materials, such as those having a dielectric constant less than 3.6.

[0056] For example, a dielectric barrier layer 183 containing SiN or SiC can be deposited after the CMP process, for example, to protect the exposed top surface of the metal structure 180 from oxidation or corrosion.

[0057] Next, as Figure 3A (Cross-section side view) and Figure 3BAs shown in the top view, an IMD region 190 may be deposited on the structure, followed by the deposition and patterning of a photoresist layer 200 on the IMD region 190. The IMD region 190 may include one or more dielectric materials, such as silicon oxide, FSG, OSG, porous OSG, or at least one of other low-k dielectric materials. The photoresist layer 200 may be deposited on the IMD region 190 and patterned to simultaneously define various mask openings 202a-202d, including interconnect via mask openings 202a, MIM barrel mask openings 202b, MIM contact via mask openings 202c, and a pair of TFR contact via mask openings 202d.

[0058] like Figure 3B As shown in the top view, the interconnect via mask opening 202a can have a circular or elliptical shape, the MIM barrel mask opening 202b can have a square or rectangular shape with rounded corners, the MIM contact via mask opening 202c can have a circular or elliptical shape, and the TFR contact via mask opening 202d can have an elongated shape with rounded corners. The circular shape or rounded corners of the mask openings 202a-202d can improve the breakdown voltage of the structure formed using the mask openings 202a-202d.

[0059] Next, as Figure 4A (Cross-section side view) and Figure 4B As shown in the top view, it can be accessed via... Figures 3A to 3B The mask openings 202a-202d shown are used to etch IMD regions 190 to simultaneously form corresponding IMD openings 206a-206d, including (a) an interconnect via opening 206a for forming interconnect vias 114, (b) a MIM barrel opening 206b for forming a bottom electrode cup 128, a cup-shaped MIM insulator 124, and a top MIM electrode 122, (c) a MIM contact via opening 206c for forming a base plate contact via 162, and (d) a pair of TFR contact via openings 206d for forming a TFR contact via 174. IMD openings 206a-206d can be formed using plasma etching or other suitable etching, followed by resist stripping or other suitable processes to remove any remaining portion of the photoresist layer 200. Figures 3A to 3B The shape and size of the mask openings 202a-202d shown can be designed to produce for Figures 4A to 4B The specified shape and size of the corresponding IMD openings 206a-206d are shown.

[0060] Regarding interconnect structure 102, interconnect via opening 206a can have a width (or diameter) W in the range of, for example, 0.1 μm to 0.5 μm. 通孔 Through-hole opening. Interconnect width W 通孔It can significantly affect the performance of IC devices that are still in the process of being manufactured.

[0061] Compared to the MIM capacitor 104, the MIM contact via opening 206c can be formed to have a width W MIM_接触 The through-hole opening. In some embodiments, the MIM contact through-hole opening 206c is formed to be identical to the interconnect through-hole opening 206a, and therefore has the same width W. 通孔 Conversely, the MIM barrel opening 206b may have a significantly larger width (x-direction) and / or length (y-direction) than the interconnect via opening 206a and the MIM contact via opening 206c. The shape and size of the MIM barrel opening 206b may be selected based on various parameters, such as those for efficiently manufacturing the MIM capacitor 104 (e.g., efficiently depositing top plate material (e.g., aluminum) into the MIM opening 206b) and / or for the desired performance characteristics of the resulting MIM capacitor 104. Figure 4B As shown, from a top view, the MIM barrel opening 206b may have a square or rectangular shape. In other embodiments, from a top view, the MIM barrel opening 206b may have a circular or elliptical shape.

[0062] As described above, the x-direction width W of the MIM barrel opening 206b MIM_桶 and / or length L in the y direction MIM_桶 It can be substantially larger than the width W of the through-hole opening 206a. 通孔 For example, in some implementations, the width W of the MIM barrel opening 206b MIM_桶 and / or length L MIM_桶 The width W of the through hole opening 206a 通孔 At least twice that. In a particular embodiment, the width W of the MIM barrel opening 206b is... MIM_桶 and / or length L MIM_桶 The width W of the through hole opening 206a 通孔 At least five times. In some implementations, the width W of the MIM barrel opening 206b is... MIM_桶 and length L MIM_桶 Each is within the range of 1μm-10μm.

[0063] Furthermore, the MIM barrel opening 206b can be formed to have a height-to-width ratio (H) of less than or equal to 2.0. MIM_桶 / W MIM_桶 and / or a height-to-length aspect ratio (H) less than or equal to 2. MIM_桶 / L MIM_桶 For example, to allow the MIM barrel opening 206b to be efficiently filled by a conformal material. For example, the MIM barrel opening 206b can be formed to have an aspect ratio H in the range of 0.1-2.0, for example, in the range of 0.5-2.0.MIM_桶 / W MIM_桶 and H MIM_桶 / L MIM_桶 In some implementations, the aspect ratio H MIM_桶 / W MIM_桶 and H MIM_桶 / L MIM_桶 Each is less than or equal to 1.5, for example, for effectively filling the MIM barrel opening 206b with a conformal material (e.g., aluminum). For example, the MIM barrel opening 206b can be formed to have an aspect ratio H in the range of 0.5-1.5, or more preferably in the range of 0.8-1.2. MIM_桶 / W MIM_桶 and H MIM_桶 / L MIM_桶 .

[0064] Compared to TFR 106, the TFR contact via opening 206d can be formed as an elongated or "slotted" via opening, which can be laterally elongated in the y-direction, such that the y-direction length L of each TFR contact via opening 206d is... TFR_接触 It is the width W in the x direction. TFR_接触 At least 2 times, at least 5 times, at least 10 times, at least 20 times, at least 50 times, or at least 100 times. In some embodiments, the TFR contact via opening 206d is formed as an elongated version of the interconnect via opening 206a, wherein the width W TFR_接触 Equal to the interconnect via width W 通孔 And length L TFR_接触 The interconnect via width W 通孔 At least 2 times, at least 5 times, at least 10 times, at least 20 times, at least 50 times, or at least 100 times. For example, each TFR contact via opening 206d can have a width W in the range of 0.1μm-0.5μm. TFR_接触 and length L in the range of 1μm-100μm TFR_接触 .

[0065] Next, as Figure 5A (Cross-section side view) and Figure 5B As shown in the top view, a via layer 210 comprising a conductive conformal material (e.g., W, TiN, or other conformal metal) is deposited on structure 100 and extends downward into each IMD opening 206a-206d. A CMP process is then performed to remove the upper portion of the via layer 210, including the portion deposited on top of the IMD region 190. The via layer 210 can be deposited by chemical vapor deposition (CVD) or other suitable deposition processes. Figure 5A and Figure 5B The structure after CMP is shown.

[0066] As shown in the figure, the deposited via layer 210 (a) fills the interconnect via opening 206a to form an interconnect via 114, (b) covers the inner surface of the MIM barrel opening 206b to form a bottom electrode cup 128 defining an internal volume 136, (c) fills the MIM contact via opening 206c to form a base plate contact via 162, and (d) fills the TFR contact via opening 206d to form a TFR contact via 174. As discussed above, the bottom electrode cup 128 includes four plurality of vertically extending bottom electrode cup sidewalls 132 extending upward from a laterally extending bottom electrode cup base 130.

[0067] Next, as Figure 6 As shown, the process can be continued by depositing a TFR layer 171, followed by depositing an insulating layer 123, and then depositing and patterning a photoresist layer to form a photomask 230. As shown, the TFR layer 171, the insulating layer 123, and the photomask 230 can each extend downward into the internal volume 136 of the bottom electrode cup 128.

[0068] TFR layer 171 may include, for example, having in Films of thickness within a certain range, including, for example, SiCCr, SiCr, TaN, NiCr, AlNiCr, or TiNiCr. Insulator layer 123 may include films having a thickness within a certain range. Within or approximately The thickness of SiN can serve as the MIM insulator for MIM capacitor 104, and also as the protective TFR cap for TFR 106, as described below. Figures 7A to 7B The above discussion. In other embodiments, the insulating layer 123 may comprise a high-k dielectric material, i.e., having a dielectric constant greater than 3.6, such as Al2O3, ZrO2, HfO2, ZrSiO2. x HfSiO x HfAlOx or Ta2O5 are deposited through atomic layer deposition (ALD) or other suitable deposition processes.

[0069] Next, as Figure 7A (Cross-section side view) and Figure 7B (Top view) Etching is performed to remove the insulating layer 123 and the underlying TFR layer 171 that were not covered by the photomask 230. Figure 6The portion of the photomask 230 (shown in the diagram) is protected, and the remaining portion can then be removed by resist stripping or other suitable removal process. The resulting portion of the TFR layer 171 defines the TFR element 172 of the TFR 106 and the TFR layer region 148 of the MIM capacitor 104. The resulting portion of the insulating layer 123 defines the cup-shaped MIM insulator 124 of the MIM capacitor 104 and the TFR insulator cap 176 on the TFR element 172. The MIM insulator 124 is cup-shaped and includes four vertically extending insulator sidewalls 142 extending upward from a laterally extending insulator cup base 140, and an insulator top flange 144 extending laterally from the top of each vertically extending insulator sidewall 142.

[0070] Next, as Figure 8 As shown, multiple conductive elements 184 can be simultaneously formed on the metal layer M. x+1 In the middle (i.e., by metal layer M) x+1 (partially defined), the metal layer is formed on the IMD region 190. The conductive element 184 may include the upper interconnect 112 of the interconnect structure 102, the MIM top electrode 122 and bottom electrode connection pad 160 of the MIM capacitor 104, and the TFR metal cap 178 formed on the TFR insulator cap 176 and the underlying TFR element 172.

[0071] To form the conductive element 184, a metal layer M, for example, comprising aluminum, copper, or other metals, is used. x+1 It is deposited on structure 100 and extends downward into the internal volume 136 of the bottom electrode cup 128. Then, the metal layer M can be... x+1 Patterning (e.g., using photoresist) and etching are performed to define conductive element 184, including upper interconnect 112, MIM top electrode 122, bottom electrode connection pad 160, and TFR metal cap 178. In other embodiments, the metal layer M... x+1 Interconnect layers (e.g., copper or aluminum interconnects) can be formed at any depth in the integrated circuit structure 100.

[0072] Next, as Figure 9 As shown, a passivation layer 186 can be formed on the conductive element 184, which is formed on the metal layer M. x+1 The passivation layer 186 can be formed as a multilayer deposition, for example comprising depositing a 1.1 μm thick silicon oxide film by a high-density plasma (HDP) chemical vapor deposition process, followed by depositing a 1 μm thick silicon oxynitride (SiON) film by a plasma-enhanced chemical vapor deposition (PECVD) process. The passivation layer 186 can then be patterned and etched to expose the upper interconnect 112, for example in an embodiment where the upper interconnect 112 acts as a bonding pad.

[0073] As discussed above, IC structure 100 can be implemented in any two metal layers M x and M x+1 (each comprising copper, aluminum, or other metals) are formed between, wherein a first conductive element 180, a MIM capacitor 104, and a TFR 106, which define the first component of the interconnect structure 102, are formed on the metal layer M. x In the middle, and defining the second component of the interconnect structure 102, the second conductive element 184, the MIM capacitor 104, and the TFR 106 are formed on the metal layer M. x+1 In the discussion above. Figures 1 to 9 In the example shown, metal layer M x The conductive element 180 can be formed by an inlay process (e.g., to form a copper inlay element). As another example, the metal layer M x The conductive element 180 can be formed by depositing, patterning, and etching a metal layer, such as one containing copper or aluminum. As another example, see the reference below. Figure 10 The metal layer M discussed x It may be a polysilicon silicide layer, wherein each conductive element 180 (including interconnect element 110, bottom electrode plate 126 and TFR head 170) includes a metal silicide region formed on the corresponding polysilicon region.

[0074] Figure 10 This diagram shows a cross-sectional side view of an exemplary IC structure 100', similar to the exemplary IC structure 100 discussed above, according to an exemplary embodiment, and wherein the lower metal layer M... x This includes a polysilicon silicide layer. The IC structure 100' includes an interconnect structure 102', a MIM capacitor 104', and a TFR 106', which can be similar to the interconnect structure 102, MIM capacitor 104, and TFR 106 of the IC structure 100 discussed above, except that they are formed on the lower metal layer M... x The conductive element 180' is constructed including a lower interconnect 110', a bottom electrode plate 126', and a TFR head 170'. Specifically, the conductive element 180' can be formed by depositing, patterning, and etching a polysilicon layer to define discrete polysilicon elements 250a-250c, followed by forming conductive silicide regions 252a-252c on each respective polysilicon element 250a-250c, for example, by a self-aligned self-aligned silicide process. Titanium silicide, cobalt silicide, or nickel silicide are within the range. As shown, the lower interconnect 110' is defined by a polysilicon element 250a having a conductive silicide region 252a, the bottom electrode plate 126' is defined by a polysilicon element 250b having a conductive silicide region 252b, and each TFR head 170' is defined by a corresponding polysilicon element 250c having a conductive silicide region 252c.

[0075] Although the metal silicide regions 252a-252c may be very thin compared to the underlying polysilicon elements 250a-250c, for the purposes of this disclosure, the silicided polysilicon layer (including the lower interconnect 110', the bottom electrode plate 126', and the TFR head 170') defines the lower metal layer M. x In this exemplary embodiment, the silicided polycrystalline silicon layer M x It can be limited to the first metal interconnect layer M1 (where M x+1 The layer M0 below (where x = 0) is usually called the metal-1 layer.

Claims

1. An integrated circuit structure, the integrated circuit structure comprising: (a) A metal-insulator-metal (MIM) capacitor, the MIM capacitor comprising: MIM bottom electrode, the MIM bottom electrode comprising: Bottom electrode plate, the bottom electrode plate being formed in a first metal layer; and The bottom electrode cup includes a laterally extending bottom electrode cup base and a plurality of vertically extending bottom electrode cup sidewalls extending upward from the bottom electrode cup base; The bottom plate has a contact through hole, which is separated from the bottom electrode cup and laterally separated from the bottom electrode cup; MIM top electrode, the MIM top electrode being formed in a second metal layer above the first metal layer; and A bottom electrode connection pad, wherein the bottom electrode connection pad is electrically connected to the bottom electrode plate via a contact through-hole in the base plate; and MIM insulator, the MIM insulator comprising: An insulator base, the insulator base being disposed between the top electrode and the bottom electrode cup base of the MIM; and Multiple vertically extending insulator sidewalls, each insulator sidewall disposed between the top electrode and the corresponding bottom electrode cup sidewall of the MIM; and (b) A thin-film resistor (TFR), the TFR comprising: A pair of TFR heads, the pair of TFR heads being formed in the first metal layer; and TFR element, the TFR element being connected to the pair of TFR heads through a corresponding TFR contact through hole in a pair of TFR contact through holes; The bottom electrode cup, the bottom plate contact via, and the pair of TFR contact vias comprise portions of the conformal metal layer.

2. The integrated circuit structure according to claim 1, wherein the MIM insulator is cup-shaped.

3. The integrated circuit structure according to claim 1, wherein the TFR contact via and the vertically extending bottom electrode cup sidewall are formed in the dielectric region between the first metal layer and the second metal layer.

4. The integrated circuit structure according to claim 1, wherein: The TFR includes a TFR insulating cap formed on the TFR element; and The TFR insulator cap and the MIM insulator are formed in the insulator layer.

5. The integrated circuit structure according to claim 1, further comprising an interconnect structure, the interconnect structure comprising: Lower interconnects are formed in the first metal layer; as well as An upper interconnect line is formed in the second metal layer and connected to the lower interconnect line through at least one interconnect via.

6. The integrated circuit structure of claim 1, wherein a corresponding TFR contact via in the pair of TFR contact vias has a width in a first lateral direction and a length in a second lateral direction, the length in the second lateral direction being at least 5 times the width in the first lateral direction.

7. The integrated circuit structure of claim 1, wherein the first metal layer is an interconnect layer comprising copper or aluminum, and the second metal layer comprises aluminum.

8. The integrated circuit structure according to claim 1, wherein the first metal layer comprises a polysilicon silicide layer, the polysilicon silicide layer comprising a metal silicide region formed on each of a plurality of polysilicon regions.

9. An integrated circuit structure, the integrated circuit structure comprising: Interconnection structure, the interconnection structure comprising: Lower interconnects; Upper interconnect line, the upper interconnect line being connected to the lower interconnect line; and At least one interconnect via, the at least one interconnect via being connected between the lower interconnect and the upper interconnect; Metal-insulator-metal (MIM) capacitors, wherein the MIM capacitors include: Bottom electrode plate; A bottom electrode cup, the bottom electrode cup being formed on the bottom electrode plate; MIM top electrode; and A MIM insulator, the MIM insulator being disposed between the top electrode and the bottom electrode cup of the MIM; and Thin-film resistors (TFRs), the TFRs comprising: A pair of TFR heads; TFR elements connected to the pair of TFR heads; and A pair of TFR contact through holes, the pair of TFR contact through holes being connected between the pair of TFR heads and the TFR element; The lower interconnect, the bottom electrode plate, and the pair of TFR heads are formed in the first metal layer; The at least one interconnect via, the bottom electrode cup, and the pair of TFR contact vias are formed of a conformal metal layer; and The upper interconnect and the top electrode of the MIM are formed in a second metal layer above the first metal layer.

10. The integrated circuit structure of claim 9, wherein the MIM capacitor further comprises a bottom electrode connection pad formed in the second metal layer and connected to the bottom electrode plate through a bottom plate contact via.

11. The integrated circuit structure according to claim 9, wherein: The bottom electrode cup includes: A laterally extending bottom electrode cup base formed on the bottom electrode plate; and Multiple vertically extending bottom electrode cup sidewalls; The MIM insulator and the MIM top electrode are located at least partially within the internal volume of the bottom electrode cup.

12. The integrated circuit structure of claim 9, wherein the first metal layer is an interconnect layer comprising copper or aluminum, and the second metal layer comprises aluminum.

13. The integrated circuit structure of claim 9, wherein the first metal layer comprises a polysilicon silicide layer, the polysilicon silicide layer comprising a metal silicide region formed on each of a plurality of polysilicon regions.

14. A method for forming an integrated circuit structure comprising a metal-insulator-metal (MIM) capacitor and a thin-film resistor (TFR), the method comprising: A plurality of first conductive elements are formed in a first metal layer, the plurality of first conductive elements comprising: MIM bottom electrode plate; and First TFR head and second TFR head; A bottom electrode cup of the MIM is formed on the bottom electrode plate of the MIM; A first TFR contact via is formed that is electrically connected to the first TFR head and a second TFR contact via is electrically connected to the second TFR head; The MIM bottom electrode cup, the first TFR contact through hole, and the second TFR contact through hole are formed simultaneously. A TFR element is formed that is electrically connected to the first TFR head through the first TFR contact via and electrically connected to the second TFR head through the second TFR contact via; An insulating layer is formed over the first metal layer to define: The cup-shaped MIM insulator above the bottom electrode cup of the MIM; and The TFR insulating cap on the TFR element; and A plurality of second conductive elements are formed in a second metal layer above the first metal layer, the plurality of second conductive elements including a top electrode of the MIM above the cup-shaped MIM insulator; The MIM insulator is formed between the bottom electrode plate of the MIM and the top electrode of the MIM.

15. The method of claim 14, wherein the MIM bottom electrode cup comprises a bottom electrode cup base and a plurality of vertically extending bottom electrode cup sidewalls extending upward from the bottom electrode cup base; and The MIM insulator includes a plurality of vertically extending insulator sidewalls, each vertically extending insulator sidewall being formed adjacent to a corresponding vertically extending MIM bottom electrode sidewall.

16. The method of claim 14, further comprising, after forming the plurality of first conductive elements in the first metal layer and before forming the TFR elements, simultaneously forming at least one MIM base plate contact via with the MIM bottom electrode cup, the first TFR contact via, and the second TFR contact via; and The plurality of second conductive elements include bottom electrode connection pads connected to the bottom electrode plate of the MIM by at least one MIM base plate contact through hole.

17. The method of claim 14, wherein the MIM bottom electrode cup comprises: Laterally extending bottom electrode cup base; as well as Multiple vertically extending bottom electrode cup sidewalls; The cup-shaped MIM insulator and the top electrode of the MIM are at least partially formed within the internal volume of the bottom electrode cup of the MIM.

18. The method of claim 14, wherein: The plurality of first conductive elements further includes lower interconnect lines; and The plurality of second conductive elements also include an upper interconnect line connected to the lower interconnect line via at least one interconnect via.

19. The method of claim 14, wherein: Forming the TFR element includes forming and patterning a TFR layer to form: (a) The TFR element; as well as (b) The TFR layer region above the bottom electrode cup of the MIM; and The MIM insulator is formed above the TFR layer region.

20. The method of claim 14, comprising: A TFR layer is formed extending above the bottom electrode cup of the MIM and above the first and second TFR contact vias; An insulating layer is formed on top of the TFR layer; as well as Pattern and etch the TFR layer and insulating layer to define: The TFR element; The cup-shaped MIM insulator; as well as The TFR insulating cap above the TFR element.

21. The method of claim 14, comprising: A TFR layer is formed extending above the bottom electrode cup of the MIM and above the first and second TFR contact vias; An insulating layer is formed on top of the TFR layer; as well as Pattern and etch the TFR layer and the insulating layer to define: The first remaining portion of the TFR layer defines the TFR element; The second remaining portion of the TFR layer defines a TFR layer region above the bottom electrode cup of the MIM; The first remaining portion of the insulating layer defines the TFR insulator cap above the TFR element; as well as The second remaining portion of the insulating layer defines the cup-shaped MIM insulator, wherein the TFR layer region is located between the bottom electrode cup of the MIM and the cup-shaped MIM insulator.

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