A method for preparing TEM samples

Abstract

This invention provides a method for preparing TEM samples, applicable to the field of semiconductor technology. Specifically, the sample preparation method provided by this invention combines laser marking, I-beam bombardment, and a resist remover to address the problem in existing technologies where laser marking for coated samples can only achieve coarse positioning, failing to provide accurate or highly accurate positioning. In other words, this invention ultimately improves the accuracy and efficiency of failure analysis of semiconductor structures.

Description

Technical Field

[0001] This invention relates to the field of semiconductor chip failure analysis technology, and in particular to a method for preparing TEM samples and an electronic device thereof. Background Technology

[0002] When performing failure analysis, especially TEM sample structure analysis, it is usually necessary to prepare the target location for analysis using FIB. However, since the sample is bombarded by a high-voltage ion beam during FIB preparation, if the FIB sample is not protected in advance, it will cause a certain degree of damage to the target location to be analyzed. Therefore, various protection methods are required before FIB preparation.

[0003] Currently, common protection methods before FIB sample preparation include: protective layer deposition under E-beam (E-beamdep), direct application of a marker pen, and adhesive coating. Adhesive coating is particularly common when preparing FIB samples with low-k or PR-type materials or easily deformable target structural patterns. However, it has significant drawbacks: the coated sample cannot be accurately positioned within the FIB apparatus, especially in critical and singular analytical locations with small discrepancies (CD). Summary of the Invention

[0004] The purpose of this invention is to provide a method for preparing TEM samples to solve the problem in the prior art that when preparing TEM samples with low-k dielectric materials or easily deformable semiconductor structures, a protective adhesive layer is usually required. However, the TEM samples with the protective adhesive layer cannot be accurately positioned inside the FIB instrument, which leads to the inability to accurately perform failure analysis on the semiconductor chip.

[0005] In a first aspect, to solve the above-mentioned technical problems, the present invention provides a method for preparing a TEM sample, which may specifically include the following steps:

[0006] A semiconductor structure with a target location is provided, and a photoresist layer is formed on the surface of the semiconductor structure;

[0007] At least two first marks are formed on a photoresist layer in a portion of the area outside the target location using a laser;

[0008] A protective layer is formed under I-beam, which covers the surface of the photoresist layer corresponding to the target location and extends to cover the sidewalls of the exposed semiconductor structure corresponding to the target location.

[0009] The semiconductor structure is subjected to a photoresist removal process to expose the semiconductor structure outside the target location while retaining the protective layer and photoresist layer formed at the target location.

[0010] The target positions in the semiconductor structure after resist removal are precisely located and TEM samples are prepared.

[0011] Furthermore, the two first marks can be located on the photoresist layer of the outer regions corresponding to the two sides of the target location.

[0012] Furthermore, the protective layer may include a first protective layer and a second protective layer;

[0013] Specifically, the step of forming a protective layer under I-beam may include:

[0014] A first protective layer is formed on the surface of the photoresist layer corresponding to the target location;

[0015] The semiconductor structures corresponding to the front and rear sides of the target location are bombarded under I-beam to form two grooves in the semiconductor structure that expose the sidewalls of the semiconductor structure corresponding to the target location.

[0016] A second protective layer is formed in the two grooves, covering the sidewall of the semiconductor structure corresponding to the exposed target location.

[0017] Furthermore, the materials of the first protective layer and / or the second protective layer may contain carbon.

[0018] Furthermore, the solvent used to remove the adhesive from the semiconductor structure can be an organic solvent, which may include alcohol, styrene, or perchloroethylene.

[0019] Furthermore, the step of precisely locating the target position in the semiconductor structure after the resist removal process may include:

[0020] The semiconductor structure after resist removal is placed in a FIB machine, and at least one second mark is formed on the surrounding structure of the exposed target location using I-beam; further, the exact location of the target location is determined based on the second mark.

[0021] Furthermore, prior to the step of forming a photoresist layer on the surface of the semiconductor structure, the fabrication method may further include: a step of finding a rough location of the target location on the semiconductor structure based on layout design data.

[0022] Furthermore, prior to the step of forming a photoresist layer on the surface of the semiconductor structure, the fabrication method may further include the step of using an optical microscope to locate the approximate position of the target location on the semiconductor structure.

[0023] Furthermore, the semiconductor structure corresponding to the target location may include a material with a dielectric constant K < 3.

[0024] Secondly, based on the same inventive concept as the method for fabricating the TEM sample, the present invention also provides an electronic device, which may specifically include a processor, a communication interface, a memory, and a communication bus, wherein the processor, the communication interface, and the memory communicate with each other through the communication bus.

[0025] Memory, used to store computer programs;

[0026] The processor, when executing a program stored in memory, implements the steps of the method for preparing a TEM sample as described in any of the first aspects.

[0027] Thirdly, based on the same inventive concept as the method for preparing the TEM sample, the present invention also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps of the method for preparing the TEM sample as described in any of the first aspects.

[0028] Fourthly, based on the same inventive concept as the method for fabricating the TEM sample, the present invention also provides a computer program product containing instructions that, when run on a computer, cause the computer to execute the method for fabricating the TEM sample as described in any of the first aspects above.

[0029] Compared with the prior art, the technical solution of the present invention has at least one of the following beneficial effects:

[0030] The TEM sample fabrication method provided by this invention is mainly applied in the process of TEM sample preparation at a target location in a semiconductor structure with a photoresist layer formed on the surface as a protective layer. Specifically, after the photoresist layer is formed, at least two first marks (laser marks) are first formed on the area corresponding to the non-target location on the photoresist layer to coarsely locate the target location. Then, a protective layer is formed on the surface of the semiconductor structure corresponding to the target location and its two sidewalls under I-beam to protect the semiconductor structure corresponding to the target location to be TEM sampled. Then, the protective layer and photoresist layer formed on the area corresponding to the target location are removed using a solvent that cannot dissolve the protective layer formed above, thereby exposing the surface of the semiconductor structure other than the target location. Finally, the target location is accurately located using FIB marks to form the TEM sample at the target location.

[0031] Obviously, the sample preparation method provided by this invention is a method that combines laser marking, I-beam bombardment and adhesive removal solvent to solve the problem that the existing technology of laser marking for positioning of coated samples can only achieve coarse positioning and cannot accurately position or has low positioning accuracy. In other words, the preparation method of this invention ultimately improves the accuracy and efficiency of failure analysis of semiconductor structures. Attached Figure Description

[0032] Figure 1 This is a schematic flowchart of a method for preparing a TEM sample according to an embodiment of the present invention;

[0033] Figure 2 This is a TEM image of a semiconductor structure containing a target location (target region) provided in one embodiment of the present invention;

[0034] Figure 3 This is an embodiment of the invention that utilizes the present invention. Figure 1 The method shown forms a TEM image of the first laser mark on the surface of the photoresist layer;

[0035] Figure 4 This is an embodiment of the invention that utilizes the present invention. Figure 1 The method shown is illustrated in the TEM image of forming a first protective layer 110a and grooves 101 on the front and back sides of the target area (target location);

[0036] Figure 5 This is an embodiment of the invention that utilizes the invention. Figure 1The method shown is used to form a second protective layer 110b on the sidewall of the semiconductor structure corresponding to the exposed target locations of the two grooves 101. TEM image;

[0037] Figure 6 This is an embodiment of the invention that utilizes the invention. Figure 1 The method shown is a TEM image of the protective layer and photoresist layer formed in a portion of the area outside the target region (target location);

[0038] Figure 7 This is an embodiment of the invention that utilizes the invention. Figure 1 The method shown is illustrated in the TEM image of a second mark (FIB Mark) formed on the exposed semiconductor structure after the protective layer and photoresist layer are formed in a certain area;

[0039] Figure 8 This is a TEM image of a TEM sample formed after TEM preparation of a target area (target location) according to an embodiment of the present invention. Detailed Implementation

[0040] The method for preparing TEM samples according to the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention. Many specific details are set forth in the following description to provide a thorough understanding of the present invention; however, the present invention may be implemented in other ways different from those described herein, and therefore the present invention is not limited to the specific embodiments disclosed below.

[0041] As shown in this application and claims, unless the context clearly indicates otherwise, the words "a," "an," "an," and / or "the" do not specifically refer to the singular and may also include the plural. Generally speaking, the terms "comprising" and "including" only indicate the inclusion of explicitly identified steps and elements, which do not constitute an exclusive list, and the method or apparatus may also include other steps or elements. In detailing the embodiments of the present invention, for ease of explanation, the cross-sectional views showing the device structure may be partially enlarged without adhering to the general scale, and the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. Furthermore, in actual manufacturing, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0042] As described in the background section, common protection methods before FIB sample preparation include: protective layer deposition under E-beam (E-beamdep), direct application of a marker pen, and protective coating. However, the E-beamdep method is only suitable for preparing conventional samples to avoid ion beam damage to the FIB sample surface; that is, protective layer deposition under E-beam will not cause damage to the target location or deviation in the CD or morphology of the areas to be analyzed.

[0043] The direct marking pen is suitable for use when directly depositing a protective layer inside the FIB instrument would damage the FIB sample structure, or when directly depositing a protective layer inside the FIB instrument takes a long time or cannot effectively protect the pattern. Its disadvantage is that there is a certain risk of damaging the structural pattern of the FIB sample when applying the marking pen, or the coating is too thick and the target position cannot be located under FIB and optical microscope OM.

[0044] The aforementioned adhesive coating protection method is a common sample preparation method used when preparing FIB samples with low-k or PR-type materials or easily deformable target structure patterns. However, it also has significant drawbacks. Specifically, the sample preparation location cannot be accurately positioned inside the FIB instrument after adhesive coating, especially for important and singular analysis locations and locations with small CD values. In other words, in the existing technology, the adhesive coating protection method used in the sample preparation process for preparing FIB samples with low-k or PR-type materials or easily deformable target structure patterns only uses laser marking and optical microscopes (OM) for rough positioning, and cannot accurately locate the target position. This leads to problems such as incomplete target positions in the TEM samples formed using existing technology.

[0045] Therefore, the purpose of this invention is to provide a method for preparing TEM samples to solve the problem in the prior art that when preparing TEM samples with low-k dielectric materials or easily deformable semiconductor structures, a protective adhesive layer is usually required. However, the TEM samples with the protective adhesive layer cannot be accurately positioned inside the FIB instrument, which leads to the inability to accurately perform failure analysis on the semiconductor chip.

[0046] See Figure 1 , Figure 1 The following is a flowchart illustrating a method for preparing a TEM sample according to the present invention. Figure 1 As shown, the manufacturing method provided by this invention may include the following steps:

[0047] Step S100: Provide a semiconductor structure with a target location, and form a photoresist layer on the surface of the semiconductor structure.

[0048] Step S200: Use a laser to form at least two first marks on a photoresist layer in a portion of the area outside the target location.

[0049] Step S300: A protective layer is formed under the I-beam, the protective layer covering the surface of the photoresist layer corresponding to the target location and extending to cover the sidewall of the exposed semiconductor structure corresponding to the target location.

[0050] Step S400: Perform a photoresist removal process on the semiconductor structure to expose the semiconductor structure outside the target location while retaining the protective layer and photoresist layer formed at the target location.

[0051] Step S500: The target position in the semiconductor structure after the resist removal process is precisely located and a TEM sample is prepared.

[0052] See Figure 2 In step S100 above, when performing failure analysis on a semiconductor structure, a planar sample corresponding to the semiconductor structure is typically fabricated first. Then, a TEM image of the planar sample is taken to observe the failure point at a specific location within the semiconductor structure. Next, the planar sample is further processed using a planar-to-section technique to obtain cross-sectional samples of each failure point at the target location of the semiconductor structure, allowing for further failure analysis. The semiconductor structure to be analyzed can be formed on a semiconductor substrate, such as silicon, germanium, silicon germanium, silicon carbide, silicon germanium carbide, indium arsenide, gallium arsenide, indium phosphide, or other III / V compound semiconductors, or silicon-on-insulator, silicon-on-insulator stacked on silicon, silicon-on-insulator stacked on silicon germanide, silicon-on-insulator, and germanium-on-insulator, etc.

[0053] For example, in this embodiment, the region within the semiconductor structure to be sampled is referred to as the target location, such as... Figure 2 The area enclosed by the box in the middle.

[0054] It should be noted that the sample preparation method provided by this invention can be specifically used to analyze the morphology of a specific location (target location or target region) of a 14nm sample and to perform related dimensional verification and measurement. However, due to the involvement of low-k material and the presence of easily deformable structures, a special sample preparation method with adhesive coating is required. For example, the low-k material in the semiconductor structure corresponding to the target location can be a material with a dielectric constant K < 3.

[0055] See Figure 3In step S200 above, after obtaining the semiconductor structure containing the target location to be sampled, the target location can be found on the semiconductor structure according to the handbook. Then, a photoresist layer of a certain thickness is coated on the surface of the semiconductor structure using a laser. The material of the photoresist layer is not limited. Then, the approximate location of the target location (target area) on the semiconductor structure is roughly confirmed in the presence of the photoresist layer using an optical microscope (OM). After that, multiple first marks (lasermarks) are formed to coarsely locate the target location (target area).

[0056] It should be noted that, in the present invention provided Figures 2-8 In this context, the target area and the target location refer to the same area, namely the area corresponding to the semiconductor structure to be sampled for TEM.

[0057] As an example, such as Figure 3 As shown, two first laser marks can be formed on the photoresist layer, i.e., as shown... Figure 3 The image shows two elongated laser marks, and the two first marks are respectively located on the photoresist layer of the outer regions corresponding to the two sides of the target location (target region).

[0058] It is understood that, in other embodiments, after obtaining the semiconductor structure containing the target location to be sampled, the approximate location of the target location can be found directly on the semiconductor structure based on the layout design data, or the approximate location of the target location (target area) can be found directly on the semiconductor structure using an optical microscope.

[0059] See Figure 4 and Figure 5 In step S300 above, a first protective layer 110a can be formed on the surface of the photoresist layer corresponding to the target location (target area); the semiconductor structure corresponding to the front and rear sides of the target location is bombarded under I-beam to form two grooves 101 exposing the sidewalls of the semiconductor structure corresponding to the target location within the semiconductor structure; a second protective layer 110b is formed in the two grooves 101, covering the exposed sidewalls of the semiconductor structure corresponding to the target location, to prevent damage to the semiconductor structure corresponding to the target location during the partial photoresist removal process using organic solvent in the subsequent step S400. The materials of the first protective layer 110a and / or the second protective layer 110b contain carbon.

[0060] See Figures 6-8 In step S400 above, an organic solvent, such as alcohol, styrene, or perchloroethylene, can be used to treat the semiconductor structure to remove the protective layer and photoresist layer formed on other areas of the semiconductor structure besides the target location (or target region), thereby exposing the surface of the semiconductor structure other than the semiconductor structure corresponding to the target region in step S100. Figure 6 As shown, proceed to the subsequent step S500, as follows. Figure 7 As shown, a FIBMark (second mark) is formed on it to accurately locate the target area, such as... Figure 8 As shown, TEM sample preparation was then performed.

[0061] In the sample preparation method provided by the present invention, since a protective layer material containing carbon elements (i.e., a first protective layer 110a and a second protective layer 110b) is used to cover and protect the surface and sides of the target area (target location) to be sampled, when the protective layer and photoresist layer in other areas are removed by organic solvent, the protective layer material will not undergo a dissolution reaction during the dissolution process of the organic solvent, thereby protecting the semiconductor structure corresponding to the target location.

[0062] Furthermore, the present invention provides a specific implementation step for precisely locating a target position in the semiconductor structure after resist removal, including:

[0063] The semiconductor structure after resist removal is placed in a FIB machine, and at least one second mark (FIBMark) is formed on the surrounding structure of the exposed target location using I-beam; further, the exact location of the target location is determined based on the second mark.

[0064] In summary, the TEM sample fabrication method provided by this invention is mainly applied in the TEM sample preparation process of a target location in a semiconductor structure with a photoresist layer formed on its surface as a protective layer. Specifically, after the photoresist layer is formed, at least two first marks (laser marks) are first formed on the area corresponding to the non-target location on the photoresist layer to coarsely locate the target location. Then, a protective layer is formed on the surface of the semiconductor structure corresponding to the target location and its two sidewalls under I-beam to protect the semiconductor structure corresponding to the target location to be TEM sampled. Then, the protective layer and photoresist layer formed on the area corresponding to the target location are removed using a solvent that cannot dissolve the protective layer formed above, thus exposing the surface of the semiconductor structure other than the target location. Finally, the target location is accurately located using FIB marks to form the TEM sample at the target location.

[0065] Obviously, the sample preparation method provided by this invention is a method that combines laser marking, I-beam bombardment and adhesive removal solvent to solve the problem that the existing technology of laser marking for positioning of coated samples can only achieve coarse positioning and cannot accurately position or has low positioning accuracy. In other words, the preparation method of this invention ultimately improves the accuracy and efficiency of failure analysis of semiconductor structures.

[0066] This invention also provides an electronic device, including a processor, a communication interface, a memory, and a communication bus, wherein the processor, the communication interface, and the memory communicate with each other via the communication bus.

[0067] Memory, used to store computer programs;

[0068] When the processor executes the program stored in the memory, it implements the steps described in the embodiments of the above-described method for preparing TEM samples.

[0069] For details on the implementation of each step of this method and related explanations, please refer to the above. Figures 1 to 8 The method embodiments shown are not described in detail here.

[0070] In addition, other implementations of the application setup method implemented by the processor executing the program stored in the memory are the same as those mentioned in the aforementioned method embodiment section, and will not be repeated here.

[0071] The communication bus of the aforementioned user terminal can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. This communication bus can be divided into address bus, data bus, control bus, etc. For ease of illustration, only one thick line is used to represent it in the figure, but this does not indicate that there is only one bus or one type of bus.

[0072] The communication interface is used for communication between the aforementioned user terminal and other devices.

[0073] The memory may include random access memory (RAM) or non-volatile memory, such as at least one disk storage device. Optionally, the memory may also be at least one storage device located remotely from the aforementioned processor.

[0074] The processors mentioned above can be general-purpose processors, including central processing units (CPUs), network processors (NPs), etc.; they can also be digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components.

[0075] In another embodiment of the present invention, a computer-readable storage medium is provided, wherein a computer program is stored therein, and when the computer program is executed by a processor, the steps of the above-described method for preparing a TEM sample are implemented.

[0076] In another embodiment of the present invention, the present invention also provides a computer program product containing instructions that, when run on a computer, causes the computer to execute the above-described method for preparing a TEM sample.

[0077] In the above embodiments, implementation can be achieved entirely or partially through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented entirely or partially in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of the present invention are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid-state disk (SSD)).

[0078] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0079] The various embodiments in this specification are described in a related manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the embodiments for apparatus, user terminals, computer-readable storage media, and computer program products are basically similar to the method embodiments, and therefore the descriptions are relatively simple; relevant parts can be referred to the descriptions of the method embodiments.

[0080] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention are included within the scope of protection of the present invention.

Claims

1. A method for preparing a TEM sample, characterized in that, It should include at least the following steps: A semiconductor structure with a target location is provided, and a photoresist layer is formed on the surface of the semiconductor structure; At least two first marks are formed on a photoresist layer in a portion of the area outside the target location using a laser; A protective layer is formed under I-beam, which covers the surface of the photoresist layer corresponding to the target location and extends to cover the sidewalls of the exposed semiconductor structure corresponding to the target location. The semiconductor structure is subjected to a photoresist removal process to expose the semiconductor structure outside the target location while retaining the protective layer and photoresist layer formed at the target location. The target positions in the semiconductor structure after the resist removal process are precisely located and TEM samples are prepared. The protective layer includes a first protective layer and a second protective layer; The step of forming a protective layer under I-beam includes: A first protective layer is formed on the surface of the photoresist layer corresponding to the target location; The semiconductor structures corresponding to the front and rear sides of the target location are bombarded under I-beam to form two grooves in the semiconductor structure that expose the sidewalls of the semiconductor structure corresponding to the target location. A second protective layer is formed in the two grooves, covering the sidewall of the semiconductor structure corresponding to the exposed target location.

2. The method for preparing a TEM sample as described in claim 1, characterized in that, The two first marks are respectively located on the photoresist layer of the outer regions corresponding to the two sides of the target position.

3. The method for preparing a TEM sample as described in claim 1, characterized in that, The material of the first protective layer and / or the second protective layer contains carbon.

4. The method for preparing a TEM sample as described in claim 1, characterized in that, The solvent used to remove the adhesive from the semiconductor structure is an organic solvent, including alcohol, styrene, or perchloroethylene.

5. The method for preparing a TEM sample as described in claim 1, characterized in that, The step of precisely locating the target position in the semiconductor structure after resist removal includes: The semiconductor structure after resist removal is placed in an FIB machine, and at least one second mark is formed on the surrounding structure of the exposed target location using I-beam; further, the exact location of the target location is determined based on the second mark.

6. The method for preparing a TEM sample as described in claim 1, characterized in that, Prior to the step of forming a photoresist layer on the surface of the semiconductor structure, the fabrication method further includes: finding a rough location of the target location on the semiconductor structure based on layout design data.

7. The method for preparing a TEM sample as described in claim 1, characterized in that, Prior to the step of forming a photoresist layer on the surface of the semiconductor structure, the fabrication method further includes: using an optical microscope to locate the approximate position of the target location on the semiconductor structure.

8. The method for preparing a TEM sample as described in claim 1, characterized in that, The semiconductor structure corresponding to the target location includes a material with a dielectric constant K < 3.

9. An electronic device, characterized in that, It includes a processor, a communication interface, a memory, and a communication bus, wherein the processor, the communication interface, and the memory communicate with each other through the communication bus; Memory, used to store computer programs; A processor, when executing a program stored in a memory, implements the method steps of the method for preparing a TEM sample according to any one of claims 1 to 8.

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