A UVLO circuit and voltage generation method overcoming temperature effects

Abstract

The application discloses a UVLO circuit capable of overcoming temperature influence, characterized in that the circuit comprises a bias unit, a reference voltage generating unit and a comparison unit; wherein the bias unit is connected with the comparison unit, used for generating a bias current and mirroring the bias current into the comparison unit; the reference voltage generating unit is connected with the comparison unit, used for generating a reference voltage and outputting the reference voltage into the comparison unit; and the comparison unit is used for receiving the bias current and the reference voltage, generating a comparison voltage based on the bias current, realizing comparison in the same temperature direction with the reference voltage, and generating a UVLO voltage. The application has the advantages of simple method, simple circuit, few components, small power consumption, small area, fast response, and sufficient realization of comparison under zero temperature coefficient condition and accurate UVLO output.

Description

Technical Field

[0001] This invention relates to the field of integrated circuits, and more specifically, to a UVLO circuit and a UVLO voltage generation method that overcomes the effects of temperature. Background Technology

[0002] UVLO (Under Voltage Lock Out) circuits protect circuits when the supply voltage falls below the turn-on threshold voltage of the chip or integrated circuit. Undervoltage lockout ensures that the chip is not damaged due to logic errors in subsequent circuits caused by insufficient supply voltage during soft-start or other situations, and is therefore widely used in various integrated circuits.

[0003] Existing UVLO circuits are typically complex in structure. They generally require a bandgap reference circuit to first generate a reference voltage, then simultaneously inputting this reference voltage and a voltage divider from the power supply into a five-transistor comparator to compare the power supply voltage with the reference voltage. Undervoltage lockout functionality is only achieved when the power supply voltage is less than the reference voltage. The five-transistor comparator mentioned here refers to a comparator composed of at least five MOSFETs. Because this comparator can compare the reference voltage and the power supply voltage at zero temperature coefficient, the output result is highly accurate.

[0004] However, this precise output comes at the cost of complex circuit structure, high power consumption, and large chip area.

[0005] To address this problem, there is an urgent need for a simple circuit structure and an accurate undervoltage lockout implementation method and circuit. Summary of the Invention

[0006] To address the shortcomings of existing technologies, the present invention aims to provide a UVLO circuit and a UVLO voltage generation method that overcomes the influence of temperature. By balancing and canceling the temperature coefficients generated by the bias unit and the comparison unit, the power supply voltage divider and the comparison voltage, which have the same temperature coefficient (in other words, both have zero temperature coefficient), are compared to achieve accurate determination of the undervoltage lockout mode.

[0007] The present invention adopts the following technical solution.

[0008] A first aspect of the present invention relates to a UVLO circuit that overcomes the effects of temperature, wherein the circuit includes a bias unit, a reference voltage generation unit, and a comparison unit; the bias unit, connected to the comparison unit, is used to generate a bias current and mirror the bias current to the comparison unit; the reference voltage generation unit, connected to the comparison unit, is used to generate a reference voltage and output the reference voltage to the comparison unit; the comparison unit is used to receive the bias current and the reference voltage, and generate a comparison voltage based on the bias current to achieve a comparison with the reference voltage in the same temperature direction, and generate a UVLO voltage.

[0009] Preferably, the comparator unit includes a third PMOS transistor (PMOS3), a third NMOS transistor (NMOS3), and a fourth resistor (R4); wherein the source of the third PMOS transistor is connected to the power supply voltage Vdd, and the drain is connected to the drain of the third NMOS transistor (NMOS3), together serving as the output terminal of the comparator unit to output the UVLO voltage; the source of the third NMOS transistor (NMOS3) is grounded through the fourth resistor (R4); the gate of the third PMOS transistor receives the bias current I from the output terminal of the bias unit. bias The gate of the third NMOS transistor, NMOS3, receives the reference voltage V from the reference voltage generation unit. ref .

[0010] Preferably, when the bias current output by the bias unit is The reference voltage of the reference voltage generation unit is When the comparison voltage is

[0011] Wherein, K is the ratio of the width to length of the third MOS transistor PMOS3 in the comparator unit to the width to length of the first PMOS transistor PMOS1 and the second PMOS transistor PMOS2 in the bias unit; V gs1 V gs2 and V gs3 R1 and R4 represent the gate-source voltage differences of the first NMOS transistor NMOS1, the second NMOS transistor NMOS2 in the bias unit, and the third NMOS transistor NMOS3 in the comparator unit, respectively; R1 and R4 represent the resistance values ​​of the bias resistor R1 in the bias unit and the fourth resistor R4 in the comparator unit, respectively.

[0012] Preferably, when comparing voltage V comp and reference voltage V ref When they are equal, the UVLO level state flips.

[0013] Preferably, the comparison voltage V comp and reference voltage V ref They have the same temperature coefficient.

[0014] Preferably, the circuit is configured to meet the following conditions. Where, ΔV gs1ΔV gs2 and ΔV gs3 These represent the changes in gate-source voltage of the first NMOS transistor NMOS1, the second NMOS transistor NMOS2, and the third NMOS transistor NMOS3 in the comparator unit when the circuit temperature changes by a unit.

[0015] Preferably, the bias resistor R1, voltage divider resistors R2 and R3, and fourth resistor R4 in the circuit are all high-precision resistors with zero temperature coefficient.

[0016] A second aspect of the present invention relates to a UVLO voltage generation method that overcomes the effects of temperature, wherein the method is implemented using a UVLO circuit that overcomes the effects of temperature as described in the first aspect of the present invention.

[0017] The beneficial effects of this invention are that, compared with the prior art, the UVLO circuit and UVLO voltage generation method of this invention overcome the influence of temperature by balancing and canceling the temperature coefficients generated by the bias unit and the comparison unit, so that the power supply voltage divider and the comparison voltage have the same temperature coefficient. In other words, they are compared with the power supply voltage divider and the comparison voltage, both of which have zero temperature coefficient, thus achieving accurate determination of the undervoltage lockout mode. The method of this invention is simple, the circuit is simple, there are few components, low power consumption, small area, and fast response, and it can fully realize comparison and accurate UVLO output under zero temperature coefficient conditions. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of an undervoltage lockout circuit in the prior art of this invention;

[0019] Figure 2 This is a schematic diagram of a UVLO circuit that overcomes the effects of temperature according to the present invention. Detailed Implementation

[0020] The present application will be further described below with reference to the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solutions of the present invention, and should not be construed as limiting the scope of protection of the present application.

[0021] Figure 1 This is a schematic diagram of an undervoltage lockout circuit in the prior art of this invention. Figure 1 As shown, commonly used undervoltage lockout (UVLO) circuits in the prior art typically compare the power supply voltage output by a voltage divider circuit with the bandgap reference voltage output by a bandgap reference source to generate the UVLO mode control signal. Normally, when the bandgap reference voltage is less than the power supply voltage divider, the circuit will not enter UVLO mode, and the circuit's output voltage Vout will be low. However, when the bandgap reference voltage output by the bandgap reference source is greater than the power supply voltage divider, it indicates that the power supply voltage is too low, and UVLO mode needs to be activated to protect the circuit.

[0022] Figure 2 This is a schematic diagram of a UVLO circuit that overcomes the effects of temperature according to the present invention. Figure 2 As shown, a second aspect of the present invention relates to a UVLO circuit that overcomes the effects of temperature, wherein the circuit includes a bias unit, a reference voltage generation unit, and a comparison unit; the bias unit, connected to the comparison unit, is used to generate a bias current and mirror the bias current to the comparison unit; the reference voltage generation unit, connected to the comparison unit, is used to generate a reference voltage and output the reference voltage to the comparison unit; the comparison unit is used to receive the bias current and the reference voltage, and generate a comparison voltage based on the bias current to achieve a comparison with the reference voltage in the same temperature direction, and generate a UVLO voltage.

[0023] The comparison in the same temperature direction mentioned here can refer to both the reference voltage and the comparison voltage being zero temperature coefficient voltages, or both being voltages with positive or negative temperature coefficients. In this embodiment of the invention, to simplify the implementation of the circuit, such as the selection of components, the case where both are approximately zero temperature coefficients is adopted.

[0024] Furthermore, when both the bias current source and the reference voltage are zero-temperature rarefaction, the bias current output can be configured to have a positive temperature coefficient, while the component in the comparator power supply that converts the bias current into a comparator voltage can simultaneously have a negative temperature coefficient. In this way, the generated comparator voltage can have a zero temperature coefficient. With both reference voltages having zero temperature coefficients, accurate comparison can be achieved, unaffected by temperature, and the direction of the output UVLO voltage is highly accurate.

[0025] Preferably, the comparator unit includes a third PMOS transistor (PMOS3), a third NMOS transistor (NMOS3), and a fourth resistor (R4); wherein the source of the third PMOS transistor is connected to the power supply voltage Vdd, and the drain is connected to the drain of the third NMOS transistor (NMOS3), together serving as the output terminal of the comparator unit to output the UVLO voltage; the source of the third NMOS transistor (NMOS3) is grounded through the fourth resistor (R4); the gate of the third PMOS transistor receives the bias current I from the output terminal of the bias unit. bias The gate of the third NMOS transistor, NMOS3, receives the reference voltage V from the reference voltage generation unit. ref .

[0026] In this invention, the comparator unit employs a very simple structure, using a PMOS transistor and an NMOS transistor connected in a common-source, common-gate configuration, with a resistor R4 connected to form a branch. In this branch, the gate of the PMOS3 is controlled by the bias unit, thereby generating a mirrored bias current between its source and drain. Additionally, the gate of the NMOS3 is subjected to a reference voltage V. refThe control enables the NMOS3 to be turned on or off, as well as the direction and magnitude of the UVLO voltage output from its drain.

[0027] Specifically, the amplitude, or magnitude, of the UVLO voltage is not very important, because a simple reversal of the UVLO voltage's direction will trigger a change in the operation of the subsequent circuitry. Therefore, the timing and method of determining the UVLO voltage's direction change need to be precisely controlled.

[0028] Therefore, in this invention, NMOS3 and the fourth resistor R4 together realize the conversion of the mirrored bias current, generating a comparison voltage to be compared with the reference voltage V. ref Compare them.

[0029] Preferably, when the bias current output by the bias unit is The reference voltage of the reference voltage generation unit is When the comparison voltage is Wherein, K is the ratio of the width to length of the third MOS transistor PMOS3 in the comparator unit to the width to length of the first PMOS transistor PMOS1 and the second PMOS transistor PMOS2 in the bias unit; V gs1 V gs2 and V gs3 R1 and R4 represent the gate-source voltage differences of the first NMOS transistor NMOS1, the second NMOS transistor NMOS2 in the bias unit, and the third NMOS transistor NMOS3 in the comparator unit, respectively; R1 and R4 represent the resistance values ​​of the bias resistor R1 in the bias unit and the fourth resistor R4 in the comparator unit, respectively.

[0030] Preferably, when comparing voltage V comp and reference voltage V ref When they are equal, the UVLO level state flips.

[0031] Understandably, when the bias current after mirroring causes the sum of the voltage across R4 and the threshold voltage of NMOS3 to exceed the reference voltage, NMOS3 should be in the off state and will not output UVLO voltage. However, when the sum of the threshold voltage of NMOS3 and the voltage drop across resistor R4 is less than the reference voltage, NMOS3 will be turned on, generating UVLO voltage, which is Vout as shown in the diagram. At this time, NMOS3 will transition from the off state to the on state, and the voltage level in UVLO will flip from high to low, thus enabling the subsequent circuit to achieve undervoltage protection under the control of the falling edge of this signal.

[0032] Preferably, the comparison voltage V comp and reference voltage V ref They have the same temperature coefficient. In one embodiment of the present invention, both voltages are zero temperature coefficient voltages.

[0033] Preferably, the circuit is configured to meet the following conditions. Where, ΔV gs1 ΔV gs2 and ΔV gs3 These represent the changes in gate-source voltage of the first NMOS transistor NMOS1, the second NMOS transistor NMOS2, and the third NMOS transistor NMOS3 in the comparator unit when the circuit temperature changes by a unit.

[0034] In order for two voltages to have the same temperature coefficient, the magnitude of the change in the two voltages should be the same when the temperature changes.

[0035] Preferably, the bias resistor R1, voltage divider resistors R2 and R3, and fourth resistor R4 in the circuit are all high-precision resistors with zero temperature coefficient.

[0036] Since all voltage divider resistors are set to zero-temperature coefficient resistors, the reference voltage also has a zero-temperature coefficient. Therefore, the reference voltage does not change with temperature. In other words, the comparison voltage should also not change with temperature. This is based on the formula for calculating the comparison voltage. After calculating the comparison voltages at two different temperatures, the difference is taken to obtain the formula. In other words, when the resistances do not change with temperature, the offset of the gate-source voltage difference between the three MOSFETs (NMOS1, NMOS2, and NMOS3) as they change with temperature can be set to a proportional relationship constrained by the formula. Generally, this can be achieved by adjusting... The resistance ratio between R1 and R4 in this index fulfills the constraint conditions of the above formula.

[0037] By configuring it in this way, the comparison voltage remains unchanged with temperature variations, ensuring accurate UVLO voltage output. In other words, the change in the gate-source threshold voltage of the NMOS transistor at different temperatures cancels out the positive temperature coefficient output of the bias current source, thus achieving zero-temperature characteristics for the UVLO voltage.

[0038] A second aspect of the present invention relates to a UVLO voltage generation method that overcomes the effects of temperature, the method being implemented using a UVLO circuit that overcomes the effects of temperature as described in the first aspect of the present invention.

[0039] The beneficial effects of this invention are that, compared with the prior art, the UVLO circuit and UVLO voltage generation method of this invention overcome the influence of temperature by balancing and canceling the temperature coefficients generated by the bias unit and the comparison unit, so that the power supply voltage divider and the comparison voltage have the same temperature coefficient. In other words, they are compared with the power supply voltage divider and the comparison voltage, both of which have zero temperature coefficient, thus achieving accurate determination of the undervoltage lockout mode. The method of this invention is simple, the circuit is simple, there are few components, low power consumption, small area, and fast response, and it can fully realize comparison and accurate UVLO output under zero temperature coefficient conditions.

[0040] The applicant of this invention has provided a detailed description of the embodiments of the invention in conjunction with the accompanying drawings. However, those skilled in the art should understand that the above embodiments are merely preferred embodiments of the invention. The detailed description is only intended to help readers better understand the spirit of the invention and is not intended to limit the scope of protection of the invention. On the contrary, any improvements or modifications made based on the inventive spirit of the invention should fall within the scope of protection of the invention.

Claims

1. A UVLO circuit that overcomes the effects of temperature, characterized in that: The circuit includes a bias unit, a reference voltage generation unit, and a comparison unit; wherein... The bias unit is connected to the comparison unit and is used to generate a bias current and mirror the bias current to the comparison unit; The reference voltage generation unit is connected to the comparison unit and is used to generate a reference voltage and output the reference voltage to the comparison unit. The comparator unit includes a third PMOS transistor (PMOS3), a third NMOS transistor (NMOS3), and a fourth resistor (R4); it is used to generate a comparison voltage based on the bias current to achieve a comparison with the reference voltage in the same temperature direction, and to generate a UVLO voltage; wherein, the source of the third PMOS transistor is connected to the power supply voltage Vdd, and the drain is connected to the drain of the third NMOS transistor (NMOS3), together serving as the output terminal of the comparator unit to output the UVLO voltage; the source of the third NMOS transistor (NMOS3) is grounded through the fourth resistor (R4); the gate of the third PMOS transistor receives the bias current from the output terminal of the bias unit. The gate of the third NMOS transistor NMOS3 receives the reference voltage from the reference voltage generation unit. .

2. The UVLO circuit for overcoming temperature effects according to claim 1, characterized in that: When the bias current output by the bias unit is The reference voltage of the reference voltage generation unit is When, the comparison voltage is ; in, The width-to-length ratio of the third MOS transistor PMOS3 in the comparison unit to the width-to-length ratio of the first PMOS transistor PMOS1 and the second PMOS transistor PMOS2 in the bias unit; , and These are the gate-source voltage differences of the first NMOS transistor NMOS1, the second NMOS transistor NMOS2 in the bias unit, and the third NMOS transistor NMOS3 in the comparison unit, respectively. and These are the resistance values ​​of the bias resistor R1 in the bias unit and the resistance value of the fourth resistor R4 in the comparison unit, respectively.

3. The UVLO circuit for overcoming temperature effects according to claim 2, characterized in that: When the comparison voltage and the reference voltage When they are equal, the UVLO level state is flipped.

4. A UVLO circuit for overcoming temperature effects according to claim 3, characterized in that: The comparison voltage and the reference voltage They have the same temperature coefficient.

5. A UVLO circuit for overcoming temperature effects according to claim 4, characterized in that: The circuit is configured to meet the conditions. ; in, , and These represent the changes in gate-source voltage of the first NMOS transistor NMOS1, the second NMOS transistor NMOS2, and the third NMOS transistor NMOS3 in the bias unit, respectively, when the circuit temperature undergoes a unit change.

6. A UVLO circuit for overcoming temperature effects according to claim 4, characterized in that: The bias resistor R1, voltage divider resistors R2 and R3, and the fourth resistor R4 in the circuit are all high-precision resistors with zero temperature coefficient.

7. A method for generating UVLO voltage to overcome the influence of temperature, characterized in that: The method is implemented using a UVLO circuit that overcomes the effects of temperature, as described in any one of claims 1-6.

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