Display device with embedded touch electrodes

Abstract

A display device in which a touch electrode is embedded includes a display panel including gate lines and touch groups including touch electrodes, a generator generating a lower gate clock corresponding to a lower gate pulse output to a lower gate line included in a touch group and a normal gate clock supplied to a normal gate line among the gate lines other than the lower gate line corresponding to the touch group, a controller supplying a gate control signal to the generator, and a gate driver generating a gate pulse by using the gate control signal, the lower gate clock, and the normal gate clock and supplying the gate pulse to the gate line corresponding to the touch group. The lower gate clock has a shape different from a shape of each of the normal gate clocks, each of the touch groups is arranged in parallel with the gate lines, and the touch groups are arranged in a direction perpendicular to the gate lines.

Description

Technical Field

[0001] This disclosure relates to a display device in which touch electrodes are embedded. Background Technology

[0002] Display devices include liquid crystal display (LCD) devices and light-emitting display devices, both of which include a display panel for displaying images.

[0003] Touch electrodes can be embedded in the display panel, and the touch electrodes can be divided into at least two touch groups.

[0004] The display device can repeatedly execute a display period in which an image is displayed and a touch sensing period in which a touch is sensed during a frame period.

[0005] In this situation, the brightness of the horizontal line set at the bottom of a touch group differs from the brightness of different areas, resulting in horizontal stripes appearing at the bottom of each touch group. Summary of the Invention

[0006] Accordingly, this disclosure relates to providing a display device that substantially eliminates one or more problems caused by the limitations and disadvantages of related technologies.

[0007] This disclosure relates to a display device in which touch electrodes are embedded, wherein the waveform of a lower gating clock corresponding to a lower gating pulse output from a touch group in the signal supplied to the gating driver is changed to a waveform different from that of a normal gating clock.

[0008] Additional advantages and features of this disclosure will be set forth in part in the description which follows, and will in part become apparent to one of ordinary skill in the art upon reading the narration, or may be learned by practice of this disclosure. The objects and other advantages of this disclosure may be realized and obtained by means of the written description, the claims, and the structures particularly pointed out in the accompanying drawings.

[0009] To achieve these and other advantages and in accordance with the purposes of this disclosure, as implemented and broadly described herein, a display device in which touch electrodes are embedded is provided, the display device comprising: a display panel including gating lines and touch groups including touch electrodes; a generator generating a lower gating clock corresponding to a lower gating pulse output to a lower gating line included in the touch group and a normal gating clock supplied to normal gating lines other than the lower gating lines in the gating lines corresponding to the touch group; a controller supplying a gating control signal to the generator; and a gating driver generating gating pulses using the gating control signal, the lower gating clock, and the normal gating clocks, and supplying the gating pulses to the gating lines corresponding to the touch group, wherein the shape of the lower gating clocks differs from the shape of each of the normal gating clocks, each of the touch groups is arranged parallel to the gating lines, and the touch groups are arranged in a direction perpendicular to the gating lines.

[0010] It should be understood that both the above general description of this disclosure and the following detailed description are exemplary and illustrative, and are intended to provide further explanation of the disclosed information. Attached Figure Description

[0011] The accompanying drawings are included to provide a further understanding of this disclosure and are incorporated in and constitute a part of this application. They illustrate embodiments of the disclosure and, together with the specification, serve to explain the principles of the disclosure. In the drawings: Figure 1 This is an example diagram illustrating a configuration of a display device in which touch electrodes are embedded, according to the present disclosure; Figure 2 and Figure 3 This is an example diagram illustrating the structure of a pixel in a display device in which touch electrodes are embedded, according to the present disclosure; Figure 4 This is an example diagram illustrating the structure of a controller applied to a display device in which touch electrodes are embedded, according to the present disclosure; Figure 5 This is an example diagram illustrating the structure of a gating driver applied to a display device in which touch electrodes are embedded, according to the present disclosure; Figure 6 This is an illustrative example. Figure 5 Example diagram of the hierarchical structure shown in the figure; Figure 7A This is an example diagram illustrating a method for repeatedly displaying a period of time and a period of touch sensing in a display device in which touch electrodes are embedded; Figure 7B This illustrates when based on Figure 7AAn example diagram illustrating the change in the common voltage applied to the touch electrodes when driving a display device using a specific method; Figure 8 This is an example diagram illustrating the internal configuration of a generator applied to a display device in which touch electrodes are embedded, according to the present disclosure; Figure 9 This is an example of... Figure 8 An example diagram illustrating the lower strobe clock generated by the generator; Figure 10 This is another example diagram illustrating the internal configuration of a generator applied to a display device in which touch electrodes are embedded, according to the present disclosure; Figure 11 This is an example Figure 10 Example diagram illustrating the configuration of a lower voltage generator; Figure 12 This is an example of... Figure 10 An example diagram illustrating the lower gating clock generated by the generator is shown in the image; and Figure 13A and Figure 13B It is used to describe based on Figure 10 An example diagram illustrating the effect of the generator of this disclosure is shown in the figure. Detailed Implementation

[0012] Exemplary embodiments of this disclosure will now be described in detail with reference to the accompanying drawings, examples of which are illustrated. Wherever possible, the same reference numerals will be used throughout the drawings to refer to the same or similar parts.

[0013] The advantages and features of this disclosure and its implementation methods will be illustrated by the following embodiments described with reference to the accompanying drawings. However, this disclosure may be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of this disclosure to those skilled in the art. Furthermore, this disclosure is limited only by the scope of the claims.

[0014] The shapes, sizes, ratios, angles, and numbers disclosed in the accompanying drawings for the purpose of describing embodiments of this disclosure are merely examples, and therefore, this disclosure is not limited to the illustrated details. Similar reference numerals always refer to similar elements. In the following description, detailed descriptions of related known functions or configurations will be omitted when it is determined that such detailed descriptions unnecessarily obscure the essential points of this disclosure. When using the terms "comprising," "having," and "including" as described in this specification, an additional part may be added unless "only" is used. Singular terms may include plural forms unless the opposite is indicated.

[0015] When interpreting an element, it is understood to include a range of errors or tolerances, although there is no explicit description of such a range of errors or tolerances.

[0016] When describing positional relationships, for example, when the positional relationship between two parts is described as such as "above", "over", "below", and "next to", one or more other parts may be placed between the two parts unless further restrictive terms such as "right" or "exactly" are used.

[0017] When describing temporal relationships, such as when time sequence is described as “after,” “following,” “next,” and “before,” discontinuous situations may be included unless further restrictive terms such as “right,” “exactly,” or “just right” are used.

[0018] It should be understood that while the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are merely used to distinguish one element from another. For example, without departing from the scope of this disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0019] In describing the elements of this disclosure, the terms “first,” “second,” “A,” “B,” “(a),” “(b),” etc., may be used. These terms are intended to identify the corresponding element from other elements, and the basis, order, or number of corresponding elements shall not be limited by these terms. The expression that an element is “connected,” “joined,” or “adhered” to another element or layer means that the element or layer may be directly connected or adhered to another element or layer, or indirectly connected or adhered to another element or layer, such that one or more intermediate elements or layers are “set” or “interposed” between these elements or layers, unless otherwise specified.

[0020] The term "at least one" should be understood to include any and all combinations of one or more of the associated items. For example, "at least one of the first, second, and third items" means a combination of all items derived from two or more of the first, second, and third items, as well as the first, second, or third item.

[0021] Features of the various embodiments of this disclosure may be linked or combined with each other in part or in whole, and may interact with each other and be technically driven in various ways, as will be fully understood by those skilled in the art. Embodiments of this disclosure may be performed independently of each other, or may be implemented together in an interdependent manner.

[0022] In the following description, embodiments of the present disclosure will be illustrated in detail with reference to the accompanying drawings.

[0023] Figure 1 This is an example diagram illustrating the configuration of a display device according to the present disclosure, in which touch electrodes are embedded. Figure 2 and Figure 3 This is an example diagram illustrating the structure of a pixel in a display device in which touch electrodes are embedded, according to the present disclosure. Figure 4 This is an example diagram illustrating the structure of a controller applied to a display device in which touch electrodes are embedded, according to the present disclosure. Figure 5 This is an example diagram illustrating the structure of a gating driver applied to a display device in which touch electrodes are embedded, according to the present disclosure. Figure 6 This is an illustrative example. Figure 5 Example diagram of the hierarchical structure shown in the figure.

[0024] According to this disclosure, a display device in which touch electrodes are embedded (hereinafter referred to as a display device) can constitute a variety of electronic devices. Electronic devices may include, for example, smartphones, tablet personal computers (PCs), televisions (TVs), and monitors.

[0025] like Figure 1 As illustrated in the present disclosure, a display device in which touch electrodes are embedded may include a display panel 100, a strobe driver 200, a data driver 300, a controller 400, a generator 500, and a touch driver 600.

[0026] First, the display panel 100 can be divided into a display area for displaying images and a non-display area surrounding the outer portion of the display area.

[0027] Display panel 100 may include gating lines GL1 to GLg, data lines DL1 to DLd, and pixels 110. Each of the pixels 110 may be connected to both the gating lines and the data lines. The gating lines GL1 to GLg may be connected to a gating driver 200, and the data lines DL1 to DLd may be connected to a data driver. Here, g and d may both be natural numbers.

[0028] The display panel 100 may include touch electrodes TE, and the touch electrodes TE may be divided into at least two touch groups TG1 to TGn (where n is a natural number of 1 or greater). That is, each of the touch groups may include multiple touch electrodes TE.

[0029] Each of the touch groups TG can be set parallel to the gate lines GL1 to GLg, and the touch groups TG can be set in a direction perpendicular to the gate lines GL1 to GLg.

[0030] Each of the touch electrodes TE can be connected to the touch driver 600 via the touch cable TL.

[0031] A touch electrode TE can overlap with at least two gate lines GL and at least two data lines DL. Accordingly, a touch electrode TE can overlap with at least two pixels.

[0032] Therefore, each of the touch groups TG1 to TGn can overlap with at least two gate lines.

[0033] The touch electrode TE can be embedded in the display panel 100. In this case, the touch electrode TE can overlap with at least two pixels, and the voltage applied to the at least two pixels can be supplied to the touch electrode TE.

[0034] When the display panel includes, for example Figure 2 When the display panel includes the pixel 110 illustrated, the touch electrode TE can be a common electrode. When the display panel includes, for example... Figure 3 In the example of a light-emitting display panel with pixel 110, the touch electrode TE can be a cathode electrode.

[0035] That is, the display panel 100 can be a liquid crystal display panel that displays images using liquid crystal, or it can be a light-emitting display panel equipped with a light-emitting device ED.

[0036] For example, when the display panel 100 is a liquid crystal display panel, such as Figure 2 As illustrated, the pixels 110 included in the display panel 100 may include a pixel driving circuit PDC comprising a switching transistor Tsw1 and a common electrode, and a light-emitting area comprising liquid crystal. Figure 2 In this context, reference numeral Clc can denote the liquid crystal disposed between the pixel electrode and the common electrode connected to the switching transistor Tsw1. In the liquid crystal display panel, as described above, the touch electrode TE can be the common electrode. In this case, during the display period, a common voltage Vcom can be supplied to the touch electrode TE, and during the touch sensing period, a touch drive signal can be supplied to the touch electrode TE. When the display panel 100 is a liquid crystal display panel, the display device may further include a backlight that illuminates the liquid crystal display panel.

[0037] For example, when the display panel 100 is a light-emitting display panel, such as Figure 3As illustrated, the pixels 110 included in the display panel 100 may include a pixel driving circuit PDC comprising a switching transistor Tsw1, a storage capacitor Cst, a driving transistor Tdr, and a sensing transistor Tsw2, as well as a light-emitting area including a light-emitting device ED. In the light-emitting display panel, as described above, the touch electrode TE may be a cathode electrode. The cathode electrode may be an electrode connected to the light-emitting device ED. In this case, during the display period, a cathode voltage EVSS may be supplied to the cathode electrode, and during the touch sensing period, a touch driving signal may be supplied to the cathode electrode. In addition to... Figure 3 In addition to the structure illustrated herein, the pixels 110 applied to the light-emitting display panel can also be implemented in various structures.

[0038] In the following description, for ease of description, display devices in which the display panel is a liquid crystal display panel will be described as examples of this disclosure.

[0039] The data driver 300 can be mounted on the on-film chip attached to the display panel 100. In this case, the data driver 300 can be connected to the data lines DL1 to DLd included in the display panel 100 and the controller 400 mounted on the main substrate.

[0040] The data driver 300 can be directly mounted on the display panel 100 and then connected to the controller 400 located in the main board.

[0041] The data driver 300 can be implemented as an integrated circuit (IC) together with the controller 400. In this case, the IC can be mounted on a chip-on-film device or can be directly mounted in the display panel 100.

[0042] Generator 500 (e.g., circuitry) can generate a lower gating clock corresponding to a lower gating pulse output to a lower gating line Gala, GLb, or GLg located at the lower end of the touch group TG (where a is a natural number greater than 1, b is a natural number greater than a, and g is a natural number greater than b) and a normal gating clock corresponding to the normal gating pulses supplied to the normal gating lines other than the lower gating lines among the gating lines corresponding to the touch group. That is, generator 500 generates a lower gating clock (e.g., a first gating pulse) corresponding to the lower gating pulse (e.g., a first gating pulse) output to the last gating line in each touch group and generates a normal gating clock (e.g., a second gating pulse) corresponding to the normal gating pulses (e.g., a second gating pulse) output to all remaining gating lines in the touch group. In one embodiment, the last gating line in each touch group is the gating line in the touch group that is closest to the touch driver 600.

[0043] In this disclosure, the shape of the lower strobe clock may differ from the shape of each of the ordinary strobe clocks. That is, the lower strobe clock differs from the ordinary strobe clock. The shape of the lower strobe pulse may be similar to the shape of the lower strobe clock, and the shape of the ordinary strobe pulse may be similar to the shape of the ordinary strobe clock.

[0044] Generator 500 can generate a control clock for generating a lower gating clock based on a gating control signal transmitted from controller 400.

[0045] A lower gate line (e.g., GLa) can be set between a touch group corresponding to the lower gate line (e.g., first touch group TG1) and another touch group adjacent to that touch group (e.g., second touch group TG2).

[0046] The following text will refer to Figures 6 to 13B This section describes the detailed structure and function of generator 500 in detail.

[0047] The controller 400 can realign the input video data Ri, Gi, and Bi transmitted from the external system using the timing synchronization signal TSS transmitted from the external system, and can generate the gating control signal GCS to be supplied to the generator 500 and the gating driver 200.

[0048] For this purpose, such as Figure 4 As illustrated, controller 400 may include: a data aligner 430 that realigns input video data Ri, Gi, and Bi to generate image data Data and supplies the image data Data to data driver 300; a control signal generator 420 that generates a gating control signal GCS and a data control signal DCS using a timing synchronization signal TSS; an input unit 410 that receives the timing synchronization signal TSS and input video data Ri, Gi, and Bi transmitted from an external system and transmits the timing synchronization signal and input video data to the data aligner and control signal generator, respectively; and an output unit 440 that supplies the image data Data generated by the data aligner and the data control signal DCS generated by the control signal generator to data driver 300, and supplies the gating control signal GCS generated by the control signal generator to generator 500 and gating driver 200.

[0049] The gating control signal GCS supplied to the generator 500 may be the same as or different from the gating control signal GCS supplied to the gating driver 200.

[0050] The controller 400 can analyze the sensing signals transmitted from the touch driver 600 to sense the occurrence of a touch and the corresponding touch position or absence of a touch, and can transmit information about the sensed touch position to an external system. The controller 400 can transmit information about the touch position transmitted from the touch driver 600 or another component to an external system.

[0051] An external system can perform the functions of the drive controller 400 and the electronic device. For example, when the electronic device is a TV, the external system can receive various audio, video, and audio information via a communication network and can transmit the received video information to the controller 400. In this case, the image information may include input video data Ri, Gi, and Bi.

[0052] The touch driver 600 can supply a common voltage to the touch electrode TE during the display period. The touch driver 600 can supply touch drive signals to the touch electrode TE during the touch sensing period and can receive touch sensing signals transmitted from the touch electrode TE.

[0053] The display period and the touch sensing period can be repeated multiple times within a single frame.

[0054] For example, it is possible to display during the display period in conjunction with Figure 1 An image is displayed on the first area corresponding to the first touch group TG1 in the illustrated touch groups TG1 to TGn. Then, the touch applied to the first area can be sensed during the touch sensing period by using the touch electrodes included in the first area.

[0055] After a touch is sensed in the first area, an image can be displayed in the second area corresponding to another touch group (second touch group TG2) adjacent to the first touch group TG1 during the display period. After the image is displayed in the second area, the touch applied to the second area can be sensed during the touch sensing period by using the touch electrodes included in the second area.

[0056] Here, a frame period can represent the period during which an image is displayed by the display panel when all the gate lines GL1 to Glg included in the display panel are driven.

[0057] The touch driver 600 can convert touch sensing signals received from the touch electrode TE into digital sensing signals and can transmit the sensing signals to the controller 400 or another component. The touch driver 600 can analyze the touch sensing signals to sense whether a touch has occurred and the touch location, and can transmit information about the sensed touch location to the controller 400.

[0058] The touch driver 600 can be driven by the touch control signal TCS transmitted from the controller 400.

[0059] Finally, the gate driver 200 can be configured as an IC and installed in the non-display area. Alternatively, the gate driver 200 can be directly embedded into the non-display area using a gate-in-panel (GIP) type. When using the GIP type, the transistors constituting the gate driver 200 can be placed in the non-display area using the same process as the transistors included in each of the pixels 110 in the display area.

[0060] When a gating pulse generated by the gating driver 200 is supplied to the gate of the switching transistor Tsw1 included in the pixel 110, the switching transistor Tsw1 can be turned on. When the switching transistor Tsw1 is turned on, the data voltage supplied through the data line can be supplied to the pixel 110. When a gating cutoff signal is supplied to the switching transistor Tsw1, the switching transistor Tsw1 can be turned off. When the switching transistor Tsw1 is turned off, the data voltage may not be supplied to the pixel 110. The gating signal GS supplied to the gating line GL may include a gating pulse and a gating cutoff signal.

[0061] Specifically, the gating driver 200 can generate gating pulses using the gating control signal GCS, the lower gating clock CLKb, and the normal gating clock CLK, and can supply the gating pulses to the gating lines corresponding to the touch groups.

[0062] For this purpose, such as Figure 5 As illustrated, the gating driver 200 may include a stage 201 that supplies gating pulses GP1 to GPg to gating lines GL1 to GLg connected to the pixel 110.

[0063] Each of stage 201 may include multiple transistors, and a gating control signal GCS, a lower gating clock, a normal gating clock, and voltages of various levels may be supplied to stage 201. Stage 201 may generate gating pulses GP1 to GPg using various signals and voltages, and may sequentially supply gating pulses GP1 to GPg to gating lines GL1 to GLG.

[0064] For this purpose, such as Figure 6 As illustrated, each of stages 201 may include: a node signal generator 202 that generates a Q-node signal supplied to the Q-node Q and a QB-node signal having a phase opposite to the Q-node signal to output a gating pulse GP; and a gating signal output unit 203 that outputs the gating pulse GP based on the Q-node signal supplied to the Q-node and outputs a gating cutoff signal Goff based on the QB-node signal supplied to the QB-node. The gating signal GS may include the gating pulse GP and the gating cutoff signal Goff.

[0065] First, the node signal generator 202 may include multiple transistors for generating Q-node signals and QB-node signals. Figure 6 In order to describe the basic structure and basic function of the node signal generator 202 applied in this disclosure, a node signal generator 202 including two transistors Tst and Trs and an inverter IN is illustrated. That is, Figure 6 The node signal generator 202 illustrated herein is an example of a node signal generator applied to this disclosure and is illustrated schematically.

[0066] The start-up transistor Tst can be turned on by the start-up signal Vst, and a high voltage VD can be supplied to the gating signal output unit 203 through the Q node Q. Here, the start-up signal Vst can be a gating start signal transmitted from the controller 400, or it can be a gating pulse GP transmitted from the previous stage. Based on the high voltage VD transmitted to the Q node, the pull-up transistor Tup of the gating signal output unit 203 can be turned on, so the gating pulse GP can be output through the pull-up transistor Tup.

[0067] The high voltage VD of the start-up transistor Tst can be changed to a low voltage by the inverter IN and transmitted to the QB node QB. However, the inverter IN can change a voltage different from the high voltage VD to a low voltage and transmit the low voltage to the QB node QB, or it can transmit a low voltage applied externally to the QB node QB. Based on the low voltage transmitted to the QB node QB, the pull-down transistor Tdown of the gating signal output unit 203 can be turned off. Therefore, only the gating pulse GP can be output to the gating line GL through the pull-up transistor Tup.

[0068] When the reset transistor Tsr is turned on due to the reset signal Rest, the first low voltage GVSS1 can be supplied to the Q node Q through the reset transistor Trs. Correspondingly, the pull-up transistor Tup can be turned off, therefore, no strobe pulse GP will be output.

[0069] The first low voltage GVSS1 can be changed to a high voltage by the inverter IN and can be supplied to the QB node QB. The pull-down transistor Tdown of the gating signal output unit 203 can be turned on due to the high voltage transmitted to the QB node QB. Therefore, the gating cutoff signal Goff can be output to the gating line GL through the pull-down transistor Tdown.

[0070] For additional description, the inverter IN can supply a high voltage VD or a first low voltage GVSS1 to the Q node Q, change the high voltage VD or the first low voltage GVSS1 to a low voltage or a high voltage, and supply that low voltage or high voltage to the QB node QB.

[0071] For this purpose, the inverter IN can be implemented in various structures, and the node signal generator 202 including the inverter IN can also be implemented in various structures.

[0072] That is, the node signal generator 202 can generate a Q node signal supplied to the Q node Q and a QB node signal having a phase opposite to that of the Q node signal in order to output a gating pulse GP, and for this purpose, it can be implemented in various structures.

[0073] In this configuration, various gating control signals (e.g., gating start signals) can be supplied from controller 400 to node signal generator 202.

[0074] Second, the gating signal output unit 203 can output the gating pulse GP or the gating cutoff signal Goff to the gating line GL.

[0075] For this purpose, such as Figure 6 As illustrated, the strobe signal output unit 203 may include a pull-up transistor Tup that outputs a strobe pulse GP based on a Q node signal transmitted from Q node Q and a pull-down transistor Tdown that outputs a strobe cutoff signal Goff based on a QB node signal transmitted from QB node QB.

[0076] When the pull-up transistor Tup is turned on by the Q node signal, the normal gating clock CLK or the lower gating clock CLKb supplied to the first terminal of the pull-up transistor Tup can be output to the gating line GL through the second terminal of the pull-up transistor Tup.

[0077] The signal output to the gating line GL via the second terminal of the pull-up transistor Tup can be called a normal gating pulse or a lower gating pulse. That is, the signal generated from the normal gating clock CLK can be called a normal gating pulse, and the signal generated from the lower gating clock CLKb can be called a lower gating pulse. The normal gating pulse can be supplied to the normal gating line, and the lower gating clock CLKb can be supplied to the lower gating line.

[0078] The lower gate line can represent the gate line set at the lower end of the touch group TG, and the normal gate line can represent the gate line other than the lower gate line.

[0079] In the following description, when there is no need to distinguish between ordinary gating lines and lower gating lines, ordinary gating lines and lower gating lines can be collectively referred to as gating lines.

[0080] Furthermore, when there is no need to distinguish between normal gating pulses and lower gating pulses, the general term for normal gating pulses and lower gating pulses can be gating pulses.

[0081] Furthermore, when there is no need to distinguish between the normal strobe clock CLK and the lower strobe clock CLKb, the normal strobe clock CLK and the lower strobe clock CLKb can be collectively referred to as strobe pulses.

[0082] When the pull-up transistor Tup is turned off based on the Q node signal, the strobe pulse may not be output to the strobe line.

[0083] When the pull-down transistor Tdown is turned on based on the QB node signal, the second low voltage GVSS2 supplied to the first terminal of the pull-down transistor Tdown can be output to the gating line GL through the second terminal of the pull-down transistor Tdown. The signal output to the gating line GL through the second terminal of the pull-down transistor Tdown can be called the gating cutoff signal Goff.

[0084] When the pull-down transistor Tdown is cut off based on the QB node signal, the gating cutoff pulse may not be output to the gating line.

[0085] The following text will refer to Figure 7A and Figure 7B Let me briefly describe the background to the introduction of this disclosure.

[0086] Figure 7A This is an example diagram illustrating a method for repeatedly displaying a period of time and a period of touch sensing in a display device in which touch electrodes are embedded. Figure 7B This illustrates when based on Figure 7A An example diagram illustrating the change in the common voltage applied to the touch electrodes when driving a display device.

[0087] In display devices that embed touch electrodes, such as Figure 7A As illustrated, the display period D for displaying an image and the touch sensing period T for sensing a touch can be repeated multiple times within a single frame period (1 frame period). Here, a single frame period can represent the period during which the display panel displays an image while all the gate lines GL1 to GLg included in the display panel are driven.

[0088] For example, such as Figure 1 As illustrated, when the display panel 100 includes n touch groups TG1 to TGn, an image can be displayed on a first area corresponding to the first touch group TG1 during a first display period D1, and then a touch can be sensed by the touch electrode TE included in the first area during a first touch sensing period T1.

[0089] Subsequently, an image can be displayed on a second area corresponding to the second touch group TG2 during the second display period D2, and then touch can be sensed by the touch electrode TE included in the second area during the second touch sensing period T2.

[0090] After the operation can be repeated for up to the (n-1)th touch group, an image can be displayed on the nth region corresponding to the nth touch group TGn during the nth display period Dn, and then touch can be sensed by the touch electrode TE included in the nth region during the nth touch sensing period Tn.

[0091] This operation can be performed during a single frame, so the display panel 100 can display an image. The operation can then be repeated during another frame.

[0092] In this case, when Figure 1 When each of the touch groups TG1 to TGn illustrated includes nine gate lines, such as Figure 7B As illustrated, during the first display period D1, the first to ninth strobe pulses GP can be sequentially output to the first to ninth strobe lines. During the first display period D1, a common voltage can be supplied to the touch electrodes TE that constitute the first touch group TG1.

[0093] In this case, such as Figure 7B As illustrated, the common voltage (hereinafter referred to as the actual common voltage VCOMd) applied to the touch electrode TE of the first touch group TG1 can be gradually reduced in the direction from the start time of the first display period D1 to its end time.

[0094] like Figure 7B The reason why the level of the actual common voltage VCOMd shown in the example decreases is because only the rising gating pulse GP is in the beginning part A of the first display period D1, the rising gating pulse and the falling gating pulse are in the middle part B of the first display period D1, and the falling gating pulse without any rising gating pulse GP is in the end part C of the first display period D1.

[0095] For further description, the actual common voltage VCOMd may rise based on the rising gating pulse in the starting portion A, may rise and fall based on the rising and falling gating pulses in the intermediate portion B, and may fall based on the falling gating pulse in the ending portion C. That is, the level of the actual common voltage VCOMd applied to the touch electrode TE can be affected by the level of the gating pulse form. In other words, the amplitude of the actual common voltage VCOMd is affected by the rising and falling gating pulses GP.

[0096] Therefore, the actual common voltage VCOMd of the end portion C can be less than the actual common voltage VCOMd of the beginning portion A.

[0097] Because the actual common voltage VCOMd applied to the touch electrodes when displaying an image in the end portion C of the first display period D1 is less than the actual common voltage VCOMd applied to the touch electrodes when displaying an image in the beginning portion A of the first display period D1, the actual brightness of the image displayed in the end portion C of the first display period D1 can be less than the basic brightness expected under ideal conditions. Here, ideal conditions can refer to a state where the actual common voltage VCOMd does not change in the beginning portion A, the middle portion B, and the end portion C.

[0098] This brightness reduction phenomenon may occur in the final portion C of the first display period D1, and specifically, it may occur severely in the gate line located at the lower end of the first touch group TG1. That is, in the final portion C of the first display period D1, because a gate pulse is output from the gate line located at the lower end of the first touch group TG1, the brightness reduction phenomenon may occur severely in the gate line located at the lower end of the first touch group TG1.

[0099] In this implementation, the ninth gate line, to which the ninth gate signal GS is supplied, can be located at the lower end of the first touch group TG1. The ninth gate line can be adjacent to the second touch group TG2, and specifically, it can be adjacent to the tenth gate line located at the uppermost end of the second touch group TG2.

[0100] A gate line that is set at the lower end of the Touch Group TG, like the ninth gate line, can be called a lower gate line, and all other gate lines in the Touch Group TG other than the lower gate lines can be called normal gate lines.

[0101] Therefore, in Figure 1 In the illustrated display panel 100, the a-th gate line GLa, the b-th gate line GLb, and the g-th gate line GLg can be lower gate lines, and the other gate lines can be ordinary gate lines.

[0102] That is, in each of the touch groups, the actual brightness of the image displayed in the lower gate line can be less than the base brightness. Accordingly, horizontal stripes with lower brightness than other areas can be shown at the bottom of each touch group. Due to the horizontal stripes, it can be determined that the display device is defective, or that the image quality of the display device may be degraded.

[0103] In the above text, the lower gate line is described as a single gate line located at the bottom of the touch group, but the lower gate line can be two or more gate lines located at the bottom of the touch group.

[0104] For example, in the above reference Figure 7BIn the described implementation, the ninth gating line supplied with the ninth gating signal GS9 may be a lower gating line, or the eighth gating line supplied with the eighth gating signal GS8 and the ninth gating line supplied with the ninth gating signal GS9 may be lower gating lines.

[0105] That is, the lower gate line can represent the gate line in which the above-mentioned horizontal stripe defect occurs, and the number of lower gate lines can be set differently based on the width of the gate pulse and whether the horizontal stripe defect occurs.

[0106] In the following description, for ease of description, a display device in which only one lower gate line is in each of the touch groups TG1 to TGn will be described as an example of this disclosure.

[0107] This disclosure can be used to prevent the occurrence of the aforementioned horizontal stripe defects.

[0108] Because the actual common voltage VCOMd when the selected pulse is supplied to the lower selected line of the touch group TG is less than the actual common voltage VCOMd when the selected pulse is supplied to the normal selected line set at the upper end of the touch group TG, the horizontal stripe defect described above may occur.

[0109] To compensate for this difference, this disclosure may use the following methods: increasing the time period for supplying data voltage to the pixel so that the data voltage is fully charged into the pixel, or setting the lower fall level of the lower gating clock to be higher than the fall level of the normal gating clock.

[0110] The following will refer to Figure 8 and Figure 9 This disclosure describes a method for increasing the time interval of the data voltage supplied to the pixel, and references will be made below. Figures 10 to 13B This disclosure describes a method for setting a lower falling level of a lower gating clock to be higher than the falling level of a normal gating clock.

[0111] Figure 8 This is an example diagram illustrating the internal configuration of a generator applied to a display device in which touch electrodes are embedded, according to the present disclosure. Figure 9 This is an example of... Figure 8 The example diagram shows a lower strobe clock generated by the generator.

[0112] As mentioned above, please refer to the above references. Figures 1 to 6 As described, generator 500 can generate a lower gating clock CLKb corresponding to the lower gating pulse output to the lower gating line set at the lower end of the touch group TG, and a normal gating clock CLK corresponding to the normal gating pulse supplied to the normal gating lines other than the lower gating line in the gating lines corresponding to the touch group TG.

[0113] Specifically, such as Figure 9 As illustrated, generator 500 can perform the function of increasing the falling period F of the lower strobe clock CLKb to be longer than the falling period E of each of the normal strobe clocks CLK. Therefore, the duration of the falling period F of the lower strobe clock CLKb is increased relative to the falling period E of the normal strobe clock CLK, such that the falling period F of the lower strobe clock CLKb is longer than the falling period E of the normal strobe clock CLK.

[0114] Before describing the structure and function of the generator, refer to Figure 9 Describe the period of decline.

[0115] In this disclosure, such as Figure 9 As illustrated in signal (c), each of the lower gating clock CLKb and the normal gating clock CLK can be a pulse having a minimum level Vmin (e.g., a first level), a maximum level Vmax (e.g., a second level greater than the first level), and a falling level Vf (e.g., a third level less than the second level and greater than the first level).

[0116] Each of the lower gating clock CLKb and the normal gating clock CLK can rise from the minimum level Vmin to the maximum level Vmax based on the control clock and can fall from the maximum level to the falling level Vf, and can finally fall back to the minimum level Vmin.

[0117] In the following description, the falling period can refer to the time from the maximum level Vmax to the falling level Vf.

[0118] The reason why the lower gating clock CLKb and the normal gating clock CLK have a falling level Vf is to prevent the normal gating pulse corresponding to the normal gating clock CLK and the lower gating pulse corresponding to the lower gating clock CLKb from rapidly dropping from their maximum values ​​to their minimum values. That is, when the normal gating pulse and the lower gating pulse rapidly drop from their maximum values ​​to their minimum values, other metal electrodes and metal lines of the display panel may be affected by backlash. To solve this problem, the normal gating pulse and the lower gating pulse can drop from their maximum values ​​to their minimum values ​​via a falling level.

[0119] The maximum level Vmax, the falling level Vf, and the minimum level Vmin of each of the lower gating clock CLKb and the normal gating clock CLK can correspond to the maximum value, the falling value, and the minimum value of each of the normal gating pulse and the lower gating pulse.

[0120] In this disclosure, in order to make the falling period F of the lower gating clock CLKb longer than the falling period E of each normal gating clock CLK, the generator can generate a lower falling control clock MCLKb with a width greater than the falling control clock MCLK used to control the falling period E of each normal gating clock CLK.

[0121] For example, such as Figure 9 As illustrated in signal (b), the width of the lower fall control clock MCLKb can be set to be greater than the width of the fall control clock MCLK. That is, the pulse width of the lower fall control clock MCLKb is wider than the pulse width of the fall control clock MCLK.

[0122] The lower strobe clock CLKb can begin to fall from the timing when the lower fall control clock MCLKb rises, and can fall (e.g., decrease) until the timing when the lower fall control clock MCLKb falls to a predetermined level, and thus can reach the fall level Vf.

[0123] Therefore, the falling period F of the lower strobe clock CLKb can be determined based on the width of the lower falling control clock MCLKb.

[0124] In this case, the interval between the normal strobe clock CLK, which is generated before the lower strobe clock CLKb, and the lower strobe clock CLKb can be equal to the interval between the normal strobe clocks CLK.

[0125] That is, in the above implementation, since the falling period F of the lower gating clock CLKb is increased and the timing of generating the lower gating clock CLKb remains unchanged, the interval between the normal gating clock CLK and the lower gating clock CLKb can be equal to the interval between the normal gating clocks CLK.

[0126] However, in another embodiment of this disclosure, the interval between the normal strobe clock CLK generated before the lower strobe clock and the lower strobe clock CLKb can be smaller than the interval between the normal strobe clocks CLK.

[0127] For example, in Figure 9 In signal (c), the following example is illustrated: the falling period F of the lower gating clock CLKb is greater than the falling period E of the normal gating clock CLK, and the interval between the normal gating clock CLK and the lower gating clock CLKb generated just before the lower gating clock CLKb is less than the interval between the normal gating clocks CLK.

[0128] For this purpose, generator 500 can generate a lower rising control clock GCLKb with a width greater than the rising control clock GCLK used to control the rising timing of a normal strobe clock CLK. In this case, as Figure 9 As illustrated in signals (a) and (c), the lower strobe clock CLKb can rise at a timing that allows the lower rise control clock GCLKb to rise.

[0129] That is, generator 500 can perform control such that the rise timing of the lower rise control clock GCLKb is earlier than the rise timing of each of the rise control clocks GCLK generated before the lower rise control clock GCLKb, and therefore the rise timing of the lower rise control clock GCLKb can be earlier, thereby the interval between the lower strobe clock CLKb and the normal strobe clock CLK generated before the lower strobe clock CLKb can be smaller than the interval between the normal strobe clocks CLK.

[0130] In this case, the fall timing of the lower rise control clock GCLKb can be the same as the fall timing of each of the rise control clocks GCLK. That is, the width of the lower rise control clock GCLKb can be increased because the rise timing of the lower rise control clock GCLKb is earlier.

[0131] To perform the above functions, such as Figure 8 As illustrated, generator 500 may include: a control clock generator 510 for generating a lower falling control clock MCLKb with a width greater than that of the falling control clock MCLK transmitted from controller 400; and a level shifter 520 for increasing the falling period F of the lower strobe clock CLKb to be longer than the falling period E of each of the ordinary strobe clocks CLK by using the lower falling control clock MCLKb.

[0132] First, the control clock generator 510 can generate a lower falling control clock MCLKb using the falling control clock MCLK transmitted from the controller 400, and can transmit the lower falling control clock MCLKb to the level shifter 520 at the timing of generating the lower strobe clock CLKb. The falling control clock MCLK can be included in the strobe control signal GCS.

[0133] For example, the control clock generator 510 can delay the falling control clock MCLK transmitted from the controller 400 by using a resistor or capacitor, and thus generate a lower falling control clock MCLKb with a width greater than the width of the falling control clock MCLK. Alternatively, by using other methods besides those described above, the control clock generator 510 can generate a lower falling control clock MCLKb with a width greater than the width of the falling control clock MCLK.

[0134] The control clock generator 510 can generate a lower rising control clock GCLKb by using the rising control clock GCLK transmitted from the controller 400, and can transmit the lower rising control clock GCLKb to the level shifter 520 at the timing of generating the lower strobe clock CLKb.

[0135] For example, the control clock generator 510 can accelerate the rising timing of the rising control clock GCLK transmitted from the controller 400, and can delay the rising signal by using a resistor or capacitor, thus generating a lower rising control clock GCLKb that rises at a timing earlier than the rising control clock GCLK. Alternatively, by using other methods besides those described above, the control clock generator 510 can generate a lower rising control clock GCLKb that rises at a timing earlier than the rising control clock GCLK.

[0136] Second, the level shifter 520 can generate a lower gating clock CLKb using the gating control signal GCS transmitted from the controller 400 and the lower falling control clock MCLKb transmitted from the control clock generator 510, and can transmit the generated lower gating clock CLKb to the gating driver 200. In this case, the gating control signal GCS transmitted from the controller 400 can be used directly to generate the lower gating clock CLKb, or it can be transmitted to the gating driver 200 via the level shifter 520. For example, the gating control signal GCS transmitted from the controller 400 may include a signal that is used directly or indirectly to generate the lower gating clock CLKb, or it may include a signal transmitted to the gating driver 200 via the level shifter 520.

[0137] Furthermore, when the level shifter 520 generates a lower strobe clock CLKb as described above, the level shifter 520 can also use a lower rising control clock GCLKb transmitted from the control clock generator 510.

[0138] Furthermore, the level shifter 520 can generate a normal gating clock CLK using the gating control signal GCS transmitted from the controller 400, and can transmit the generated normal gating clock CLK to the gating driver 200. The gating control signal GCS transmitted from the controller 400 may include a rising control clock GCLK and a falling control clock MCLK.

[0139] That is, the level shifter 520 can generate the general strobe clock CLK by using the rising control clock GCLK and the falling control clock MCLK transmitted from the controller 400.

[0140] To generate the normal strobe clock CLK and the lower strobe clock CLKb, the level shifter 520 can be supplied with power of various levels from the power supply 700. For example, the power supply 700 can supply the level shifter 520 with voltages corresponding to the minimum level Vmin, the maximum level Vmax, and the falling level Vf, and the level shifter 520 can use these voltages to generate the normal strobe clock CLK and the lower strobe clock CLKb.

[0141] The power supply 700 can be integrated with the level shifter 520, or as... Figure 8 As illustrated, it can be implemented as a separate element from the level shifter 520.

[0142] For additional description, the level shifter 520 can be supplied with a voltage corresponding to the maximum level Vmax at the rising timing of the rising control clock GCLK, a voltage corresponding to the falling level Vf after the rising and before the falling control clock MCLK falls, and a voltage corresponding to the minimum level Vmin after the falling control clock MCLK falls, thereby generating the normal strobe clock CLK.

[0143] In addition, the level shifter 520 can be supplied with a voltage corresponding to the maximum level Vmax when the rising control clock GCLK or the lower rising control clock GCLKb rises, be supplied with a voltage corresponding to the falling level Vf after the rise and before the lower falling control clock MCLKb falls, and be supplied with a voltage corresponding to the minimum level Vmin after the lower falling control clock MCLKb falls, thereby generating the lower strobe clock CLKb.

[0144] As described above, the falling period of the lower gating clock CLKb can be longer than the falling period E of the normal gating clock CLK. Therefore, since the lower gating pulse is generated based on the lower gating clock CLKb, the falling period of the lower gating pulse supplied to the lower gating line can be longer than the falling period of the normal gating pulse supplied to the normal gating line. That is, the gating signal with a pulse generated based on the lower gating clock CLKb has a different form than the gating signal with a pulse generated based on the normal gating clock CLK. For example, the pulse of the gating signal generated based on the lower gating clock CLKb can have a wider width than the pulse of the gating signal generated based on the normal gating clock CLK. Furthermore, the duration of the pulse of the gating signal generated based on the lower gating clock CLKb decreasing from the maximum level to the falling level Vf is longer than the duration of the pulse of the gating signal generated based on the normal gating clock CLK decreasing from the maximum level to the falling level Vf.

[0145] When the falling period of the lower gating pulse is increased, the period during which the data voltage transmitted through the data line is supplied to the pixel through the switching transistor Tsw1 can be increased.

[0146] For example, in Figure 2 In the example where the pixel is connected to the lower gating line (hereinafter referred to as the lower pixel), as the falling period of the lower gating pulse increases, the period during which the switching transistor Tsw1 of the lower pixel is turned on can also increase. When the period during which the switching transistor Tsw1 is turned on increases, the period during which the data voltage is supplied to the pixel electrode through the switching transistor Tsw1 can also increase. When the period during which the data voltage is supplied to the pixel electrode increases, the period during which the pixel electrode is charged with the data voltage can also increase; therefore, the data voltage can be charged into the pixel electrode.

[0147] Therefore, as described above, although the actual common voltage VCOMd applied to the touch electrode when displaying an image with a lower gating pulse is less than the actual common voltage VCOMd applied to the touch electrode when a normal gating pulse is supplied, the brightness of the pixel connected to the lower gating line is not significantly reduced, and the brightness corresponding to the original data voltage can be output.

[0148] That is, in this disclosure, the period for supplying data voltage to the pixel can be increased to compensate for the decrease in the actual common voltage VCOMd supplied to the lower pixel. When the data voltage is fully charged into the pixel, the brightness of the lower pixel will not decrease and can be maintained at a level corresponding to the data voltage, even though the actual common voltage VCOMd decreases.

[0149] The effect can be further enhanced when the pulse width of the lower gating clock CLKb, based on the lower rising control clock GCLKb, is increased to be greater than the pulse width of the normal gating clock CLK.

[0150] Figure 10 This is another example diagram illustrating the internal configuration of a generator applied to a display device in which touch electrodes are embedded, according to the present disclosure. Figure 11 This is an example Figure 10 An example diagram illustrating the configuration of a lower voltage generator is shown in the figure. Figure 12 This is an example of... Figure 10 The example diagram shows a lower strobe clock generated by the generator. Figure 13A and Figure 13B It is used to describe based on Figure 10 An example diagram illustrating the effect of the generator of this disclosure is shown in the figure. In the following description, descriptions related to the above references are omitted or will be briefly described. Figures 1 to 9 The details described are the same or similar.

[0151] As mentioned above, please refer to the above references. Figures 1 to 6As described, generator 500 can generate a lower gating clock CLKb corresponding to the lower gating pulse output to the lower gating line set at the lower end of the touch group TG, and a normal gating clock CLK corresponding to the normal gating pulse supplied to the normal gating lines other than the lower gating line in the gating lines corresponding to the touch group TG.

[0152] Specifically, such as Figure 12 As illustrated, generator 500 can perform the function of changing the falling level (hereinafter referred to as the lower falling level) Vbf of the lower strobe clock CLKb to a higher level than the falling level (hereinafter referred to as the falling level) Vf of the normal strobe clock CLK.

[0153] Before describing the structure and function of the generator, refer to Figure 12 Describe the falling level.

[0154] In this disclosure, such as Figure 12 As illustrated in signal (d), the general gating clock CLK can be a pulse having a minimum level Vmin (e.g., a first level), a maximum level Vmax (e.g., a second level greater than the first level), and a falling level Vf (e.g., a third level greater than the first level and less than the second level), and as... Figure 12 As illustrated in signal (d), the lower gating clock CLKb can be a pulse having a minimum level Vmin, a maximum level Vmax, and a lower falling level Vbf (e.g., a fourth level that is greater than the first and third levels and less than the second level).

[0155] The normal gating clock CLK can rise from the minimum level Vmin to the maximum level Vmax based on the control clock, and can fall from the maximum level to the falling level Vf, and then can finally fall back to the minimum level Vmin. The lower gating clock CLKb can rise from the minimum level Vmin to the maximum level Vmax based on the control clock, and can fall from the maximum level to the lower falling level Vbf, and then can finally fall back to the minimum level Vmin.

[0156] In the following description, the falling period can refer to the period from the maximum level Vmax to the falling level Vf, or it can refer to the period from the maximum level Vmax to the lower falling level Vbf.

[0157] The reason why the normal gating clock CLK has a falling level Vf and the lower gating clock CLKb has a lower falling level Vbf is to prevent the normal gating pulse corresponding to the normal gating clock CLK and the lower gating pulse corresponding to the lower gating clock CLKb from rapidly dropping from their maximum values ​​to their minimum values. That is, when the normal gating pulse and the lower gating pulse rapidly drop from their maximum values ​​to their minimum values, other metal electrodes and metal lines of the display panel may be affected by backlash. To solve this problem, the normal gating pulse can drop from its maximum value to its minimum value via a falling value, and the lower gating pulse can drop from its maximum value to its minimum value via a lower falling value.

[0158] The maximum level Vmax, fall level Vf, and minimum level Vmin of the normal gating clock CLK correspond to the maximum, fall, and minimum values ​​of the normal gating pulse. The maximum level Vmax, lower fall level Vbf, and minimum level Vmin of the lower gating clock CLKb correspond to the maximum, lower fall, and minimum values ​​of the lower gating pulse.

[0159] In this disclosure, by using a falling control clock MCLK for controlling the falling period of the lower strobe clock CLKb, generator 500 can generate a falling level control clock FCLK for shifting the level to which the lower strobe clock CLKb falls, such that the lower falling level Vbf to which the lower strobe clock CLKb falls is higher than the falling level Vf to which the normal strobe clock CLK falls.

[0160] For example, such as Figure 12 As illustrated in signal (c), the falling-level control clock FCLK can have the same width as the falling-level control clock MCLK, and can have a phase opposite to that of the falling-level control clock MCLK. That is, the width, rise timing, and fall timing of the falling-level control clock FCLK can be the same as those of the falling-level control clock MCLK, and the phase of the falling-level control clock FCLK can be opposite to that of the falling-level control clock MCLK.

[0161] Therefore, the falling level control clock FCLK can be generated by inverting the falling control clock MCLK.

[0162] The generator can shift the falling level of the lower strobe clock CLKb (i.e., the lower falling level Vbf) by using the falling level control clock FCLK.

[0163] The lower strobe clock CLKb can begin to fall at the rising timing of the falling control clock MCLK and can fall until the falling control clock falls at the falling timing, thus reaching a lower fall level. In this case, the lower fall level Vbf of the lower strobe clock CLKb can be generated by a fall level control clock FCLK generated at the same timing as the falling control clock MCLK.

[0164] The lower fall level Vbf can be set to a value that is higher than the fall level Vf of the normal strobe clock CLK.

[0165] In this case, such as Figure 12 As illustrated in signal (d), the falling period K of the lower gating clock CLKb from the maximum level Vmax to the lower falling level Vbf can be the same as the falling period K of the normal gating clock CLK from the maximum level Vmax to the falling level Vf.

[0166] That is, the width of the falling control clock MCLK used to generate the lower strobe clock CLKb can be the same as the width of the falling control clock MCLK used to generate the normal strobe clock CLK, and therefore, the falling period K of the lower strobe clock can be the same as the falling period K of the normal strobe clock.

[0167] Furthermore, since the rise timing, fall timing, and width of the rise control clock GCLK used to generate the lower strobe clock CLKb are the same as the rise timing, fall timing, and width of the rise control clock GCLK used to generate the normal strobe clock CLK, the interval between the normal strobe clock CLK generated before the lower strobe clock CLKb and the lower strobe clock CLKb can be equal to the interval between normal strobe clocks CLK.

[0168] That is, based on the above references Figure 9 In the described implementation, because the width of the lower fall control clock MCLKb is different from the width of the fall control clock MCLK, the fall period F of the lower strobe clock CLKb can be different from the fall period E of the normal strobe clock CLK.

[0169] However, in the above reference Figure 12 In the described implementation, since the same falling control clock MCLK is used to generate the lower strobe clock CLKb and the normal strobe clock CLK, the falling period of the lower strobe clock can be the same as the falling period of the normal strobe clock.

[0170] In addition, in the above references Figure 9In the described implementation, because the rising timings of the lower rising control clock GCLKb and the rising control clock GCLK used to control the timing of generating the lower strobe clock CLKb and the normal strobe clock CLK are different, the interval between the normal strobe clock CLK generated before the lower strobe clock CLKb and the lower strobe clock CLKb in the normal strobe clock CLK can be smaller than the interval between the normal strobe clocks CLK.

[0171] However, in the above reference Figure 12 In the described implementation, because the same falling control clock MCLK is used to generate the lower strobe clock CLKb and the normal strobe clock CLK, the interval between the normal strobe clock CLK generated before the lower strobe clock CLKb and the lower strobe clock CLKb can be the same as the interval between normal strobe clocks CLK. Furthermore, for this reason, the width K of each of the normal strobe clocks CLK can be the same as the width K of the lower strobe clock CLKb.

[0172] As described above, generator 500 can increase the voltage from a minimum level Vmin to a maximum level Vmax, and then reduce the voltage to a falling level Vf that is less than the maximum level Vmax but greater than the minimum level Vmin based on the falling control clock MCLK, thereby generating a normal gating clock CLK. Alternatively, generator 500 can generate a normal gating clock by increasing the voltage from the minimum level Vmin to the maximum level Vmax, and then reducing the voltage to a lower falling level Vbf that is less than the maximum level Vmax but greater than the falling level Vf based on the falling control clock MCLK, thereby generating a lower gating clock CLKb.

[0173] In this case, generator 500 can generate a lower voltage Vb corresponding to a lower falling level Vbf based on a falling level control clock FCLK generated simultaneously with the falling control clock MCLK.

[0174] To perform the above functions, such as Figure 10 As illustrated, generator 500 may include: a control clock generator 510 for generating a falling-level control clock FCLK having the same width and timing as the falling control clock MCLK transmitted from controller 400; a lower voltage generator 530 for generating a lower voltage Vb corresponding to a lower falling level Vbf by using the falling-level control clock FCLK; and a level shifter 520 for increasing the falling level (i.e., the lower falling voltage Vbf) of the lower gating clock CLKb by using the lower voltage Vb to be longer than the falling level (i.e., the falling level Vf) of each of the ordinary gating clocks CLK.

[0175] First, the control clock generator 510 can generate a falling level control clock FCLK by using the falling control clock MCLK transmitted from the controller 400, and can transmit the falling level control clock FCLK to the level shifter 520 at the timing of generating the lower strobe clock CLKb.

[0176] For example, the control clock generator 510 can shift the phase of the falling control clock MCLK transmitted from the controller 400 to generate a falling level control clock FCLKb. The method for shifting the phase of the falling control clock MCLK can be one of the various methods currently used for phase shifting clocks.

[0177] The preceding text described an example where the phase of the falling-level control clock FCLKb is opposite to the phase of the falling-level control clock MCLK. However, in this disclosure, the phase of the falling-level control clock FCLKb can be formed to have the same shape as the phase of the falling-level control clock MCLK, or it can be formed to have a width different from that of the falling-level control clock MCLK, and additionally, it can be formed to have various shapes. Furthermore, the falling-level control clock FCLKb can be formed using a clock other than the falling-level control clock MCLK.

[0178] Second, the lower voltage generator 530 can generate a lower voltage Vb corresponding to a lower falling level Vbf by using a falling level control clock FCLK. For this purpose, as... Figure 11 As illustrated, the lower voltage generator 530 may include: a first transistor T1, which includes a first terminal connected to a first resistor R1, a second terminal connected to ground, and a gate for receiving a falling level control clock FCLK; a first resistor R1, which includes a first terminal connected to a second resistor R2 and a second terminal connected to the first transistor T1; a second resistor R2, which includes a first terminal connected to the first resistor R1 and a second terminal connected to ground; and a third resistor R3, which includes a first terminal supplied with a drive voltage VD and a second terminal connected to the first resistor R1 and the second resistor R2, and the first terminals of the first resistor, the first terminals of the second resistor, and the second terminals of the third resistor may be connected to a level shifter 520.

[0179] In this case, the drive voltage VD can be supplied from power supply 700.

[0180] For example, during the period when the normal strobe clock CLK is generated, the falling-level control clock FCLK may not be supplied to the gate of the first transistor T1. Accordingly, the first transistor T1 may be turned on.

[0181] In this case, the resistance of the lower voltage generator 530 can be determined based on the first resistor R1, the second resistor R2, and the third resistor R3. Accordingly, the drive voltage VD can be shifted by the first resistor R1, the second resistor R2, and the third resistor R3 to a voltage corresponding to the falling level Vf, and the voltage corresponding to the falling level Vf can be transmitted to the level shifter 520.

[0182] The level shifter 520 can generate a normal gating clock CLK by using a voltage corresponding to the falling level Vf.

[0183] During the timing of generating the lower strobe clock CLKb, the first transistor T1 can be turned off when the falling-level control clock FCLK generated by the control clock generator 510 is transmitted to the gate of the first transistor T1.

[0184] In this case, the resistance of the lower voltage generator 530 can be determined based on the second resistor R2 and the third resistor R3 instead of the first resistor R1. Accordingly, the drive voltage VD can be shifted by the second resistor R2 and the third resistor R3 to the voltage (hereinafter referred to as the lower voltage) Vb corresponding to the lower drop level Vbf, and the lower voltage Vb corresponding to the lower drop level Vbf can be transmitted to the level shifter 520.

[0185] The level shifter 520 can generate a lower gating clock CLKb by using a lower voltage Vb corresponding to a lower falling level Vbf.

[0186] That is, the lower voltage generator 530 can vary its internal resistance based on the falling level control clock FCLK to generate a lower voltage Vb.

[0187] The specification has described examples where the lower fall level Vbf is higher than the fall level Vf, but in this disclosure, the lower fall level Vbf can be set to be lower than the fall level Vf. That is, based on the characteristics of the display panel, the lower fall level Vbf can be set to be higher or lower than the fall level Vf. Figure 12 In the embodiment shown, the gating signal having a pulse generated based on a lower gating clock CLKb has a different form than the gating signal having a pulse generated based on a normal gating clock CLK. For example, the pulse of the gating signal generated based on the lower gating clock CLKb can have the same width as the pulse of the gating signal generated based on the normal gating clock CLK. Furthermore, the duration for the pulse of the gating signal generated based on the lower gating clock CLKb to decrease from a maximum level to a lower falling level Vbf is the same as the duration for the pulse of the gating signal generated based on the normal gating clock CLK to decrease from a maximum level to a falling level Vf.

[0188] For additional description, a phenomenon may occur where horizontal stripes are shown at the bottom of each touch group. This is because the actual common voltage VCOMd when a gating pulse is supplied to the lower gating line (e.g., the nth gating line) of the touch group TG is less than the actual common voltage VCOMd when a gating pulse is supplied to the ordinary gating line (e.g., the (n-1)th gating line) located at the top of the touch group TG.

[0189] To compensate for this difference, in this disclosure, when it is determined that the nth gating line is darker than the (n-1)th gating line, the lower drop level Vbf can be increased, and therefore, the nth gating line can be brighter.

[0190] Furthermore, in this disclosure, when it is determined that the nth gating line is brighter than the (n-1)th gating line, the lower drop level Vbf can be reduced, thus the nth gating line can be dimmer.

[0191] That is, in this disclosure, the phenomenon of horizontal stripes can be prevented by reducing the brightness difference between the lower gate line of the touch group TG and the ordinary gate line set at its upper end.

[0192] In this case, the voltage difference between the lower drop level Vbf and the drop level Vf can vary based on the magnitude of each of the minimum level Vmin, the maximum level Vmax, and the drop level Vf, and can be, for example, one of 3 V and 4 V.

[0193] Third, the level shifter 520 can generate a lower gating clock CLKb by using a gating control signal transmitted from the controller 400 and a lower voltage Vb transmitted from the lower voltage generator 530, and can transmit the lower gating clock CLKb to the gating driver 200.

[0194] In this scenario, the gating control signal GCS transmitted from the controller 400 can be directly used to generate a lower gating clock CLKb, or it can be transmitted to the gating driver 200 via the level shifter 520. For example, the gating control signal GCS transmitted from the controller 400 may include a signal that is directly or indirectly used to generate a lower gating clock CLKb, or it may include a signal transmitted to the gating driver 200 via the level shifter 520.

[0195] In addition, the level shifter 520 can generate a normal gating clock CLK by using the gating control signal GCS transmitted from the controller 400, and can transmit the generated normal gating clock CLK to the gating driver 200.

[0196] That is, the level shifter 520 can generate the general strobe clock CLK by using the rising control clock GCLK and the falling control clock MCLK transmitted from the controller 400.

[0197] To generate the normal strobe clock CLK and the lower strobe clock CLKb, the level shifter 520 can be supplied with power of various levels from the power supply 700. For example, the power supply 700 can supply the level shifter 520 with voltages corresponding to the minimum level Vmin, the maximum level Vmax, and the falling level Vf, and the level shifter 520 can use these voltages to generate the normal strobe clock CLK and the lower strobe clock CLKb.

[0198] The power supply 700 can be integrated with the level shifter 520, or as... Figure 8 As illustrated, it can be implemented as a separate element from the level shifter 520.

[0199] For additional description, the level shifter 520 can be supplied with a voltage corresponding to the maximum level Vmax at the rising timing of the rising control clock GCLK, a voltage corresponding to the falling level Vf after the rising and before the falling control clock MCLK falls, and a voltage corresponding to the minimum level Vmin after the falling control clock MCLK falls, thereby generating the normal strobe clock CLK.

[0200] Furthermore, the level shifter 520 can be supplied with a voltage corresponding to the maximum level Vmax during the rising timing of the rising control clock GCLK, a voltage corresponding to the falling level Vbf after the rising timing and before the falling control clock MCLK falls, and a voltage corresponding to the minimum level Vmin after the falling control clock MCLK falls, thereby generating a lower gating clock CLKb. The falling level control clock FCLK can rise and fall at the same timing as the falling control clock MCLK.

[0201] As described above, this disclosure can perform control such that a lower drop level Vbf is higher or lower than a drop level Vf, thereby preventing horizontal stripe defects.

[0202] In the following description, the effects of this disclosure obtained when the lower drop level Vbf is higher or lower than the drop level Vf will be described as examples of this disclosure.

[0203] That is, according to the present disclosure described above, the lower fall level Vbf of the lower gating clock CLKb can be higher than the fall level Vf of the normal gating clock CLK. Accordingly, the lower fall voltage of the lower gating pulse supplied to the lower gating line can be higher than the fall voltage of the normal gating pulse supplied to the normal gating line.

[0204] A lower drop voltage than a higher drop voltage indicates that the lower gating pulse decreases more slowly compared to the normal gating pulse. This means that the reduction in the actual common voltage VCOMd caused by the lower gating pulse is less than the reduction in the actual common voltage VCOMd caused by the lower gating pulse in display devices of the related art.

[0205] For example, Figure 13A An example is given of the actual common voltage VCOMd of the end portion C of a display period in a display device in which touch electrodes are embedded. In this case, the difference between the actual common voltage VCOMd supplied to the normal gate line and the actual common voltage VCOMd supplied to the lower gate line when the end portion C begins (hereinafter referred to as the common voltage difference of the related technology) is illustrated by X.

[0206] For example, Figure 13B An example is given of the actual common voltage VCOMd of the end portion C of a display period in a display device in which touch electrodes are embedded, according to the present disclosure. In this case, the difference between the actual common voltage VCOMd supplied to the normal gate line and the actual common voltage VCOMd supplied to the lower gate line when the end portion C begins (hereinafter referred to as the common voltage difference of the present disclosure) is illustrated by Y.

[0207] In this case, the common voltage difference Y of this disclosure can be less than the common voltage difference of related technologies. According to this disclosure, this can mean that the reduction in the actual common voltage VCOMd is reduced.

[0208] For further description, in related display devices, the lower gating pulse can rapidly decrease to a falling voltage corresponding to the falling level Vf, and the decrease in the actual common voltage VCOMd can be increased due to the rapidly decreasing lower gating pulse. That is, the rapidly decreasing lower gating pulse may affect the touch electrode, and therefore, the actual common voltage may decrease rapidly. In this case, because the actual common voltage VCOMd is lower than the normal common voltage, the brightness of the pixel connected to the lower gating line may be less than the brightness based on the actual data voltage.

[0209] However, in this disclosure, the lower gating pulse can gradually decrease to a lower drop voltage corresponding to the lower drop level Vbf, and the decrease in the actual common voltage VCOMd is reduced due to the gradually decreasing lower gating pulse. That is, the effect of the gradually decreasing lower gating pulse on the touch electrode can be reduced compared to the effect of display devices in related technologies. Accordingly, the brightness of the pixel connected to the lower gating line can be the brightness corresponding to the actual data voltage.

[0210] That is, in this disclosure, in order to compensate for the decrease in the actual common voltage VCOMd supplied to the lower pixel, the lower falling level Vbf of the lower gating clock CLKb can be set higher than the falling level Vf of the normal gating clock. When the lower falling level Vbf of the lower gating clock CLKb is set higher than the falling level Vf of the normal gating clock, the decrease in the actual common voltage VCOMd can be reduced when an image is displayed on the lower gating line. Therefore, the brightness of the lower pixel does not decrease and can be maintained at a level corresponding to the data voltage.

[0211] like Figure 8 and Figure 10 The generator 500 illustrated can be configured independently of the controller 400, or it can be included in the controller 400.

[0212] Furthermore, in the above description, the lower gate line can be defined as a gate line disposed at the lower end of the corresponding touch group, but this disclosure is not limited thereto. That is, the lower gate line can be a gate line disposed at the lower end of the gate lines corresponding to the touch group, and furthermore, it can be a gate line exhibiting horizontal stripe defects.

[0213] For the purpose of further description, regardless of the location of the touch group, the gate line for which a horizontal stripe defect occurs due to a change in the actual common voltage VCOMd can be the lower gate line described above, and the above disclosure can be applied to the lower gate line where a horizontal stripe defect occurs.

[0214] According to this disclosure, defects such as horizontal stripes caused by brightness differences can be prevented from appearing in specific areas of a display panel in which touch electrodes are embedded.

[0215] Specifically, according to this disclosure, when the touch electrodes are divided into touch groups and the display period and touch sensing period are repeated during a frame period, horizontal stripe defects can be prevented at the lower end of each touch group.

[0216] Therefore, according to this disclosure, the yield rate of the display device can be enhanced, and the image quality of the display device can be improved.

[0217] The features, structures, and effects described above are included in at least one embodiment of this disclosure, but are not limited to only one embodiment. Furthermore, the features, structures, and effects described in at least one embodiment of this disclosure can be achieved by combinations or modifications of other embodiments by those skilled in the art. Therefore, any content associated with combinations and modifications should be interpreted as falling within the scope of this disclosure.

[0218] Those skilled in the art will understand that various modifications and variations can be made to this disclosure without departing from its spirit or scope. Therefore, this disclosure is intended to cover modifications and variations thereof, provided they fall within the scope of the appended claims and their equivalents.

[0219] Cross-reference to related applications

[0220] This application claims the benefit of Korean Patent Application No. 10-2021-0189819, filed on December 28, 2021, which is hereby incorporated by reference as fully set forth herein.

Claims

1. A display device with embedded touch electrodes, the display device comprising: The display panel includes a gate line and a touch group including touch electrodes; A generator that generates a down-gated clock corresponding to a down-gated pulse and a normal-gated clock corresponding to a normal-gated pulse. The down-gated pulse is output to the down-gated line in the gated line corresponding to the touch group, and the normal-gated pulse is supplied to the normal-gated lines in the gated line corresponding to the touch group other than the down-gated line. Controller, which supplies a gating control signal to the generator; as well as A gating driver generates gating pulses using the gating control signal, the down-gating clock, and the normal-gating clock, and supplies the gating pulses to the gating line corresponding to the touch group. The shape of the lower strobe clock differs from the shape of each of the ordinary strobe clocks. Each of the touch groups extends parallel to the gate line, and One of the touch groups is adjacent to another of the touch groups in a direction perpendicular to the gate line.

2. The display device according to claim 1, wherein, The generator generates a control clock for generating the next strobe clock based on a strobe control signal transmitted from the controller.

3. The display device according to claim 2, wherein, Each of the normal strobe clock and the down strobe clock is a pulse with a minimum level, a maximum level, and a falling level. Each of the normal strobe clock and the down strobe clock rises from the minimum level to the maximum level and falls from the maximum level to the down level based on the control clock, and then falls back to the minimum level. The period during which the maximum level drops to the decreasing level is the falling period.

4. The display device according to claim 1, wherein, The generator makes the falling period of the down-gated clock different from the falling period of each of the normal-gated clocks.

5. The display device according to claim 4, wherein, The generator generates a lower fall control clock with a width different from the fall control clock used to control the fall period of each of the ordinary strobe clocks, and The lower strobe clock begins to fall from the timing of the rise of the lower strobe control clock and continues to fall until the timing of the fall of the lower strobe control clock reaches the falling level.

6. The display device according to claim 5, wherein, The interval between the normal strobe clock generated before the next strobe clock and the next strobe clock is equal to the interval between the normal strobe clocks.

7. The display device according to claim 5, wherein, The interval between the normal strobe clock generated before the next strobe clock and the next strobe clock is different from the interval between the normal strobe clocks.

8. The display device according to claim 7, wherein, The generator generates a lower rising control clock with a width different from the rising control clock used to control the rising timing of a normal strobe clock, and The lower strobe clock rises during the timing of the rise of the lower control clock.

9. The display device according to claim 1, wherein, The generator includes: A control clock generator that generates a lower falling control clock with a width different from the falling control clock transmitted from the controller; and A level shifter that, by using the lower falling control clock, makes the falling period of the lower strobe clock different from the falling period of each of the ordinary strobe clocks.

10. The display device according to claim 9, wherein, The level shifter generates the down-gated clock by using a gating control signal transmitted from the controller and a down-feed control clock transmitted from the generator, and transmits the generated down-gated clock to the gating driver.

11. The display device according to claim 1, wherein, The generator shifts the level to which the down-selection clock drops to a different level than the level to which the normal selection clock drops.

12. The display device according to claim 11, wherein, The generator generates a falling level control clock to shift the falling level of the down-select clock based on a falling control clock used to control the falling period of the down-select clock, and The generator shifts the level to which the down-select clock drops based on the falling level control clock.

13. The display device according to claim 12, wherein, The width and timing of the falling level control clock are equal to the width and timing of the falling control clock.

14. The display device according to claim 12, wherein, The generator increases the voltage of the normal gating clock from a minimum level to a maximum level, and then, based on the falling control clock, reduces the voltage of the normal gating clock to a falling level that is less than the maximum level but greater than the minimum level, in order to generate the normal gating clock. The generator generates the normal strobe clock, increases the voltage of the down-strobe clock from the minimum level to the maximum level, and reduces the voltage of the down-strobe clock to a lower falling level that is less than the maximum level and greater than the falling level based on the falling control clock, thereby generating the down-strobe clock. The generator generates a lower falling voltage corresponding to the lower falling level based on the falling level control clock generated simultaneously with the falling control clock.

15. The display device according to claim 11, wherein, The interval between the normal strobe clock generated before the next strobe clock and the next strobe clock is equal to the interval between the normal strobe clocks.

16. The display device according to claim 11, wherein, The width of each of the normal strobe clocks is equal to the width of the lower strobe clock.

17. The display device according to claim 14, wherein, The generator includes: A control clock generator generates a falling-level control clock with the same width and timing as the falling control clock transmitted from the controller; A lower voltage generator, wherein the lower voltage generator generates a lower voltage corresponding to the lower falling level by using the falling level control clock; and A level shifter that, based on the lower voltage, causes the lower strobe clock to fall to a level different from the level fallen to by each of the normal strobe clocks.

18. The display device according to claim 17, wherein, The level shifter generates the down-gated clock by using a gating control signal transmitted from the controller and the down-voltage transmitted from the down-voltage generator, and transmits the down-gated clock to the gating driver.

19. The display device according to claim 1, wherein, The lower gate line is positioned between the touch group corresponding to the lower gate line and another touch group adjacent to the touch group.

20. The display device according to claim 1, wherein, An image is displayed on a first area corresponding to the touch group. Then, a touch applied to the first area is sensed using touch electrodes included in the first area. After a touch is sensed in the first region, an image is displayed in a second region corresponding to another touch group adjacent to the first touch group, and after the image is displayed in the second region, a touch applied to the second region is sensed by using touch electrodes included in the second region.

21. The display device according to claim 1, wherein, A brightness difference occurs between the pixel corresponding to the lower gate line and the pixel corresponding to the normal gate line.

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