Write request buffer

Abstract

This application relates to write request buffers. The described devices and methods relate to write request buffers for memory systems that can support non-deterministic protocols. A host device and a connected memory device can include a controller with a read queue and a write queue. The controller includes a write request buffer for buffering write addresses and write data associated with write requests directed to the memory device. The write request buffer can include a write address buffer that stores unique write addresses and a write data buffer that stores the most recent write data associated with the unique write addresses. An incoming read request is compared to the write requests stored in the write request buffer. If a match is found, the write request buffer can service the requested data without forwarding the read request downstream to a backend memory. Thus, the write request buffer can improve latency and bandwidth when accessing a memory device via an interconnect.

Description

Technical Field

[0001] This disclosure relates to a write request buffer. Background Technology

[0002] Computers, smartphones, and other electronic devices rely on processors and memory. The processor executes code based on data to run applications and deliver features to the user. The processor obtains code and data from memory. Memory in electronic devices can include volatile memory (such as random access memory (RAM)) and non-volatile memory (such as flash memory). Similar to the number of cores or speed of a processor, the rate at which data can be accessed and the latency during data access can affect the performance of an electronic device.

[0003] The demand for memory in electronic devices continues to evolve and grow. For example, as manufacturers design processors to execute code faster, processors benefit from faster access to data in memory. Applications on electronic devices also operate on increasingly larger datasets that require ever-growing amounts of memory. Summary of the Invention

[0004] One embodiment of this disclosure provides an apparatus comprising: a link controller coupled to an interconnect, the link controller being configured to manage signaling instructing write and read requests to be directed to a memory device connected to the interconnect; and a write request buffer configured to: store an address and data associated with the write request; and compare the address associated with the read request with the address stored in the write request buffer.

[0005] Another embodiment of this disclosure provides a method comprising: receiving at a controller a signaling instruction to be directed to a write request to a memory device, the write request comprising an address and data; determining, by a write request buffer of the controller, that the address of the write request is different from one or more stored write requests in the write request buffer; and, in response to determining that the address of the write request is different, storing the write request in the write request buffer; or, in response to determining that the address of the write request is not different, removing information from the write request buffer, invalidating the information, or overwriting the information and storing the write request in the write request buffer, the information being included in the stored write request and having the same address as the address of the write request.

[0006] Another embodiment of this disclosure provides a method comprising: receiving at a controller a signaling instruction indicating a read request, the signaling being received from a host device and directed to a memory device, the read request including addresses associated with a plurality of addresses of the memory device; determining, by a write request buffer of the controller, that the addresses of the read request match addresses associated with one or more write requests stored in the write request buffer; and, in response to determining that the addresses of the read request match addresses associated with the one or more write requests stored in the write request buffer, adding the read request or the signaling instruction indicating the read request to a response queue associated with the host device; or, in response to determining that the addresses of the read request do not match addresses associated with the one or more write requests stored in the write request buffer, transmitting the read request or the signaling instruction indicating the read request to a read queue associated with the memory device.

[0007] Another embodiment of this disclosure provides an apparatus comprising: at least one memory array; and a controller coupled to the at least one memory array and configured to manage signaling instructing write requests and read requests received from a host device via interconnects and directed to the at least one memory array; and a write request buffer configured to: store an address and data associated with the write request; and compare the address associated with the read request with the address stored in the write request buffer. Attached Figure Description

[0008] This document refers to the following diagrams describing the devices and technologies used for write request buffers. The same labels are used in all diagrams to refer to the same features and components:

[0009] Figure 1 An example device is shown that can implement a write request buffer;

[0010] Figure 2 An example computing system is shown that can implement aspects of a write request buffer with a memory device;

[0011] Figure 3 Example memory device is shown;

[0012] Figure 4 An example of a system is shown, comprising a host device and a memory device coupled together via interconnects;

[0013] Figure 5 This shows the instance schema of the write request buffer;

[0014] Figure 6 A flowchart illustrating an instance of a process in response to a write request from an aspect that implements a write request buffer; and

[0015] Figure 7 A flowchart illustrates an instance of a process in response to a read request from an aspect that implements a write request buffer. Detailed Implementation

[0016] Overview

[0017] Processors and memory work in tandem to deliver features in computers and other electronic devices, including smartphones. Electronic devices often offer enhanced features such as high-resolution graphics and artificial intelligence due to the faster tandem operation of the processor and memory. Some applications, such as those for artificial intelligence and virtual reality graphics, require ever-increasing amounts of memory. Advances in processors have often outpaced advancements in the connection between processors and memory.

[0018] The processor and memory can be mounted to a printed circuit board (PCB), such as a motherboard. A PCB may contain sockets for accepting at least one processor and one or more memory modules, as well as various wiring infrastructures to enable communication between the two or more components. However, the area provided by a PCB for sockets and wiring infrastructure is limited. Some PCBs contain sockets shaped as linear slots and designed to accept multiple dual in-line memory modules (DIMMs). These sockets can be fully occupied by the DIMMs, while the processor can still utilize more memory. In such cases, if more memory is available, the system can have improved performance.

[0019] The printed circuit board may also include at least one peripheral component interconnect (PCI) high-speed (PCI) (PCIe) slots. PCIe is designed to provide a common interface for various types of components that can be coupled to a PCB. Compared to some older standards, PCIe offers higher data transfer rates or a smaller footprint on a PCB, combining both higher speed and smaller size. PCIe links can interconnect processors and peripheral memory devices at increased speeds compared to older standards. Therefore, some PCBs enable the processor to access memory devices connected to the PCB via PCIe slots.

[0020] However, PCIe links have limitations in environments with large pools and devices requiring high bandwidth and low latency. For example, PCIe links do not specify mechanisms to support coherence and often cannot efficiently manage isolated pools of memory. Furthermore, the latency of PCIe links can be too high to efficiently manage shared memory access across multiple devices within a system.

[0021] Therefore, using only the PCIe protocol to access memory may not provide as much functionality, flexibility, or reliability as required. In such cases, another protocol can be layered on top of the PCIe protocol. Another example of a higher-level protocol is the Computing High-Speed ​​Link (CXL) protocol or standard (hereinafter referred to as the "CXL protocol" or "CXL standard"). The CXL protocol can be implemented above the physical layer governed by, for example, the PCIe protocol. The CXL protocol is designed for processor- and memory-intensive workloads (e.g., accelerators, memory expanders) where efficient, coherent memory access or interaction between the processor and memory is required. The CXL protocol addresses some of the limitations of the PCIe link by providing an interface that utilizes the PCIe 5.0 physical layer and electrical devices, while providing a low-latency path for memory access and coherent cache storage between the processor and memory devices. It provides high-bandwidth, low-latency connectivity between host devices (e.g., processors, CPUs, SoCs) and memory devices (e.g., accelerators, memory expanders, memory buffers, smart input / output (I / O) devices). The CXL protocol also addresses growing high-performance computing workloads by supporting heterogeneous processing and memory systems with potential applications in artificial intelligence, machine learning, communication systems, and other high-performance computing.

[0022] Various electronic devices, such as mobile phones with System-on-Chip (SoC) or cloud computing servers with dozens of processing units, may employ memory coupled to a processor via CXL-based interconnects (which may be referred to as "CXL links" in this document). For clarity, consider a device having a host device coupled to a memory device via a CXL link. The host device may include a processor and a controller (e.g., a host-side controller) coupled to the interconnects. The memory device may include another controller (e.g., a memory-side controller) coupled to the interconnects and one or more memory arrays for storing information in static RAM (SRAM), dynamic RAM (DRAM), flash memory, etc.

[0023] During operation, the host-side controller sends a memory request to the memory-side controller via the interconnect. The memory request can be a read request or a write request. The memory-side controller receives the request and, directly or indirectly, uses the memory array to fulfill the memory request with a memory response. Therefore, the host-side controller sends a memory response to the memory-side controller via the interconnect. To fulfill a read request, the memory-side controller returns the requested data as a memory response. To fulfill a write request, the memory-side controller can acknowledge that the write operation has been completed as a memory response.

[0024] While the CXL protocol addresses the high latency issue of PCIe links, read requests from the processor can still experience considerable latency due to chip encapsulation and decapsulation of requests and responses via the CXL link (e.g., at the CXL initiator and CXL device), as well as various other queuing and scheduling delays. Furthermore, chip payload overhead reduces the effective bandwidth of the CXL link.

[0025] Furthermore, CXL links can introduce additional latency associated with the placement of the memory controller. For example, conventional DIMM-attached systems connect memory directly to the processor to optimize memory access latency by implementing access methods primarily in the memory controller. This design typically reduces memory access latency attributable to page hits and page conflicts. However, in systems with CXL links, the memory controller operates after the processor (e.g., a CXL initiator) sends a request to the memory device (e.g., a CXL device) as a chip via the CXL link. Once the chip is unpacked at the memory device, the request is forwarded to the memory controller. Therefore, in a CXL system, a request (e.g., a read request) can introduce latency from different blocks in the transport chain before it reaches the memory controller and back-end memory. Simulation data shows that after a request is packaged as a chip and received by the memory device, the processor in a CXL system introduces up to 70% to 80% read latency.

[0026] To improve the performance of CXL systems, this document describes write request buffers. For example, a link controller (such as a CXL controller) may employ write request buffers along the write request path to store unique write requests and associated write data. Write request buffers can be contained within the link controller of a host device (such as a processor, CXL initiator) or anywhere along the write request path (such as the CXL controller or CXL target of a memory device). Write request buffers store write requests along with the write data, rather than flushing the write request once it is transferred across the interconnect to the memory device or otherwise forwarded downstream toward the back-end memory.

[0027] At least a portion of the write request buffer may also be coupled along the read request path. The address of an incoming host read is compared to the write address of a write request stored in the write request buffer. If a match is found, the read request can bypass the interconnect and be fulfilled without being sent to the memory device via the interconnect. The described write request buffer can improve performance metrics (e.g., both memory bandwidth and latency) for memory access performed by the host device. For example, processor read latency can be improved by approximately 20% to 40%, and processor bandwidth can be improved by approximately 5% to 10%.

[0028] Instance operating environment

[0029] Figure 1 Overall, an instance device 102, illustrated as 100, is shown as an example device that can implement a write request buffer. Device 102 may include various types of electronic devices, including Internet of Things (IoT) devices 102-1, tablet devices 102-2, smartphones 102-3, laptop computers 102-4, passenger vehicles 102-5, server computers 102-6, and server clusters 102-7, which may be part of cloud computing infrastructure or data centers or portions thereof (e.g., printed circuit boards (PCBs)). Other instances of device 102 include wearable devices (e.g., smartwatches or smart glasses), entertainment devices (e.g., set-top boxes, video hardware protection devices, smart TVs, gaming devices), desktop computers, motherboards, blade servers, consumer appliances, vehicles, drones, industrial equipment, security devices, sensors, or electronic components thereof. Each type of device may include one or more components to provide computing functionality or features.

[0030] In an example implementation, device 102 may include at least one host device 104, at least one interconnect 106, and at least one memory device 108. Host device 104 may include at least one processor 110, at least one cache memory 112, and a link controller 114. Memory device 108, which may also be a memory module, may include, for example, a dynamic random access memory (DRAM) die or module (e.g., low-power dual data rate synchronous DRAM (LPDDR SDRAM)). The DRAM die or module may include a three-dimensional (3D) stacked DRAM device, which may be a high-bandwidth memory (HBM) device or a hybrid memory cube (HMC) device. Memory device 108 may operate as the main memory of device 102. Although not shown, device 102 may also include storage memory. Storage memory may include, for example, storage-type memory devices (e.g., flash memory, hard disk drive, solid-state drive, phase-change memory (PCM), or those employing 3D XPoint). TM (memory).

[0031] Processor 110 is operatively coupled to cache memory 112, which is operatively coupled to link controller 114. Processor 110 is also directly or indirectly coupled to link controller 114. Host device 104 may include other components to form, for example, a system-on-a-chip (SoC). Processor 110 may include a general-purpose processor, central processing unit (CPU), graphics processing unit (GPU), neural engine or accelerator, application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) integrated circuit (IC), or communication processor (e.g., modem or baseband processor).

[0032] In operation, link controller 114 may provide a higher-level or logical interface between processor 110 and at least one memory (e.g., external memory). Link controller 114 may, for example, receive memory requests from processor 110 and provide the memory requests to external memory in a suitable format, timing, and reordering manner. Link controller 114 may also forward responses to memory requests received from external memory to processor 110.

[0033] Host device 104 is operatively coupled to memory device 108 via interconnect 106. In some instances, memory device 108 is connected to host device 104 via interconnect 106 having an interlock buffer or cache memory. Memory device 108 is operatively coupled to storage memory (not shown). Host device 104 may also be directly or indirectly coupled to memory device 108 and storage memory via interconnect 106. Interconnect 106 and other interconnects ( Figure 1 (Not shown) Data can be transferred between two or more components of device 102. Examples of interconnect 106 include a bus, a switching structure, or one or more wires carrying voltage or current signals.

[0034] Interconnect 106 may include at least one command and address bus 122 (CA bus 122) and at least one data bus 124 (DQ bus 124). Each bus may be unidirectional or bidirectional. The CA bus 122 and DQ bus 124 may be coupled to the CA and DQ pins of the memory device 108, respectively. In some embodiments, interconnect 106 may also include a chip select (CS) I / O. Figure 1 (Not shown in the image), which may be coupled, for example, to one or more CS pins of memory device 108. Interconnect 106 may also include a clock bus (CK bus— Figure 1 (not shown in the image), which is part of or separate from the CA bus 122.

[0035] Interconnector 106 may be a CXL link. In other words, interconnector 106 may conform to at least one CXL standard or protocol. A CXL link may provide an interface on top of the physical layer and electrical devices of the PCIe 5.0 physical layer. A CXL link may allow requests to memory device 108 and responses from said memory device to be encapsulated as microchips. Regarding... Figure 4 An example implementation of device 102 with a CXL link is discussed in more detail. In other implementations, interconnect 106 may be another type of link, including a PCIe 5.0 link. In this document, for clarity, some terms may be taken from one or more of these standards or versions thereof, such as the CXL standard. However, the principles described also apply to memories and systems conforming to other standards and interconnects.

[0036] The components shown in device 102 represent an instance architecture with a hierarchical memory system. A hierarchical memory system may contain memories at different tiers, each with a different speed or capacity. As shown, cache memory 112 logically couples processor 110 to memory device 108. In the shown embodiment, cache memory 112 is at a higher tier than memory device 108. Storage memory may be at a lower tier than main memory (e.g., memory device 108). Memory at a lower tier may have a reduced speed but increased capacity compared to memory at a higher tier.

[0037] Device 102 can be implemented in various ways to have more, fewer, or different components. For example, host device 104 may include multiple cache memories (e.g., cache memories with multiple tiers) or no cache memory. In other embodiments, host device 104 may omit processor 110 or link controller 114. Memory (e.g., memory device 108) may have “internal” or “local” cache memory. As another example, device 102 may include cache memory between interconnect 106 and memory device 108. Computer engineers may also include the illustrated components in a distributed or shared memory system.

[0038] Computer engineers can implement host device 104 and various types of memory in a variety of ways. In some cases, host device 104 and memory device 108 may be mounted on or physically supported by a PCB (e.g., a rigid or flexible motherboard). Host device 104 and memory device 108 may also be integrated onto an IC or fabricated on a separate IC packaged together. Memory device 108 may also be coupled to multiple host devices 104 via one or more interconnects 106 and may respond to memory requests from two or more host devices 104. Each host device 104 may include a corresponding link controller 114, or multiple host devices 104 may share a link controller 114. This document references... Figure 2 An instance computing system architecture is described, having at least one host device 104 coupled to a memory device 108.

[0039] Two or more memory components (e.g., modules, dies, memory banks, or groups of memory banks) may share the electrical path or coupling of interconnect 106. In some embodiments, CA bus 122 transmits addresses and commands from link controller 114 to memory device 108, which may exclude data propagation. DQ bus 124 may propagate data between link controller 114 and memory device 108. Memory device 108 may also include link controller 118, similar to link controller 114 of host device 104. Link controllers 114 and 118 may, for example, encapsulate and decapsulate requests and responses in a suitable format (e.g., as microchips) for transmission via interconnect 106. Memory device 108 includes memory 120, which may contain multiple memory banks ( Figure 1 (Not shown in the image). The memory device 108 may also be implemented as any suitable memory, including but not limited to DRAM, SDRAM, three-dimensional (3D) stacked DRAM, DDR memory, or LPDDR memory (e.g., LPDDR DRAM or LPDDR SDRAM).

[0040] Memory device 108 may form at least a portion of the main memory of device 102. However, memory device 108 may form at least a cache memory, storage memory, or a SoC of device 102. In some embodiments and as per [reference to...] Figure 2 As discussed in more detail, the write request buffer 116 may also be incorporated into the memory device 108 at the link controller 118 or at another functional location between the interconnect 106 and the memory 120.

[0041] like Figure 1 As shown, link controller 114 may include write request buffer 116. For example, link controller 114 (e.g., a CXL controller) may employ write request buffer 116 in the write request path to store unique write requests and their data. Write request buffer 116 may be included in the CXL controller of host device 104 (e.g., a CXL initiator) or anywhere along the write request path (e.g., link controller 118 of memory device 108). Write request buffer 116 may store write requests and associated write data, rather than flushing write requests once they are transferred across interconnect 106 to memory device 108. Write request buffer 116 may compare incoming read requests with write requests stored in write request buffer 116. If a match is found, then the read request may bypass interconnect 106, and the read request may be serviced by write request buffer 116 to improve performance metrics (e.g., both bandwidth and latency for host device 104). For example, the read latency of host device 104 can be improved by about 20% (20) to 40% (40), while the host bandwidth can be improved by about 5% to 10%.

[0042] Figure 2 An example computing system 200 is shown that can implement a write request buffer in a memory device. In some embodiments, the computing system 200 includes at least one memory device 108, at least one interconnect 106, and at least one processor 218. In the illustrated embodiment, a write request buffer 206 is included in or on the memory device 108.

[0043] Memory device 108 may include at least one memory array 216, at least one interface 202, and a control circuitry system 204 operatively coupled to, or associated with, the memory array 216. Memory device 108 may correspond to... Figure 1 The device 102 comprises one or more of a cache memory, main memory, or storage memory. Therefore, the memory array 216 may include an array of memory cells, including, but not limited to, memory cells of DRAM, SDRAM, 3D stacked DRAM, DDR memory, low-power DRAM, or LPDDR SDRAM. For example, the memory array 216 may include memory cells of SDRAM configured as memory modules, with one channel containing 16 or 8 data (DQ) signals, dual data rate input / output (I / O) signaling, and supporting a supply voltage of 0.3 to 0.5V. The density of the memory device 108 may range, for example, from 2Gb to 32Gb. The memory array 216 and the control circuitry 204 may be components on a single semiconductor die or on individual semiconductor dies. The memory array 216 or the control circuitry 204 may also span multiple dies.

[0044] Control circuitry system 204 may include various components that can be used by memory device 108 to perform various operations. These operations may include communicating with other devices, managing memory performance, and performing memory read or write operations. For example, control circuitry system 204 may include one or more registers 208, at least one example of array control logic 210, controller 212, and clock circuitry system 214. Register 208 may be implemented as, for example, one or more registers (e.g., a write-mask enable register) that can store information to be used by control circuitry system 204 or another part of memory device 108. Array control logic 210 may be a circuitry providing command decoding, address decoding, input / output functions, amplification circuitry, power supply management, power control modes, and other functions. Clock circuitry system 214 may synchronize various memory components with one or more external clock signals provided via interconnect 106, said external clock signals including command / address clocks or data clocks. Clock circuitry system 214 may also use internal clock signals to synchronize memory components.

[0045] Controller 212 includes a write request buffer 206. For example, controller 212 may employ write request buffer 206 in the write request path to store unique write requests and their data. Write request buffer 206 may be included in the link controller of memory device 108 (e.g., a CXL controller) or anywhere along the write request path between interface 202 and memory array 216. As described with respect to write request buffer 116, write request buffer 206 may store write requests and associated write data, rather than flushing the write request once it is transferred to memory array 216. Write request buffer 206 may compare incoming read requests with write requests stored in write request buffer 206. If a match is found, the read request may bypass downstream components or functionality of memory device 108, and the read request may be serviced by write request buffer 206 to improve performance metrics (e.g., both bandwidth and latency for at least one processor 218).

[0046] Interface 202 can directly or indirectly couple the control circuitry 204 or the memory array 216 to the interconnect 106. For example... Figure 2 As shown, register 208, array control logic 210, controller 212, and clock circuitry 214 may be part of a single component (e.g., control circuitry 204). In other embodiments, one or more of register 208, array control logic 210, controller 212, or clock circuitry 214 may be separate components on a single semiconductor die or spanning multiple semiconductor dies. These components may be individually or jointly coupled to interconnect 106 via interface 202.

[0047] Interconnector 106 may use one or more of a variety of interconnects that communicatively couple various components together and enable commands, addresses, or other information and data to be transferred between two or more components (e.g., between memory device 108 and processor 218). Although in Figure 2 Interconnector 106 is shown as a single line, but interconnector 106 may include at least one bus, at least one switching structure, one or more wires or traces carrying voltage or current signals, at least one switch, one or more buffers, etc. Furthermore, interconnector 106 may be separated into at least a CA bus 122 and a DQ bus 124 (e.g., Figure 1 As shown above (as indicated). Figure 1 As discussed, interconnect 106 can be a CXL link or conform to at least one CXL standard. A CXL link can provide an interface on top of the physical layer and electrical devices of the PCIe 5.0 physical layer.

[0048] In some aspects, memory device 108 may be relative to ( Figure 1The memory device 108 is a "separate" component of the host device 104 or any processor 218. This separate component may include a PCB, memory card, memory stick, and memory module (e.g., a single in-line memory module (SIMM) or a dual in-line memory module (DIMM)). Therefore, the separate physical components may reside together within the same housing of the electronic device, or may be distributed across server racks, data centers, etc. Alternatively, the memory device 108 may be integrated with other physical components containing the host device 104 or processor 218, either on a PCB or in a single package or SoC.

[0049] The designed devices and methods are adaptable to memories designed for low-power operation or energy-efficient applications. Examples of memory standards related to low-power applications include the LPDDR standard for SDRAM, as published by the Joint Electronics Equipment and Materials Engineering Committee (JEDEC) Solid State Technology Association. In this document, for clarity, some terms may be taken from one or more of these standards or their versions, such as the LPDDR5 standard. However, the principles described also apply to memories that conform to other standards that include other LPDDR standards (e.g., earlier or future versions of LPDDR6), and to memories that do not conform to standards.

[0050] like Figure 2 As shown, processor 218 may include a computer processor 218-1, a baseband processor 218-2, and an application processor 218-3 coupled to memory device 108 via interconnect 106. Processor 218 may include a CPU, GPU, SoC, ASIC, or FPGA, or form part thereof. In some cases, a single processor may include multiple processing resources, each dedicated to a different function (e.g., modem management, application, graphics, central processing). In some embodiments, baseband processor 218-2 may include or be coupled to a modem (…). Figure 2 (Not shown in the image) and is referred to as a modem processor. The modem or baseband processor 218-2 can be connected via, for example, a cellular network. Near-field or another technology or protocol used for wireless communication is wirelessly coupled to the network.

[0051] In some embodiments, processor 218 may be directly connected to memory device 108 (e.g., via interconnect 106). In other embodiments, one or more of processors 218 may be indirectly connected to memory device 108 (e.g., via a network connection or through one or more other devices). Furthermore, similar to... Figure 1 The processor 218 is implemented using a processor 110. Therefore, the corresponding processor 218 may include components similar to... Figure 1The link controller 114 shown is a corresponding link controller or associated with it. Alternatively, two or more processors 218 may use the shared link controller 114 to access the memory device 108.

[0052] Example technology and hardware

[0053] Figure 3 Example memory device 300 is shown. Example memory module 302 includes a plurality of dies 304. As shown, memory module 302 includes a first die 304-1, a second die 304-2, a third die 304-3, and a D-th die 304-D, where "D" represents a positive integer. As several examples, memory module 302 may be a SIMM or a DIMM. As another example, memory module 302 may interface with other components via a bus interconnect (e.g., a Peripheral Component Interconnect High Speed ​​(PCIe) bus). Figure 1 and 2 The memory device 108 shown may correspond, for example, to a single die 304, a plurality of dies 304-1 to 304-D, or a memory module 302 having at least one die 304. As shown, the memory module 302 may include one or more electrical contacts 306 (e.g., pins) to interface the memory module 302 to other components.

[0054] The memory module 302 can be implemented in various ways. For example, the memory module 302 may include a PCB, and multiple dies 304-1 to 304-D may be mounted or otherwise attached to the PCB. The dies 304 (e.g., memory dies) may be arranged in a line or along two or more dimensions (e.g., forming a grid or array). The dies 304 may have similar sizes or may have different sizes. Each die 304 may be similar to another die 304 or unique in size, shape, data capacity, or control circuitry. The dies 304 may also be located on one or more sides of the memory module 302.

[0055] Figure 4 An example of system 400 is shown, which includes a host device 104 and a memory device 108 coupled together via interconnect 106. System 400 can be configured as follows: Figure 1 The device 102 shown in the diagram represents at least a portion of the device 102. As shown, the host device 104 includes a processor 110 and a link controller 114, which can be implemented using at least one initiator 402. Thus, the initiator 402 can be coupled to the processor 110 or to the interconnect 106 (including coupling to both), and the initiator 402 can be coupled between the processor 110 and the interconnect 106. Instances of the initiator 402 may include a preamble component, a main component, a master component, a primary component, etc.

[0056] In the illustrated example system 400, memory device 108 includes a link controller 118 that can be implemented using at least one target 404. Target 404 can be coupled to interconnect 106. Thus, target 404 and initiator 402 can be coupled to each other via interconnect 106. Examples of target 404 may include follower components, secondary components, dependent components, responsive components, etc. Memory device 108 also includes memory 120, which can be implemented using at least one memory module such as DRAM 410 or other components, as further described below.

[0057] In an example implementation, initiator 402 includes link controller 114, and target 404 includes link controller 118. Link controller 114 or link controller 118 may facilitate, coordinate, initiate, or otherwise control signaling across a physical or logical link implemented by interconnect 106 according to one or more protocols. Link controller 114 may be coupled to interconnect 106. Link controller 118 may also be coupled to interconnect 106. Therefore, link controller 114 may be coupled to link controller 118 via interconnect 106. Each link controller 114 or 118 may, for example, control communication via interconnect 106 at the link layer or at one or more other layers of a given protocol. Communication signaling may include, for example, requests 412 (e.g., write requests or read requests), responses 414 (e.g., write responses or read responses), etc.

[0058] The memory device 108 may further include at least one interconnect 406 and at least one memory controller 408 (e.g., MC 408-1 and MC 408-2). Within the memory device 108, and relative to target 404, the interconnect 406, memory controller 408, and / or DRAM 410 (or other memory components) may be referred to as “back-end” components of the memory device 108. In some cases, the interconnect 406 is internal to the memory device 108 and may operate in the same or different manner as the interconnect 406.

[0059] As shown, memory device 108 may include multiple memory controllers 408-1 and 408-2 and / or multiple DRAMs 410-1 and 410-2. Although two of each are shown, memory device 108 may include one or more memory controllers and / or one or more DRAMs. For example, memory device 108 may include four memory controllers and 16 DRAMs, such as four DRAMs per memory controller. The memory components of memory device 108 are depicted as DRAMs only as examples, because one or more of the memory components may be implemented as another type of memory. For example, the memory components may include non-volatile memory such as flash memory or PCM. Alternatively, the memory components may include other types of volatile memory such as SRAM. Memory device 108 may also include any combination of memory types.

[0060] In some cases, the memory device 108 may contain the target 404, interconnect 406, at least one memory controller 408, and at least one DRAM 410 within a single housing or other enclosure. However, the enclosure may be omitted or may be used with the host device 104, system 400, or ( Figure 1 The housing of device 102 is integrated. Interconnect 406 may be mounted on a PCB. Each of target 404, memory controller 408, and DRAM 410 may be manufactured on at least one IC and packaged together or separately. The packaged IC may be secured to or otherwise supported by the PCB and may be directly or indirectly coupled to interconnect 406. However, components of memory device 108 may be otherwise manufactured, packaged, combined, and / or housed.

[0061] like Figure 4 As shown, target 404, including its link controller 118, is coupleable to interconnect 406. Each memory controller 408 of the plurality of memory controllers 408-1 and 408-2 is also coupled to interconnect 406. Thus, target 404 and each memory controller 408 of the plurality of memory controllers 408-1 and 408-2 can communicate with each other via interconnect 406. Each memory controller 408 is coupled to at least one DRAM 410. As shown, each respective memory controller 408 of the plurality of memory controllers 408-1 and 408-2 is coupled to at least one respective DRAM 410 of the plurality of DRAMs 410-1 and 410-2. However, each memory controller 408 of the plurality of memory controllers 408-1 and 408-2 may be coupled to a plurality of DRAMs 410 or other memory components in a corresponding group.

[0062] Each memory controller 408 may implement one or more memory access protocols to facilitate access to at least one DRAM 410 by reading or writing data based on at least one memory address. The memory controller 408 may increase the bandwidth or reduce the latency for memory access based on the memory type or organization of the memory components, such as the DRAM 410. Multiple memory controllers 408-1 and 408-2 and multiple DRAMs 410-1 and 410-2 may be organized in many different ways. For example, each memory controller 408 may implement one or more memory channels for accessing the DRAM 410. Furthermore, the DRAM 410 may be manufactured to include one or more classes, such as single-class or dual-class memory modules. Each DRAM 410 (e.g., at least one DRAM IC chip) may also include multiple memory banks, such as 8 or 16 memory banks.

[0063] This document now describes an example of a host device 104 accessing memory device 108. The example is described in terms of general access, which may include memory read access (e.g., a retrieval operation) or memory write access (e.g., a storage operation). Processor 110 may provide memory access request 416 to initiator 402. Memory access request 416 may be propagated via a bus or other interconnect within host device 104. This memory access request 416 may be or may include a read request or a write request. Initiator 402, such as its link controller 114, may further format the memory access request to be suitable for interconnect 106. This formatting may be performed based on a physical protocol or logical protocol (both) applicable to interconnect 106. Examples of such protocols are described below.

[0064] Initiator 402 can thus prepare request 412 and transmit request 412 to target 404 via interconnect 106. Target 404 receives request 412 from initiator 402 via interconnect 106. Target 404, including its link controller 118, can process request 412 to determine (e.g., extract or decode) a memory access request. Based on the determined memory access request, target 404 can forward memory request 418 to memory controller 408 via interconnect 406, which in this example is first memory controller 408-1. For other memory accesses, target data can be accessed using a second DRAM 410-2 via second memory controller 408-2.

[0065] The first memory controller 408-1 can prepare a memory command 420 based on a memory request 418. The first memory controller 408-1 can provide the memory command 420 to the first DRAM 410-1 via an interface or interconnect suitable for DRAM or other memory components. The first DRAM 410-1 receives the memory command 420 from the first memory controller 408-1 and can perform the corresponding memory operation. Based on the result of the memory operation, the first DRAM 410-1 can generate a memory response 422. If the memory request 412 is for a read operation, then the memory response 422 can contain the requested data. If the memory request 412 is for a write operation, then the memory response 422 can contain an acknowledgment that the write operation has been successfully performed. The first DRAM 410-1 can return the memory response 422 to the first memory controller 408-1.

[0066] The first memory controller 408-1 receives a memory response 422 from the first DRAM 410-1. Based on the memory response 422, the first memory controller 408-1 can prepare a memory response 424 and transmit the memory response 424 to the target 404 via interconnect 406. The target 404 receives the memory response 424 from the first memory controller 408-1 via interconnect 406. Based on this memory response 424, and in response to the corresponding request 412, the target 404 can formulate a response 414 for the requested memory operation. The response 414 may include read data or write confirmation, and is formulated according to one or more protocols of interconnect 106.

[0067] In response to a memory request 412 from host device 104, target 404 may transmit a response 414 to initiator 402 via interconnect 106. Initiator 402 then receives response 414 from target 404 via interconnect 106. Initiator 402 can thus respond to a “originating” memory access request 416, which in this instance originates from processor 110. To do so, initiator 402 prepares a memory access response 426 using information from response 414 and provides memory access response 426 to processor 110. In this way, host device 104 can obtain memory access services from memory device 108 using interconnect 106. Example aspects of interconnect 106 will now be described.

[0068] Interconnect 106 can be implemented in various ways to enable the exchange of memory-related communications between initiator 402 and target 404. Generally, interconnect 106 can carry memory-related information, such as data or memory addresses, between initiator 402 and target 404. In some cases, either initiator 402 or target 404 (including both) may prepare memory-related information for communication across interconnect 106 by encapsulating such information. Memory-related information may be encapsulated into, for example, at least one packet (e.g., a chip). One or more packets may contain headers with information indicating or describing the contents of each packet.

[0069] In example implementations, interconnect 106 may support, enforce, or implement memory coherence for shared memory systems, cache memories, combinations thereof, etc. Alternatively, interconnect 106 may operate based on a credit allocation system. Ownership of credit enables an entity, such as initiator 402, to transfer another memory request 412 to target 404. Target 404 may return credit to "refill" the credit balance at initiator 402. Credit-based communication schemes across interconnect 106 may be implemented by credit logic of target 404 or by credit logic of initiator 402 (including operations cascaded together). Alternatively, link controller 114 may utilize write request buffer 116 or link controller 118 may utilize write request buffer 206 to improve the latency and bandwidth of initiator 402 when serving read requests from processor 110. References below. Figures 5 to 7 Describe an instance of write request buffer 116 or write request buffer 206.

[0070] System 400, the initiator 402 of host device 104, or the target 404 of memory device 108 may operate according to one or more physical or logical protocols or interface with interconnect 106. For example, interconnect 106 may be built according to the Peripheral Component Interconnect High Speed ​​(PCIe or PCI-e) standard. Applicable versions of the PCIe standard may include 1.x, 2.x, 3.x, 4.0, 5.0, 6.0, and future or alternative versions. In some cases, at least one other standard is layered on top of the physically-oriented PCIe standard. For example, initiator 402 or target 404 may communicate via interconnect 106 according to the Computing High Speed ​​Link (CXL) standard. Applicable versions of the CXL standard may include 1.x, 2.0, and future or alternative versions. The CXL standard may operate based on credits, such as read credits and write credits. In such embodiments, link controller 114 and link controller 118 may be CXL controllers.

[0071] Figure 5An example architecture 500 of a write request buffer is shown. As shown, write request buffer 116 is contained in link controller 114 of host device 104. In other embodiments, write request buffer 116 may be contained in link controller 118 of memory device 108. In still other embodiments, write request buffer 116 may be contained in other functional locations within host device 104 or memory device 108, such as memory controller 408.

[0072] As discussed above, link controller 114 may receive signaling indicating a write request 502 and a read request 504 to be directed to memory 120 (or another memory or another connected memory device of memory 108) of memory device 108. Write requests 502 and read requests 504, or their signaling, may be received directly or indirectly from processor 110 via cache memory 112. Each write request 502 includes an address (which may be referred to herein as a “write address”) and data (which may be referred to herein as “write data”). The write address corresponds to the location within memory 120 where the write data will be written. Each read request 504 includes an address (which may be referred to herein as a “read address”) corresponding to a location within memory 120 from which existing data will be read.

[0073] Write request buffer 116 may include write address buffer 506, write data buffer 508, read hit detector 510, AND gate 512, and multiplexer 514. Write address buffer 506 may be a dedicated portion of write request buffer 116 to store the write address associated with the write request 502 stored in write request buffer 116. Specifically, write address buffer 506 may store the write address associated with a unique write request. For example, if write request buffer 116 receives two write requests 502 with the same write address, then write address buffer 506 has a single entry associated with the write address. In other words, write request buffer 116 or write address buffer 506 stores a single entry for any given write address among multiple addresses associated with memory 120.

[0074] Each write request 502 is also forwarded to write queue 516. Write queue 516 stores or buffers each write request 502. After transmitting a write request 502 across interconnect 106 or forwarding the write request to arbitrator 520, write queue 516 deletes, removes, invalidates, or overwrites the write request. Arbitrator 520 can manage and prioritize read requests 504 to improve read latency of host device 104 when accessing memory 120.

[0075] Write data buffer 508 may be a separate dedicated portion of write request buffer 116 to store write data associated with write requests 502 stored in write request buffer 116. Specifically, write data buffer 508 may store write data associated with unique write requests. For example, if write request buffer 116 receives two write requests 502 with the same write address, then write data buffer 508 has a single entry corresponding to the data of the most recent write request 502 associated with said write address. In other words, write request buffer 116 or write data buffer 508 stores a single most recent data entry for any given write address among a plurality of addresses associated with memory 120. The physical or logical location of the write data in write data buffer 508 may represent or reflect the relative age of the associated write request 502.

[0076] Write data buffer 508 typically has a fixed size (e.g., four kilobytes, eight kilobytes, sixteen kilobytes). The size of write data buffer 508 can be determined based on a multiplexing distance metric. The multiplexing distance metric represents the average number of unique write request entries between incoming read requests 504 and write request buffer 116, which have the same read address as write request 502 stored in write request buffer 116.

[0077] The read hit detector 510 includes a comparator that determines whether the read address associated with a read request 504 booted into memory 120 matches a write address stored in write request buffer 116 or write address buffer 506. The read hit detector 510 may be implemented as hardware, software, fixed circuitry, or other logic to perform the described comparison.

[0078] AND gate 512 can use a logical "AND" operation to gate whether to provide write data stored in write data buffer 508 to response queue 522 based on the output of read hit detector 510. If read hit detector 510 indicates an address match or hit, then AND gate 512 forwards write data from write data buffer 508 to the write address corresponding to the write address in write address buffer 506, which matches the read address of read request 504. In this way, if the read address matches the write address stored in write request buffer 116, then write request buffer 116 can serve the read request without forwarding read request 504 to memory device 108.

[0079] Multiplexer 514 can receive read request 504 as a single input and transmit read request 504 to the appropriate destination based on a hit signal from read hit detector 510. The hit signal indicates whether the read address of read request 504 matches a write address stored in write request buffer 116 or write address buffer 506. Based on whether the hit signal indicates a match or not, multiplexer 514 transmits read request 504 to read queue 518 or response queue 522. If the hit signal indicates no match, then multiplexer 514 transmits read request 504 to read queue 518, which forwards the read request to arbitrator 520. Arbitrator 520 can then transmit read request 504 to memory device 108 via interconnect 106. If the hit signal indicates a match, then multiplexer 514 transmits read request 504 to response queue 522. Response queue 522 may combine write data from write request buffer 116 or write data buffer 508 with read request 504 to produce read response 526. Response queue 522 sends read response 526 to processor 110. Generally, read response 526 may be provided by write request buffer 116 as described above or by memory device 108 as read response 524 from memory 120.

[0080] In this way, write request buffer 116 can bypass interconnect 106 and provide read response 526 to host device 104 without sending read request 504 to memory device 108. Write request buffer 116 can improve the bandwidth and latency experienced by host device 104 when accessing memory 120. For example, read latency of processor 110 can be improved by about 20% to 40%, and bandwidth can be improved by about 5% to 10%.

[0081] Instance methods

[0082] This chapter references Figure 6 and 7 The flowcharts and diagrams describe instance methods for implementing write request buffers for the link controller. These descriptions may also refer to... Figures 1 to 5 The components, entities, and other aspects described herein are for reference only by way of examples.

[0083] Figure 6 A flowchart illustrates an example process 600 in response to a write request from an aspect that implements a write request buffer. Process 600 may be implemented at link controller 114 of host device 104 or at link controller 118 of memory device 108. In other embodiments, process 600 may be implemented at different functional locations in the memory access chain (e.g., at the memory controller or other controller in memory device 108).

[0084] At block 602, the controller receives signaling indicating a write request to be directed to the memory device. The write request contains an address and data. For example, device 102 is operable in a package (e.g., host device 104 and memory device 108). The link controller 114 of host device 104 may receive a write request 502 containing a write address and write data. The write request 502 is directed to memory 120 of memory device 108.

[0085] At block 604, the controller's write request buffer determines that the address of the write request is different from one or more stored write requests in the write request buffer. For example, the write request buffer 116 of the link controller 114 may determine whether the write address of write request 502 is different from one or more stored write requests 502 in the write request buffer 116. This can be determined by comparing the write address of write request 502 with a stored write address in write address buffer 506 corresponding to a write address received in one or more other write requests 502 stored in write request buffer 116. Write address buffer 506 may be a dedicated portion of write request buffer 116 to store the write address of write request 502 stored in write request buffer 116. In some embodiments, write address buffer 506 or a dedicated portion of write request buffer 116 may store a single entry for each of a plurality of addresses associated with memory 120 of memory device 108.

[0086] At block 606, a write request buffer stores a write request in response to determining that the address of the write request is different. For example, write request buffer 116 may store write request 502 in response to determining that the write address of write request 502 is different or unique. The write address associated with write request 502 may be stored in write address buffer 506. Similarly, the write data associated with write request 502 may be stored in write data buffer 508, which may be another dedicated portion of write request buffer 116.

[0087] The write request buffer 116 can store the write request 502 at the initial position in the write request buffer 116 or at the initial position in the write address buffer 506 and the write data buffer 508. The position of the write request in the write request buffer 116 can indicate the order in which the write request 502 has been received or stored.

[0088] Write request buffer 116 can also determine that write request buffer 116, write address buffer 506, or write data buffer 508 contains more information than a threshold. The threshold can be the capacity, depth, number of slots, bits, or other units of the storage used for write request buffer 116, write address buffer 506, or write data buffer 508. Write request buffer 116 can also, in response to storing write request 502 and the information that write request buffer 116, write address buffer 506, or write data buffer 508 contains more information than the threshold, remove the write address and write data associated with the oldest write request 502 (e.g., last one), invalidate the write address and write data, delete the write address and write data, or overwrite the write address and write data. For example, if the number of write addresses stored in write address buffer 506 is equal to or exceeds the capacity, depth, slot, or bit size of write address buffer 506, then the threshold may be exceeded. Similarly, if the write data stored in write buffer 116 or write data buffer 508 is equal to or exceeds the capacity, depth, slot, or bit size of write buffer 116 or write data buffer 508, then the threshold may be exceeded.

[0089] At block 608, in response to determining that the address of a write request is not different, the write request buffer removes information from the write request buffer, invalidates or overwrites the information, and stores the write request in the write request buffer. The information is among the stored write requests in the write request buffer and has the same address as the write request. For example, in response to determining that the write address of write request 502 is not different or unique, write request buffer 116 may remove information (e.g., older write request 502) from the write request buffer 116 and store write request 502 in the write request buffer 116. The information (e.g., older write request 502) has the same write address as the write address of write request 502. The write address associated with write request 502 may be stored in write address buffer 506. Similarly, the write data associated with write request 502 may be stored in write data buffer 508.

[0090] Write request buffer 116 can store write request 502 at its initial position. The initial position of write request buffer 116 may correspond to the initial position of write address buffer 506 and the initial position of write data buffer 508. Write request buffer 116 can also remove write data or write address associated with said information (e.g., older write request 502) in response to storing non-unique write request 502.

[0091] Link controller 114 also transmits write request 502 to write queue 516 for transmission to memory device 108. After link controller 114 transmits write request 502 to memory device 108 via interconnect 106, write request buffer 116 stores the write address and write data associated with write request 502.

[0092] Figure 7 A flowchart illustrates an example process 700 in response to a read request from an aspect implementing a write request buffer. Process 700 may be implemented at link controller 114 of host device 104 or at link controller 118 of memory device 108. In other embodiments, process 700 may be implemented at different functional locations in the memory access chain (e.g., at the memory controller or other controller in memory device 108). Link controller 114 may be a CXL controller, and the interconnect 106 between host device 104 and memory device 108 may be a CXL interconnect or conform to at least one CXL standard.

[0093] At block 702, the controller receives signaling indicating a read request received from a host device and directed to a memory device. The read request includes addresses associated with multiple addresses of the memory device. For example, device 102 is operatively packaged (e.g., host device 104 and memory device 108). Link controller 114 of host device 104 may receive read request 504 or signaling indicating the read request, the signaling including a read address associated with one of multiple addresses of memory 120 of memory device 108. Read request 504 is received from host device 104 and directed to memory 120.

[0094] At block 704, the controller's write request buffer determines that the address of a read request matches an address associated with one or more write requests stored in the write request buffer. For example, the write request buffer 116 of link controller 114 may determine whether the read address of read request 504 matches a write address associated with write request 502 stored in write request buffer 116 or write address buffer 506. Read hit detector 510 may compare the read address of read request 504 with the write addresses stored in write request buffer 116 or write address buffer 506, and determine whether the read address matches one of the write addresses associated with write request 502 stored in write request buffer 116.

[0095] At block 706, a write request buffer adds a read request or signaling indicating a read request to a response queue associated with the host device in response to determining that the address of a read request matches an address associated with one or more write requests stored in the write request buffer. For example, in response to determining that the read address of read request 504 matches the write address of write request 502 stored in write request buffer 116 or write address buffer 506, write request buffer 116 adds read request 504 or signaling indicating the read request to response queue 522 associated with the host device 104. Write request buffer 116 or write data buffer 508 also provides data for a read response associated with read request 504 or signaling indicating the read request, the data corresponding to write data in write request buffer 116 or write data buffer 508 having matching write addresses of one or more write requests 502 stored in write request buffer 116. By adding read request 504 or a signaling indicating the read request to response queue 522, write request buffer 116 serves read request 504 and bypasses the interconnect 106 between host device 104 and memory device 108. In this way, write request buffer 116 can improve the latency and bandwidth of host device 104 or processor 110 when accessing memory 120.

[0096] At block 708, a write request buffer transmits a read request or signaling indicating a read request to a read queue associated with the memory device in response to determining that the address of a read request does not match the address associated with one or more write requests stored in the write request buffer. For example, in response to determining that the read address of read request 504 does not match the write address of write request 502 stored in write request buffer 116 or write address buffer 506, write request buffer 116 transmits or adds read request 504 or signaling indicating the read request to read queue 518 associated with memory device 108. Link controller 114 may transmit read request 504 or signaling indicating the read request from read queue 518 to memory device 108 via interconnect 106. Link controller 114 may also encapsulate the read request 504 into a chip before transmitting it to memory device 108 via interconnect 106.

[0097] The order in which operations are shown and / or described in the flowcharts and diagrams described above is not intended to be limiting. Any number or combination of the described process operations can be combined or rearranged in any order to implement a given method or an alternative method. Operations can also be omitted from the described method or added to the described method. Furthermore, the described operations can be implemented in a completely or partially overlapping manner.

[0098] These methods can be implemented, for example, in hardware (e.g., a fixed logic circuit system or a processor incorporating memory), firmware, software, or a combination thereof. The methods can be implemented using… Figures 1 to 5 The diagrams illustrate one or more of the devices or components shown, which may be further divided, combined, rearranged, etc. The devices and components in these diagrams typically represent: hardware, such as electronic devices, packaged modules, IC chips, or circuits; firmware or its operation; software; or combinations thereof. Therefore, these diagrams illustrate some of the many possible systems or devices capable of implementing the described methods.

[0099] Unless the context otherwise specifies, the use of the word “or” herein may be interpreted as the use of “inclusive or”, or as allowing the inclusion or application of a term containing or applying one or more items linked by the word “or” (e.g., the phrase “A or B” may be interpreted as allowing only “A”, only “B”, or both “A” and “B”). Furthermore, as used herein, the phrase referring to “at least one of” a list of items means any combination of those items containing a single member. For example, “at least one of a, b, or c” may cover a, b, c, ab, ac, bc, and abc, as well as any combination having multiples of the same element (e.g., aa, aaa, aab, aac, abb, acc, bb, bbb, bbc, cc, and ccc, or any other ordering of a, b, and c). Additionally, the items represented in the figures and the terms discussed herein may indicate one or more items or terms, and are therefore interchangeable with single or multiple forms of items and terms in this written description.

[0100] in conclusion

[0101] Although this document describes embodiments for a write request buffer in language specific to certain features or methods, the subject matter of the appended claims is not limited to the described features or methods. Instead, this document discloses the described features and methods as example embodiments of the write request buffer.

Claims

1. An apparatus comprising: A link controller coupled to an interconnect, the link controller being configured to manage signaling instructing write and read requests to be directed to memory devices connected to the interconnect; and Write request buffer, which is configured to: The address and data associated with the write request are stored, and the write request stored in the write request buffer has a unique address among a plurality of addresses associated with the memory device; The address and corresponding data associated with the most recent write request are stored at the initial position of the write request buffer; Compare the address associated with the read request with the unique address stored in the write request buffer; and The read request is responded to using the data stored in the write request buffer in response to an address that matches the address associated with the read request in the unique address stored in the write request buffer.

2. The device of claim 1, wherein the write request buffer is configured to store the address and the data associated with the write request after the link controller transmits the write request to the memory device via the interconnect.

3. The device of claim 1, wherein the size of the write request buffer is based on the number of unique write requests between write requests with a write address and read requests with a matching read address.

4. The device of claim 1, wherein the write request buffer is configured to: It is determined that the write request buffer includes information that the amount is greater than a threshold; and In response to storing the address and corresponding data associated with the most recent write request and the write request buffer including information greater than the threshold, the address and corresponding data associated with the oldest write request in the write request buffer are removed, the address and corresponding data are invalidated, or the address and corresponding data are overwritten.

5. The device of claim 1, wherein the buffer depth of the write request buffer is determined based on a multiplexing distance metric, the multiplexing distance metric representing the average number of unique write request entries to the write request buffer between an incoming read request having the same address as a write request stored in the write request buffer and the write request having the same address stored in the write request buffer.

6. The device of claim 1, wherein the write request buffer comprises: A write address buffer, configured to store the unique address associated with the write request; and A write data buffer, configured to store the data associated with the write request.

7. The device of claim 6, wherein the write request buffer further includes a comparator configured to determine whether an address associated with a read request directed to the memory device matches an address in the unique address stored in the write address buffer.

8. The device of claim 1, wherein the link controller further comprises: A write queue, configured to buffer write requests directed to the memory device; and A read queue, configured to buffer read requests directed to the memory device that are not served by the write request buffer.

9. The device of claim 1, wherein the interconnect conforms to at least one Computing High-Speed ​​Link (CXL) standard.

10. The device of claim 9, wherein the link controller includes a CXL controller.

11. The device of claim 9, wherein the memory device comprises a type 1 CXL device, a type 2 CXL device, or a type 3 CXL device.

12. A method comprising: The controller receives a signaling instruction to direct a write request to the memory device, the write request containing an address and data; The address of the write request is determined by the controller's write request buffer to be different from one or more stored write requests in the write request buffer, which includes an initial position; and In response to determining that the address of the write request is different, the write request is stored in the write request buffer at the initial position of the write request buffer; or In response to determining that the address of the write request is not different, information is removed from the write request buffer, the information is invalidated or overwritten, and the write request is stored in the write request buffer at the initial position of the write request buffer, the information being contained in the stored write request and having the same address as the address of the write request.

13. The method of claim 12, wherein determining that the address of the write request is different comprises comparing the address of the write request with a stored address by the write request buffer, the stored address corresponding to an address received in one or more other write requests stored in the write request buffer.

14. The method of claim 13, wherein the stored address is stored in a dedicated portion of the write request buffer.

15. The method of claim 14, wherein the dedicated portion of the write request buffer is configured to store a single entry for each of a plurality of addresses associated with the memory device.

16. The method of claim 12, further comprising: It is determined that the write request buffer includes information that the amount is greater than a threshold; and In response to storing the write request and the write request buffer including information that the amount is greater than the threshold, the address and data associated with the oldest write request are removed from the write request buffer, the address and data are invalidated, or the address and data are overwritten.

17. The method of claim 12, further comprising, in response to determining that the address of the write request is not different, removing the address and data associated with the information from the write request buffer, invalidating or overwriting the address and data in response to storing the write request.

18. The method of claim 12, further comprising: The address associated with the write request is stored in the write address buffer; and The data associated with the write request is stored in the write data buffer.

19. The method of claim 12, wherein the position of the write request in the write request buffer indicates the order in which the write requests have been stored.

20. The method of claim 12, further comprising storing the address and the data associated with the write request in response to the controller transmitting the write request to the memory device.

21. The method of claim 12, wherein the buffer depth of the write request buffer is determined based on a multiplexing distance metric, the multiplexing distance metric representing the average number of unique write request entries to the write request buffer between an incoming read request having the same address as a write request stored in the write request buffer and the write request having the same address stored in the write request buffer.

22. The method of claim 12, wherein the controller comprises a compute high-speed link CXL controller.

23. The method of claim 22, wherein the memory device comprises a type 1 CXL device, a type 2 CXL device, or a type 3 CXL device.

24. A method comprising: The controller stores write requests with unique addresses among multiple addresses of the memory device in its write request buffer; The address and corresponding data associated with the most recent write request are stored at the initial position of the write request buffer; The controller receives a signaling instruction indicating a read request, the signaling being received from the host device and directed to the memory device, the read request containing addresses associated with the plurality of addresses of the memory device; The address of the read request is determined by the write request buffer of the controller to match the address associated with a write request in one or more write requests stored in the write request buffer; and In response to determining that the address of the read request matches the address associated with a write request in one or more write requests stored in the write request buffer, the read request or the signaling indicating the read request is added to a response queue associated with the host device. or In response to determining that the address of the read request does not match the address associated with a write request in one or more write requests stored in the write request buffer, the read request or the signaling indicating the read request is transmitted to the read queue associated with the memory device.

25. The method of claim 24, further comprising providing data for a read response associated with the read request in response to adding the read request or the signaling indicating the read request to the response queue associated with the host device, the data corresponding to data in the write request buffer associated with the address of the one or more write requests stored in the write request buffer, the address matching the address of the read request.

26. The method of claim 25, further comprising bypassing the interconnect between the host device and the memory device in response to adding the read request or the signaling indicating the read request to the response queue associated with the host device.

27. The method of claim 26, wherein the interconnect conforms to at least one compute high-speed link (CXL) standard and the controller includes a CXL controller.

28. The method of claim 24, further comprising transmitting the read request or the signaling indicating the read request to the memory device via an interconnect between the host device and the memory device in response to transmitting the read request or the signaling indicating the read request to the read queue associated with the memory device.

29. The method of claim 28, further comprising encapsulating the read request as a chip in the read queue prior to performing the transfer to the memory device via the interconnect.

30. The method of claim 24, further comprising: The address associated with the write request in one or more write requests stored in the write request buffer is stored in the write address buffer of the write request buffer; and The write data buffer of the write request buffer stores data associated with the write request in one or more write requests stored in the write request buffer.

31. The method of claim 30, further comprising determining, by a comparator of the write request buffer, whether the address of the read request matches the address associated with the write request in one or more write requests stored in the write request buffer.

32. An apparatus comprising: At least one memory array; A controller coupled to the at least one memory array and configured to manage signaling indicating write and read requests received from a host device via interconnects and directed to the at least one memory array; and Write request buffer, which is configured to: The address and data associated with the write request are stored, and the write request stored in the write request buffer has a unique address among a plurality of addresses associated with the at least one memory array; The address and corresponding data associated with the most recent write request are stored at the initial position of the write request buffer; Compare the address associated with the read request with the unique address stored in the write request buffer; and The read request is responded to using the data stored in the write request buffer in response to an address that matches the address associated with the read request in the unique address stored in the write request buffer.

33. The device of claim 32, wherein the write request buffer is configured to store the address and the data associated with the write request after the controller transmits the write request to the at least one memory array.

34. The device of claim 32, wherein the size of the write request buffer is based on the number of unique write requests between write requests with a write address and read requests with a matching read address.

35. The device of claim 32, wherein the write request buffer is configured to: It is determined that the write request buffer includes information that the amount is greater than a threshold; and In response to storing the address and corresponding data associated with the most recent write request and the write request buffer including information greater than the threshold, the address and corresponding data associated with the oldest write request in the write request buffer are removed, the address and the data are invalidated, or the address and the corresponding data are overwritten.

36. The device of claim 32, wherein the buffer depth of the write request buffer is determined based on a multiplexing distance metric, the multiplexing distance metric representing the average number of unique write request entries to the write request buffer between an incoming read request having the same address as a write request stored in the write request buffer and the write request having the same address stored in the write request buffer.

37. The device of claim 32, wherein the write request buffer comprises: A write address buffer, configured to store the unique address associated with the write request; and A write data buffer, configured to store the data associated with the write request.

38. The device of claim 37, wherein the write request buffer further includes a comparator configured to determine whether an address associated with a read request directed to the at least one memory array matches an address in the unique address stored in the write address buffer.

39. The device of claim 32, wherein the controller further comprises: A write queue configured to buffer write requests directed to the at least one memory array; and A read queue configured to buffer read requests directed to the at least one memory array that are not served by the write request buffer.

40. The device of claim 32, wherein the interconnect conforms to at least one Computing High-Speed ​​Link (CXL) standard.

41. The device of claim 40, wherein the controller comprises a CXL controller.

42. The device according to claim 40, wherein the device comprises a type 1 CXL device, a type 2 CXL device, or a type 3 CXL device.

43. The device of claim 32, wherein the write request buffer is coupled between the link controller of the device and the at least one memory array.

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