A multi-core RISC-V system on chip and method for data fusion algorithm

Abstract

The application relates to the field of system on chip (SoC) architecture design, and discloses a multi-core RISC-V system on chip for data fusion algorithms and a method thereof, which comprises a RISC-V large-core processor subsystem, n RISC-V small-core processor subsystems, an arbitrator 1 module, an arbitrator 2 module, an on-chip data storage module, a DDR controller and a debugging interface. After the system on chip is powered on and works, all the processors read all the coordinates of set N from the on-chip data storage under the control of the arbitrator 1, then read a fixed number of coordinates in set M, and then perform statistical distance calculation and threshold comparison between the coordinates, and under the control of the arbitrator 2, the processors store the effective results into a DDR4 SDRAM. After the statistical distance calculation is completed, the large-core processor retrieves all the data and performs clustering processing and auction by a coprocessor, and finally stores the results into the on-chip data storage and notifies a host computer to retrieve. The system realizes multi-core processing acceleration for data fusion algorithms by reasonably designing a data flow and an arbitration structure.

Description

Technical Field

[0001] This invention belongs to the field of system-on-chip (SoC) architecture design technology, and particularly relates to a multi-core RISC-V system-on-chip and method for data fusion algorithms. Background Technology

[0002] The essence of data fusion algorithms is to optimally match and associate elements in datasets M and N, while auction algorithms are used to find the optimal matching relationships. The data fusion algorithm based on auction algorithms can be broadly divided into three parts: statistical distance calculation, clustering processing, and auction-based relationship finding. The algorithm's input consists of two sets of points, M and N, representing three-dimensional coordinates. Statistical distance calculation involves calculating the statistical distance between points in these two sets of coordinates according to a predetermined formula. Clustering processing compares all calculated statistical distance values ​​with a pre-set threshold. If a point P in set M... M With a point P in set N N The statistical distance value is less than the threshold and P M If the statistical distance between a point in set M and all other points in set N is greater than a threshold, then the relationship between these two points is considered a match. If the statistical distance between a point in set M and multiple points in set N is less than a threshold, then the matching relationship between this point and these points cannot be determined. All points with uncertain relationships are recorded and proceed to the next stage of the auction to determine the association relationship. In the auction to determine the association relationship, all unmatched points in set M are first rearranged and numbered as auctioned items, and all unmatched points in set N are rearranged and numbered as bidding items. Then, the generated auctioned items are auctioned sequentially. Each bidder's "profit" is defined as the statistical distance between the two points minus the current bidding price. The bidder with the lowest profit wins the item. If two bidders have the same profit, there will be a bidding stage where the best matching item is selected by increasing the price. Each auctioned item and bidding item can only be matched one-to-one. When a one-to-many match occurs, the auctioned item will be replaced. The algorithm will select the optimal auctioned item to replace it and re-auction the replaced auctioned item.

[0003] Currently, this algorithm runs on a CPU platform, and its main problem is:

[0004] The small area of ​​the CPU's internal arithmetic units makes it unsuitable for large-scale floating-point operations, resulting in low efficiency when handling such operations.

[0005] CPUs can only execute instructions sequentially. When performing statistical distance calculations, one instruction must be completed before the next can be calculated, making parallel computing impossible.

[0006] The clustering process requires comparing all statistical distance calculations with a threshold, which involves traversal operations and takes a long time on the CPU.

[0007] The above issues result in a relatively long overall execution time for the algorithm on the CPU. Summary of the Invention

[0008] This invention provides a multi-core RISC-V on-chip system and method for data fusion algorithms, aiming to solve the problems of long execution time and low efficiency of existing data fusion algorithms on general-purpose processors.

[0009] The technical solution of this invention:

[0010] Firstly,

[0011] This invention provides a multi-core RISC-V system-on-a-chip for data fusion algorithms, characterized in that the system includes: one RISC-V big core processor subsystem, n RISC-V little core processor subsystems, arbitrator 1 module, arbitrator 2 module, on-chip data storage module, DDR controller, and debug interface;

[0012] The one RISC-V big-core processor subsystem and the n RISC-V little-core processor subsystems are respectively connected to the arbitrator 1 module. The one RISC-V big-core processor subsystem and the n RISC-V little-core processor subsystems are respectively connected to the arbitrator 2 module. The arbitrator 1 module is also connected to the on-chip data storage module. The arbitrator 2 module is also connected to the DDR controller. The DDR controller is also connected to the external DDR SDRAM. The on-chip data storage module is also connected to the external data bus.

[0013] Furthermore, the RISC-V big core processor subsystem is used to send a start signal and a calculation completion signal to the host, as well as to execute the statistical distance calculation, clustering processing, and auction association part in the data fusion algorithm, send the calculation result to the DDR SDRAM, and retrieve the final calculation result back to the on-chip data storage module.

[0014] The n RISC-V small core processor subsystems are used to execute the statistical distance calculation and threshold comparison parts in the data fusion algorithm, and send the calculated results to DDR SDRAM;

[0015] The arbitrator 1 module is responsible for arbitrating access requests from each processor subsystem to the on-chip data storage module;

[0016] The arbitrator 2 module is responsible for arbitrating access requests from each processor subsystem to the DDR controller;

[0017] The on-chip data storage module is used to store the raw data sent from the host, as well as the result data after the data fusion algorithm is completed by the five processor subsystems.

[0018] The DDR controller is used for access control of DDR SDRAM by each processor subsystem;

[0019] The debugging interface is used for debugging multi-core RISC-V on-chip systems.

[0020] Furthermore, the RISC-V big core processor subsystem consists of a RISC-V big core processor, a receiver...

[0021] It consists of an interface bus, coprocessor, instruction cache, data cache, Tilelink bus, and BootROM; wherein, the RISC-V big core processor is responsible for sending the computation start signal and the computation completion signal.

[0022] The system performs floating-point operations for statistical distance and threshold comparison, cluster processing of custom instructions, sending custom instructions for auction association, and retrieving the final calculation results from the DDR controller to the on-chip data storage module.

[0023] The coprocessor, as an acceleration device for the RISC-V big core processor, responds to and decodes the custom instructions sent by the big core processor, performs clustering processing and auction correlation calculation, and returns the calculation result.

[0024] The interface bus is used for communication between the RISC-V big core processor and the coprocessor.

[0025] The instruction cache is used to store the processing and arithmetic instructions required by the RISC-V big core processor;

[0026] The data cache is used to store intermediate data during the calculation process;

[0027] The system bus TileLink is used for communication between the RISC-V big core processor and the arbitrator module and debug interface 0.

[0028] The Bootrom is used to store the startup code for the large-core processor.

[0029] Furthermore, the coprocessor is a custom instruction set processor based on the data fusion algorithm, and the custom instructions implemented include clustering processing instructions and auction instructions.

[0030] Furthermore, the RISC-V little core processor subsystem consists of a RISC-V little core processor, an instruction cache, a data cache, a Tilelink bus, and a BootROM;

[0031] The RISC-V small core processor is responsible for performing floating-point operations on distance and threshold comparison, and sending the calculation results to DDR SDRAM.

[0032] The instruction cache is used to store the computation and processing instructions required by the RISC-V small core processor;

[0033] The data cache is used to store intermediate data during the calculation process;

[0034] The system bus TileLink is used for communication between the RISC-V small core processor and the arbitrator module and debug interface;

[0035] The BootRom is used to store the boot code for the small-core processor.

[0036] Furthermore, both the RISC-V big-core processor and the RISC-V little-core processor are equipped with floating-point arithmetic units, supporting FP64 and FP32 floating-point operations.

[0037] Furthermore, the various RISC-V little-core processor subsystems are homogeneous and can be replicated and expanded even with limited resources.

[0038] Furthermore, the arbitrator 1 module adopts two strategies: polling arbitration and interrupt priority arbitration. When each processor performs a data retrieval operation from the on-chip data storage module, polling arbitration is used; when the large core processor needs to send the final calculation result data to the on-chip data storage module, interrupt priority arbitration is used.

[0039] Furthermore, the arbitrator 2 module employs two strategies: polling arbitration and interrupt priority arbitration. When each processor performs a data sending operation to the DDR SDRAM, polling arbitration is used; when the large core processor needs to retrieve the final calculation result data from the DDR SDRAM, interrupt priority arbitration is used.

[0040] Secondly,

[0041] This invention provides a multi-core RISC-V on-chip method for data fusion algorithms, the method being applied to the system described in the first aspect, the method comprising:

[0042] S1. After each processor powers on and resets, the RISC-V big core processor sends a startup standby signal to the host. After receiving the startup signal, the host sends the coordinates of sets M and N to the on-chip system via PCIe through DMA, and stores them in the on-chip data storage module via the AXI-Lite bus.

[0043] S2, under the control of Arbitrator 1 module, each processor sequentially reads all set N coordinates from the on-chip data storage module and stores them in its own data cache. Then, it sequentially reads the coordinates of 10 sets M from the on-chip data storage module. After reading, the processor calls FPU to perform statistical distance calculation between these 10 coordinates and all coordinates in set N.

[0044] S3, after the processor completes the calculation of a statistical distance, it compares the value with a preset threshold. If the value is less than the threshold, the value and its coordinates are stored in the data cache.

[0045] S4: After the RISC-V big core processor finishes its calculations, it gains control of the DDR controller through Arbitrator 2 module, and then writes the calculated valid data and its coordinates into the DDR controller.

[0046] After the RISC-V big core processor finishes sending data, the arbitrator 2 module sequentially transfers the control rights of the DDR controller to the RISC-V little core processors. Each RISC-V little core processor then sequentially writes the calculated valid data and its coordinates into the DDR controller.

[0047] S5, during the writing process to the DDR controller, the processor that has completed data transmission retrieves the coordinates of 10 sets M from the on-chip data storage module and calculates them. The calculation results are stored in their respective data caches. This process is repeated until all sets M have been retrieved and calculated. S6, after the statistical distance calculation is completed, the RISC-V big core processor obtains control of Arbitrator 1 and Arbitrator 2 modules and sends clustering processing instructions and auction instructions to the coprocessor. The coprocessor rearranges the coordinates that have been filtered by the threshold but still have uncertain correlations, and then auctions the rearranged coordinates for matching.

[0048] S7. After the entire algorithm is executed, the RISC-V big core processor writes the matched results back to the on-chip data storage module 5 times, and notifies the host to call DMA to read back the matching results via GPIO.

[0049] S8, after the PC reads this data back, sends a completion signal to the RISC-V big core processor via GPIO to prepare for the next data transfer and calculation.

[0050] The beneficial effects of this invention are as follows: Compared to a general single-core CPU computing scheme, the current scheme achieves higher efficiency in floating-point operations by calling a RISC-V processor configured with an FPU. Furthermore, through reasonable design of the data flow and arbitration structure, multi-core pipelined parallel computing for this data fusion algorithm is realized.

[0051] By optimizing the algorithm flow, threshold comparison is added to the statistical distance calculation process during multi-core computing, storing only valid data and avoiding the comparison and storage of a large amount of invalid data, thus saving computing time. Attached Figure Description

[0052] Figure 1 This is a diagram of the multi-core RISC-V on-chip system architecture for the data fusion algorithm of this invention; Figure 2 This is a flowchart illustrating the operation of a multi-core on-chip system in an example of the present invention. Detailed Implementation

[0053] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings and embodiments.

[0054] The technical solution of this invention addresses several problems in the background art by proposing the following solutions:

[0055] The configurable floating-point processing unit (FPU) of the open-source RocketChip processor is used to accelerate the floating-point processing performance of a single core.

[0056] By rationally designing the arbitration module and planning the data flow of the entire system, the parallel computing function of the multi-core processor can be realized, thereby accelerating the computing process.

[0057] By advancing the floating-point threshold comparison step in cluster processing, this operation is distributed across each core for parallel processing, thus reducing computation time. Calculation results outside the threshold range are deleted, and only the values ​​and coordinates of valid data are saved, which also reduces data transfer time and storage space requirements.

[0058] A multi-core RISC-V system-on-a-chip architecture for data fusion algorithms is mainly composed of a RISC-V big core processor subsystem, n RISC-V little core processor subsystems, arbitrator 1 module, arbitrator 2 module, on-chip data storage module, DDR controller and debug interface.

[0059] The RISC-V big core processor subsystem is used to send a start signal and a calculation completion signal to the host, and to execute the statistical distance calculation (including threshold comparison), clustering processing, and auction association part in the data fusion algorithm, send the calculation result to the DDR SDRAM, and retrieve the final calculation result back to the on-chip data memory.

[0060] The n RISC-V small core processor subsystems are used to execute the statistical distance calculation and threshold comparison parts in the data fusion algorithm, and send the calculated results to DDR SDRAM;

[0061] The arbitrator 1 module is responsible for arbitrating the access requests of each processor to the on-chip data storage;

[0062] The arbitrator 2 module is responsible for arbitrating the access requests of each processor to the DDR controller;

[0063] The on-chip data storage module is used to store the raw data sent from the host, as well as the result data after the on-chip system executes the data fusion algorithm.

[0064] The DDR4 controller is used for access control of DDR SDRAM by each processor;

[0065] The aforementioned debugging interface is used for debugging multi-core on-chip systems.

[0066] The RISC-V big-core processor subsystem consists of a RISC-V big-core processor, an interface bus, a coprocessor, an instruction cache, a data cache, a Tilelink bus, and a BootROM, among which:

[0067] The RISC-V big core processor is responsible for sending computation start signals and computation completion signals, performing floating-point operations for distance and threshold comparison, processing custom instructions in clusters, sending custom instructions for auctioning associations, and retrieving the final computation results from DDR to on-chip data storage.

[0068] The coprocessor, as an acceleration device for the RISC-V big core processor, responds to and decodes the custom instructions sent by the big core processor, performs clustering and auction-based association operations, and returns the operation results.

[0069] The aforementioned interface bus is used for communication between the RISC-V big core processor and the coprocessor;

[0070] The instruction cache is used to store the processing and arithmetic instructions required by the RISC-V big core processor.

[0071] The aforementioned data cache is used to store intermediate data during the calculation process;

[0072] The TileLink system bus is used for communication between the RISC-V big core processor and modules such as the arbitrator and debug interface.

[0073] The Bootrom is used to store the startup code for large-core processors.

[0074] The RISC-V little-core processor subsystem consists of a RISC-V little-core processor, instruction cache, data cache, Tilelink bus, and BootROM.

[0075] The RISC-V small core processor is responsible for statistical distance and threshold comparison floating-point operations, and sends the calculation results to DDR SDRAM;

[0076] The instruction cache is used to store the computation and processing instructions required by the RISC-V small core processor.

[0077] The aforementioned data cache is used to store intermediate data during the calculation process;

[0078] The TileLink system bus is used for communication between the RISC-V small core processor and modules such as the arbitrator and debug interface;

[0079] The BootRom mentioned above is used to store the boot code for the small-core processor.

[0080] Arbitrator 1 module employs two strategies: polling arbitration and interrupt priority arbitration. When each processor performs a data retrieval operation from the on-chip data storage, polling arbitration is used; when the large core processor needs to send the final calculation result data to the on-chip data storage, interrupt priority arbitration is used.

[0081] Arbitrator 2 module employs two strategies: polling arbitration and interrupt priority arbitration. When each processor performs a data sending operation to DDR SDRAM, polling arbitration is used; when the large core processor needs to retrieve the final calculation result data from DDR SDRAM, interrupt priority arbitration is used.

[0082] Both RISC-V big-core processors and RISC-V little-core processors are equipped with a floating-point unit (FPU) that supports FP64 and FP32 floating-point operations;

[0083] The coprocessor is a RISC-V custom instruction set processor customized based on the data fusion algorithm. The custom instructions implemented include clustering processing instructions and auction instructions.

[0084] The RISC-V little-core processor subsystem is homogeneous and can be replicated and expanded under limited resources.

[0085] The beneficial effects of this invention are as follows: Compared to a general single-core CPU computing scheme, the current scheme achieves higher efficiency in floating-point operations by calling a RISC-V processor configured with an FPU. Furthermore, through a well-designed data flow and arbitration structure, multi-core pipelined parallel computing for this data fusion algorithm is realized. In addition, by optimizing the algorithm flow, threshold comparison is incorporated into the statistical distance calculation process during multi-core computation, storing only valid data and avoiding the comparison and storage of a large amount of invalid data, thus saving computation time.

[0086] like Figure 1As shown, this is a multi-core system-on-a-chip (SoC) designed based on the RISC-V open-source processor RocketChip. The SoC includes one fully configured RISC-V big-core processor and three RISC-V little-core processors. Each processor is equipped with a floating-point unit (FPU) and includes its own instruction cache and data cache to store the instructions to be executed and intermediate data for each core. Peripherals include a BootROM containing the code for each core, an arbiter 1 for arbitrating requests to access on-chip data memory, an arbiter 2 for arbitrating requests to access the DDR controller, and a debug interface, among other things.

[0087] The entire system operation process is as follows: Figure 2 As shown, after the four processors power on and reset, the RISC-V big core processor sends a startup standby signal to the host. Upon receiving the startup signal, the host sends the coordinates of sets M and N to the on-chip system via PCIe through DMA, and stores them in the on-chip data memory via the AXI-Lite bus. Under the control of Arbitrator 1, each processor sequentially reads all the coordinates of set N from the on-chip data memory and stores them in its own data memory. Then, it sequentially reads the coordinates of 10 sets M from the on-chip data memory. After reading, the processor calls the FPU to calculate the statistical distance between these 10 coordinates and all the coordinates in set N. After each statistical distance calculation, the processor compares the value with a preset threshold. If the value is less than the threshold, the value and its coordinates are stored in the data cache. After the RISC-V big core processor finishes its calculations, it gains control of DDR4 via Arbitrator 2. It then writes the calculated valid data and its coordinates into DDR4. After the RISC-V big core processor completes its data transmission, Arbitrator 2 sequentially transfers control of DDR4 to RISC-V little core processors 1, 2, and 3. These little core processors then sequentially write their calculated valid data and coordinates into DDR4. During the DDR writing process, the processors that have already completed data transmission retrieve the coordinates of 10 sets M from the on-chip data memory and calculate them. The calculation results are stored in their respective data caches, and this process continues until all sets M have been retrieved and calculated.

[0088] After the statistical distance calculation is complete, the RISC-V big core processor gains control of arbitrators 1 and 2 and sends clustering and auction instructions to the coprocessor. The coprocessor then executes the second part of the algorithm, rearranging the coordinates that have already undergone threshold filtering but still have uncertain correlations. The third part involves auctioning and matching these rearranged coordinates. After the entire algorithm is completed, the RISC-V big core processor writes all the matching results back to the on-chip data memory and notifies the host to call DMA to read the matching results back via GPIO. Once the PC reads this data back, it sends a completion signal to the RISC-V big core processor via GPIO to initiate the next data transfer and calculation.

[0089] Compared to a general-purpose single-core CPU computing solution, the current solution utilizes a RISC-V processor configured with an FPU, resulting in higher efficiency for floating-point operations. Furthermore, through a well-designed data flow and arbitration structure, it achieves multi-core pipelined parallel computing for this data fusion algorithm. In addition, by optimizing the algorithm flow, threshold comparison is incorporated into the statistical distance calculation process during multi-core computation, storing only valid data and avoiding the comparison and storage of large amounts of invalid data, thus saving computation time.

[0090] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit them. Modifications to the above technical solutions or equivalent substitutions of some of the technical features do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A multi-core RISC-V on-chip system for data fusion algorithms, characterized in that, The system includes: one RISC-V big core processor subsystem, n RISC-V little core processor subsystems, arbitrator 1 module, arbitrator 2 module, on-chip data storage module, DDR controller, and debug interface; The one RISC-V big-core processor subsystem and the n RISC-V little-core processor subsystems are respectively connected to the arbitrator 1 module. The one RISC-V big-core processor subsystem and the n RISC-V little-core processor subsystems are respectively connected to the arbitrator 2 module. The arbitrator 1 module is also connected to the on-chip data storage module. The arbitrator 2 module is also connected to the DDR controller. The DDR controller is also connected to the external DDR SDRAM. The on-chip data storage module is also connected to the external data bus. The RISC-V big core processor subsystem is used to send a start signal and a calculation completion signal to the host, as well as to execute the statistical distance calculation, clustering processing, and auction association part of the data fusion algorithm, send the calculation result to DDR SDRAM, and retrieve the final calculation result back to the on-chip data storage module. The n RISC-V small core processor subsystems are used to execute the statistical distance calculation and threshold comparison parts in the data fusion algorithm, and send the calculated results to DDR SDRAM; The arbitrator 1 module is responsible for arbitrating access requests from each processor subsystem to the on-chip data storage module; Arbitrator 2 module is responsible for arbitrating access requests from each processor subsystem to the DDR controller; The on-chip data storage module is used to store the raw data sent from the host, as well as the result data after each processor subsystem has completed the data fusion algorithm. The DDR controller is used for access control of DDR SDRAM by each processor subsystem; The debugging interface is used for debugging multi-core RISC-V on-chip systems.

2. The multi-core RISC-V on-chip system for data fusion algorithms according to claim 1, characterized in that, The RISC-V big core processor subsystem consists of a RISC-V big core processor, an interface bus, a coprocessor, an instruction cache, a data cache, a Tilelink bus, and a BootRom. The RISC-V big core processor is responsible for sending computation start signals and computation completion signals, performing floating-point operations for distance and threshold comparison, processing custom instructions in clusters, sending custom instructions for auctioning associations, and retrieving the final computation results from the DDR controller to the on-chip data storage module. The coprocessor, as an acceleration device for the RISC-V big core processor, responds to and decodes the custom instructions sent by the big core processor, performs clustering processing and auction-based association operations, and returns the operation results. The interface bus is used for communication between the RISC-V big core processor and the coprocessor. The instruction cache is used to store the processing and arithmetic instructions required by the RISC-V big core processor; The data cache is used to store intermediate data during the calculation process; The TileLink bus is used for communication between the RISC-V big core processor and the arbitrator module and debug interface; The BootRom is used to store the boot code for large-core processors.

3. The multi-core RISC-V on-chip system for data fusion algorithms according to claim 2, characterized in that, The coprocessor is a custom instruction set processor based on the data fusion algorithm, and the custom instructions implemented include clustering processing instructions and auction instructions.

4. A multi-core RISC-V on-chip system for data fusion algorithms according to claim 2, characterized in that, The RISC-V small core processor subsystem consists of a RISC-V small core processor, instruction cache, data cache, Tilelink bus, and BootROM; The RISC-V small core processor is responsible for performing floating-point operations on distance and threshold comparison, and sending the calculation results to DDR SDRAM. The instruction cache is used to store the computation and processing instructions required by the RISC-V small core processor; The data cache is used to store intermediate data during the calculation process; The TileLink bus is used for communication between the RISC-V small core processor and the arbitrator module and debug interface; The BootRom is used to store the boot code for the small-core processor.

5. A multi-core RISC-V on-chip system for data fusion algorithms according to claim 4, characterized in that, Both the RISC-V big-core processor and the RISC-V little-core processor are equipped with floating-point arithmetic units, supporting FP64 and FP32 floating-point operations.

6. A multi-core RISC-V on-chip system for data fusion algorithms according to claim 4, characterized in that, Each RISC-V little-core processor subsystem is homogeneous and can be replicated and expanded with limited resources.

7. A multi-core RISC-V on-chip system for data fusion algorithms according to claim 1, characterized in that, The arbitrator 1 module adopts two strategies: polling arbitration and interrupt priority arbitration. When each processor performs a data retrieval operation from the on-chip data storage module, polling arbitration is used. When the large-core processor needs to send the final calculation result data to the on-chip data storage module, interrupt priority arbitration is used.

8. A multi-core RISC-V on-chip system for data fusion algorithms according to claim 1, characterized in that, The arbitrator 2 module adopts two strategies: polling arbitration and interrupt priority arbitration. When each processor performs a data sending operation to DDR SDRAM, polling arbitration is used. When the large-core processor needs to retrieve the final calculation result data from DDR SDRAM, interrupt priority arbitration is used.

9. A multi-core RISC-V on-chip method for data fusion algorithms, characterized in that, The method is applied to the system as described in any one of claims 1-8, and the method comprises: S1. After each processor powers on and resets, the RISC-V big core processor sends a startup standby signal to the host. After receiving the startup signal, the host sends the coordinates of sets M and N to the on-chip system via PCIe through DMA, and stores them in the on-chip data storage module via the AXI-Lite bus. S2, under the control of Arbitrator 1 module, each processor sequentially reads all coordinates of set N from the on-chip data storage module and stores them in its own data cache. Then, it sequentially reads the coordinates of 10 sets M from the on-chip data storage module. After reading, the processor calls FPU to perform statistical distance calculation between these 10 coordinates and all coordinates in set N. S3, after the processor completes the calculation of a statistical distance, it compares the statistical distance value with a preset threshold. If the value is less than the threshold, the statistical distance value and its coordinates are stored in the data cache. S4. After the RISC-V big core processor finishes its calculations, it obtains control of the DDR controller through the Arbitrator 2 module. Then, it writes the calculated valid data and its coordinates into the DDR controller. After the RISC-V big core processor finishes sending the data, the Arbitrator 2 module sequentially transfers control of the DDR controller to the RISC-V little core processors. Each RISC-V little core processor then sequentially writes the calculated valid data and its coordinates into the DDR controller. S5, during the writing process to the DDR controller, the processor that has completed data transmission retrieves the coordinates of 10 sets M from the on-chip data storage module again and calculates them. The calculation results are stored in their respective data caches. This process continues until all the coordinates of all sets M have been retrieved and calculated. S6. After the statistical distance calculation is completed, the RISC-V big core processor obtains control of Arbitrator 1 and Arbitrator 2 modules and sends clustering processing instructions and auction instructions to the coprocessor. The coprocessor rearranges the coordinates that have been filtered by the threshold but still have uncertain correlations, and then auctions the rearranged coordinates for matching. S7. After the entire algorithm is executed, the RISC-V big core processor writes the matched results back to the on-chip data storage module and notifies the host to call DMA to read back the matching results via GPIO. S8, after the PC reads this data back, sends a completion signal to the RISC-V big core processor via GPIO to prepare for the next data transfer and calculation.

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