Wiring resource pre-allocation method and apparatus, computing device, and storage medium

Abstract

The application discloses a wiring resource pre-allocation method and device, a computing device and a storage medium, and belongs to the field of electronic design automation. The method comprises the following steps: determining a target grid in an integrated circuit layout and a total amount of wiring resources in the target grid; taking target resource demand amounts of each target line net in the target grid as variables, inputting the target resource demand amounts as variables and the total amount of wiring resources into a preset resource pre-allocation model to perform quadratic programming solving, and obtaining resource allocation amounts of each target line net in the target grid. Through the wiring resource pre-allocation method in the application, pre-allocation of resources can be performed before integrated circuit wiring, so that the problem of wiring congestion can be greatly avoided, and the utilization rate of integrated circuit layout resources is improved.

Description

Technical Field

[0001] This invention relates to the field of electronic design automation, and more particularly to a method, apparatus, computing device, and computer-readable storage medium for pre-allocating wiring resources. Background Technology

[0002] As transistor sizes continue to shrink and the number of cells and target nets increases, chip design becomes increasingly difficult. Routing is a crucial physical implementation task following placement and clock tree synthesis. The routing phase is divided into global routing and detailed routing, with global routing forming the foundation for detailed routing, ensuring the feasibility and rationality of the routing results. The quality of the global routing solution directly affects chip area, speed, power consumption, and the number of iterations required to complete the design cycle; therefore, this routing process plays a vital role in determining circuit performance. Due to limited resources and the influence of target net order, routing congestion is inevitable. Therefore, a high-quality resource pre-allocation method is extremely important for layout routing.

[0003] In existing methods, most routing algorithms first obtain the initial routing solution for all target nets through sequential routing, either by adding layers of 2D routing or by directly routing in 3D. During the routing process, resource contention among the target nets can cause significant congestion, which is then resolved by tearing down and rerouting. However, this requires substantial time and manpower, and most routing methods address congestion issues through this post-processing rather than addressing resource allocation between target nets at the outset. Summary of the Invention

[0004] The main objective of this invention is to provide a method, apparatus, computing device, and computer-readable storage medium for pre-allocating wiring resources, aiming to solve the technical problem of wiring congestion caused by the lack of pre-allocation of resources in existing integrated circuit wiring schemes.

[0005] To achieve the above objectives, the present invention provides a method for pre-allocating cabling resources, the method comprising the following steps:

[0006] The cabling resource pre-allocation method includes the following steps:

[0007] Determine the target grid in the integrated circuit layout and the total amount of wiring resources in the target grid;

[0008] The target resource requirements of each target net in the target grid are used as variables. The target resource requirements and the total cabling resources are input into a preset resource pre-allocation model to perform secondary planning on the target resource requirements, thereby obtaining the resource allocation of each target net in the target grid.

[0009] Optionally, the step of inputting the target resource demand and the total cabling resources as variables into a preset resource pre-allocation model for quadratic programming solution includes:

[0010] The target resource demand and the total cabling resources, which are variables, are input into a preset resource pre-allocation model, and all the target resource demands input into the resource pre-allocation model are summarized to obtain the total target resource demand.

[0011] Establish a target quadratic function between the total target resource demand and the total amount of cabling resources, and use the minimum difference between the total target resource demand and the total amount of cabling resources as the target to perform secondary planning and adjustment of the target resource demand.

[0012] Optionally, the step of inputting the target resource demand and the total cabling resources as variables into a preset resource pre-allocation model for quadratic programming solution includes:

[0013] The target resource requirement and the total wiring resources, which are variables, are input into a preset resource pre-allocation model, and the total resource requirement of the target net in the integrated circuit layout is obtained at the same time.

[0014] Based on the total resource demand, constraints are constructed for the target resource demand, and these constraints are applied to the target resource demand for secondary planning adjustments.

[0015] Optionally, the step of inputting the target resource demand and the total cabling resources as variables into a preset resource pre-allocation model for quadratic programming solution includes:

[0016] The resource pre-allocation model is expanded using quadratic terms to transform it into a resource iteration model.

[0017] The set of all the target resource requirements is used as the target vector and input into the resource iteration model for iterative quadratic programming solution.

[0018] Optionally, after the step of inputting the target resource demand and the total cabling resources as variables into a preset resource pre-allocation model for quadratic programming to obtain the resource allocation of each target net in the target grid, the method further includes:

[0019] Determine the congestion weight of the target grid, and input the resource allocation amount as the resource weight along with the congestion weight into a preset cabling cost function to obtain the cabling cost value of the target grid;

[0020] Based on the routing cost value of each target mesh, global routing is performed on all nets in the integrated circuit layout.

[0021] Optionally, the step of globally routing all nets in the integrated circuit layout based on the routing cost value of each of the target nets includes:

[0022] Based on the routing cost value of each target mesh, determine the set of total routing cost values ​​that each net in the integrated circuit layout can pass through the mesh;

[0023] Obtain the acceptable length range of the net, and determine the target Steiner tree topology corresponding to the total cabling cost set based on the acceptable length range.

[0024] Optionally, the step of obtaining the acceptable range of wire lengths for the wire mesh includes:

[0025] Determine each connection point in the wire mesh, and determine the circumscribed rectangle formed between the connection points;

[0026] Based on the circumscribed rectangle, determine all edge vectors for each combination of connection points;

[0027] The lengths of each bus in the net are calculated based on all the edge vectors.

[0028] The optimal Steiner tree length corresponding to the net is determined based on the bus length.

[0029] The optimal Steiner tree line length is used as the lower limit of the acceptable line length range, and the total resource requirement of the net in the integrated circuit layout is used as the upper limit of the acceptable line length range.

[0030] Furthermore, to achieve the above objectives, the present invention also provides a cabling resource pre-allocation device, the cabling resource pre-allocation device comprising:

[0031] The resource statistics module is used to determine the target grid in the integrated circuit layout and the total amount of wiring resources in the target grid;

[0032] The resource planning module is used to take the target resource demand of each target network in the target grid as a variable, and input the target resource demand and the total cabling resources as variables into a preset resource pre-allocation model to perform secondary planning on the target resource demand, so as to obtain the resource allocation of each target network in the target grid.

[0033] In addition, to achieve the above objectives, the present invention also provides a computing device, including a processor, a storage unit, and a cabling resource pre-allocation program stored on the storage unit and executable by the processor, wherein when the cabling resource pre-allocation program is executed by the processor, it implements the steps of the cabling resource pre-allocation method as described above.

[0034] The present invention also provides a computer-readable storage medium storing a cabling resource pre-allocation program, wherein when the cabling resource pre-allocation program is executed by a processor, it implements the steps of the cabling resource pre-allocation method as described above.

[0035] The wiring resource pre-allocation method in this invention involves determining the target grid in the integrated circuit layout and the total amount of wiring resources in the target grid; using the target resource demand of each target net in the target grid as a variable; and inputting the target resource demand and the total amount of wiring resources as variables into a preset resource pre-allocation model for secondary planning to obtain the resource allocation amount of each target net in the target grid. Before wiring the integrated circuit, based on the wiring resources available in each grid, resource pre-allocation is performed on the resource demand of the nets in the grid. This can greatly reduce congestion problems during wiring and avoid the occurrence of wire removal and rewiring. Furthermore, this application transforms the wiring resource pre-allocation problem into a quadratic programming problem, which can maximize the solution to ensure that the total demand of multiple nets in the grid is basically consistent with the total resources of the grid, so that the resources in each grid can be maximized and the resource utilization rate of the integrated circuit layout can be improved. In this way, by solving the resource allocation problem, the wiring congestion problem is naturally better resolved. Attached Figure Description

[0036] Figure 1 This is a schematic diagram of the hardware operating environment of the computing device involved in the embodiments of the present invention;

[0037] Figure 2 This is a flowchart illustrating the first embodiment of the cabling resource pre-allocation method of the present invention;

[0038] Figure 3 This is a flowchart illustrating the process after step S20 in one embodiment of the cabling resource pre-allocation method of the present invention;

[0039] Figure 4 This is a schematic diagram of the H,V-tree involved in the cabling resource pre-allocation method of the present invention;

[0040] Figure 5 This is a schematic diagram of the design resource model involved in the cabling resource pre-allocation method of the present invention;

[0041] Figure 6 This is a schematic diagram of the GCell resource direction involved in the cabling resource pre-allocation method of the present invention;

[0042] Figure 7 This is a schematic diagram illustrating the Steiner tree description involved in the cabling resource pre-allocation method of the present invention;

[0043] Figure 8 This is a schematic diagram of a potential right-angle Steiner tree involved in the cabling resource pre-allocation method of the present invention;

[0044] Figure 9 This is a schematic diagram of topology compression involved in the cabling resource pre-allocation method of the present invention;

[0045] Figure 10 This is a schematic diagram of the variable clustering involved in the cabling resource pre-allocation method of the present invention;

[0046] Figure 11 This is a schematic diagram of the edge translation involved in the cabling resource pre-allocation method of the present invention;

[0047] Figure 12 This is a schematic diagram of A* inflection point prediction involved in the cabling resource pre-allocation method of the present invention;

[0048] Figure 13 This is a schematic diagram of the frame structure of the cabling resource pre-allocation device of the present invention.

[0049] The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0050] It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0051] This invention provides a computing device, which can be a personal computer, a computer workstation, a server, or other data processing device.

[0052] like Figure 1 As shown, Figure 1 This is a schematic diagram of the hardware operating environment of the computing device involved in the embodiments of the present invention.

[0053] like Figure 1As shown, the computing device may include: a processor 1001, such as a CPU; a network interface 1004; a user interface 1003; a storage unit 1005; and a communication bus 1002. The communication bus 1002 is used to enable communication between these components. The user interface 1003 may include a display or an input unit such as a control panel; optionally, the user interface 1003 may also include a standard wired interface or a wireless interface. The network interface 1004 may optionally include a standard wired interface or a wireless interface (such as a Wi-Fi interface). The storage unit 1005 may be a high-speed RAM storage unit or a stable storage unit (non-volatile memory), such as a disk storage unit. The storage unit 1005 may also optionally be a storage device independent of the aforementioned processor 1001. The storage unit 1005, as a computer storage medium, may include a wiring resource pre-allocation program.

[0054] Those skilled in the art will understand that Figure 1 The hardware structure shown does not constitute a limitation on the device and may include more or fewer components than shown, or combine certain components, or have different component arrangements.

[0055] Continue to refer to Figure 1 , Figure 1 The storage unit 1005, which is a computer-readable storage medium, may include an operating system, a user interface module, a network communication module, and a cabling resource pre-allocation program.

[0056] exist Figure 1 In this module, the network communication module is mainly used to connect to the server and communicate with it for data. The processor 1001 can call the cabling resource pre-allocation program stored in the storage unit 1005 and perform the following operations:

[0057] Determine the target grid in the integrated circuit layout and the total amount of wiring resources in the target grid;

[0058] The target resource requirements of each target net in the target grid are used as variables. The target resource requirements and the total cabling resources are input into a preset resource pre-allocation model to perform secondary planning on the target resource requirements, thereby obtaining the resource allocation of each target net in the target grid.

[0059] Furthermore, the processor 1001 can call the wiring resource pre-allocation program stored in the memory 1005 and also perform the following operations:

[0060] The target resource demand and the total cabling resources, which are variables, are input into a preset resource pre-allocation model, and all the target resource demands input into the resource pre-allocation model are summarized to obtain the total target resource demand.

[0061] Establish a target quadratic function between the total target resource demand and the total amount of cabling resources, and use the minimum difference between the total target resource demand and the total amount of cabling resources as the target to perform secondary planning and adjustment of the target resource demand.

[0062] Furthermore, the processor 1001 can call the wiring resource pre-allocation program stored in the memory 1005 and also perform the following operations:

[0063] The target resource requirement and the total wiring resources, which are variables, are input into a preset resource pre-allocation model, and the total resource requirement of the target net in the integrated circuit layout is obtained at the same time.

[0064] Based on the total resource demand, constraints are constructed for the target resource demand, and these constraints are applied to the target resource demand for secondary planning adjustments.

[0065] Furthermore, the processor 1001 can call the wiring resource pre-allocation program stored in the memory 1005 and also perform the following operations:

[0066] The resource pre-allocation model is expanded using quadratic terms to transform it into a resource iteration model.

[0067] The set of all the target resource requirements is used as the target vector and input into the resource iteration model for iterative quadratic programming solution.

[0068] Furthermore, the processor 1001 can call the wiring resource pre-allocation program stored in the memory 1005 and also perform the following operations:

[0069] Determine the congestion weight of the target grid, and input the resource allocation amount as the resource weight along with the congestion weight into a preset cabling cost function to obtain the cabling cost value of the target grid;

[0070] Based on the routing cost value of each target mesh, global routing is performed on all nets in the integrated circuit layout.

[0071] Furthermore, the processor 1001 can call the wiring resource pre-allocation program stored in the memory 1005 and also perform the following operations:

[0072] Determine each connection point in the wire mesh, and determine the circumscribed rectangle formed between the connection points;

[0073] Based on the circumscribed rectangle, determine all edge vectors for each combination of connection points;

[0074] The lengths of each bus in the net are calculated based on all the edge vectors.

[0075] The optimal Steiner tree length corresponding to the net is determined based on the bus length.

[0076] The optimal Steiner tree line length is used as the lower limit of the acceptable line length range, and the total resource requirement of the net in the integrated circuit layout is used as the upper limit of the acceptable line length range; wherein, the total resource requirement is obtained by HV tree.

[0077] To facilitate understanding of the following embodiments of the present invention, the main technical solutions of the present invention will be briefly described:

[0078] This invention leverages the relationship between layout resources and network requirements. By incorporating resource pre-allocation before 2D routing, a resource weight map of the network is obtained through pre-allocation. During routing, weighted routing is performed with reference to the weight map and congestion map, thus alleviating congestion between networks. This invention solves the congestion problem caused by resource contention between networks using resource pre-allocation, reducing congestion and the time required for rewiring. Compared with existing technologies, this invention can achieve better routing results in a shorter time, and in particular, significantly avoids the scenario of rewiring, which severely impacts routing efficiency.

[0079] This invention provides a method for pre-allocating cabling resources.

[0080] Please refer to Figure 2 , Figure 2 This is a flowchart illustrating a first embodiment of the cabling resource pre-allocation method of the present invention; in the first embodiment of the present invention, the cabling resource pre-allocation method includes the following steps:

[0081] Step S10: Determine the target grid in the integrated circuit layout and the total amount of wiring resources in the target grid;

[0082] In this embodiment, the routing resource pre-allocation method can be applied to global routing. The integrated circuit layout (hereinafter referred to as the layout) refers to the entire integrated circuit region. A grid (GCell, global routing cells) refers to a region within the entire integrated circuit region divided according to the specifications of the integrated circuit layout or other practical needs. A target grid is specific to each individual grid; different target grids can be divided into the same area within the layout, but often have different amounts of routing resources. Here, resources can be understood as the length of available routing tracks or the area, etc. The total amount of routing resources in a target grid refers to the total amount of routingable resources within the grid area of ​​a given grid.

[0083] In this embodiment, the total amount of cabling resources in the target mesh can be determined according to the following formula (1):

[0084]

[0085] Where, r i #track represents the total number of resources in the i-th GCell in the integrated circuit design, and #track represents the number of routing tracks within the GCell. The area of ​​the obstacle. The total area of ​​target grid i is denoted as i. The effective area of ​​a grid is the sum of the areas of all other areas except for obstacles. The effective area is also the total amount of cabling resources.

[0086] The process of determining the total amount of cabling resources in the target grid is also called the resource model establishment process.

[0087] Since this invention mainly addresses the issue of coordinating resource supply and demand, and the resource supply has already been determined above, the resource demand for each network in the defined area will be explained here:

[0088] The total wire mesh requirement spanning multiple grid regions is shown in Equation (2).

[0089] d j =min(wl(H_tree),wl(V_tree)) (2)

[0090] Where, d j It is the demand value of the j-th wire, and the demand can be estimated by the wire with the smallest length in the H,V-tree.

[0091] The requirements for the wire mesh of a single grid region (called the local net) are shown in Equation (3).

[0092] d j =HPWL(GCell)·#pins / 2 (3)

[0093] In this formula (3), #pins is the number of pins of the wire mesh in a single grid region, and HPWL is the traditional wire length estimation model using the half-circumference wire length model.

[0094] Using H,V-trees preserves the accuracy of the estimation without significantly increasing the time complexity.

[0095] For a better understanding of the H and V trees described above, please refer to [link / reference]. Figure 4 As shown in the figure:

[0096] An H-tree is a net that has only one horizontal axis running through the entire bounding box (the rectangle circumscribed by all given points in the net). Points within the net are either on the horizontal axis or connected to the horizontal axis by a vertical line. The horizontal axis of an H-tree is located at the y-coordinate of the centroid of all given points in the net; the same applies to a V-tree.

[0097] It should be added that in cabling practice, two-point nets account for 60% of the total design. Using HPWL is accurate for two-point nets because the length of the cabling at each point is half the perimeter of its circumscribed rectangle. For nets with more than two points, the estimated length is obtained through the H,V-tree of the net; the net with the smallest sum of segment lengths in the H,V-tree is the estimated length of the net.

[0098] The above process can be considered as the process of building a demand model.

[0099] Step S20: The target resource demand of each target net in the target grid is used as a variable. The target resource demand and the total cabling resources are input into a preset resource pre-allocation model to perform secondary planning on the target resource demand, so as to obtain the resource allocation of each target net in the target grid.

[0100] Each target mesh in the target grid refers to every mesh that passes through the target grid. The target resource requirement is the resource requirement of a specific mesh in a specific grid. The resource pre-allocation model can be used to solve quadratic programming problems, outputting the actual amount of resources to be allocated to each target mesh in its target grid.

[0101] In one embodiment, step S20, which involves inputting the target resource demand and the total cabling resources as variables into a preset resource pre-allocation model for quadratic programming solution, includes:

[0102] Step a: Input the target resource demand and the total cabling resources as variables into a preset resource pre-allocation model, and summarize all the target resource demands input into the resource pre-allocation model to obtain the total target resource demand;

[0103] Step b: Establish a target quadratic function between the total target resource demand and the total cabling resources, and perform secondary planning and adjustment of the target resource demand with the minimum difference between the total target resource demand and the total cabling resources as the target.

[0104] In another embodiment,

[0105] Step c: Input the target resource requirement and the total wiring resources as variables into the preset resource pre-allocation model, and at the same time obtain the total resource requirement of the target net in the integrated circuit layout;

[0106] Step d: Construct constraints on the target resource demand based on the total resource demand, and constrain the target resource demand for secondary planning adjustments.

[0107] To facilitate understanding of step S20 above and the two embodiments related to step S20, the following formulas (4) to (6) can be used for representation and explanation:

[0108]

[0109] Formula (4) is also the target quadratic function mentioned in step b.

[0110] Where x i，j Let r be the number of resources allocated to the j-th net on the i-th GCell (before actual allocation, i.e., the target resource requirement; after solving, it becomes the resource allocation amount). i This represents the total number of resources (total cabling resources) for the i-th GCell.

[0111] Furthermore, considering that the total demand of all nets on the i-th GCell should be close to the total resources of the GCell, this allows the nets to fully utilize the resources of the GCell without exceeding the resources that the GCell can provide. Therefore, equation (4) needs to be constrained, as shown in the following equation (5):

[0112]

[0113] In addition, the resource pre-allocation model should be based on the constraint that the network demand remains constant. Resource pre-allocation does not reduce the network demand; that is, the bus length of the network remains constant. Where N... j Let d be the j-th wire mesh, and d j This represents the total demand for the j-th net across the entire layout. The set of GCells corresponding to a net consists of the GCells covered by the BBox (bounding rectangle, also mentioned above) of this net.

[0114]

[0115]

[0116] Therefore, combining formulas (4) and (5) yields the resource pre-allocation model, as shown in formula (6).

[0117] It can be seen from the above formula (6) that each target network x i，j The value obtained by summing the superpositions (Total target resource requirement) and total cabling resources r i The closer the value is to the minimum, the more fully the total cabling resources in each grid can be utilized by the network, thereby improving the overall resource utilization of the layout. Improving the utilization rate also solves the cabling congestion problem, because cabling congestion is mainly caused by the mismatch between the cabling in each grid and the actual total cabling resources of the grid.

[0118] Furthermore, it is necessary to expand and transform formula (6) into a quadratic programming problem to obtain a better solution for each of the resource allocation quantities.

[0119] In one embodiment, step S20, which involves inputting the target resource demand and the total cabling resources as variables into a preset resource pre-allocation model for quadratic programming solution, includes:

[0120] Step e: Expand the resource pre-allocation model with quadratic terms to transform it into a resource iteration model;

[0121] Step f involves taking the set of all the target resource requirements as the target vector and inputting it into the resource iteration model for iterative quadratic programming solution.

[0122] Expanding the quadratic terms of the resource iteration model (6) transforms it into a quadratic programming model (7).

[0123]

[0124] stAx=b (7)

[0125] First, the resource iteration objective (4) is transformed into a quadratic programming objective (8) through the process of combining and converting.

[0126]

[0127] Where x and x T These are the target vector and its transpose, respectively. The target vector consists of the target resource requirement.

[0128] Q GThis refers to the quadratic terms involving GCell and the quadratic superposition state of GCell on the layout. It is a vector consisting of the resource counts of all GCells in the layout design.

[0129] The network demand equation constraint (5) is then transformed into a quadratic programming constraint (9), where Q N It is a secondary superposition state in the wire mesh. This quadratic model is a vector consisting of the number of nets required in the layout design, and is used to constrain net requirements during the iteration process.

[0130]

[0131] By adding a penalty parameter u to the online constraint (9) using the penalty function method, the original constrained optimization problem is transformed into an unconstrained optimization problem. The penalty parameter is used to adjust the constraints during the iteration process. Combining (8) and (9), we obtain the resource iteration model (10).

[0132]

[0133] The gradient descent rule is used to iteratively solve the resource iteration model (10). (10) is then rearranged and the objective is transformed into a functional expression related to x and u.

[0134]

[0135] Organized,

[0136]

[0137] pass

[0138]

[0139] Simplifying the function expression, the final f(x, u) is:

[0140]

[0141] (14) That is, a resource iteration model that incorporates a penalty function to facilitate iteratively finding the optimal solution. This is the resource iteration model described in step e, and the model incorporates a penalty function and applies the gradient descent rule.

[0142] Furthermore, the gradient descent iteration of the penalty function will be divided into two loops. The outer loop controls the penalty parameter u, and let k be the number of iterations already performed by the outer loop. The inner loop updates the variable x under different penalty parameters of the outer loop, and let t be the number of iterations already performed by the inner loop. Where u... k Let x represent the penalty parameter of the outer loop in the k-th round. tThis represents the variable value in the t-th iteration. The initial state of the iteration is defined by the penalty parameter u0, x... 0，0 .

[0143] The inner loop is solved using gradient descent, where the descent direction is...

[0144]

[0145] The step size is,

[0146]

[0147] Update variable values ​​by direction and step size.

[0148] x t+1 =x t +α t ·p t (17)

[0149] After the inner loop finishes, the penalty parameter is adjusted using the coefficient β. k+1 =β·u k Then execute the inner loop.

[0150] In this embodiment, the resource pre-allocation model is modeled as a quadratic programming mathematical model. Integrated circuit design is huge in scale, and it is difficult and time-consuming to directly solve the quadratic programming problem with equality constraints. The result of resource pre-allocation does not need to satisfy this equality to reach the optimal state. Therefore, an iterative method is used to solve this quadratic programming problem. At the same time, the penalty function method is used to transform the constrained model into an unconstrained problem, which facilitates iterative solution.

[0151] In one embodiment, since iteratively solving the model is often very time-consuming, corresponding high-performance acceleration is implemented to address the matrix characteristics in its quadratic programming.

[0152] In the quadratic term of the iterative model function, Q G and Q N The matrix is ​​a special matrix, where Q G It is a block diagonal matrix, and Q N These are diagonal symmetric matrices. The coefficients of these two matrices will only consist of (0, 1). When doing x... T When performing Qx product operations, the relationship between GCell and Net in the design can be used as the basis for operation optimization.

[0153] like Figure 5 As shown, the GCell and Net in the design have a many-to-many relationship, and the variables in the quadratic term matrix are consistent with the relationship in the design. The relationship between GCell and Net is many-to-many, and the mapping of Net within GCell is represented by Q. GIn the example below, Net1 maps to variables x1 and x2 of GCell1 and GCell2, i.e., in Q... G [1,1]、Q G [1, 2], Q G [2,1] and Q G The value is 1 above [2, 2]. Similarly, the mapping of GCell in Net is also like this. Designing all mappings into matrices and adding them together yields the final binomial matrix.

[0154] Figure 5 The model matrix is ​​shown in (18).

[0155]

[0156] In the operation vector and Q G，N When multiplying matrices, the matrix is ​​converted into a vector based on its properties, and addition is performed according to the relationship between the net and GCell. Dedicated matrix multiplication is used to avoid redundant multiplication operations.

[0157]

[0158] Meanwhile, in actual iterative calculations, only the relationship between the wired network and GCell is needed, without storing the Q matrix and using optimized matrix operations.

[0159] The computational time complexity of the previous iteration was O(n⁴), where n is the number of iteration variables, and the space complexity was O(n²). After matrix optimization, the computational time complexity is O(n²) and the space complexity is O(n²), significantly improving the efficiency of the iterative solution.

[0160] The wiring resource pre-allocation method in this invention involves determining the target grid in the integrated circuit layout and the total amount of wiring resources in the target grid; using the target resource demand of each target net in the target grid as variables; and inputting the target resource demand and the total amount of wiring resources as variables into a preset resource pre-allocation model for quadratic programming to obtain the resource allocation amount of each target net in the target grid. Before wiring the integrated circuit, based on the wiring resources available in each grid, resource pre-allocation is performed on the resource demand of the nets in the grid. This can greatly reduce congestion problems during wiring and avoid the need for rewiring. Furthermore, this application transforms the wiring resource pre-allocation problem into a quadratic programming problem, which can maximize the solution to ensure that the total demand of multiple nets in the grid is basically consistent with the total resources of the grid. This allows resources in each grid to be utilized to the maximum extent, improving the resource utilization rate of the integrated circuit layout. In this way, by solving the resource allocation problem, the wiring congestion problem is naturally better resolved.

[0161] Please refer to Figure 3 In one embodiment, after step S20, the method further includes:

[0162] Step S30: Determine the congestion weight of the target grid, and input the resource allocation amount as the resource weight along with the congestion weight into a preset cabling cost function to obtain the cabling cost value of the target grid.

[0163] The process of determining the congestion weight of the target grid:

[0164] GCell can be used for both two-dimensional and three-dimensional processing. Compressing a three-dimensional GCell grid results in a GCell mesh.

[0165] You can refer to Figure 6 The midpoint of the GCell grid serves as the start and end point of all routing. In order to control the congestion of each GCell more finely, for a 3D GCell, the congestion caused by routing will be considered from the four directions on the same plane as the routing layer and the vertical direction connecting the upper and lower layers.

[0166] The metal layer routing resources within a GCell are determined by the number of routing tracks in four directions (E, S, W, N). The number of resources in each direction is calculated independently, using the following formula:

[0167]

[0168] (19) is actually consistent with (1). The resource of GCell is the product of the effective area of ​​GCell and the number of covered tracks, rounded to the nearest whole number. Taking the N direction as an example, this formula gives the number of effective wiring tracks in the N direction of the resource of GCell as 4, which is the resource of GCell in the N direction.

[0169] The requirement for a GCell depends on the number of metal lines passing through it. If the start or end point of a line segment is the center of the GCell, only the direction in which the line segment passes is calculated. If a line segment passes through a GCell, its wiring requirements need to be recorded in both the vertical and horizontal directions. The line requirement unit for each direction is 1.

[0170] While wire routing is independent in different directions, via placement can obstruct wire passage in any direction. Therefore, the via requirement is combined with the wire requirement as the total requirement d for this GCell:

[0171]

[0172] By analyzing the resources and demands within a GCell, the congestion level of that GCell can be determined. The congestion weighting function is as follows:

[0173]

[0174] After determining the congestion weight of the target grid, the resource allocation amount is used as the resource weight along with the congestion weight and input into the preset cabling cost function (22).

[0175]

[0176] With the addition of resource pre-allocation, the weights of GCells depend not only on cabling congestion but also on the results of resource pre-allocation. To fully account for the impact of both on cabling, these two weights are placed in the same weight function order, which is called the cabling cost function.

[0177] Among them, W g W represents the cabling cost (value) of GCell, where c and r are the congestion and resource coefficients, respectively, which can be set as needed. The congestion and resource coefficients characterize the degree to which cabling costs are biased towards congestion or resources. These coefficients exist as hyperparameters of the tool, used to adjust the impact of resource pre-allocation and congestion on cabling costs. c and W r These are the congestion weight and the resource weight, respectively, W r That is, the amount of resources allocated.

[0178] It should be noted that the congestion weight W cThe wiring process is dynamic, so W g It also changes dynamically accordingly.

[0179] Step S40: Based on the routing cost value of each target mesh, perform global routing on all nets in the integrated circuit layout.

[0180] Once the routing cost of each target grid in the layout is determined, the routing cost of each grid can be planned to be as low as possible when each net passes through multiple grids, thereby avoiding potential congestion during routing. Based on this, global routing is performed on all nets.

[0181] In one embodiment, step S40 includes:

[0182] Step g: Based on the routing cost value of each target mesh, determine the set of total routing cost values ​​that each net in the integrated circuit layout can pass through the mesh;

[0183] Once the routing cost value of each grid is determined, the total routing cost value of the grids that each grid can pass through can be obtained and determined. Since the various connection points in the grid can form grids with different connection relationships, the grids formed by the connection points have multiple total routing costs based on different routing, that is, the grids traversed will have differences, thus obtaining a set of total routing cost values, i.e., the set of total routing cost values.

[0184] Step h: Obtain the acceptable wire length range of the net, and determine the target Steiner tree topology corresponding to the total cabling cost set based on the acceptable wire length range.

[0185] The target Steiner tree topology corresponding to the set of total cabling costs is the topology formed by the Steiner tree corresponding to the relatively lower total cabling cost in the set. When establishing the target Steiner tree topology, it is necessary to coordinate cabling costs with the cable length during network cabling to obtain a better solution. Therefore, within the constraints of the acceptable cable length range of the network, a better target Steiner tree topology is determined. That is, after incorporating resource pre-allocation, the focus is more on whether the Steiner tree can better conform to the weight distribution while achieving optimal cable length.

[0186] In one embodiment, step h, obtaining the acceptable wire length range of the wire mesh, includes:

[0187] Determine each connection point in the wire mesh, and determine the circumscribed rectangle formed between the connection points;

[0188] Based on the circumscribed rectangle, determine all edge vectors for each combination of connection points;

[0189] The lengths of each bus in the net are calculated based on all the edge vectors.

[0190] The optimal Steiner tree length corresponding to the net is determined based on the bus length.

[0191] The optimal Steiner tree line length is used as the lower limit of the acceptable line length range, and the total resource requirement of the net in the integrated circuit layout is used as the upper limit of the acceptable line length range; wherein, the total resource requirement is obtained by HV tree.

[0192] To facilitate understanding of the steps described above in this embodiment, please refer to... Figure 7 and Figure 8 Explanation:

[0193] like Figure 7 As shown, all points will be scaled to a grid with a unit of 1. To better describe all point combinations, the relative positions of the points are used to uniquely represent each combination. Figure 7 In the diagram, P1, P2, P3, and P4 represent a combination of four points. Arranging the y-coordinates of these four points in ascending order, the resulting x-coordinate index is 3142. This number will be used to represent the relative positions of these points. The total number of edges in this point combination is also represented by the Potentially Optimal Line Length Vector (POWV), which consists of (h1, h2, h3, v1, v2, v3). Each dimension of this vector represents the number of line segments at the current position.

[0194] like Figure 8 As shown, POWV is represented in these three cases as ①(1,1,1,1,1,1), ②(1,1,1,1,2,1), and ③(1,1,1,1,1,2). POWV can be easily calculated using h1+h2+h3+v1+v2+v3 to determine the bus length of the net. Therefore, this paper uses the optimal Steiner tree length as the lower limit of POWV and the H and V-trees as the upper limit to constrain the generated POWV to an acceptable length range. Finally, the Steiner tree topology of POWV under all point combinations is generated, which is the target Steiner tree topology. This significantly reduces some possible Steiner tree topologies and improves routing quality.

[0195] The above process can be considered as a Steiner tree database construction process.

[0196] In one embodiment, the topology generation process is as follows:

[0197] Please refer to Figure 9 For the search process, topology compression is performed on the wire mesh.

[0198] Please refer to Figure 10The generation of large wire networks was solved by variable clustering. At the same time, a cost function based on variable clustering was designed, which made a trade-off between the optimal wire length and the search time.

[0199] Under different weights, multiple points of a large wire network are divided into several sub-wire networks. Each sub-wire network has a corresponding Steiner tree topology. In order to connect these sub-wire networks, the centroids of all sub-wire networks are used as their feature points. These feature points are connected by Steiner trees to make the sub-wire networks have topological relationships.

[0200] Please refer to Figure 11 To avoid congestion during subsequent routing that could prevent routing from being completed, the impact of the Steiner tree on layout congestion must be considered during the topology phase. Topology edges that need routing should be shifted to areas with less congestion. This involves moving edges of the existing topology tree to avoid congestion; such movements do not change the length of the Steiner tree.

[0201] In addition, please refer to Figure 12 In one embodiment, an A* inflection point estimation algorithm is also designed to determine the inflection point through the A* rule.

[0202] The number of vias is estimated using a pre-connection method from point x to the endpoint. Since L-shaped routing is simple, with only two solutions and low time complexity, it is used in the pre-connection process. When two points can be routed, if the topology from point x to the endpoint is a straight line, there are no vias between them. If the topology from point x to the endpoint is a diagonal line, then L-shaped routing implies that there is a solution that requires only one via to complete the routing from point x to the endpoint. The number of vias in the final solution is always greater than or equal to the number of vias generated by L-shaped routing, so using the number of vias in L-shaped routing as an estimate is convergent. The estimated number of vias from point x to the endpoint is calculated from the pre-routing situation. Assuming the line segment connected to point x and with point x as the endpoint is the preceding line segment of point x, if the pre-routing is successful, a via will appear at point x, generated by the preceding line segment and the pre-routing line segment. Such a via is called an auxiliary via. The sum of the number of pre-routing vias and the number of auxiliary vias is the estimated number of vias.

[0203] When two points cannot be routed together, if the route is a straight line, it indicates an obstacle on the line connecting the two points. When the topology is a straight line and there is an obstacle, the best routing solution is a U-shaped route. A U-shaped route requires two vias, so when a straight line cannot be routed, the estimated lower bound for the number of vias is 2. When the route is a diagonal line, an L-shaped route cannot be routed, so an additional inflection point must be added to avoid the obstacle; the estimated lower bound for the number of vias is also 2. Since the pre-routed route is not routed, the number of vias generated by the preceding segment and the pre-routed segment cannot be calculated. Therefore, when a route cannot be routed together, the estimated number of vias is always 2.

[0204] In addition, refer to Figure 13 , Figure 13 This is a schematic diagram of the frame structure of the cabling resource pre-allocation device of the present invention. The present invention also proposes a cabling resource pre-allocation device, which includes:

[0205] Resource statistics module A10 is used to determine the target grid in the integrated circuit layout and the total amount of wiring resources in the target grid;

[0206] The resource planning module A20 is used to take the target resource demand of each target network in the target grid as a variable, and input the target resource demand and the total wiring resources as variables into a preset resource pre-allocation model for secondary planning solution to obtain the resource allocation of each target network in the target grid.

[0207] Optionally, the resource planning module A20 is further configured to:

[0208] The target resource demand and the total cabling resources, which are variables, are input into a preset resource pre-allocation model, and all the target resource demands input into the resource pre-allocation model are summarized to obtain the total target resource demand.

[0209] Establish a target quadratic function between the total target resource demand and the total amount of cabling resources, and use the minimum difference between the total target resource demand and the total amount of cabling resources as the target to perform secondary planning and adjustment of the target resource demand.

[0210] Optionally, the resource planning module A20 is further configured to:

[0211] The target resource requirement and the total wiring resources, which are variables, are input into a preset resource pre-allocation model, and the total resource requirement of the target net in the integrated circuit layout is obtained at the same time.

[0212] Based on the total resource demand, constraints are constructed for the target resource demand, and these constraints are applied to the target resource demand for secondary planning adjustments.

[0213] Optionally, the resource planning module A20 is further configured to:

[0214] The resource pre-allocation model is expanded using quadratic terms to transform it into a resource iteration model.

[0215] The set of all the target resource requirements is used as the target vector and input into the resource iteration model for iterative quadratic programming solution.

[0216] Optionally, the resource planning module A20 is further configured to:

[0217] Determine the congestion weight of the target grid, and input the resource allocation amount as the resource weight along with the congestion weight into a preset cabling cost function to obtain the cabling cost value of the target grid;

[0218] Based on the routing cost value of each target mesh, global routing is performed on all nets in the integrated circuit layout.

[0219] Optionally, the resource planning module A20 is further configured to:

[0220] Based on the routing cost value of each target mesh, determine the set of total routing cost values ​​that each net in the integrated circuit layout can pass through the mesh;

[0221] Obtain the acceptable length range of the net, and determine the target Steiner tree topology corresponding to the total cabling cost set based on the acceptable length range.

[0222] Optionally, the resource planning module A20 is further configured to:

[0223] Determine each connection point in the wire mesh, and determine the circumscribed rectangle formed between the connection points;

[0224] Based on the circumscribed rectangle, determine all edge vectors for each combination of connection points;

[0225] The lengths of each bus in the net are calculated based on all the edge vectors.

[0226] The optimal Steiner tree length corresponding to the net is determined based on the bus length.

[0227] The optimal Steiner tree line length is used as the lower limit of the acceptable line length range, and the total resource requirement of the net in the integrated circuit layout is used as the upper limit of the acceptable line length range; wherein, the total resource requirement is obtained by HV tree.

[0228] The specific implementation of the cabling resource pre-allocation device of the present invention is basically the same as the embodiments of the cabling resource pre-allocation method described above, and will not be repeated here.

[0229] Furthermore, the present invention also provides a computer-readable storage medium. The computer-readable storage medium of the present invention stores a cabling resource pre-allocation program, wherein, when executed by a processor, the cabling resource pre-allocation program implements the steps of the cabling resource pre-allocation method as described above.

[0230] The method implemented when the cabling resource pre-allocation procedure is executed can be referred to in various embodiments of the cabling resource pre-allocation method of the present invention, and will not be repeated here.

[0231] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0232] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0233] These computer program instructions may also be stored in a computer-readable storage unit that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage unit produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0234] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0235] It should be noted that any reference signs placed between parentheses in the claims should not be construed as limiting the claims. The word "comprising" does not exclude the presence of components or steps not listed in the claims. The word "a" or "an" preceding a component does not exclude the presence of a plurality of such components. The invention can be implemented by means of hardware comprising several different components and by means of a suitably programmed computer. In a unit claim enumerating several means, several of these means may be embodied by the same item of hardware. The use of the words first, second, and third, etc., does not indicate any order. These words can be interpreted as names.

[0236] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the invention.

[0237] The above description is merely a preferred embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent structural transformations made using the contents of the present invention's specification and drawings under the inventive concept of the present invention, or direct / indirect applications in other related technical fields, are included within the patent protection scope of the present invention.

Claims

1. A method for pre-allocating cabling resources, characterized in that, Before routing the integrated circuit, the routing resource pre-allocation method includes the following steps: Determine the target grid in the integrated circuit layout and the total amount of wiring resources in the target grid; The target resource requirement of each target net in the target grid is used as a variable. The target resource requirement and the total cabling resources are input into a preset resource pre-allocation model to perform a secondary planning on the target resource requirement, thereby obtaining the resource allocation amount of each target net in the target grid. The target resource requirement is the resource requirement of the target net in the target grid. The resource pre-allocation model is modeled as a quadratic programming mathematical model, and the resource allocation amount is the actual amount of resources to be allocated to the target net in the target grid.

2. The cabling resource pre-allocation method as described in claim 1, characterized in that, The step of inputting the target resource demand and the total cabling resources, which are used as variables, into a preset resource pre-allocation model for quadratic programming solution includes: The target resource demand and the total cabling resources, which are variables, are input into a preset resource pre-allocation model, and all the target resource demands input into the resource pre-allocation model are summarized to obtain the total target resource demand. Establish a target quadratic function between the total target resource demand and the total amount of cabling resources, and use the minimum difference between the total target resource demand and the total amount of cabling resources as the target to perform secondary planning and adjustment of the target resource demand.

3. The cabling resource pre-allocation method as described in claim 1, characterized in that, The step of inputting the target resource demand and the total cabling resources, which are used as variables, into a preset resource pre-allocation model for quadratic programming solution includes: The target resource requirement and the total wiring resources, which are variables, are input into a preset resource pre-allocation model, and the total resource requirement of the target net in the integrated circuit layout is obtained at the same time. Based on the total resource demand, constraints are constructed for the target resource demand, and these constraints are applied to the target resource demand for secondary planning adjustments.

4. The cabling resource pre-allocation method as described in claim 1, characterized in that, The step of inputting the target resource demand and the total cabling resources, which are used as variables, into a preset resource pre-allocation model for quadratic programming solution includes: The resource pre-allocation model is expanded using quadratic terms to transform it into a resource iteration model. The set of all the target resource requirements is used as the target vector and input into the resource iteration model for iterative quadratic programming solution.

5. The cabling resource pre-allocation method as described in claim 1, characterized in that, After the step of inputting the target resource demand and the total cabling resources as variables into a preset resource pre-allocation model for quadratic programming to obtain the resource allocation of each target net in the target grid, the method further includes: Determine the congestion weight of the target grid, and input the resource allocation amount as the resource weight along with the congestion weight into a preset cabling cost function to obtain the cabling cost value of the target grid; Based on the routing cost value of each target mesh, global routing is performed on all nets in the integrated circuit layout.

6. The cabling resource pre-allocation method as described in claim 5, characterized in that, The step of globally routing all nets in the integrated circuit layout based on the routing cost value of each target net includes: Based on the routing cost value of each target mesh, determine the set of total routing cost values ​​that each net in the integrated circuit layout can pass through the mesh; Obtain the acceptable length range of the net, and determine the target Steiner tree topology corresponding to the total cabling cost set based on the acceptable length range.

7. The cabling resource pre-allocation method as described in claim 6, characterized in that, The step of obtaining the acceptable wire length range of the wire mesh includes: Determine each connection point in the wire mesh, and determine the circumscribed rectangle formed between the connection points; Based on the circumscribed rectangle, determine all edge vectors for each combination of connection points; The lengths of each bus in the net are calculated based on all the edge vectors. The optimal Steiner tree length corresponding to the net is determined based on the bus length. The optimal Steiner tree line length is used as the lower limit of the acceptable line length range, and the total resource requirement of the net in the integrated circuit layout is used as the upper limit of the acceptable line length range.

8. A cabling resource pre-allocation device, characterized in that, The wiring resource pre-allocation device, which pre-allocates wiring resources before routing the integrated circuit, includes: The resource statistics module is used to determine the target grid in the integrated circuit layout and the total amount of wiring resources in the target grid; The resource planning module is used to take the target resource demand of each target network in the target grid as variables, and input the target resource demand and the total cabling resources as variables into a preset resource pre-allocation model for quadratic programming solution to obtain the resource allocation amount of each target network in the target grid; the target resource demand is the resource demand of the target network in the target grid, the resource pre-allocation model is modeled as a quadratic programming mathematical model, and the resource allocation amount is the actual amount of resources to be allocated to the target network in the target grid.

9. A computing device, characterized in that, The computing device includes a processor, a storage unit, and a cabling resource pre-allocation program stored on the storage unit that can be executed by the processor, wherein when the cabling resource pre-allocation program is executed by the processor, it implements the steps of the cabling resource pre-allocation method as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a cabling resource pre-allocation program, wherein when the cabling resource pre-allocation program is executed by a processor, it implements the steps of the cabling resource pre-allocation method as described in any one of claims 1 to 7.

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