Scan driving circuit, display device and driving method thereof

Abstract

The application discloses a scanning driving circuit, a display device and a driving method thereof. The scanning driving circuit comprises a plurality of shift registers; the shift register comprises a driving control module, a first potential control module and a scanning output module. The driving control module is used for controlling the potentials of a first node and a second node according to a clock signal and an input signal; the first potential control module is used for controlling whether a first potential signal is transmitted to a third node according to a first switch signal; the scanning output module is electrically connected with the first node, the second node and the third node respectively, and is used for outputting the potential of the third node or a second potential signal as a scanning signal to a pixel circuit in response to the potentials of the first node and the second node; wherein the first switch signal controls the frequency of the scanning signal by controlling the on-off state of the first potential control module. The embodiment of the application can make the display device have the function of partition frequency display, and the partition position is adjustable.

Description

Technical Field

[0001] This invention relates to the field of display technology, and in particular to a scanning driving circuit, a display device, and a driving method thereof. Background Technology

[0002] With the development of display technology, the application scenarios of display devices are increasing, and users' display needs are becoming more diversified. Based on the release of products such as foldable phones and foldable laptops, the application scenarios of display devices have been further expanded. For users' needs to display multiple applications simultaneously on a terminal product, some interfaces (such as game interfaces) require high-frequency display to ensure smooth visuals, while other interfaces can meet display requirements with low frequencies. This latter part is expected to use low-frequency display to reduce product power consumption. However, existing scanning drive circuits only support the full-screen switching frequency of the display panel, which cannot meet users' needs for displaying multiple scenes on a single screen. They cannot achieve zoned frequency display on the display device, nor can they adjust the zone positions. Summary of the Invention

[0003] The present invention provides a scanning driving circuit, a display device and a driving method thereof, so that the display device has a segmented frequency display function and the segmented position is adjustable.

[0004] In a first aspect, embodiments of the present invention provide a scan driving circuit, including: a plurality of shift registers;

[0005] The shift register includes:

[0006] The drive control module is used to control the potential of the first node and the second node according to the clock signal and the input signal;

[0007] The first potential control module is used to control whether the first potential signal is transmitted to the third node according to the first switch signal;

[0008] The scanning output module is electrically connected to the first node, the second node, and the third node respectively, and is used to respond to the potential of the first node and the second node, and output the potential of the third node or the second potential signal as a scanning signal to the pixel circuit; wherein, the first switch signal controls the frequency of the scanning signal by controlling the on and off state of the first potential control module.

[0009] Optionally, the first potential control module includes: a first transistor; the gate of the first transistor is connected to the first switching signal, the first terminal of the first transistor is connected to the first potential signal, and the second terminal of the first transistor is electrically connected to the third node;

[0010] Preferably, the first potential control module in all shift registers is connected to the same first switch signal.

[0011] Optionally, the shift register further includes: a second potential control module, electrically connected to the third node and connected to a second switch signal; the second switch signal is used to control the switching state of the second potential control module to be opposite to the switching state of the first potential control module;

[0012] Preferably, the second potential control module in all shift registers is connected to the same second switch signal.

[0013] Preferably, the second potential control module includes: a second transistor; the gate of the second transistor is connected to the second switching signal, the first terminal of the second transistor is connected to the second potential signal, and the second terminal of the second transistor is electrically connected to the third node;

[0014] Preferably, the aspect ratio of the first transistor is greater than that of the second transistor;

[0015] Preferably, the first transistor and the second transistor have the same channel type, and the first switching signal and the second switching signal are inverted signals.

[0016] Alternatively, the first transistor and the second transistor may have different channel types, and the first switching signal may be multiplexed as the second switching signal.

[0017] Optionally, the scan output module includes: a third transistor and a fourth transistor;

[0018] The gate of the third transistor is electrically connected to the first node, the first terminal of the third transistor is connected to the second potential signal, and the second terminal of the third transistor serves as the output terminal of the scan output module; the gate of the fourth transistor is electrically connected to the second node, the first terminal of the fourth transistor is electrically connected to the third node, and the second terminal of the fourth transistor is electrically connected to the second terminal of the third transistor.

[0019] Optionally, the drive control module includes:

[0020] An input unit, electrically connected to the first node, is used to transmit the input signal to the first node in response to a first clock signal;

[0021] The first control unit is electrically connected to the fourth node and is used to transmit the second potential signal to the fourth node in response to the first clock signal.

[0022] The second control unit is electrically connected to the fourth node and the second node respectively, and is used to transmit the second clock signal to the second node in response to the second clock signal and the potential of the fourth node;

[0023] The first node mutual control unit is electrically connected to the first node and the fourth node respectively, and is used to transmit the first clock signal to the fourth node in response to the potential of the first node, and to transmit the first potential signal to the first node in response to the second clock signal and the potential of the fourth node.

[0024] The second node mutual control unit is electrically connected to both the first node and the second node, and is used to transmit the first potential signal to the second node in response to the potential of the first node.

[0025] Optionally, the plurality of shift registers are cascaded; the scan signal serves as the input signal for the next-stage shift register.

[0026] Optionally, the plurality of shift registers are cascaded; the shift register further includes: a stage output module, electrically connected to the first node and the second node respectively, for outputting a first potential signal or a second potential signal as a stage transmission signal according to the potential of the first node and the second node; the stage transmission signal is used as the input signal of the next stage shift register;

[0027] Preferably, the stage transmission module includes a fifth transistor and a sixth transistor;

[0028] The gate of the fifth transistor is electrically connected to the first node, the first terminal of the fifth transistor is connected to the second potential signal, and the second terminal of the fifth transistor serves as the output terminal of the stage transmission module; the gate of the sixth transistor is electrically connected to the second node, the first terminal of the sixth transistor is connected to the first potential signal, and the second terminal of the sixth transistor is electrically connected to the second terminal of the fifth transistor.

[0029] Optionally, the pixel circuit includes: a driving transistor, a gate initialization transistor, and a threshold compensation transistor; the gate initialization transistor and the threshold compensation transistor are both electrically connected to the gate of the driving transistor;

[0030] For the same pixel circuit, the scan signal output by the front-stage shift register is provided to the gate of the gate initialization transistor, and the scan signal output by the rear-stage shift register is provided to the gate of the threshold compensation transistor.

[0031] Preferably, the driving transistor is a P-type transistor, and the gate initialization transistor and the threshold compensation transistor are both N-type transistors; the potential of the first potential signal is higher than the potential of the second potential signal.

[0032] Secondly, embodiments of the present invention also provide a display device, including a pixel circuit and a scanning driving circuit provided in any embodiment of the present invention.

[0033] Thirdly, embodiments of the present invention also provide a driving method for a display device, used to drive the display device provided in any embodiment of the present invention, the driving method comprising:

[0034] Based on the target partition position of the display device, the potential transition time of the first switch signal in a frame display is determined, thereby determining the position of the two adjacent shift registers that output scan signals of different frequencies in the scan drive circuit, so as to realize the display device's partitioned frequency display based on the target partition position.

[0035] The scanning drive circuit provided in this embodiment of the invention includes multiple shift registers, each of which includes a drive control module, a first potential control module, and a scan output module. By adjusting the on / off state of the first potential control module through a first switch signal, the transmission of the first potential signal to the third node can be allowed / blocked, thereby allowing / blocking the scan output module to output the conduction potential of the scan signal, thus achieving frequency control of the scan signal. By controlling the potential transition of the first switch signal during a frame display, some shift registers in the scanning drive circuit can operate in a high-frequency mode, while other shift registers operate in a low-frequency mode, thereby achieving segmented frequency display in the column direction of the display device. Furthermore, by adjusting the specific potential transition time of the first switch signal, the display partition position of the display device can be flexibly adjusted. Therefore, compared to the prior art, this embodiment of the invention enables the display device to have segmented frequency display functionality, and the partition position is adjustable.

[0036] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0037] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0038] Figure 1 This is a schematic diagram illustrating the composition of a display frame at different refresh rates.

[0039] Figure 2 This is a schematic diagram of a scanning drive circuit provided in an embodiment of the present invention;

[0040] Figure 3 This is a schematic diagram of another scanning drive circuit provided in an embodiment of the present invention;

[0041] Figure 4 This is a schematic diagram of the structure of a shift register provided in an embodiment of the present invention;

[0042] Figure 5 This is a schematic diagram of the driving timing of a shift register in high-frequency operating mode provided by an embodiment of the present invention;

[0043] Figure 6 This is a schematic diagram of the driving timing of a shift register in low-frequency operating mode provided by an embodiment of the present invention;

[0044] Figure 7 This is a schematic diagram of the driving timing of a display device provided in an embodiment of the present invention;

[0045] Figure 8 This is a schematic diagram of another shift register structure provided in an embodiment of the present invention;

[0046] Figure 9 This is a schematic diagram of another shift register structure provided in an embodiment of the present invention;

[0047] Figure 10 This is a schematic diagram of another shift register structure provided in an embodiment of the present invention;

[0048] Figure 11 This is a schematic diagram of another shift register structure provided in an embodiment of the present invention;

[0049] Figure 12 This is a schematic diagram of another shift register structure provided in an embodiment of the present invention;

[0050] Figure 13 This is a schematic diagram of the driving timing of a display device in a first type of display frame provided by an embodiment of the present invention;

[0051] Figure 14 This is a schematic diagram of the driving timing of a display device in a second type of display frame provided by an embodiment of the present invention;

[0052] Figure 15 This is a schematic diagram of the driving timing of another display device provided in an embodiment of the present invention;

[0053] Figure 16This is a schematic diagram of a pixel circuit provided in an embodiment of the present invention;

[0054] Figure 17 This is a schematic diagram of the driving timing of a pixel circuit provided in an embodiment of the present invention;

[0055] Figure 18 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention;

[0056] Figure 19 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention. Detailed Implementation

[0057] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0058] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion.

[0059] To better explain the solution of the present invention, the basic structure and driving process of the display panel in the display device will be briefly described below.

[0060] Display panels typically include a scan drive circuit (or GIP circuit) and pixel circuits arranged in an array in the display area. The scan drive circuit includes multiple cascaded shift registers. The pixel circuits, together with the light-emitting devices, form a sub-pixel. Each shift register is connected to at least one scan line and provides a scan signal to the corresponding row of sub-pixels through the scan lines. Each column of sub-pixels is connected to a data line.

[0061] During screen display, data is written to each pixel circuit through a line-by-line scan. Specifically, the shift register provides scan signals to the pixel circuits via scan lines. Corresponding to the duration of the scan signal's on-state potential, the data voltage on the data lines is transmitted to the corresponding pixel circuit to achieve data writing. Each pixel circuit outputs a drive current based on the data voltage, driving the light-emitting device to emit light for display. When the scan line provides a cutoff potential, the data voltage on the data lines cannot be transmitted to the corresponding pixel circuit, and no data is written.

[0062] In existing technologies, for display panels capable of switching display frequencies, the display frames of sub-pixels can be divided into active frames and idle frames. In an active frame, a shift register provides an on-potential to the pixel circuit, allowing data voltage to be written to the pixel circuit; in an idle frame, the shift register provides an off-potential to the pixel circuit, and the pixel circuit no longer writes data.

[0063] Refresh rate can be understood as the number of refresh frames contained within a unit of time. For example, a high-frequency display may only include refresh frames. See [link to relevant documentation] for details. Figure 1 A refresh frame is represented by a shaded box, and a hold frame by a blank box. At a refresh rate f, the display panel only displays refresh frames. For example, when f = 60Hz, the display panel refreshes 60 display frames per second. Low-frequency refresh is implemented as follows: as the refresh rate decreases, hold frames are inserted between adjacent refresh frames, maintaining the total number of display frames per unit time and the display duration of each frame. When the refresh rate is f / 2, one hold frame is inserted between every two adjacent refresh frames. When the refresh rate is f / 3, two hold frames are inserted between every two adjacent refresh frames. And so on, until the refresh rate is f / (N+1), where N hold frames are inserted between every two adjacent refresh frames.

[0064] In the driving process of existing display devices, the frequency switching of the entire screen is usually achieved by adjusting the input signal provided to the first-stage shift register in the scan drive circuit to control whether each stage of the shift register outputs the on-state potential of the scan signal. However, in the current technology, only one refresh rate can exist on the entire display panel in one frame, so it can only achieve frequency switching of the entire screen and cannot support the display device to display multiple zones with different frequencies on a single screen.

[0065] To address the aforementioned technical problems, embodiments of the present invention provide a scanning drive circuit. Figure 2 This is a schematic diagram of a scanning drive circuit provided in an embodiment of the present invention. See also... Figure 2The scan drive circuit includes multiple shift registers 10, each of which may have the same structure. Specifically, the shift register 10 includes a drive control module 110, a first potential control module 130, and a scan output module 140.

[0066] The drive control module 110 controls the potentials of the first node N1 and the second node N2 based on the clock signal ECK and the input signal. The first potential control module 130 controls whether the first potential signal VGH is transmitted to the third node N3 based on the first switch signal SW1. The scan output module 140 is electrically connected to the first node N1, the second node N2, and the third node N3 respectively, and outputs the potential of the third node N3 or the second potential signal VGL as a scan signal to the pixel circuit in response to the potentials of the first node N1 and the second node N2. The first switch signal SW controls the frequency of the scan signal by controlling the on / off state of the first potential control module 130.

[0067] For example, the first potential signal VGH is the on-state potential of the functional module in the pixel circuit that receives the scan signal, and the second potential signal VGL is the off-state potential of the functional module in the pixel circuit that receives the scan signal. This functional module is, for example, a module that controls the data voltage writing process of the gate of the driving transistor in the pixel circuit. Both the first potential signal VGH and the second potential signal VGL can be DC voltage signals; for example, the first potential signal VGH is a high potential, and the second potential signal VGL is a low potential. The first node N1 and the second node N2 are the first output terminal and the second output terminal of the drive control module 110, respectively; the third node N3 is the output terminal of the first potential control module 130. The clock signal ECK can be understood as the collective term for all clock signals received by the drive control module 110, and may include multiple clock signals with alternating high and low potentials.

[0068] For example, the scan output module 140 may include a first control terminal, a second control terminal, a first input terminal, a second input terminal, and an output terminal. The first control terminal is connected to a first node N1, the second control terminal is connected to a second node N2, the first input terminal is connected to a second potential signal VGL, the second input terminal is connected to a third node N3, and the output terminal outputs a scan signal. Therefore, the scan output module 140 can control whether the first input terminal and the output terminal are connected based on the potential of the first control terminal (i.e., the first node N1), thereby controlling whether the second potential signal VGL is output as a scan signal; and based on the potential of the second control terminal (i.e., the second node N2), control whether the second input terminal and the output terminal are connected, thereby controlling whether the potential of the third node N3 is output as a scan signal. When the scan output module 140 controls the connection between the second input terminal and the output terminal according to the potential of the second control terminal, if the first switch signal SW1 controls the first potential control module 130 to conduct, then the third node N3 stably receives the high potential of the first potential signal VGH. At this time, the scan signal is also at a high potential, which is equivalent to the scan signal including a conduction pulse in this display frame. If the first switch signal SW1 controls the first potential control module 130 to be turned off, then the potential of the third node N3 is floating and cannot provide a high potential to the output terminal of the scan output module 140. Therefore, the scan signal maintains a low potential, which is equivalent to the scan signal not containing a conduction pulse in this display frame. Therefore, controlling the on / off state of the first potential control module 130 by the first switch signal SW1 is equivalent to controlling whether the conduction potential source, the first potential signal VGH, can be provided to the second input terminal of the scan output module 140, thereby controlling whether the scan output module outputs a conduction pulse and realizing the adjustment of the frequency of the scan signal. Here, the frequency of the scan signal can be considered as the pulse frequency of the conduction pulse in the scan signal.

[0069] For ease of explanation, the operating mode of shift register 10 that enables the shifting output of the conduction pulse in the input signal is called the high-frequency operating mode, and the operating mode of shift register 10 that does not enable the shifting output of the conduction pulse in the input signal is called the low-frequency operating mode. Therefore, the first switch signal SW1 controls the on / off state of the first potential control module 130, thereby controlling the operating mode of shift register 10. When a certain stage shift register 10 always operates in the high-frequency operating mode, it can achieve the shifting output of the conduction pulse in its input signal, making the frequency of the scan signal the same as the frequency of the input signal; when a certain stage shift register 10 is in the low-frequency operating mode for at least a portion of the time, the frequency of the scan signal output by that shift register 10 is lower than the frequency of its input signal.

[0070] Taking the example of the scan signals output by each shift register 10 being transmitted through each row of scan lines to the functional modules related to the data voltage writing process in each row of pixel circuits, when a certain shift register 10 operates in high-frequency mode, the scan signal contains a conduction pulse, which can control the pixel circuit of the corresponding row to refresh data, making the current frame of that row of pixel circuits a refreshed frame; while when a certain shift register 10 operates in low-frequency mode, the scan signal does not contain a conduction pulse, so the pixel circuit of the corresponding row cannot refresh data, making the current frame of that row of pixel circuits a held frame. Therefore, the frequency of the scan signal determines the data refresh frequency of the pixel circuit. Based on this, by controlling the potential transition of the first switch signal SW1, the operating mode of each shift register 10 can be controlled in each frame of display, thereby realizing the display of different frequencies in the column direction of the display device.

[0071] The scanning drive circuit provided in this embodiment of the invention includes multiple shift registers 10, each shift register 10 comprising: a drive control module 110, a first potential control module 130, and a scan output module 140. By adjusting the on / off state of the first potential control module 130 through the first switch signal SW1, the transmission of the first potential signal VGH to the third node N3 can be allowed / blocked, thereby allowing / blocking the conduction potential of the scan output module 140 outputting the scan signal GOUT, thus achieving frequency control of the scan signal. By controlling the potential transition of the first switch signal SW1 during a frame display, some shift registers 10 in the scanning drive circuit can operate in a high-frequency mode, while other shift registers 10 operate in a low-frequency mode, thereby achieving segmented frequency display in the column direction of the display device. Furthermore, by adjusting the specific potential transition time of the first switch signal SW1, the display partition position of the display device can be flexibly adjusted. Therefore, compared to the prior art, this embodiment of the invention enables the display device to have segmented frequency display functionality, and the partition position is adjustable.

[0072] See also Figure 2 Based on the above embodiments, optionally, multiple shift registers 10 can be cascaded. Specifically, the scan signal output by the current shift register 10 can be set as the input signal for the next shift register 10. For example... Figure 2 As shown, the first-stage shift register 101 receives the first-stage input signal EIN1 and outputs the first-stage scan signal GOUT1 based on the first-stage input signal EIN1 and the first switch signal SW1. The first-stage scan signal GOUT1 serves as the second-stage input signal EIN2 and is transmitted to the second-stage shift register 102. The second-stage shift register 102 outputs the second-stage scan signal GOUT2 (serving as the third-stage input signal EIN3) based on the second-stage input signal EIN2 and the first switch signal SW1, and so on.

[0073] Based on the above embodiments, optionally, the first potential control module 130 in each level of shift register 10 can all be connected to the same first switch signal SW1, so that each level of first potential control module 130 is simultaneously turned on or off in response to the first switch signal SW1. This configuration simplifies the structure of the scan drive circuit, reduces the number of output ports of the drive chip, lowers the cost, and makes the scan drive circuit easy to implement and apply. For example, by controlling the first switch signal SW1 to maintain the on potential of the output first potential control module 130 in some display frames and to perform potential transitions in some display frames, the frequencies of the scan signals output by at least two shift registers 10 can be different, thereby realizing the segmented frequency display of the display device. Furthermore, by adjusting the potential transition time of the first switch signal SW1 in a frame of display, the boundary position of the shift register 10's working mode switching can be adjusted, thereby realizing the adjustment of the display partition position of the display device. Each level shift register 10 is connected to at least one row of pixel circuits, and the number of shift registers 10 in high-frequency working mode in a frame determines the number of pixel circuit rows refreshed in that frame.

[0074] according to Figure 2 The cascading of shift registers 10 in the display panel enables zoned frequency reduction display. Specifically, when the first switch signal SW1 controls the first potential control module 130 of any shift register 10 to turn off during the stage when the shift register 10 should output the on-state potential of the scan signal, the shift register 10 will be unable to output the on-state potential of the scan signal, making the frequency of the scan signal of this stage lower than the frequency of the scan signal of the previous stage. The shift register 10 of the previous stage and the shift register 10 of this stage correspond to the frequency reduction display zone position of the display panel. Furthermore, in the display of this frame, since the shift register 10 of this stage cannot output the on-state potential, the input signal of the shift register 10 of the next stage does not contain the on-state pulse. Therefore, even if the first switch signal SW1 restores the on-state potential of the first potential control module 130 during the stage when the shift register 10 of the next stage is active, since there is no on-state pulse in the input signal of the shift register 10 of the next stage, the shift register 10 of the next stage cannot output the on-state potential of the scan signal, but instead continuously outputs the off-state potential.

[0075] The above embodiments provide structures for scanning drive circuits capable of achieving zoned frequency reduction display, but are not intended to limit the invention. In other embodiments, by setting the shift registers 10 at each stage to adopt other cascading methods, the scanning drive circuit can support arbitrarily adjustable zoned frequency reduction and increase display functions.

[0076] Figure 3 This is a schematic diagram of another scanning drive circuit provided in an embodiment of the present invention. See also... Figure 3In one embodiment, optionally, each level of shift register 10 further includes a level output module 130, and the shift registers 10 at each level are cascaded through the level output module 130.

[0077] Specifically, in any level shift register 10, the stage output module 120 is electrically connected to the first node N1 and the second node N2, respectively, and is used to output the first potential signal VGH or the second potential signal VGL as the stage output signal according to the potentials of the first node N1 and the second node N2. The stage output signal serves as the input signal for the next level shift register 10. The cascading method between each level shift register 10 can be as follows: Figure 3 As shown, the first-stage shift register 101 receives the first-stage input signal EIN1 and outputs the first-stage transmission signal Carry1 and the first-stage scan signal GOUT1 based on the first-stage input signal EIN1, the clock signal ECK, and the first switch signal SW1. The first-stage transmission signal Carry1 serves as the second-stage input signal EIN2 and is transmitted to the second-stage shift register 102. The second-stage shift register 102 outputs the second-stage transmission signal Carry2 (serving as the input signal EIN3 of the third-stage shift register) and the second-stage scan signal GOUT2 based on the second-stage input signal EIN2, the clock signal ECK, and the first switch signal SW1, and so on.

[0078] The following is combined Figure 4 Briefly describe the control process of any level shift register 10. For example... Figure 4 As shown, the clock signal may specifically include a first clock signal ECK1 and a second clock signal ECK2. See also Figure 4For example, the drive control module 110 controls the potentials of the first node N1 and the second node N2 in response to the first clock signal ECK1, the second clock signal ECK2, the input signal EIN, the first potential signal VGH, and the second potential signal VGL. The output of the stage transmission module 120 is controlled by the potentials of the first node N1 and the second node N2. Specifically, the first control terminal 21 of the stage transmission module 120 is connected to the first node N1, the second control terminal 22 is connected to the second node N2, the first input terminal 23 is connected to the second potential signal VGL, the second input terminal 24 is connected to the first potential signal VGH, and the output terminal 25 outputs the stage transmission signal Carry. The stage transmission output module 120 determines whether there is a connection between its first input terminal 23 and output terminal 25 based on the potential of the first node N1, thereby determining whether to output the second potential signal VGL as the stage transmission signal Carry; and the stage transmission output module 120 determines whether there is a connection between its second input terminal 24 and output terminal 25 based on the potential of the second node N2, thereby determining whether to output the first potential signal VGH as the stage transmission signal Carry. The first potential control module 130 determines whether to output the first potential signal VGH to the third node N3 based on the potential of the first switch signal SW1. The scan output module 140 is controlled by the potentials of the first node N1, the second node N2, and the third potential N3, specifically: the first control terminal 41 of the scan output module 140 is connected to the first node N1, the second control terminal 42 is connected to the second node N2, the first input terminal 43 is connected to the second potential signal VGL, the second input terminal 44 is connected to the third node N3, and the output terminal 45 outputs the scan signal GOUT. Based on the potential of the first node N1, the scan output module 140 determines whether there is a connection between the first input terminal 43 and the output terminal 45 of the scan output module 140, thereby determining whether to output the second potential signal VGL as the scan signal GOUT; and based on the potential of the second node N2, the scan output module 140 determines whether there is a connection between the second input terminal 44 and the output terminal 45 of the scan output module 140, thereby determining whether to output the potential of the third node N3 as the scan signal GOUT.

[0079] In other words, under the control of the potentials of the first node N1 and the second node N2, the stage transmission output module 120 and the scan output module 140 actually have the same conduction state. When the drive control module 110 controls the first node N1 to be at an effective potential, both the stage transmission output module 120 and the scan output module 140 are connected between their first input and output terminals, making the stage transmission signal Carry and the scan signal GOUT both the second potential signal VGL. When the drive control module 110 controls the second node N2 to be at an effective potential, both the stage transmission output module 120 and the scan output module 140 are connected between their second input and output terminals. The difference is that the second input terminal 24 of the stage transmission output module 120 is directly connected to the first potential signal VGH, while the potential of the third node N3 connected to the second input terminal 24 of the scan output module 140 is controlled by the first potential control module 130. Therefore, when the second node N2 is at an effective potential, the stage transmission signal Carry is the first potential signal VGH, and the potential of the scan signal GOUT depends on the current conduction state of the first potential control module 130. The effective potential is the potential that enables conduction between the corresponding input and output terminals of the control level transmission output module 120 and the scan output module 140.

[0080] Taking the first potential control module 130 as an example, which is turned on under low potential control, and the first potential signal VGH as the turn-on potential of the functional module in the pixel circuit that receives the scan signal GOUT. (See also...) Figure 5 If the second node N2 is at a valid potential, that is, during the stage when the stage transmission module 120 outputs the conduction potential (including...) Figure 5 In stages T12-T14, the first switch signal SW1 remains at a low potential V2, turning on the first potential control module 130. Consequently, the third node N3 maintains a high potential VGH for the first potential signal. Therefore, the scan signal GOUT is also on during this stage, controlling the pixel circuit of the corresponding row to refresh data. Thus, it can be considered that the shift register 10 is operating in high-frequency mode at this time. (See also...) Figure 6 If, during the stage where the output module 120 outputs the on-state potential, the first switch signal SW1 remains at a high potential V1, causing the first potential control module 130 to turn off, the third node N3 to float, and the scan signal GOUT to maintain the off-state potential from the previous stage. Since the first input and output terminals of the scan output module 140 are connected, the third node N3 is also pulled low. Therefore, in this case, the scan signal GOUT does not contain an on-state potential, and the pixel circuit of the corresponding row cannot perform data refresh. Thus, it can be considered that the shift register 10 is operating in a low-frequency mode at this time.

[0081] In summary, during the process of the drive control module 110 controlling the first node N1 and the second node N2 to alternately change to effective potentials, the stage output module 120 can realize the shift output of the input signal EIN. When the input signal EIN has a conduction pulse, the stage output module 120 of each stage shift register 10 can realize the step-by-step transmission of the conduction pulse, providing a high-frequency stage transmission signal Carry sequence, which provides a basis for the free switching of each stage shift register 10 in high-frequency operating mode and low-frequency operating mode. For any shift register 10, the first switch signal SW1 controls the shift register 10 to work in high-frequency operating mode or low-frequency operating mode by controlling the conduction state of the first potential control module 130.

[0082] It should be noted that the first switch signal SW1 functions during the period when the Carry transmission signal is outputting its on-state potential. Controlling the potential of the first switch signal SW1 during this period controls whether the scan signal GOUT can output its on-state potential in one frame of display. In other stages, since the first node N1 is at an effective potential, the first input terminal and the output terminal of the scan output module 140 are connected, and the potential of the third node N3 does not affect the potential of the scan signal GOUT. Therefore, the potential of the first switch signal SW1 can be arbitrarily set. For example... Figure 5 The first switching signal SW1 can always be kept at a low potential V2 to reduce signal potential jumps and simplify control logic. For example, the high potential V1 can be the potential of the first potential signal VGH, and the low potential V2 can be the potential of the second potential signal VGL.

[0083] For the entire scan drive circuit, the output terminal 45 of the scan output module 140 in each shift register 10 is connected to at least one row of pixel circuits. Therefore, by controlling the operating mode of each shift register 10 in each frame of display, the display device can achieve different frequencies of display in the column direction. Figure 7 This is a schematic diagram of the driving timing of a display device provided in an embodiment of the present invention. Figure 7Taking a three-screen display as an example, assuming the display panel is divided into a first display area A1, a second display area A2, and a third display area A3 from top to bottom, with refresh rates of f, f / 2, and f respectively. Then, the transition from the first display area A1 to the second display area A2 is equivalent to a frequency division display where the display frequency decreases from high to low, and the transition from the second display area A2 to the third display area A3 is equivalent to a frequency division display where the display frequency increases from low to high. The pulse frequency of the scan signal GOUTA1 output by the shift register in the first display area A1 is f, for example, one conduction pulse per frame; the pulse frequency of the scan signal GOUTA2 output by the shift register in the second display area A2 is f / 2, for example, one conduction pulse per odd-numbered frame; and the pulse frequency of the scan signal GOUTA3 output by the shift register in the third display area A3 returns to f, for example, one conduction pulse per frame. The size of each display area is determined by the number of shift registers providing the corresponding frequency scan signal.

[0084] See Figure 7 It can be seen that during the entire display process, the display device can achieve segmented frequency display in the column direction by controlling the potential transition of the first switch signal SW1, and the display segment position can be adjusted by adjusting the potential transition time. Specifically, the segmented frequency display process of the display device includes a first type of display frame (e.g., display frames F1, F3, and F5) and a second type of display frame (e.g., display frames F2 and F4). In the first type of display frame, the first switch signal SW1 is always maintained at a low potential, so that all shift registers 10 operate in high-frequency mode, thereby causing all row pixel circuits to refresh data. In the second type of display frame, the first switch signal SW1 is maintained at a low potential for part of the time and at a high potential for the rest of the time, so that some shift registers 10 operate in high-frequency mode, and other shift registers 10 operate in low-frequency mode. The pixel circuits of the corresponding rows of shift registers 10 in high-frequency mode refresh data, while the pixel circuits of other rows maintain the data voltage at the time of the last data refresh. Specifically, the transition from a low to a high potential in the first switch signal SW1 corresponds to the display partition position between the first display area A1 and the second display area A2 in the display panel (e.g., the partition position where the refresh rate changes from high to low). Before the transition of the first switch signal SW1, each row of pixel circuits entering the scanning stage refreshes its data; after the transition, each row of pixel circuits entering the scanning stage retains its data. Similarly, the transition from a high to a low potential in the first switch signal SW1 corresponds to the display partition position between the second display area A2 and the third display area A3 in the display panel (e.g., the partition position where the refresh rate changes from low to high). Before the transition of the first switch signal SW1, each row of pixel circuits entering the scanning stage retains its data; after the transition, each row of pixel circuits entering the scanning stage refreshes its data.

[0085] Specifically, by adjusting the specific potential transition time of the first switch signal SW1, the display zone position of the display device can be flexibly adjusted. Figure 7 Taking the partition position between the first display area A1 and the second display area A2 as an example, in each even-numbered display frame, if the moment when the control signal SW1 changes from low potential to high potential is earlier than... Figure 7 When the potential jumps in the middle, the number of shift registers corresponding to the first display area A1 can be reduced, thereby realizing the upward shift of the partition position between the first display area A1 and the second display area A2.

[0086] For example, there can be multiple types of second-type display frames, each corresponding to at least one display partition position, where the operating modes of the two adjacent shift registers above and below the display partition position are different. For instance, the two potential transitions of the first switch signal SW1 in display frame F2 can correspond to two display partition positions of the display device, respectively. In this display frame, the operating modes of the shift registers corresponding to the first display area A1 and the second display area A2 are different, and the operating modes of the shift registers corresponding to the second display area A2 and the third display area A3 are different. Alternatively, in other second-type display frames, one display area may be refreshed while the other display areas retain data.

[0087] The scanning drive circuit provided in this embodiment of the invention includes multiple cascaded shift registers 10. Each shift register 10 includes a drive control module 110, a stage output module 120, a first potential control module 130, and a scan output module 140. During the process of the drive control module 110 controlling the first node N1 and the second node N2 to alternately change to effective potentials, the stage output module 120 can realize the shifted output of the input signal EIN. Through the stage output modules 120 of each shift register 10, the conduction pulse can be transmitted stage by stage, providing a high-frequency stage transmission signal Carry, which provides a basis for the free switching of each shift register 10 between high-frequency and low-frequency operating modes. By adjusting the on / off state of the first potential control module 130 through the first switch signal SW1 to enable / block the conduction potential of the scan output module 140 outputting the scan signal GOUT, the operating mode of the shift register 10 can be controlled. By controlling the potential transition of the first switch signal SW1 during a single frame display, some shift registers 10 in the scan drive circuit can operate in a high-frequency mode, while other shift registers 10 operate in a low-frequency mode. This enables segmented frequency display in the column direction of the display device. By controlling the different potential transition directions of the first switch signal SW1, the display device can freely switch between high-frequency and low-frequency displays in the column direction, as well as between low-frequency and high-frequency displays. Furthermore, by adjusting the specific potential transition time of the first switch signal SW1, the display partition positions of the display device can be flexibly adjusted. Therefore, compared to the prior art, the embodiments of the present invention enable the display device to have segmented frequency display functionality, and the partition positions are adjustable.

[0088] The specific structure of shift register 10 will be described first by example, and then the specific driving process of driving the display device to perform multi-frequency display based on the scanning driving circuit will be described by example.

[0089] Figure 8 This is a schematic diagram of another shift register structure provided in an embodiment of the present invention. See also... Figure 8 In one embodiment, the drive control module 110 may optionally include: an input unit 111, a first control unit 112, a second control unit 113, a first node mutual control unit 114, and a second node mutual control unit 115.

[0090] The input unit 111 is electrically connected to the first node N1 and transmits the input signal EIN to the first node N1 in response to the first clock signal ECK1. The first control unit 112 is electrically connected to the fourth node N4 and transmits the second potential signal VGL to the fourth node N4 in response to the first clock signal ECK1. The second control unit 113 is electrically connected to the fourth node N4 and the second node N2 respectively and transmits the second clock signal ECK2 to the second node N2 in response to the second clock signal ECK2 and the potential of the fourth node N4. The first node inter-control unit 114 is electrically connected to the first node N1 and the fourth node N4 respectively and transmits the first clock signal ECK1 to the fourth node N4 in response to the potential of the first node N1, and transmits the first potential signal VGH to the first node N1 in response to the second clock signal ECK2 and the potential of the fourth node N4. The second node inter-control unit 115 is electrically connected to the first node N1 and the second node N2 respectively and transmits the first potential signal VGH to the second node N2 in response to the potential of the first node N1.

[0091] Specifically, input unit 111 includes transistor M7. The gate of transistor M7 is connected to the first clock signal ECK1, its first terminal is connected to the input signal EIN, and its second terminal is electrically connected to the first node N1. First control unit 112 includes transistor M8. The gate of transistor M8 is connected to the first clock signal ECK1, its first terminal is connected to the second potential signal VGL, and its second terminal is electrically connected to the fourth node N4. Second control unit 113 includes transistor M12, transistor M13, and capacitor C1. The gate of transistor M12 is electrically connected to the fourth node N4, its first terminal is connected to the second clock signal ECK2, capacitor C1 is connected between the gate and the second terminal of transistor M12, the gate of transistor M13 is connected to the second clock signal ECK2, its first terminal is electrically connected to the second terminal of transistor M12, and its second terminal is electrically connected to the second node N2. The first node inter-control unit 114 includes transistors M9, M10, and M11. The gate of transistor M9 is electrically connected to the first node N1, its first terminal is connected to the first clock signal ECK1, and its second terminal is electrically connected to the fourth node N4. The gate of transistor M10 is electrically connected to the fourth node N4, its first terminal is connected to the first potential signal VGH, and the gate of transistor M11 is connected to the second clock signal ECK2. Its first terminal is electrically connected to the second terminal of transistor M10, and its second terminal is electrically connected to the first node N1. The second node inter-control unit 115 includes transistor M14. The gate of transistor M14 is electrically connected to the first node N1, its first terminal is connected to the first potential signal VGH, and its second terminal is electrically connected to the second node N2.

[0092] Furthermore, the drive control module 110 may also include a capacitor C2, one end of which is connected to the first node N1, and the other end is connected to the second clock signal ECK2, so as to maintain the potential of the first node N1 and couple the control of the potential of the first node N1. The drive control module 110 may also include a capacitor C3, one end of which is connected to the second node N2, and the other end is connected to the first potential signal VGH, so as to maintain the potential of the second node N2.

[0093] See also Figure 8 In one embodiment, optionally, the first potential control module 130 includes: a first transistor M1; the gate of the first transistor M1 is connected to a first switching signal SW1, the first terminal is connected to a first potential signal VGH, and the second terminal is electrically connected to a third node N3. This embodiment sets the first potential control module 130 to consist of a single transistor, making the structure of the first potential control module 130 simple and easy to implement.

[0094] See also Figure 8 In one embodiment, optionally, the scan output module 140 includes a third transistor M3 and a fourth transistor M4. The gate of the third transistor M3 serves as the first control terminal of the scan output module 140 and is electrically connected to the first node N1; the first terminal of the third transistor M3 serves as the first input terminal of the scan output module 140 and is connected to the second potential signal VGL; the second terminal of the third transistor M3 serves as the output terminal of the scan output module 140 and is used to output the scan signal GOUT. The gate of the fourth transistor M4 serves as the second control terminal of the scan output module 140 and is electrically connected to the second node N2; the first terminal of the fourth transistor M4 serves as the second input terminal of the scan output module 140 and is electrically connected to the third node N3; the second terminal of the fourth transistor M4 is electrically connected to the second terminal of the third transistor M3. This embodiment sets the scan output module 140 to include two transistors, which respectively control the potential of the third node N3 and the second potential signal VGL to be output as the scan signal GOUT, making the structure of the scan output module 140 simple and easy to implement.

[0095] See also Figure 8In one embodiment, optionally, the stage transmission output module 120 includes a fifth transistor M5 and a sixth transistor M6. The gate of the fifth transistor M5 serves as the first control terminal of the stage transmission output module 120 and is electrically connected to the first node N1; the first terminal of the fifth transistor M5 serves as the first input / output terminal of the stage transmission output module 120, connected to the second potential signal VGL; the second terminal of the fifth transistor M5 serves as the output terminal of the stage transmission output module 120, used to output the stage transmission signal Carry. The gate of the sixth transistor M6 serves as the second control terminal of the stage transmission output module 120 and is electrically connected to the second node N2; the first terminal of the sixth transistor M6 serves as the second input terminal of the stage transmission output module 120, connected to the first potential signal VGH; the second terminal of the sixth transistor M6 is electrically connected to the second terminal of the fifth transistor M5. This embodiment sets the stage transmission output module 120 to include two transistors, which respectively control whether the first potential signal VGH and the second potential signal VGL are output as the stage transmission signal Carry, making the stage transmission output module 120 simple in structure and easy to implement.

[0096] The following is based on Figure 8 The structure of shift register 10, taking the example where all transistors in shift register 10 are P-type transistors, combined with... Figure 5 , Figure 6 and Figure 8 The driving process of shift register 10 is explained.

[0097] See Figure 5 and Figure 8 In high-frequency operating mode, taking the first switch signal SW1 maintaining a low potential V2 during one frame of display as an example, if the first potential control module 130 remains on during one frame of display, then the third node N3 maintains a high potential for the first potential signal VGH. The driving process of the shift register 10 includes:

[0098] In the first stage (T11), the first clock signal ECK1 is at a low level, while the second clock signal ECK2 and the input signal EIN are at a high level. Transistors M7 and M8 are turned on, while transistors M11 and M13 are turned off. The high level of the input signal EIN is transmitted to the first node N1 through transistor M7, turning off transistors M9, M14, M3, and M5. The low level of the second potential signal VGL is transmitted to the fourth node N4 through transistor M8, turning on transistors M10 and M12. Due to the storage effect of capacitor C3, the second node N2 maintains the high level of the previous stage, turning off transistors M4 and M6. Therefore, the stage pass signal Carry and the scan signal GOUT both maintain the low level of the previous stage.

[0099] In the second stage (T12), the second clock signal ECK2 is at a low level, while the first clock signal ECK1 and the input signal EIN are at a high level. Transistors M11 and M13 are turned on, while transistors M7 and M8 are turned off. Due to the storage effect of capacitor C1, the fourth node N4 maintains the low level of the previous stage, causing transistors M10 and M12 to turn on. The high level of the first potential signal VGH is transmitted to the first node N1 through transistors M10 and M11, keeping transistors M9, M14, M3, and M5 off. The low level of the second clock signal ECK2 is transmitted to the second node N2 through transistors M12 and M13, causing transistors M4 and M6 to turn on. The first potential signal VGH is transmitted through the sixth transistor M6, and the stage signal Carry becomes high. The high level of the third node N3 is output through the fourth transistor M4, and the scan signal GOUT becomes high.

[0100] In the third stage (T13), the first clock signal ECK1 is at a low level, while the second clock signal ECK2 and the input signal EIN are at a high level. Transistors M7 and M8 are turned on, while transistors M11 and M13 are turned off. The high level of the input signal EIN is transmitted to the first node N1 through transistor M7, turning off transistors M9, M14, M3, and M5. The low level of the second potential signal VGL is transmitted to the fourth node N4 through transistor M8, turning on transistors M10 and M12. Due to the storage effect of capacitor C3, the second node N2 maintains the low level of the previous stage, keeping the fourth transistor M4 and the sixth transistor M6 on, while the stage transfer signal Carry and the scan signal GOUT remain at a high level.

[0101] In the fourth stage (T14), the first clock signal ECK1 is high, while the second clock signal ECK2 and the input signal EIN are low. Transistors M7 and M8 are off, while transistors M11 and M13 are on. Due to the storage effect of capacitor C1, the fourth node N4 maintains the low potential from the previous stage, turning on transistors M10 and M12. The high potential of the first potential signal VGH is transmitted to the first node N1 through transistors M10 and M11, keeping transistors M9, M14, M3, and M5 off. The low potential of the second clock signal ECK2 is transmitted to the second node N2 through transistors M12 and M13, turning on transistors M4 and M6. The high potential of the first potential signal VGH is transmitted through the sixth transistor M6, and the stage signal Carry remains high. The high potential of the third node N3 is output through the fourth transistor M4, and the scan signal GOUT remains high.

[0102] In stage T15, the second clock signal ECK2 is high, while the first clock signal ECK1 and the input signal EIN are low. Transistors M7 and M8 are turned on, while transistors M11 and M13 are turned off. The low potential of the input signal EIN is transmitted to the first node N1 through transistor M7, turning on transistors M9, M14, M3, and M5. The low potential of the first clock signal ECK1 is transmitted to the fourth node N4 through transistor M9, turning on transistors M10 and M12. However, because transistor M13 is turned off, the low potential of the fourth node N4 cannot be transmitted to the second node N2. The high potential of the first potential signal VGH is transmitted to the second node N2 through transistor M14, turning off the fourth transistor M4 and the sixth transistor M6. The low potential of the second potential signal VGL is output through the fifth transistor M5, turning the stage signal Carry low; and the low potential of the second potential signal VGL is output through the third transistor M3, turning the scan signal GOUT low.

[0103] In stage 6 (T16), the first clock signal ECK1 is high, while the second clock signal ECK2 and the input signal EIN are low. Transistors M11 and M13 are turned on. Due to the coupling effect of capacitor C2, as the second clock signal ECK2 goes low, the potential of the first node N1 becomes even lower than in stage 5 (T15), keeping transistors M9, M14, M3, and M5 on. The high potential of the first clock signal ECK1 is transmitted to the fourth node N4 through transistor M9; the high potential of the first potential signal VGH is transmitted to the second node N2 through transistor M14, keeping the fourth transistor M4 and the sixth transistor M6 off. Compared to the previous stage, although transistor M13 is turned on in this stage, because the fourth node N4 has gone high and transistor M12 is off, it does not pull down the potential of the second node N2. Therefore, the cascade signal Carry and the scan signal GOUT remain low in this stage.

[0104] The fifth stage (T15) and the sixth stage (T16) are then repeated, with both the transmission signal Carry and the scan signal GOUT remaining at low levels until the input signal EIN goes high again.

[0105] See Figure 6 and Figure 8The difference between the low-frequency operating mode and the high-frequency operating mode is that, in the second stage (T12) to the fourth stage (T14), the first switching signal SW1 becomes a high potential V1, causing the first potential control module 130 to turn off, and the third node N3 changes to a low potential. Therefore, in the low-frequency operating mode, during the second stage (T12) to the fourth stage (T14), the scan signal GOUT remains at a low potential because there is no high potential source, which is different from the potential of the stage transmission signal Carry.

[0106] Figure 9 This is a schematic diagram of another shift register provided in an embodiment of the present invention. See also... Figure 9 Based on the above embodiments, optionally, the drive control module 110 further includes transistor M15, connected between the gate of the fourth node N4 and transistor M12, with the gate of transistor M15 connected to the second potential signal VGL. When the potential of the second clock signal ECK2 changes from high to low, capacitor C1 couples this potential change to the gate of transistor M12, turning off transistor M12 when its gate potential is too low, thereby preventing the low potential from being transmitted to the fourth node N4 and ensuring the stability of the shift register 10. Furthermore, the first node can be divided into a first sub-node N11 and a second sub-node N12. Transistors M9 and M11 are both connected to the first sub-node N11, while transistors M14, M3, M5, and capacitor C2 are all connected to the second sub-node N12. The drive control module 110 may also include transistor M16, connected between the first sub-node N11 and the second sub-node N12, with the gate of transistor M16 connected to the second potential signal VGL. Transistor M15 can switch from high to low when the potential of the second clock signal ECK2 changes. Capacitor C2 couples this potential change to the second sub-node N12, so that the second sub-node N12 is turned off when the potential is too low, thereby preventing the low potential from being transmitted to the first sub-node N11, and further ensuring the stability of shift register 10.

[0107] The above embodiments exemplarily provide a first potential control module 130. However, when the first potential control module 130 is turned off, the potential of the third node N3 is floating and needs to be maintained at a low potential by the output terminal of the scan output module. The third node N3 is prone to noise coupling and potential changes, thereby affecting the potential of the scan signal GOUT. To solve the above problem, the inventors improved the circuit of the shift register 10 by adding a second potential control module to help stabilize the potential of the third node N3.

[0108] Figure 10 This is a schematic diagram of another shift register provided in an embodiment of the present invention. See also... Figure 10, based on each of the foregoing implementation manners, optionally, the shift register 10 further includes: a second potential control module 150, which is electrically connected to the third node N3 and connected to the second switch signal SW2. The second switch signal SW2 is configured to control the second potential control module 150 to have an on-off state opposite to that of the first potential control module 130. That is, at the same time, one of the first potential control module 130 and the second potential control module 150 is conductive and the other is turned off.

[0109] Since the first potential signal VGH accessed by the first potential control module 130 and the second potential signal VGL accessed by the second potential control module 150 are inverted signals of each other, when the first potential control module 130 is turned off, the second potential control module 150 is conductive and can stably provide a low potential to the third node N3. In this way, on one hand, the third node N3 can quickly change to a low potential, avoiding the false short high-level output of the scanning signal COUT caused by delayed potential change; on the other hand, it can cooperate with the first potential control module 130 to alternately provide high and low potentials to the third node N3, so that the third node N3 has a stable power supply at any time, preventing the potential of the third node N3 from floating.

[0110] By way of example, the second potential control module 150 includes: a second transistor M2; a gate of the second transistor M2 is connected to the second switch signal SW2, a first electrode of the second transistor M2 is connected to the second potential signal VGL, and a second electrode of the second transistor M2 is electrically connected to the third node N3. In this embodiment, the second potential control module 150 is configured to include only one transistor, so that the second potential control module 150 has a simple structure and is easy to implement. By way of example, if the second transistor M2 is a P-type transistor, the second switch signal SW2 needs to provide a low potential to turn on the second transistor M2, and the turn-on voltage Vop2 of the second switch signal SW2 can be set as Vop2 < VGL + Vth2, where Vth2 is the threshold voltage of the second transistor M2.

[0111] As shown in Figure 10 , by way of example, the first transistor M1 and the second transistor M2 have the same channel type, and the first switch signal SW1 and the second switch signal SW2 are inverted signals of each other, so as to control the first transistor M1 and the second transistor M2 to have opposite conduction states. Both the first transistor M1 and the second transistor M2 can be P-type transistors, which facilitates being manufactured together with other transistors in the shift register 10 in the same process and helps simplify the manufacturing steps.

[0112] Alternatively, as shown in Figure 11 , the first transistor M1 and the second transistor M2 have different channel types, and the first switch signal SW1 can be reused as the second switch signal SW2, so as to reduce the number of control signals, simplify the wiring of the display panel, and help achieve a narrow bezel. By way of example, as shown in Figure 11 As shown, the first transistor M1 can be set to be a P-type transistor and the second transistor M2 to be an N-type transistor.

[0113] Or, such as Figure 12 As shown, the first transistor M1 can be configured as an N-type transistor, and the second transistor M2 as a P-type transistor. In this case, considering the transmission of the first potential signal VGH, the first switching signal SW1 needs to provide a high potential to turn on the first transistor M1. The turn-on voltage Vop1 of the first switching signal SW1 can be set to Vop1 > VGH + Vth1, where Vth1 is the threshold voltage of the first transistor M1.

[0114] Based on the above embodiments, optionally, the on-potential of the scanning signal GOUT output by the fourth transistor M4 is used to drive one or more rows of pixel circuits to work. The load is relatively large. In order to ensure the driving capability of the shift register 10, the width-to-length ratio of the fourth transistor M4 can be set to be greater than the width-to-length ratio of any one of the transistors M7 to M16.

[0115] Based on the above embodiments, optionally, the aspect ratio of the first transistor M1 is greater than that of the second transistor M2. Since the first potential signal VGH, as the conduction potential, needs to be output to the load through the first transistor M1 and the fourth transistor M4, the first transistor M1 also needs to be made as a transistor with strong driving capability; for example, the aspect ratio of the first transistor M1 can be set to be the same as that of the fourth transistor M4. The second transistor M2 is only used as a switching transistor to stably provide a low potential to the third node N3; its aspect ratio does not need to be too large and can be the same as that of any one of the transistors M7-16.

[0116] The above embodiments exemplify that transistors M7-M16 in the shift register are all P-type transistors, but this is not intended to limit the invention. In other embodiments, some or all of transistors M7-M16 may be replaced with N-type transistors.

[0117] The above embodiments exemplify the specific structure of the shift register 10. The driving process of the display device will now be described.

[0118] In one embodiment, optionally, the first potential control modules 130 in all shift registers 10 are connected to the same first switch signal SW1, and each level of the first potential control module 130 simultaneously turns on or off in response to the first switch signal SW1. This configuration simplifies the structure of the scan drive circuit, reduces the number of output ports of the drive chip, lowers costs, and makes the scan drive circuit easy to implement and apply. By adjusting the potential transition time of the first switch signal SW1 in a frame of display, the boundary position of the shift register 10's working state switching can be adjusted, thereby realizing the adjustment of the display partition position of the display device. The number of shift registers 10 in high-frequency working mode in a frame determines the number of pixel circuit rows to be refreshed. Correspondingly, the second potential control modules 150 in all shift registers 10 can be connected to the same second switch signal SW2. The on / off states of each level of the first potential control module 130 and the second potential control module 150 are coordinated, which can improve the output stability of each level of scan signal GOUT.

[0119] The following is combined Figure 10 and Figure 13 Taking a display device comprising three display areas as an example, the driving process of the first type of display frame and the second type of display frame will be explained respectively. Specifically, the pixel circuits of each row in the first display area A1 are controlled by shift registers from level 1 to level k-1; the pixel circuits of each row in the second display area A2 are controlled by shift registers from level k to level m-1; and the pixel circuits of each row in the third display area A3 are controlled by shift registers from level m onwards. It should be noted that... Figure 10 and Figure 13 The diagram illustrates the process using the first switch signal SW1 and the second switch signal SW2 as inverses of each other, with the waveform of the first switch signal SW1 exemplarily shown on the right side of the accompanying figure. Furthermore, in the figure, shaded areas represent data refresh operations of the pixel circuits in each row of the display area, while blank areas represent data retention operations. The i-th stage shift register is labeled 10i, the i-th stage pass signal is labeled Carryi, and the i-th stage scan signal is labeled GOUTi, where i is a positive integer.

[0120] Figure 13 This is a schematic diagram of the driving timing of a display device in a first type of display frame provided by an embodiment of the present invention. See also Figure 13 In the first type of display frame, the first switch signal SW1 maintains a low potential V2, and the second switch signal SW2 maintains a high potential V1. Each first potential control module 130 is always on in this display frame, and each second potential control module 150 is always off. Each level of scan signal is consistent with the corresponding level transmission signal. The scan drive circuit realizes the step-by-step transmission of the scan signal conduction potential, ensuring that the pixel circuits of all display areas are refreshed.

[0121] Figure 14 This is a schematic diagram of the driving timing of a display device in a second type of display frame provided by an embodiment of the present invention. See also Figure 14 Taking the pixel circuits of the first display area A1 and the third display area A3 for data refresh and the pixel circuit of the second display area A2 for data retention as an example.

[0122] During the scanning phase TA1 of the first display area A1, the first switch signal SW1 is maintained at a low potential V2, and the second switch signal SW2 is maintained at a high potential V1, so that the scanning signals output by each level of the shift register corresponding to the first display area A1 are consistent with the corresponding level transmission signals, including conduction pulses, so that the pixel circuits in the first display area A1 are refreshed.

[0123] During the scanning phase TA2 of the second display area A2, the first switch signal SW1 is at a high potential V1 and the second switch signal SW2 is at a low potential V2, so that the scanning signals output by each level of the shift register corresponding to the second display area A2 are different from the corresponding level transmission signals and do not contain conduction pulses, so that the pixel circuit in the second display area A2 does not perform data refresh.

[0124] During the scanning phase TA3 of the third display area A3, the first switch signal SW1 is at a low potential V2 and the second switch signal SW2 is at a high potential V1, so that the scanning signals output by each level of the shift registers corresponding to the third display area A3 are consistent with the corresponding level transmission signals, including conduction pulses, so that the pixel circuits in the third display area A3 are refreshed.

[0125] The driving process of other second-type display frames and Figure 14 Similarly, it is sufficient to control the high-potential period of the first switch signal SW1 to correspond to the scanning time of each row of pixel circuits that need data retention; the specific process will not be elaborated further. Furthermore, whether the scanning signal GOUT of each stage shift register 10 outputs a conduction potential is controlled by the first potential control module 130 of that stage, and is independent of the output state of the scanning signals GOUT of other stages. Therefore, the refresh frequency corresponding to each display area is only related to the output state of the shift register corresponding to that display area, and has no correlation with the refresh frequency of other display areas. This embodiment of the invention allows for arbitrary switching of the refresh frequency of different display areas.

[0126] In practical applications, by adjusting the order and number of the first type of display frames and various second type of display frames, combinations of various display frequencies for each partition can be achieved.

[0127] For example, when the first display area A1 displays at a refresh rate f, the second display area A2 displays at a refresh rate f / 4, and the third display area A3 displays at a refresh rate f / 2, the combination of various display frames is as follows: Figure 15 As shown. See also Figure 15For each row of sub-pixels in the first display area A1, data can be refreshed in each display frame. Figure 15 The waveform of the first-level scan signal GOUT1 is given as an example. It can be seen that the first-level scan signal GOUT1 contains a conduction pulse in each display frame. For each row of sub-pixels in the second display area A2, a hold frame interval of 3 can be set between two adjacent refresh frames. Figure 15 The waveform of the k-th level scan signal GOUTk is given as an example. It can be seen that the k-th level scan signal GOUTk contains a conduction pulse in display frames F1 and F5, that is, it only contains a conduction pulse in the 4i-3 display frames, and maintains a cutoff potential in other display frames. For each row of sub-pixels in the third display area A3, odd-numbered frames can be set as refresh frames and even-numbered frames as hold frames. Figure 15 The waveform of the m-th level scan signal GOUTm is given as an example. It can be seen that the m-th level scan signal GOUTm contains conduction pulses only in odd-numbered frames.

[0128] By repeating the driving process within a cycle of four display frames (F1 to F4), a stable multi-frequency display with a refresh rate of f for the first display area A1, f / 4 for the second display area A2, and f / 2 for the third sub-display area A3 can be achieved. Display frame F1 corresponds to the first type of display frame, while display frames F2-F4 all correspond to the second type of display frames.

[0129] If it is necessary to adjust the partitioning positions between the sub-display areas, this can be achieved by adjusting the potential transition times of the first switch signal SW1 and the second switch signal SW2 in various display frames. For example, ... Figure 14 By adjusting the first potential transition times of the first switch signal SW1 and the second switch signal SW2 forward, the partition positions of the first display area A1 and the second display area A2 can be shifted upwards. If it is necessary to adjust the refresh rate of each display area, this can be achieved by controlling the order and number of various display frames in different cycles. Furthermore, by using different cycles for display in different time periods, a display scheme with dynamic refresh rate adjustment can be realized.

[0130] The structure of the pixel circuit that uses the above scanning signal, and the connection between the pixel circuit and the scanning drive circuit, will be explained below.

[0131] Figure 16 This is a schematic diagram of a pixel circuit provided in an embodiment of the present invention. See also... Figure 16 In one embodiment, optionally, the pixel circuit 20 includes:

[0132] A pixel circuit with a 7T1C architecture is constructed from a driving transistor DTFT, a data writing transistor M24, a threshold compensation transistor M25, a gate initialization transistor M22, an anode initialization transistor M23, a first light-emitting control transistor M26, a second light-emitting control transistor M27, and a storage capacitor Cst. The first light-emitting control transistor M26, the driving transistor DTFT, the second light-emitting control transistor M27, and the light-emitting device OLED are connected in series. The data writing transistor M24 is connected to the data voltage Vdata and electrically connected to the first electrode of the driving transistor DTFT. The threshold compensation transistor M25 is connected between the gate and the second electrode of the driving transistor DTFT. The gate initialization transistor M22 is connected to the first initialization signal Vref1 and electrically connected to the gate of the driving transistor DTFT. The anode initialization transistor M23 is connected to the second initialization signal Vref2 and electrically connected to the anode of the light-emitting device OLED. The cathode of the light-emitting device OLED is connected to the second power supply signal VSS. One end of the storage capacitor Cst is connected to the gate of the driving transistor DTFT, and the other end is connected to the first power supply signal VDD. Among them, the gate of the gate initialization transistor M22 is connected to the first control signal S1, the gates of the data writing transistor M24 and the anode initialization transistor M23 are both connected to the second control signal S2, the gate of the threshold compensation transistor M25 is connected to the third control signal S3, and the gates of the first light-emitting control transistor M26 and the second light-emitting control transistor M27 are both connected to the light-emitting control signal EM.

[0133] For example, the threshold compensation transistor M25 and the gate initialization transistor M22 can be N-type transistors, and the other transistors can be P-type transistors, forming an LTPO pixel circuit.

[0134] Figure 17 This is a schematic diagram of the driving timing of a pixel circuit according to an embodiment of the present invention. Combined with... Figure 16 and Figure 17 For example, in low-frequency display, the pixel circuit may include a refresh frame FA and at least one hold frame FI in one display cycle. In high-frequency display, one display cycle may include only the refresh frame FA. The refresh frame FA includes an initialization phase T21, a data writing phase T22, and a first light-emitting phase T23. The hold frame FI includes a black insertion phase T24 and a second light-emitting phase T25, during which no data is written.

[0135] Specifically, taking a low-frequency refresh rate scenario as an example, the driving process of the pixel circuit includes:

[0136] During the initialization phase T21, the first control signal S1, the second control signal S2, and the light emission control signal EM are all at high potentials. Transistor M22 is turned on, and the first initialization signal Vref1 initializes the gate of the driving transistor DTFT through transistor M22.

[0137] During the data writing phase T22, the first control signal S1 and the second control signal S2 are both at low potentials, while the third control signal S3 and the light-emitting control signal EM are both at high potentials. Transistor M22 is turned off, while transistors M23, M24, and M25 are all turned on. The data signal Vdata is transmitted to the gate of the driving transistor DTFT through transistor M24, the first and second terminals of the driving transistor DTFT, and transistor M25, completing the data writing. Simultaneously, the second initialization signal Vref2 initializes the anode of the OLED light-emitting device through transistor M23.

[0138] In the first light-emitting stage T23, the first control signal S1, the third control signal S3, and the light-emitting control signal EM are all at low potentials, while the second control signal S2 is at a high potential. Transistor M25 is turned off, while transistors M26 and M27 are both turned on, allowing the driving current generated by the driving transistor DTFT to be transmitted to the light-emitting device OLED, driving the OLED to emit light.

[0139] During the black insertion phase T24, the first control signal S1 and the third control signal S3 remain at a low potential, the second control signal S2 remains at a high potential, and the light emission control signal EM becomes high. Transistors M26 and M27 are both turned off, and the OLED stops emitting light.

[0140] In the second light-emitting stage T25, the first control signal S1 and the third control signal S3 remain at a low potential, the second control signal S2 remains at a high potential, and the light-emitting control signal EM goes low again. Transistors M26 and M27 are turned on again, causing the driving current generated by the driving transistor DTFT to drive the OLED to emit light.

[0141] The subsequent stages repeat the driving process of frame FI until the next refresh frame FA arrives.

[0142] In the scanning drive circuit provided in this embodiment of the invention, the scanning signals output by each shift register can be used as the first control signal S1 and / or the third control signal S3 required in the pixel circuit.

[0143] In one embodiment, optionally, two sets of scanning drive circuits 100 may be provided in the display panel, which are used to provide the first control signal S1 and the third control signal S3 required by each row of pixel circuits, respectively.

[0144] In another implementation, such as Figure 18As shown, optionally, a set of scan drive circuits 100 can be provided in the display panel to provide a first control signal S1 and a third control signal S3 to each row of pixel circuits 20. The following is in conjunction with... Figure 18 In this case, the possible connection relationship between the scan drive circuit 100 and the pixel circuit 20 will be explained. See [link / reference] Figure 18 For example, in a display panel, pixel circuits 20 are disposed in the display area AA of the display panel, and scan driving circuits 100 are disposed in the non-display area NAA of the display panel. The scan driving circuit 100 provides corresponding control signals to each row of pixel circuits 20 through scan lines.

[0145] Specifically, shift registers 10 at different levels can be connected to the same row of pixel circuits 20. The scan signal output by the previous shift register 10 serves as the first control signal S1 of the row of pixel circuits 20, and the scan signal output by the subsequent shift registers 10 (one or more subsequent levels, which can be set according to actual needs) serves as the third control signal S3 of the row of pixel circuits 20. For example, as... Figure 18 The scan signal output by the j-th stage shift register 10 serves as the third control signal required by the (j-1)-th row pixel circuit 20, and as the first control signal required by the j-th row pixel circuit 20, to provide, as Figure 17 The conduction pulses shown have overlapping first control signal S1 and third control signal S3. For example, the second-level scan signal GOUT2 serves as the third control signal S31 required by the first row pixel circuit 20 and as the first control signal S12 required by the second row pixel circuit 20; the third-level scan signal GOUT3 serves as the third control signal S32 required by the second row pixel circuit 20 and as the first control signal S13 required by the third pixel circuit 20, and so on. The driver chip can provide a first master clock signal CLK1 and a second master clock signal CLK2. The first master clock signal CLK1 can serve as the first clock signal ECK1 required by the odd-level shift register 10 and the second clock signal ECK2 required by the even-level shift register 10; and the second master clock signal CLK2 can serve as the second clock signal ECK2 required by the odd-level shift register 10 and the first clock signal ECK1 required by the even-level shift register 10.

[0146] In addition, such as Figure 19 As shown, the display panel may also include other driving circuits, which are used to provide the second control signal S2 and the light emission control signal EM required by the pixel circuit 20, respectively. For example, the display panel may also include: a scan driving circuit 400, which provides the second control signal S2 to each row of pixel circuits 20; and a light emission control circuit 300, which provides the light emission control signal EM to each row of pixel circuits.

[0147] It should be noted that the above driving process is not intended to be a response to... Figure 16 Limitations of the pixel circuit driving scheme. In practical applications, the pulses of the first control signal S1 and the third control signal S3 can also be set to not overlap. Correspondingly, the i-th level scan signal can be used as the first control signal S1 of the i-th row pixel circuit, and the (i+n)-th level scan signal can be used as the third control signal S3 of the i-th row pixel circuit, wherein the i-th level scan signal and the (i+n)-th level scan signal do not overlap.

[0148] The above embodiments exemplify a scheme where the pulse width of the input signal EIN is greater than the pulse width of the clock signal, causing the pulses of the input signal EIN and the stage transmission signal Carry to overlap. In this scheme, when there is no conduction pulse controlling the i-th stage scan signal, since all the first potential control modules 130 are connected to the same first switch signal SW1, the first switch signal SW1 controls all the first potential control modules 130 to turn off simultaneously. This may affect the scan signals GOUT of the preceding and following stages, causing them to change to a low potential following the i-th stage scan signal. However, since the display panel typically includes thousands of pixel circuits, this effect is negligible in actual display.

[0149] Furthermore, the above embodiments are not intended to limit the present invention. In other embodiments, by controlling the pulse width of the input signal EIN to be the same as the pulse width of the first clock signal ECK1, the pulses of the input signal EIN and the stage transmission signal Carry can be prevented from overlapping, thus avoiding the aforementioned situation of affecting the potential of the scanning signals of the preceding and following stages.

[0150] It should be noted that the structures of the shift registers 10 given in the above embodiments are not intended to limit the present invention. In other embodiments, the shift registers 10 can be improved based on existing shift register circuits of any structure. For any shift register circuit, the original output module is used as a cascaded output module. On this basis, an additional set of outputs is added, and a first potential control module and a second potential control module are added to the end of the added output module connected to the conduction potential to realize the function of the shift register 10 in the embodiments of the present invention.

[0151] It should also be noted that the above embodiments exemplify the application in the LTPO pixel circuit of the scan driving circuit, but are not intended to limit the present invention. In other embodiments, when both the gate initialization transistor M22 and the threshold compensation transistor M25 in the pixel circuit are N-type transistors, the shift register 10 can also be configured to have a long output high potential, for example, by modifying the 8T2C basic architecture.

[0152] In summary, this embodiment of the invention adds a first potential control module 130 to the shift register 10 to realize the function of blocking / allowing the scan signal GOUT to output the conduction potential, thereby realizing the display of high and low frequency switching; at the same time, the construction stage transmission output module 120 serves as a high-frequency output unit to provide the input signal EIN required for normal startup of the next stage shift register 10. The overall concept is simple, and the refresh frequency can be switched arbitrarily from high to low and from low to high. The solution is easy to implement and promote.

[0153] This invention also provides a display device, including the scanning driving circuit provided in any embodiment of this invention, which has corresponding beneficial effects. See also Figure 19 For example, the display device may include a display panel and a driver chip 50. The driver chip 50 is used to provide input signals to the first-stage shift registers in each driver circuit and to provide data voltages to each pixel circuit 20. Figure 19 The example provided illustrates providing a first control signal S1 and a third control signal S3 to each row of pixel circuits 20 via a set of scan driving circuits 100, but this is not intended to limit the invention. In other embodiments, two sets of scan driving circuits 100 may be provided to provide the first control signal S1 and the third control signal S3 to each row of pixel circuits 20, respectively; the specific configuration is not limited here.

[0154] This invention also provides a driving method for a display device, used to drive the display device provided in any embodiment of this invention, and has corresponding beneficial effects. Exemplarily, the driving method includes:

[0155] Based on the target partition position of the display device, the potential transition time of the first switch signal in a frame display is determined, thereby determining the position of the two adjacent shift registers that output scan signals of different frequencies in the scan drive circuit, so as to realize the display device's partitioned frequency display based on the target partition position.

[0156] Specifically, the timing of the potential transition of the first switching signal in a single frame of display determines the positions of two adjacent shift registers with different operating modes in the scan drive circuit. The shift registers have two operating modes: a high-frequency operating mode and a low-frequency operating mode. The first switching signal controls the operating mode of the shift register by controlling the conduction state of the first potential control module. In the high-frequency operating mode, the duration for which the first potential control module is on in a single frame of display covers the conduction potential maintenance time of the stage transmission signal, ensuring that both the stage transmission signal and the scan signal include a conduction potential maintenance phase in a single frame of display. In the low-frequency operating mode, the duration for which the first potential control module is off in a single frame of display covers the conduction potential maintenance time of the stage transmission signal, ensuring that the stage transmission signal includes a conduction potential maintenance phase in a single frame of display, while keeping the scan signal at a cutoff potential in a single frame of display.

[0157] For example, if the i-th stage shift register operates in a high-frequency operating mode (or a low-frequency operating mode) and the (i+1)-th stage shift register operates in a low-frequency operating mode (or a high-frequency operating mode), then the i-th stage and the (i+1)-th stage shift registers are two adjacent stages of shift registers with different operating modes; the boundary position between the i-th stage and the (i+1)-th stage shift registers corresponds to the display partition position of the display device.

[0158] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0159] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A scanning drive circuit, characterized in that, include: Multiple shift registers; The shift register includes: The drive control module is used to control the potential of the first node and the second node according to the clock signal and the input signal; The first potential control module is used to control whether the first potential signal is transmitted to the third node according to the first switch signal; the first potential signal is the conduction potential of the functional module in the pixel circuit that receives the scan signal. The scanning output module is electrically connected to the first node, the second node, and the third node, respectively, and is used to respond to the potentials of the first node and the second node, and output the potential of the third node or the second potential signal as a scanning signal to the pixel circuit; wherein, the first switch signal controls the frequency of the scanning signal by controlling the on / off state of the first potential control module; the second potential signal is the cutoff potential of the functional module in the pixel circuit that receives the scanning signal. The multiple shift registers are cascaded; each shift register further includes a cascade output module, electrically connected to the first node and the second node respectively, used to output a first potential signal or a second potential signal as a cascade signal according to the potentials of the first node and the second node; the cascade output module is only used for cascading, and the cascade signal is only used as the input signal for the next-level shift register; the potential of the first switch signal during the period when the cascade signal outputs the conduction potential is controlled to control whether the scan signal outputs the conduction potential in one frame of display; the frequency of the cascade signal output by the shift register is equal to the frequency of the input signal connected to the shift register, and the frequency of the scan signal output by the shift register is equal to or lower than the frequency of the input signal connected to the shift register; All the first potential control modules in the shift registers are connected to the same first switch signal; the scanning drive circuit supports the display function of arbitrarily adjustable partition frequency rise and fall. In the whole display process, the display device can realize partition frequency display in the column direction by controlling the potential jump of the first switch signal, and the display partition position can be adjusted by adjusting the potential jump time of the first switch signal.

2. The scanning drive circuit according to claim 1, characterized in that, The first potential control module includes: a first transistor; the gate of the first transistor is connected to the first switching signal, the first electrode of the first transistor is connected to the first potential signal, and the second electrode of the first transistor is electrically connected to the third node.

3. The scanning drive circuit according to claim 2, characterized in that, The shift register further includes a second potential control module, which is electrically connected to the third node and connected to a second switch signal; the second switch signal is used to control the switching state of the second potential control module to be opposite to the switching state of the first potential control module.

4. The scanning drive circuit according to claim 3, characterized in that, The second potential control module in all shift registers is connected to the same second switch signal.

5. The scanning drive circuit according to claim 3, characterized in that, The second potential control module includes: a second transistor; the gate of the second transistor is connected to the second switching signal, the first terminal of the second transistor is connected to the second potential signal, and the second terminal of the second transistor is electrically connected to the third node.

6. The scanning drive circuit according to claim 5, characterized in that, The aspect ratio of the first transistor is greater than that of the second transistor.

7. The scanning drive circuit according to claim 5, characterized in that, The first transistor and the second transistor have the same channel type, and the first switching signal and the second switching signal are inverted signals. Alternatively, the first transistor and the second transistor may have different channel types, and the first switching signal may be multiplexed as the second switching signal.

8. The scanning drive circuit according to claim 1, characterized in that, The scan output module includes: a third transistor and a fourth transistor; The gate of the third transistor is electrically connected to the first node, the first terminal of the third transistor is connected to the second potential signal, and the second terminal of the third transistor serves as the output terminal of the scan output module; the gate of the fourth transistor is electrically connected to the second node, the first terminal of the fourth transistor is electrically connected to the third node, and the second terminal of the fourth transistor is electrically connected to the second terminal of the third transistor.

9. The scanning drive circuit according to claim 1, characterized in that, The drive control module includes: An input unit, electrically connected to the first node, is used to transmit the input signal to the first node in response to a first clock signal; The first control unit is electrically connected to the fourth node and is used to transmit the second potential signal to the fourth node in response to the first clock signal. The second control unit is electrically connected to the fourth node and the second node respectively, and is used to transmit the second clock signal to the second node in response to the second clock signal and the potential of the fourth node; The first node mutual control unit is electrically connected to the first node and the fourth node respectively, and is used to transmit the first clock signal to the fourth node in response to the potential of the first node, and to transmit the first potential signal to the first node in response to the second clock signal and the potential of the fourth node. The second node mutual control unit is electrically connected to both the first node and the second node, and is used to transmit the first potential signal to the second node in response to the potential of the first node.

10. The scanning drive circuit according to claim 1, characterized in that, The stage transmission module includes: a fifth transistor and a sixth transistor; The gate of the fifth transistor is electrically connected to the first node, the first terminal of the fifth transistor is connected to the second potential signal, and the second terminal of the fifth transistor serves as the output terminal of the stage transmission module; the gate of the sixth transistor is electrically connected to the second node, the first terminal of the sixth transistor is connected to the first potential signal, and the second terminal of the sixth transistor is electrically connected to the second terminal of the fifth transistor.

11. The scanning drive circuit according to claim 1, characterized in that, The pixel circuit includes: a driving transistor, a gate initialization transistor, and a threshold compensation transistor; the gate initialization transistor and the threshold compensation transistor are both electrically connected to the gate of the driving transistor. For the same pixel circuit, the scan signal output by the front-stage shift register is provided to the gate of the gate initialization transistor, and the scan signal output by the rear-stage shift register is provided to the gate of the threshold compensation transistor.

12. The scanning drive circuit according to claim 11, characterized in that, The driving transistor is a P-type transistor, and the gate initialization transistor and the threshold compensation transistor are both N-type transistors; the potential of the first potential signal is higher than the potential of the second potential signal.

13. A display device, characterized in that, It includes pixel circuitry and the scan drive circuitry as described in any one of claims 1-12.

14. A driving method for a display device, characterized in that, The driving method for driving the display device of claim 13 includes: Based on the target partition position of the display device, the potential transition time of the first switch signal in a frame display is determined, thereby determining the position of the two adjacent shift registers that output scan signals of different frequencies in the scan drive circuit, so as to realize the display device's partitioned frequency display based on the target partition position.

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