Display driver and driving method thereof

Abstract

A display driver and a driving method thereof. The display driver includes at least one first latch, at least one second latch, an output buffer, and a comparator. The first latch receives input data. An input terminal of the second latch is coupled to an output terminal of the first latch. The output buffer includes at least one variable current source, and the output buffer is coupled to the second latch. The comparator is coupled to the first latch, the second latch, and the variable current source. The comparator generates at least one control signal of the variable current source.

Description

Technical Field

[0001] This invention relates to a driving technology, and more particularly to a display driver and its driving method. Background Technology

[0002] LCD displays are characterized by their light weight, low power consumption, and zero radiation, and are widely used in many information technology products, such as computer systems, mobile phones, and personal digital assistants.

[0003] Figure 1 This is a schematic diagram of a prior art display device. Figure 2 This is a waveform diagram of the source driver output enable signal, output signal, and high drive signal for a prior art display device. Please refer to... Figure 1 and Figure 2The display device 1 includes a liquid crystal display panel 10, a gate driver 11, and a source driver 12. The display panel 10 includes multiple pixels, each pixel being composed of a thin-film transistor. Generally, the source driver 12 is used to drive multiple data lines (or source lines) of the display panel 10. The source driver 12 has multiple drive channel circuits. Each drive channel circuit uses a different output buffer 120 to drive one of the corresponding data lines. In the source driver 12, the output buffer 120 can output a signal Y to the data lines of the display panel 10. The larger the size of the display panel 10, the more pixels there are. As the frame rate and / or the resolution of the display panel 10 increases, the charging time of the scan lines becomes shorter. In order to drive (i.e., charge or discharge) a pixel in a short time, the output buffer 120 needs to have sufficient driving capability. That is, the output buffer 120 needs to have sufficient slew rate. To enhance the slew rate, the source driver 12 receives a source driver output enable signal SOE and a high drive signal HDR. The source driver output enable signal SOE comprises multiple periodically generated voltage pulses, and the high drive signal HDR comprises multiple periodically generated voltage pulses. In each time period T0, T1, and T2, one voltage pulse for the source driver output enable signal SOE and one voltage pulse for the high drive signal HDR are generated. When the voltage pulse for the source driver output enable signal SOE is generated, the source driver 12 gradually stops transferring old data to the corresponding data line and transfers new data to the corresponding data line. If the difference between the old and new data is large, the voltage of the output signal Y will change. For example, the output signal Y will drop from a high voltage to a low voltage in time period T1. When the voltage pulse for the high drive signal HDR is generated, the tail current of the output buffer 120 statically increases to enhance slew rate. However, the increase in slew rate also means an increase in power consumption. Because the voltage pulse for the high drive signal HDR is generated periodically, the power consumption of the source driver 12 will increase significantly. Furthermore, when the size of the display panel 10 is large, the number of drive channel circuits will increase, resulting in excessive heat or high power consumption. Summary of the Invention

[0004] This invention provides a display driver and its driving method that reduce unnecessary power waste and heat at a fixed refresh rate, and achieve maximum power efficiency.

[0005] In one embodiment of the present invention, a display driver is provided, comprising at least one first latch, at least one second latch, an output buffer, and a comparator. The first latch is used to receive input data, and the input terminal of the second latch is coupled to the output terminal of the first latch. The output buffer includes at least one variable current source, wherein the output buffer is coupled to the second latch. The comparator is coupled to the first latch, the second latch, and the variable current source, wherein the comparator is used to generate at least one control signal for the variable current source.

[0006] In one embodiment of the present invention, the comparator includes a first logic circuit, a register, and a second logic circuit. The first logic circuit is coupled to a first latch and a second latch, the register is coupled to the first logic circuit, and the second logic circuit is coupled to the register and a variable current source.

[0007] In one embodiment of the present invention, the first logic circuit includes a first inverter, a second inverter, a third inverter, a fourth inverter, a first NAND gate, a second NAND gate, a third NAND gate, a fourth NAND gate, a fifth NAND gate, a first XOR gate, a second XOR gate, a first NOR gate, and a second NOR gate. The first inverter and the second inverter are coupled to a first latch, the third inverter and the fourth inverter are coupled to a second latch, the first NAND gate is coupled to the first inverter, the third inverter, and the fourth inverter, the second NAND gate is coupled to the first inverter, the second inverter, and the third inverter, the third NAND gate is coupled to the first inverter, the second inverter, and the third inverter, the fourth NAND gate is coupled to the first inverter, the third inverter, and the fourth inverter, and the fifth NAND gate is coupled to the first NAND gate, the second NAND gate, the third NAND gate, the fourth NAND gate, and a register. The first XOR gate couples the first latch to the second latch, the second XOR gate couples the first latch to the second latch, the first NOR gate couples the first XOR gate to the second XOR gate, and the second NOR gate couples the first NOR gate, the fifth NAND gate, and the register.

[0008] In one embodiment of the present invention, the register includes a first D flip-flop and a second D flip-flop. The first D flip-flop is coupled to a fifth NAND gate, and the second D flip-flop is coupled to a second NOR gate.

[0009] In one embodiment of the present invention, at least one variable current source includes two first variable current sources and two second variable current sources.

[0010] In one embodiment of the present invention, the second logic circuit includes a sixth NAND gate, a fifth inverter, a seventh NAND gate, and a sixth inverter. The sixth NAND gate is coupled to a first D flip-flop, the fifth inverter is coupled to the sixth NAND gate, and the seventh NAND gate is coupled to a second D flip-flop. The sixth inverter is coupled to the seventh NAND gate, wherein the sixth NAND gate and the fifth inverter are respectively coupled to two first variable current sources, and the seventh NAND gate and the sixth inverter are respectively coupled to two second variable current sources.

[0011] In one embodiment of the present invention, the output buffer further includes an input differential pair circuit, a gain stage circuit, and an output stage circuit. The input differential pair circuit is coupled to a second latch and a variable current source, the gain stage circuit is coupled to the input differential pair circuit, and the output stage circuit is coupled to the gain stage circuit.

[0012] In one embodiment of the present invention, at least one first latch includes a plurality of first latches, and at least one second latch includes a plurality of second latches.

[0013] In one embodiment of the invention, the display driver further includes a digital-to-analog converter coupled to a second latch and an output buffer.

[0014] In one embodiment of the invention, the display driver further includes an electrical shifter coupled to a digital-to-analog converter and a second latch.

[0015] A driving method for a display driver includes the following steps: sequentially receiving first data and second data; transferring the first data to an output buffer during a first time period to drive a display panel, wherein the buffer includes at least one variable current source; controlling the variable current source according to the difference between the values ​​of the corresponding first data and second data and a preset value; and transferring the second data to the output buffer during a second time period to drive the display panel, wherein there is a transition period between the second time period and the first time period, and the output buffer with the controlled variable current source drives the display panel during the transition period.

[0016] In one embodiment of the present invention, when the difference is greater than a preset value, the variable current source is turned on.

[0017] In one embodiment of the present invention, the turn-on time of the variable current source is positively correlated with the difference.

[0018] In one embodiment of the present invention, the variable current source is turned off when the difference is less than or equal to a preset value.

[0019] In one embodiment of the present invention, both the first data and the second data have N bits, where N is a natural number greater than 1, and the difference is obtained by comparing the most significant bit and the second most significant bit of the first data and the second data.

[0020] In one embodiment of the present invention, the binary code of the preset value is 00.

[0021] In one embodiment of the present invention, in the step of transferring the first data to the output buffer, a digital-to-analog conversion is performed on the first data to generate an analog signal, and the output buffer receives the analog signal. Based on the above, the display driver and its driving method control a variable current source according to the difference between the values ​​of the corresponding first data and second data and a preset value, thereby reducing unnecessary power waste and unnecessary heat at a fixed update rate and achieving maximum power efficiency. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of a prior art display device.

[0023] Figure 2 The waveforms of the source driver output enable signal, output signal, and high drive signal for a prior art display device are shown.

[0024] Figure 3 This is a schematic diagram of a display device according to an embodiment of the present invention.

[0025] Figure 4 This is a schematic diagram of a display driver according to an embodiment of the present invention.

[0026] Figure 5 The waveform diagram shows the enable signal, drive signal, adaptive drive signal output by the source driver of the display driver according to an embodiment of the present invention, and the data output by the first latch and the second latch.

[0027] Figure 6 The waveforms of the source driver output enable signal, adaptive high drive signal, variable current and output signal, and the high drive signal of the prior art are shown in the figure for a display driver according to an embodiment of the present invention.

[0028] Figure 7 This is a schematic diagram of a comparator according to an embodiment of the present invention.

[0029] Figure 8 This is a schematic diagram of an output buffer according to an embodiment of the present invention.

[0030] Figure 9 This is a schematic diagram of a comparator according to another embodiment of the present invention.

[0031] Figure 10 This is a schematic diagram of an output buffer according to another embodiment of the present invention.

[0032] Figure 11 This is a waveform diagram of the output signal and the adaptive high drive signal of the display driver according to an embodiment of the present invention.

[0033] Figure 12 The waveform diagram of the output signal and the adaptive high drive signal of the display driver is shown in another embodiment of the present invention. Detailed Implementation

[0034] Embodiments of the present invention will be further explained below with reference to the accompanying drawings. Wherever possible, the same reference numerals in the drawings and description represent the same or similar components. In the drawings, shapes and thicknesses may be exaggerated for simplicity and convenience. It is understood that elements not specifically shown in the drawings or described in the description are forms known to those skilled in the art. Those skilled in the art can make various changes and modifications based on the content of this invention.

[0035] Unless otherwise specified, certain conditional clauses or words, such as "can," "could," "might," or "may," are generally intended to express features, elements, or steps that are present in the embodiments of this invention, but may also be interpreted as features, elements, or steps that may not be required. In other embodiments, these features, elements, or steps may be unnecessary.

[0036] In the following description of "one embodiment" or "an embodiment," the term refers to a specific element, structure, or feature associated with at least one embodiment. Therefore, the multiple descriptions of "one embodiment" or "an embodiment" appearing in various places below do not refer to the same embodiment. Furthermore, specific components, structures, and features in one or more embodiments may be combined in a suitable manner.

[0037] Certain terms are used in the specification and claims to refer to specific elements. However, those skilled in the art will understand that the same element may be referred to by different names. The specification and claims do not distinguish elements by differences in name, but by differences in function. The term "comprising" in the specification and claims is an open-ended term and should be interpreted as "including but not limited to". Furthermore, "coupled" here includes any direct and indirect means of connection. Therefore, if the text describes a first element coupled to a second element, it means that the first element can be directly connected to the second element via electrical connection or signal connection such as wireless transmission or optical transmission, or indirectly electrically or signalally connected to the second element via other elements or connection means.

[0038] The disclosure is specifically described with reference to the following examples, which are merely illustrative. Various modifications and refinements can be made by those skilled in the art without departing from the spirit and scope of this disclosure. Therefore, the scope of protection of this disclosure shall be determined by the appended claims. Throughout the specification and claims, unless explicitly stated otherwise, the words “a” and “described” include “a or at least one” of the element or component. Furthermore, as used in this disclosure, the singular article also includes descriptions of multiple elements or components unless clearly excluded from the specific context. Moreover, when applied in this description and throughout the claims below, unless explicitly stated otherwise, “in which” may include both “in which” and “on which”. The terms used throughout the specification and claims, unless otherwise specified, generally have their ordinary meaning in the context of this disclosure and in specific contexts. Certain terms used to describe this disclosure will be discussed below or elsewhere in this specification to provide additional guidance to practitioners in describing this disclosure. Examples throughout this specification, including examples of any terms discussed herein, are merely illustrative and do not, of course, limit the scope or meaning of this disclosure or any illustrative terms. Similarly, this disclosure is not limited to the various embodiments set forth in this specification.

[0039] The following description provides a display driver and its driving method, which controls at least one variable current source based on the difference between the values ​​of corresponding first and second data and a preset value, thereby reducing unnecessary power waste and heat at a fixed update rate and achieving maximum power efficiency. The display driver provided below can also be applied to other circuit architectures.

[0040] Figure 3 This is a schematic diagram of a display device according to an embodiment of the present invention. Please refer to [link / reference]. Figure 3 The following describes the display device 2. The display device 2 includes a display panel 20, a gate driver 21, and a plurality of display drivers 22. The display drivers 22 serve as source drivers. The display panel 20 is coupled to the gate driver 21 and each display driver 22. Each display driver 22 receives input data D, a source driver output enable signal SOE, and a drive signal DR to generate an output signal Y and drive the display panel 20.

[0041] Figure 4 This is a schematic diagram of a display driver according to an embodiment of the present invention. Please refer to [link / reference]. Figure 4The display driver 22 includes at least one first latch 220, at least one second latch 221, an output buffer 222, and a comparator 223. The input of the second latch 221 is coupled to the output of the first latch 220. The output buffer 222 includes at least one variable current source 2220, such as a portion of a tail current source or other bias current source. The input of the output buffer 222 is coupled to the output of the second latch 221, and the output of the output buffer 222 is coupled to the display panel 20. The input of the comparator 223 is coupled to the outputs of the first latch 220 and the second latch 221, and the output of the comparator 223 is coupled to the variable current source 2220. For clarity and convenience, the first embodiment uses multiple first latches 220, multiple second latches 221, and one variable current source 2220 as an example. The number of first latches 220 can be equal to the number of second latches 221, but the present invention does not limit the number of first latches 220, second latches 221 and variable current source 2220.

[0042] In another embodiment, the display driver 22 may further include an electrical shifter 224 and a digital-to-analog converter 225. The digital-to-analog converter 225 is coupled between the electrical shifter 224 and the output buffer 222, and the electrical shifter 224 is coupled between the digital-to-analog converter 225 and the second latch 221. The electrical shifter 224 can shift the output signal of the second latch 221 from one voltage level to another. The digital-to-analog converter 225 performs digital-to-analog conversion on the output signal of the electrical shifter 224. In some embodiments, the electrical shifter 224 may be omitted as needed. When the electrical shifter 224 is omitted, the digital-to-analog converter 225 is coupled between the second latch 221 and the output buffer 222. In this example, the digital-to-analog converter 225 performs digital-to-analog conversion on the output data of the second latch 221.

[0043] Figure 5 The image shows waveforms of the source driver output enable signal SOE, drive signal DR, adaptive drive signal AHDR, and the data output from the first latch and the second latch, according to an embodiment of the present invention. Please refer to [link to relevant documentation]. Figure 4 and Figure 5The following describes the driving method of the display driver 22. A first latch 220 receives input data D including first data D1 and second data D2. That is, the first latch 220 receives the first data D1 and the second data D2 sequentially, with the timing of the first data D1 being earlier than that of the second data D2. The first latch 220 sequentially transfers the first data D1 and the second data D2 to a second latch 221. The second latch 221 receives the source driver output enable signal SOE and transfers the first data D1 to the output buffer 222 during a first time period to output the aforementioned output signal Y and drive the display panel 20. Simultaneously, the first latch 220 and the second latch 221 respectively output the second data D2 and the first data D1 to a comparator 223. The comparator 223 receives the drive signal DR and generates at least one control signal for the variable current source 2220 based on a preset value and the difference between the values ​​of the corresponding first data D1 and second data D2, and uses this control signal as the adaptive high-drive signal AHDR. The first embodiment uses a single control signal as an example, but the present invention does not limit the number of control signals. The control signal can control the variable current source 2220. For example, when the difference between the values ​​corresponding to the first data D1 and the second data D2 is greater than a preset value, the control signal can turn on the variable current source 2220. The time for turning on the variable current source 2220 can be positively correlated with this difference. Alternatively, when the difference is less than or equal to the preset value, the control signal can turn off the variable current source 2220. Next, the second latch 221 transfers the second data D2 to the output buffer 222 in the second time period to output the aforementioned output signal Y and drive the display panel 20, replacing the first data D1 with the second data D2. There is a transition period between the second time period and the first time period. The output buffer 222 with the controlled variable current source 2220 drives the display panel 20 during this transition period. If the same result can be achieved, it is not necessary to follow the order of the steps in the driving method, and the steps in the driving method do not necessarily have to be performed consecutively, that is, other steps can also be inserted.

[0044] In some embodiments of the present invention, each of the first data D1 and the second data D2 has N bits, where N is a natural number greater than 1. The difference between the values ​​of the first data D1 and the second data D2 is obtained by comparing the most significant bit MSB-0 and the second most significant bit MSB-1 of the second data D2 with the most significant bit MSB'-0 and the second most significant bit MSB'-1 of the first data D1. The binary code of the preset value can be 00, but the present invention is not limited thereto. The source driver output enable signal SOE includes multiple periodically generated voltage pulses, which are generated in time periods T0, T1, T3, and T4. The drive signal DR includes multiple periodically generated voltage pulses, which are generated in time periods T0, T1, T3, and T4. Assuming N = 10, then in time periods T0 and T1, the first data D1 can be 1000000000, and the second data D2 can be 1111111111. Therefore, the value of the first data D1 is 512, and the value of the second data D2 is 1023. The most significant bit (MSB-0) and the second most significant bit (MSB-1) of the second data D2 are 1 and 1 respectively, and the most significant bit (MSB'-0) and the second most significant bit (MSB'-1) of the first data D1 are 1 and 0 respectively. Because the difference between 11 and 10 is greater than 00, the difference between the values ​​of the first data D1 and the second data D2 is greater than a preset value. The first time period is considered to be the time period between time point e of time period T0 and time point a of time period T1, as shown in the profile. The transition period is considered to be the time period between time points a and b of time period T1. The second time period is considered to be the time period between time points b and e of time period T1. In the first time period, the first latch 220 transfers the second data D2 to the second latch 221 and the comparator 223, the second latch 221 transfers the first data D1 to the output buffer 222 and the comparator 223, and the comparator 223 determines that the difference between the values ​​of the first data D1 and the second data D2 is greater than a preset value. During the transition period, a voltage pulse is generated to enable the source driver output signal SOE, causing the second latch 221 to gradually stop transferring the first data D1 to the output buffer 222, but to transfer the second data D2 to the output buffer 222. Additionally, during the transition period, a voltage pulse is generated to drive the signal DR. Because the difference between the values ​​of the first data D1 and the second data D2 is greater than a preset value, the comparator 223 uses the voltage pulse of the adaptive high drive signal AHDR to turn on the variable current source 2220. The width of the voltage pulse of the adaptive high drive signal AHDR represents the time during which the variable current source 2220 is turned on. The width of the voltage pulse of the drive signal DR is equal to the width of the voltage pulse of the adaptive high drive signal AHDR. During the transition period, the output buffer 222 with the turned-on variable current source 2220 increases its slew rate to drive the display panel 20.During the second time period, the second latch 221 transfers the second data D2 to the output buffer 222 to drive the display panel 20.

[0045] In time periods T2 and T3, the value of the first data D1 is 1023, and the value of the second data D2 is 512. The driving method of the display driver 22 in time periods T2 and T3 is similar to that in time periods T0 and T1, so it will not be described again here.

[0046] In time periods T1 and T2, both the first data D1 and the second data D2 are 1111111111. Therefore, the value of the first data D1 is 1023, and the value of the second data D2 is also 1023. The most significant bit (MSB-0) and the second most significant bit (MSB-1) of the second data D2 are 1 and 1 respectively, and the most significant bit (MSB'-0) and the second most significant bit (MSB'-1) of the first data D1 are 1 and 1 respectively. Because the difference between 11 and 11 is equal to 00, the difference between the values ​​of the first data D1 and the second data D2 is equal to a preset value. The first time period is considered to be the time period between time point e of time period T1 and time point a of time period T2, as shown in the profile. The transition period is considered to be the time period between time points a and b of time period T2. The second time period is considered to be the time period between time points b and e of time period T2. In the first time period, comparator 223 determines that the difference between the values ​​of the first data D1 and the second data D2 is equal to a preset value. In the transition period, a voltage pulse of the drive signal DR is generated. Because the difference between the values ​​of the first data D1 and the second data D2 equals a preset value, comparator 223 shuts down the variable current source 2220. During the transition period, the output buffer 222, with the variable current source 2220 turned off, drives the display panel 20 without increasing the slew rate. During the second period, the second latch 221 transfers the second data D2 to the output buffer 222 to drive the display panel 20.

[0047] Table 1 shows the values ​​of the most significant bit MSB-0 and the second most significant bit MSB-1, and Table 2 shows the values ​​of the most significant bit MSB'-0 and the second most significant bit MSB'-1.

[0048] Table 1

[0049] 0 0 0～255 0 1 256～511 1 0 512～767 1 1 768～1023

[0050] Table 2

[0051] 0 0 0～255 0 1 256～511 1 0 512～767 1 1 768～1023

[0052] Figure 6The waveforms of the source driver output enable signal SOE, the adaptive high drive signal AHDR, the variable current and output signal Y of a display driver according to an embodiment of the present invention, and the high drive signal HDR of the prior art are shown below. Figure 6 and Figure 4 When the source driver outputs the enable signal SOE voltage pulse during each time period T0' and T1', the display driver 22 receives a high drive signal HDR voltage pulse to turn on the variable current source 2220 and increase the variable current. The power waste of the display driver 22 increases with the increase in variable current. However, because the difference between the values ​​of the first data D1 and the second data D2 is less than or equal to a preset value, the adaptive high drive signal AHDR and the output signal Y maintain a fixed voltage. Therefore, compared to the prior art high drive signal HDR, the adaptive high drive signal AHDR reduces unnecessary power waste and heat, achieving maximum power efficiency.

[0053] Figure 7 This is a schematic diagram of a comparator according to an embodiment of the present invention. Please refer to [link / reference]. Figure 7 and Figure 4 The comparator 223 may include a first logic circuit 2230, a register 2231, and a second logic circuit 2232. The first logic circuit 2230 is coupled to a first latch 220 and a second latch 221. The register 2231 is coupled to the first logic circuit 2230. The second logic circuit 2232 is coupled to the register 2231 and a variable current source 2220. The first logic circuit 2230 receives first data D1 and second data D2, and performs logical operations on the most significant bit (MSB-0) and the second most significant bit (MSB-1) of the second data D2 and the most significant bit (MSB'-0) and the second most significant bit (MSB'-1) of the first data D1 to generate at least one logical value. The register 2231 receives and stores this logical value, and the second logic circuit 2232 receives a drive signal DR. When a voltage pulse of the drive signal DR is generated, the second logic circuit 2232 retrieves a logical value from the register 2231. The second logic circuit 2232 performs logical operations on the logical value to generate an adaptive high drive signal AHDR. Figure 7 The architecture can be applied to Figure 4 The architecture or other embodiments may be used, but the present invention is not limited thereto. Figure 7 The architecture of comparator 223.

[0054] Figure 8 This is a schematic diagram of an output buffer according to an embodiment of the present invention. Please refer to [link / reference]. Figure 8 and Figure 4The output buffer 222 may include an input differential pair circuit 2221, a gain stage circuit 2222, and an output stage circuit 2223. The input differential pair circuit 2221 couples a digital-to-analog converter 225 to a variable current source 2220. The gain stage circuit 2222 couples the input differential pair circuit 2221. The output stage circuit 2223 couples the gain stage circuit 2222 to the display panel 20. The digital-to-analog converter 225 performs digital-to-analog conversion on first data D1 and second data D2 to generate an analog signal. The input differential pair circuit 2221 of the output buffer 222 receives the analog signal to generate an output signal Y that drives the display panel 20. Figure 8 The architecture can be applied to Figure 4 The architecture or other embodiments may be used, but the present invention is not limited thereto. Figure 8 The architecture of the output buffer 222.

[0055] Figure 9 This is a schematic diagram of a comparator according to another embodiment of the present invention. Please refer to [link / reference]. Figure 9 and Figure 7 The first logic circuit 2230 includes a first inverter INV1, a second inverter INV2, a third inverter INV3, a fourth inverter INV4, a first NAND gate NAND1, a second NAND gate NAND2, a third NAND gate NAND3, a fourth NAND gate NAND4, a fifth NAND gate NAND5, a first XOR gate XOR1, a second XOR gate XOR2, a first NOR gate NOR1, and a second NOR gate NOR2. The first inverter INV1 and the second inverter INV2 are coupled to a first latch 220. The third inverter INV3 and the fourth inverter INV4 are coupled to a second latch 221. The first NAND gate NAND1 is coupled to the first inverter INV1, the third inverter INV3, and the fourth inverter INV4. The second NAND gate NAND2 is coupled to the first inverter INV1, the second inverter INV2, and the third inverter INV3. The third NAND gate (NAND3) couples the first inverter (INV1), the second inverter (INV2), and the third inverter (INV3). The fourth NAND gate (NAND4) couples the first inverter (INV1), the third inverter (INV3), and the fourth inverter (INV4). The fifth NAND gate (NAND5) couples the first NAND gate (NAND1), the second NAND gate (NAND2), the third NAND gate (NAND3), the fourth NAND gate (NAND4), and register 2231. The first XOR gate (XOR1) couples the first latch (XOR1) and the second latch (XOR2). The second XOR gate (XOR2) couples the first latch (XOR1), the fifth NAND gate (NAND5), and register 2231.

[0056] The first inverter INV1 receives the most significant bit MSB-0 to generate an inverted most significant bit. The second inverter INV2 receives the second most significant bit MSB-1 to generate an inverted second most significant bit. The third inverter INV3 receives the most significant bit MSB'-0 to generate an inverted most significant bit. The fourth inverter, INV4, receives the second most significant bit, MSB'-1, to generate an inverted second most significant bit. The first NAND gate NAND1 and the fourth NAND gate NAND4 receive the most significant bit in the reverse direction. The second most significant bit in the opposite direction The second NAND gate NAND2 and the third NAND gate NAND3 receive the most significant bit in the opposite direction. The second most significant bit in the opposite direction The first XOR gate (XOR1) receives the most significant bit in the reverse direction. The second XOR gate (XOR2) receives the inverted second most significant bit. The first logic circuit 2230 reverses the most significant bit. The second most significant bit in the opposite direction Perform logical operations to produce a logical value for each of the fifth NAND gate (NAND5) and the second NOR gate (NOR2).

[0057] Register 2231 may include a first D flip-flop F1 and a second D flip-flop F2. The first D flip-flop F1 is coupled to a fifth NAND gate (NAND5), and the second D flip-flop F2 is coupled to a second NOR gate (NOR2). The first D flip-flop F1 and the second D flip-flop F2 receive and store logic values.

[0058] The second logic circuit 2232 may include a sixth NAND gate NAND6, a fifth inverter INV5, a seventh NAND gate NAND7, and a sixth inverter INV6. The sixth NAND gate NAND6 is coupled to a first D flip-flop F1, the fifth inverter INV5 is coupled to the sixth NAND gate NAND6, the seventh NAND gate NAND7 is coupled to a second D flip-flop F2, and the sixth inverter INV6 is coupled to the seventh NAND gate NAND7. The sixth NAND gate NAND6 receives a drive signal DR and a logic value to generate a first control signal. The fifth inverter INV5 receives the first control signal. This generates a first control signal C1. The seventh NAND gate (NAND7) receives the drive signal DR and a logic value to generate a second control signal. The sixth inverter INV6 receives the second control signal. This generates a second control signal C2. Figure 9 The architecture can be applied to Figure 4 The architecture or other embodiments may be used, but the present invention is not limited thereto. Figure 9 The architecture of comparator 223.

[0059] Figure 10 This is a schematic diagram of an output buffer according to another embodiment of the present invention. This embodiment uses four variable current sources as an example. Please refer to... Figure 4 , Figure 8 , Figure 9 and Figure 10 The output buffer 222 may include two first variable current sources 2220_1 and 2220_1' and two second variable current sources 2220_2 and 2220_2'. The first currents of the first variable current sources 2220_1 and 2220_1' are equal, and the second currents of the second variable current sources 2220_2 and 2220_2' are also equal. It is assumed that the second current is greater than the first current. The input differential pair circuit 2221 may include two N-channel MOSFETs MN1, one N-channel MOSFET MN2, two P-channel MOSFETs MP1, and one P-channel MOSFET MP2. The N-channel MOSFETs MN1 and MP1 couple the digital-to-analog converter 225, and the N-channel MOSFETs MN1 and MP1 receive the input analog signal. N-channel MOSFET MN2 receives a high bias voltage VN as a fixed current source. P-channel MOSFET MP2 receives a low bias voltage VP as a fixed current source. The fixed currents of the fixed current sources are equal. The fixed current sources, the first variable current sources 2220_1, 2220_1', and the second variable current sources 2220_2, 2220_2' form the tail current source of the output buffer 222. The tail current of the tail current source is denoted by I and is formed by the fixed current, the first current, and the second current. The first variable current sources 2220_1, 2220_1' are coupled to the sixth NAND gate NAND6 and the fifth inverter INV5, respectively. The second variable current sources 2220_2, 2220_2' are coupled to the seventh NAND gate NAND7 and the sixth inverter INV6, respectively. The first variable current source 2220_1 and the second variable current source 2220_2 are coupled in parallel, and the first variable current source 2220_1' and the second variable current source 2220_2' are coupled in parallel.

[0060] The first variable current source 2220_1 may include an electronic switch W1 and an N-channel metal-oxide-semiconductor field-effect transistor MN3. Electronic switch W1 is coupled to a fifth inverter INV5 and N-channel MOSFETs MN1, MN2, and MN3. N-channel MOSFET MN3 receives a high bias voltage VN1. Electronic switch W1 receives a first control signal C1 to be turned on or off. The first variable current source 2220_1' may include an electronic switch W2 and a P-channel MOSFET MP3. Electronic switch W2 is coupled to a sixth NAND gate NAND6 and P-channel MOSFETs MP1, MP2, and MP3. P-channel MOSFET MP3 receives a low bias voltage VP1. Electronic switch W2 receives the first control signal. It can be turned on or off.

[0061] The second variable current source 2220_2 may include an electronic switch W3 and an N-channel metal-oxide-semiconductor field-effect transistor MN4. Electronic switch W3 is coupled to a sixth inverter INV6 and N-channel MOSFETs MN1, MN2, and MN4. N-channel MOSFET MN4 receives a high bias voltage VN2. Electronic switch W3 receives a second control signal C2 to be turned on or off. The second variable current source 2220_2' may include an electronic switch W4 and a P-channel MOSFET MP4. Electronic switch W4 is coupled to a seventh NAND gate NAND7 and P-channel MOSFETs MP1, MP2, and MP4. P-channel MOSFET MP4 receives a low bias voltage VP2. Electronic switch W4 receives a second control signal. It can be turned on or off.

[0062] The gain stage circuit 2222 may include P-channel MOSFETs MP5, MP6, MP7, and MP8, current sources S1 and S2, N-channel MOSFETs MN5, MN6, MN7, and MN8, and capacitors CM1 and CM2. P-channel MOSFETs MP5, MP6, MP7, and MP8 are coupled to N-channel MOSFET MN1. N-channel MOSFETs MN5, MN6, MN7, and MN8 are coupled to P-channel MOSFET MP1. The conversion efficiency can be defined as I / m1 or I / m2, where m1 and m2 are the Miller compensation capacitance values ​​of capacitors CM1 and CM2, respectively.

[0063] The output stage circuit may include a P-channel MOSFET MP9 and an N-channel MOSFET MN9. The nodes between the P-channel MOSFET MP9 and the N-channel MOSFET MN9 are coupled to capacitors CM1 and CM2. The P-channel MOSFET MP9 and the N-channel MOSFET MN9 output the aforementioned output signal Y. Figure 10 The architecture can be applied to Figure 4 The architecture or other embodiments may be used, but the present invention is not limited thereto. Figure 10 The architecture of the buffer 222.

[0064] The difference between the first data D1 and the second data D2 is obtained by comparing the most significant bits MSB-0 and MSB'-0 with the second most significant bits MSB-1 and MSB'-1, so this difference can be 0, 1, 2, or 3. Table 3 shows this difference, the first control signal C1, and the second control signal C2. According to Table 3, when this difference is large, the tail current will also be high.

[0065] Table 3

[0066] 0 0 0 1 0 1 2 1 0 3 1 1

[0067] Figure 11 This is a waveform diagram of the output signal and the adaptive high-drive signal of a display driver according to an embodiment of the present invention. Please refer to... Figure 11 and Figure 10 When a voltage pulse is generated for the adaptive high drive signal AHDR of the first variable current sources 2220_1 and 2220_1', electronic switches W1 and W2 are turned on. When a voltage pulse is generated for the adaptive high drive signal AHDR of the second variable current sources 2220_2 and 2220_2', electronic switches W3 and W4 are turned on. When only the voltage pulse for the adaptive high drive signal AHDR of the first variable current sources 2220_1 and 2220_1' is generated, the output signal Y changes slowly. When voltage pulses for the adaptive high drive signals AHDR of both the first and second variable current sources 2220_1 and 2220_1' and the second variable current sources 2220_2 and 2220_2' are generated, the output signal Y changes rapidly. In other words, increasing the number of activated variable current sources increases the slew rate of the output buffer 222.

[0068] Figure 12 The waveform diagram shows the output signal of the display driver and the adaptive high-drive signal according to another embodiment of the present invention. Please refer to... Figure 12 and Figure 10When the voltage pulses of the adaptive high drive signal AHDR used for the first variable current sources 2220_1, 2220_1' and the second variable current sources 2220_2, 2220_2' have a narrow width, the output signal Y changes slowly. When the voltage pulses of the adaptive high drive signal AHDR used for the first variable current sources 2220_1, 2220_1' and the second variable current sources 2220_2, 2220_2' have a wide width, the output signal Y changes rapidly. In other words, increasing the width of the voltage pulses of the adaptive high drive signal AHDR can increase the slew rate of the output buffer 222.

[0069] According to the above embodiments, the display driver and its driving method control at least one variable current source based on the difference between the values ​​of the corresponding first data and the second data and a preset value, thereby reducing unnecessary power waste and unnecessary heat at a fixed update rate and achieving maximum power efficiency.

[0070] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of the present invention. Therefore, all equivalent variations and modifications made in accordance with the shape, structure, features and spirit described in the claims of the present invention should be included within the scope of the claims of the present invention.

[0071] Symbol Explanation

[0072] 1… Display device

[0073] 10… LCD display panel

[0074] 11…Gate Driver

[0075] 12…Source Driver

[0076] 120… Output Buffer

[0077] 2… Display device 2

[0078] 20… Display Panel

[0079] 21… Gate Driver

[0080] 22… Display Driver

[0081] 220…First latch

[0082] 221…Second latch

[0083] 222… Output Buffer

[0084] 2221…Input Differential Pair Circuit

[0085] 2222…Gain Stage Circuit

[0086] 2223… Output stage circuit

[0087] 2220…Variable Current Source

[0088] 2220_1, 2220_1'... First Variable Current Source

[0089] 2220_2, 2220_2'... Second Variable Current Source

[0090] 223… comparator

[0091] 2230…First Logic Circuit

[0092] 2231… register

[0093] 2232…Second Logic Circuit

[0094] 224…Electrical displacement device

[0095] 225… Digital-to-Analog Converter

[0096] Y…output signal

[0097] SOE…Source driver output enable signal

[0098] HDR…High Drive Signal

[0099] Time periods T0, T1, T2, T3, T4, T0', T1'...

[0100] D… Input data

[0101] DR…drive signal

[0102] AHDR… Adaptive Drive Signal

[0103] D1…First Data

[0104] D2…Second Data

[0105] MSB-0, MSB'-0... most significant bit

[0106] MSB-1, MSB'-1... second most significant bit

[0107] a, b, c, d, e... time points

[0108] INV1…First Inverter

[0109] INV2…Second Inverter

[0110] INV3…Third Inverter

[0111] INV4…Fourth Inverter

[0112] INV5... Fifth Inverter

[0113] INV6…Sixth Inverter

[0114] NAND1…First NAND gate

[0115] NAND2…Second NAND gate

[0116] NAND3…Third NAND gate

[0117] NAND4... Fourth NAND gate

[0118] NAND5… Fifth AND gate

[0119] NAND6…Sixth NAND gate

[0120] NAND7…The Seventh AND Gate

[0121] XOR1…First XOR gate

[0122] XOR2…the second XOR gate

[0123] NOR1…First NOR gate

[0124] NOR2…Second NOR gate

[0125] …the most significant bit in reverse order

[0126] …the second most significant bit in reverse order

[0127] F1…First D flip-flop

[0128] F2...Second D flip-flop

[0129] C1, …first control signal

[0130] C2, …second control signal

[0131] N-channel metal-oxide-semiconductor field-effect transistors…MN1, MN2, MN3, MN4, MN5, MN6, MN7, MN8, MN9

[0132] P-channel metal-oxide-semiconductor field-effect transistors…MP1, MP2, MP3, MP4, MP5, MP6, MP7, MP8, MP9

[0133] VN, VN1, VN2… High bias voltage

[0134] VP, VP1, VP2... Low bias voltage

[0135] I…tail current

[0136] W1, W2, W3, W4… Electronic switches

[0137] S1, S2... Current source

[0138] CM1, CM2... capacitors

Claims

1. A display driver for driving a display panel, characterized in that, The display driver includes: At least one first latch is used to receive input data; At least one second latch, the input of which is coupled to the output of the at least one first latch; An output buffer, including at least one variable current source, wherein the output buffer is coupled to the at least one second latch; and A comparator, coupled to the at least one first latch, the at least one second latch, and the at least one variable current source, wherein the comparator is used to generate at least one control signal for the at least one variable current source; The comparator includes: A first logic circuit, coupled to the at least one first latch and the at least one second latch; Register, coupled to the first logic circuit; and A second logic circuit is coupled to the register and the at least one variable current source; The first logic circuit includes: The first inverter and the second inverter are coupled to the at least one first latch; The third inverter and the fourth inverter are coupled to the at least one second latch; The first NAND gate couples the first inverter, the third inverter, and the fourth inverter; The second NAND gate couples the first inverter, the second inverter, and the third inverter; The third NAND gate couples the first inverter, the second inverter, and the third inverter. The fourth NAND gate couples the first inverter, the third inverter, and the fourth inverter. The fifth NAND gate couples the first NAND gate, the second NAND gate, the third NAND gate, the fourth NAND gate, and the register; A first XOR gate couples the at least one first latch to the at least one second latch; A second XOR gate couples the at least one first latch to the at least one second latch; A first NOR gate, coupled to the first XOR gate and the second XOR gate; and The second NOR gate couples the first NOR gate, the fifth NAND gate, and the register.

2. The display driver as claimed in claim 1, characterized in that, The registers mentioned therein include: The first D flip-flop, coupled to the fifth NAND gate; and The second D flip-flop is coupled to the second NOR gate.

3. The display driver as described in claim 2, characterized in that, The at least one variable current source includes two first variable current sources and two second variable current sources.

4. The display driver as claimed in claim 3, characterized in that, The second logic circuit includes: The sixth NAND gate is coupled to the first D flip-flop; The fifth inverter is coupled to the sixth NAND gate; The seventh NAND gate is coupled to the second D flip-flop; and The sixth inverter is coupled to the seventh NAND gate, wherein the sixth NAND gate and the fifth inverter are respectively coupled to the two first variable current sources, and the seventh NAND gate and the sixth inverter are respectively coupled to the two second variable current sources.

5. The display driver as claimed in claim 1, characterized in that, The output buffer further includes: An input differential pair circuit is used to couple the at least one second latch to the at least one variable current source; Gain stage circuit, coupled to the input differential pair circuit; and The output stage circuit is coupled to the gain stage circuit.

6. The display driver as claimed in claim 1, characterized in that, The at least one first latch includes a plurality of first latches, and the at least one second latch includes a plurality of second latches.

7. The display driver as claimed in claim 1, characterized in that, It also includes a digital-to-analog converter coupled to the at least one second latch and the output buffer.

8. The display driver of claim 7, further comprising an electrical shifter coupled to the digital-to-analog converter and the at least one second latch.

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