Display panel and display device

Abstract

The application discloses a display panel and a display device. The display area of the display panel comprises a plurality of arrayed sub-pixels, the non-display area comprises a plurality of multipath gating units, a plurality of signal source lines and M timing control lines, wherein M is an integer greater than 1; the multipath gating unit comprises N gating switches, the input ends of the plurality of gating switches in the same multipath gating unit are electrically connected with the same signal source line, the output end of each gating switch is electrically connected with a column of sub-pixels, and the control ends of the plurality of gating switches are electrically connected with different timing control lines, wherein M=K*N, K and N are both integers greater than 1; there is at least one timing control line, when the gating switches controlled by the timing control line are turned on, the voltage polarities of the data signals transmitted by the at least two signal source lines electrically connected with the at least two gating switches controlled by the timing control line are opposite. The above technical scheme can avoid charging delay of part of the sub-pixels, ensure the charging balance of the sub-pixels in the display panel, and improve the display effect of the display panel.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a display panel and display device. Background Technology

[0002] With the rapid development of display technology, people have increasingly higher requirements for the quality of display panels. The non-display area of ​​a monitor houses a display driver chip that controls the display. This chip provides data signals to the data lines to charge the sub-pixels for display. For small-sized display panels, where space is limited, the display driver chip primarily provides data signals to the data lines through a multiplexing circuit. A signal source line connected to one of the display driver chip's signal output ports can provide data signals to multiple data lines in a time-division manner, thus charging the connected sub-pixels.

[0003] However, existing display panels may have charging delays or uneven charging of subpixels, which can lead to vertical lines in severe cases and affect the display effect of the panel. Summary of the Invention

[0004] The present invention provides a display panel and display device to avoid charging delay of some sub-pixels, ensure balanced charging of sub-pixels in the display panel, and improve the display effect of the display panel.

[0005] In a first aspect, embodiments of the present invention provide a display panel, including a display area and a non-display area located on one side of the display area. The display area includes a plurality of sub-pixels arranged in an array, and the non-display area includes a plurality of multiplexing units, a plurality of signal source lines and M timing control lines, wherein M is an integer greater than 1.

[0006] The multiplexing unit includes N gating switches. In the same multiplexing unit, the input terminals of multiple gating switches are electrically connected to the same signal source line, the output terminal of each gating switch is electrically connected to a column of sub-pixels, and the control terminals of multiple gating switches are electrically connected to different timing control lines. Where M = K * N, and K and N are both integers greater than 1.

[0007] During the display phase, N timing control lines electrically connected to the same multiplexing unit are used to output valid timing control signals in a time-division manner to control the N gating switches of the multiplexing unit to be turned on in a time-division manner; there exists at least one timing control line, when the gating switch it controls is turned on, the voltage polarity of the data signals transmitted by at least two signal source lines electrically connected to at least two gating switches it controls is opposite.

[0008] In a second aspect, embodiments of the present invention provide a display device, including a display panel as described in the first aspect.

[0009] The solution provided by this invention sets the display area to include multiple arrayed sub-pixels, and the non-display area to include multiple multiplexing units, multiple signal source lines, and M timing control lines, where M is an integer greater than 1. Each multiplexing unit includes N gating switches. Within the same multiplexing unit, the input terminals of multiple gating switches are electrically connected to the same signal source line, the output terminal of each gating switch is electrically connected to a column of sub-pixels, and the control terminals of multiple gating switches are electrically connected to different timing control lines, where M = K*N, and K and N are both integers greater than 1. This reduces the number of gating switches electrically connected to each timing control line, thereby avoiding problems such as sub-pixel charging delay and uneven charging due to excessive load on the timing control lines. During the display stage, the N timing control lines electrically connected to the same multiplexing unit output effective timing control signals in a time-division manner, controlling the N gating switches of the multiplexing unit to conduct in a time-division manner. This helps reduce the number of signal source lines, thereby reducing the number of data signal pins in the driver chip, and ultimately reducing the cost of the display panel driven by this driver chip. There is at least one timing control line. When the gating switch controlled by it is turned on, the voltage polarities of the data signals transmitted by at least two signal source lines electrically connected to at least two gating switches controlled by it are opposite. This allows the coupling effects of data signals with opposite voltage polarities on the timing control signal to cancel each other out. This ensures that the effective timing control signal transmitted by the timing control line can be quickly maintained at a stable effective level, avoids charging delay of some sub-pixels, ensures balanced charging of each sub-pixel in the display area, and thus improves the display effect of the display panel.

[0010] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0011] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, although the drawings described below are some specific embodiments of the present invention, those skilled in the art can extend and extend the basic concepts of the device structure, driving method and manufacturing method disclosed and indicated by various embodiments of the present invention to other structures and drawings. Undoubtedly, these should all be within the scope of the claims of the present invention.

[0012] Figure 1 This is a partial structural diagram of a display panel in the prior art;

[0013] Figure 2 for Figure 1 The driving timing diagram;

[0014] Figure 3 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention;

[0015] Figure 4 This is a partial structural diagram of a display panel provided in an embodiment of the present invention;

[0016] Figure 5 A partial structural schematic diagram of another display panel provided in an embodiment of the present invention;

[0017] Figure 6 A partial structural schematic diagram of another display panel provided in an embodiment of the present invention;

[0018] Figure 7 A partial structural schematic diagram of another display panel provided in an embodiment of the present invention;

[0019] Figure 8 A partial structural schematic diagram of another display panel provided in an embodiment of the present invention;

[0020] Figure 9 A partial structural schematic diagram of another display panel provided in an embodiment of the present invention;

[0021] Figure 10 A partial structural schematic diagram of another display panel provided in an embodiment of the present invention;

[0022] Figure 11 A partial structural schematic diagram of another display panel provided in an embodiment of the present invention;

[0023] Figure 12 A partial structural schematic diagram of another display panel provided in an embodiment of the present invention;

[0024] Figure 13 A partial structural schematic diagram of another display panel provided in an embodiment of the present invention;

[0025] Figure 14 A partial structural schematic diagram of another display panel provided in an embodiment of the present invention;

[0026] Figure 15 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention. Detailed Implementation

[0027] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of this invention. Obviously, the described embodiments are only some embodiments of this invention, not all embodiments. Based on the basic concepts disclosed and indicated in the embodiments of this invention, all other embodiments obtained by those skilled in the art are within the scope of protection of this invention.

[0028] As described in the background technology description, Figure 1 This is a partial structural diagram of a display panel in the prior art, such as... Figure 1 As shown, the display area AA' of the display panel 100' includes multiple arrayed sub-pixels P', and the non-display area NA' of the display panel 100' includes multiple multiplexing units 10'. Each multiplexing unit 10' includes multiple selection switches T', for example, each multiplexing unit 10' includes three selection switches T', namely T1', T2', and T3'. The input terminals of T1', T2', and T3' within the same multiplexing unit 10' are electrically connected to the same signal source line S' (for example, signal source lines S' include S1', S2', S3', and S4'). The control terminals of the multiple selection switches T' are electrically connected to different timing control lines CKH'. To reduce the number of selection switches T' electrically connected to each timing control line CKH', two sets of timing control lines CKH' are usually set, for example, the two sets of timing control lines CKH' include CKH1. In the '~CKH6' series, the selector switches T1', T2', and T3' of the odd-numbered multiplexer units 10' are electrically connected to the first set of timing control lines CKH1', CKH2', and CKH3', respectively. Conversely, the selector switches T1', T2', and T3' of the even-numbered multiplexer units 10' are electrically connected to the second set of timing control lines CKH4', CKH5', and CKH6', respectively. The output of each selector switch T' is electrically connected to a column of sub-pixels P'. Thus, when a valid timing control signal provided by the timing control line CKH' turns on the selector switch T', the signal source line S' electrically connected to the selector switch T' can provide a data signal to the sub-pixel P', thereby charging the sub-pixel P'.

[0029] However, the inventors discovered that due to the parasitic capacitance (not shown in the figure) between the control terminal and input terminal of the gating switch T', a coupling effect occurs between the timing control signal transmitted by the timing control line CKH' and the data signal transmitted by the signal source line S', which is a problem in existing technologies. Figure 1The voltage polarities of the data signals provided by adjacent signal source lines S' are opposite. The voltages of the data signals provided by the signal source lines S' electrically connected to the odd-numbered multiplexing units 10' are all positive, while the voltages of the data signals provided by the signal source lines S' electrically connected to the even-numbered multiplexing units 10' are all negative. This results in the data signals transmitted by the signal source lines S' electrically connected to the selection switches T' controlled by each timing control line CKH having the same polarity. Thus, under the coupling effect between the timing control line CKH' and the signal source line S', the data signals provided by the signal source line S' will couple to the effective timing control signal provided by the timing control line CKH', pulling down or raising the effective timing control signal Ckh, thereby affecting the normal charging of the sub-pixel P' and causing charging abnormalities or imbalances. Figure 2 for Figure 1 The driver timing diagram is shown in the reference. Figure 1 and Figure 2 As shown, the effective timing control signal Ckh provided by the timing control line CKH' is a high-level signal. At this time, the timing control signal Ckh controls the gating switch T' to be turned on, so that the data signal s provided by the signal source line S' is transmitted to the sub-pixel P' through the gating switch T'. When the data signal provided by the signal source line S' is a negative polarity signal (i.e., s(-)), due to the coupling effect, the timing control signal Ckh will be pulled low, so the process of the timing control signal Ckh jumping from low level to high level is very long (see reference). Figure 2 The dotted circle indicates the location of the output signal. This causes the timing control signal Ckh to delay to reach a stable high level and reduces the duration of its high-level state, thus delaying the turn-on of the gating switch T' and shortening the charging time. However, when the data signal s provided by the signal source line S' is a positive signal (i.e., s(+)), the coupling effect will raise the timing control signal Ckh, allowing it to quickly transition from a low level to a high level, thus ensuring that the timing control signal Ckh quickly maintains a stable high level. As a result, there is a charging delay in the sub-pixels P' within the display area AA', leading to uneven charging among the sub-pixels P', which in turn causes vertical lines to appear on the display panel, affecting the display effect.

[0030] Based on the above-mentioned technical problems, embodiments of the present invention provide a display panel, which includes a display area and a non-display area located on one side of the display area. The display area includes multiple sub-pixels arranged in an array, and the non-display area includes multiple multiplexing units, multiple signal source lines, and M timing control lines, where M is an integer greater than 1. The multiplexing unit includes N gating switches. In the same multiplexing unit, the input terminals of multiple gating switches are electrically connected to the same signal source line, the output terminal of each gating switch is electrically connected to a column of sub-pixels, and the control terminals of multiple gating switches are electrically connected to different timing control lines, where M = K*N, and K and N are both integers greater than 1. During the display stage, the N timing control lines electrically connected to the same multiplexing unit are used to output effective timing control signals in a time-division manner to control the N gating switches of the multiplexing unit to be turned on in a time-division manner. There is at least one timing control line, when the gating switch it controls is turned on, the voltage polarity of the data signals transmitted by at least two signal source lines electrically connected to at least two gating switches controlled by it is opposite.

[0031] By adopting the above technical solution, the display area includes multiple arrayed sub-pixels, and the non-display area includes multiple multiplexing units, multiple signal source lines, and M timing control lines, where M is an integer greater than 1. Each multiplexing unit includes N selection switches. Within the same multiplexing unit, the input terminals of multiple selection switches are electrically connected to the same signal source line, the output terminal of each selection switch is electrically connected to a column of sub-pixels, and the control terminals of multiple selection switches are electrically connected to different timing control lines. Here, M = K*N, where K and N are both integers greater than 1. This reduces the number of selection switches electrically connected to each timing control line, thus avoiding problems such as sub-pixel charging delay and uneven charging due to excessive load on the timing control lines. During the display stage, the N timing control lines electrically connected to the same multiplexing unit output effective timing control signals in a time-division manner, controlling the N selection switches of the multiplexing unit to conduct in a time-division manner. This helps reduce the number of signal source lines, thereby reducing the number of data signal pins in the driver chip and ultimately lowering the cost of the display panel driven by this driver chip. There is at least one timing control line. When the gating switch controlled by it is turned on, the voltage polarities of the data signals transmitted by at least two signal source lines electrically connected to at least two gating switches controlled by it are opposite. This allows the coupling effects of data signals with opposite voltage polarities on the timing control signal to cancel each other out. This ensures that the effective timing control signal transmitted by the timing control line can be quickly maintained at a stable effective level, avoids charging delay of some sub-pixels, ensures balanced charging of each sub-pixel in the display area, and thus improves the display effect of the display panel.

[0032] The above is the core idea of ​​this application. The technical solutions in the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this invention, and not all of them. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0033] Figure 3 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention. Figure 4 This is a partial structural diagram of a display panel provided in an embodiment of the present invention, as shown below. Figure 3 and Figure 4 As shown, the display panel 100 includes a display area AA and a non-display area NA located on one side of the display area AA. The display area AA includes multiple sub-pixels P arranged in an array. The non-display area NA includes multiple multiplexing units 10, multiple signal source lines S, and M timing control lines CKH, where M is an integer greater than 1. The multiplexing unit 10 includes N selection switches T. In the same multiplexing unit 10, the input terminals of multiple selection switches T are electrically connected to the same signal source line S, the output terminal of each selection switch T is electrically connected to a column of sub-pixels P, and the control terminals of multiple selection switches T are electrically connected to different timing control lines CKH, where M = K * N, and K and N are both integers greater than 1. During the display phase, N timing control lines CKH electrically connected to the same multiplexing unit 10 are used to output valid timing control signals Ckh in a time-division manner, controlling the N gating switches T of the multiplexing unit 10 to be turned on in a time-division manner; there exists at least one timing control line CKH, when the gating switch T it controls is turned on, the voltage polarity of the data signals transmitted by at least two signal source lines S electrically connected to at least two gating switches T controlled by it is opposite.

[0034] In the display area AA, the colors of the sub-pixels P arranged in multiple arrays can be the same or different in each column. No specific limitation is made here. Sub-pixels P can be red (R), green (G), blue (B), white (W), or yellow (Y), etc. No specific limitation is made in this invention. The arrangement of sub-pixels P in the display area AA is not limited to an array arrangement; other arrangements are also possible, such as a triangular arrangement. No specific limitation is made in this invention.

[0035] The number N of gating switches T in the multiplexing unit 10 can be any integer value greater than or equal to 2, without specific limitation here. Depending on the value of K, the number M of timing control lines CKH will also vary. Since K is an integer greater than 1, the minimum value of K is 2. In other words, the minimum number M of timing control lines CKH is twice the number N of gating switches T in the multiplexing unit 10. Compared to the case where the number of timing control lines CKH is the same as the number of gating switches T in the multiplexing unit 10 (i.e., K=1), in this embodiment, the display panel 100K is an integer greater than 1. This reduces the number of gating switches T electrically connected to each timing control line CKH, thereby avoiding problems such as charging delay and uneven charging of sub-pixels P due to excessive load on the timing control lines CKH.

[0036] It should be noted that the value of K can be set according to actual needs, and this embodiment does not impose a specific limitation on it. For the sake of detailed explanation, unless otherwise specified, the following embodiments use K=2 as an example for illustrative purposes.

[0037] Optionally, the number N of the selection switches T in the multiplexing unit 10 can be N=2, N=3, or N=6, but is not limited to these values. Figure 4 The example shown is N=3.

[0038] In other embodiments, Figure 5 This is a partial structural diagram of another display panel provided in an embodiment of the present invention. Figure 6 This is a partial structural schematic diagram of another display panel provided in an embodiment of the present invention, with reference to... Figure 5 and Figure 6 As shown, Figure 5 An exemplary connection structure diagram with N=2 is shown. Figure 6 An exemplary connection structure with N=6 is shown, but it is not limited thereto.

[0039] To facilitate a detailed explanation of the solution, unless otherwise specified, the following embodiments will be illustrated using N=3 as an example.

[0040] Optionally, the selector switch T includes an N-channel thin-film transistor. It is understood that when the selector switch T is an N-channel thin-film transistor, the selector switch T can be turned on when the timing control line CKH outputs a valid timing control signal Ckh at a high level, and turned off when the timing control line CKH outputs a valid timing control signal Ckh at a low level. The selector switch T can also be a P-channel thin-film transistor. When the timing control line CKH outputs a valid timing control signal Ckh at a low level, the selector switch T can be turned on, and when the timing control line CKH outputs a valid timing control signal Ckh at a high level, the selector switch T can be turned off. The specific type of the selector switch T can be set according to actual needs, and is not specifically limited here. For ease of detailed explanation, unless otherwise specified, the following embodiments will use an N-channel thin-film transistor as an example for the selector switch T.

[0041] Continue to refer to Figures 4 to 6 As shown, it can be understood that the output of each gating switch T (i.e., T1, T2, and T3) in the multiplexing unit 10 is electrically connected to the sub-pixels P in different columns through different data lines. During the display phase of the display panel 100, the N timing control lines CKH electrically connected to the same multiplexing unit 10 output effective timing control signals Ckh in a time-division manner, controlling the N gating switches T of the multiplexing unit 10 to be turned on in a time-division manner. This allows the data signal transmitted by the signal source line S to be transmitted to the sub-pixel P through the data line when the gating switch T is turned on, thereby charging the sub-pixel P. Since each signal source line CKH is electrically connected to N data signal lines through the multiplexing unit 10, compared to the case where one signal source line S corresponds to one data signal line, it is beneficial to reduce the number of signal source lines S, thereby reducing the number of data signal pins in the driver chip, and thus reducing the cost of the display panel 100 driven by this driver chip.

[0042] Further reference Figures 4 to 6As shown, there is at least one timing control line CKH. When the gating switch T controlled by CKH is turned on, the voltage polarities of the data signals transmitted by the at least two signal source lines S electrically connected by the at least two gating switches T are opposite. Taking the effective timing control signal Ckh transmitted by the timing control line CKH as a high level as an example, at this time, the negative polarity data signal will pull down the effective timing control signal Ckh, while the positive polarity data signal will raise the effective timing control signal Ckh. In this way, the coupling effect of the data signals with opposite voltage polarities on the timing control signal Ckh can cancel each other out, ensuring that the effective timing control signal Ckh transmitted by the timing control line CKH can be quickly maintained at a stable effective level (e.g., high level). In this way, the effective timing control signal Ckh received by each gating switch T maintains the same waveform, avoiding the charging delay of some sub-pixels P, ensuring the balanced charging of each sub-pixel P in the display area AA, thereby improving the display effect of the display panel 100.

[0043] Optional, continue to refer to Figures 4 to 6 As shown, the timing control signals of the i-th timing control line CKHi and any i+kN-th timing control line CKH(i+kN) are the same, where 1≤i≤N, 1≤k≤K, and k is an integer.

[0044] Specifically, the number M of timing control lines CKH can be a multiple of the number N of selection switches T in the multiplexing unit 10. Depending on the value of K, the timing control lines CKH can be divided into K groups, where the value of k satisfies 1≤k≤K, and k is any integer within this range.

[0045] For example, refer to Figure 4 As shown, the number of timing control lines CKH, M, is 6, and the number of selection switches T in the multiplexing unit 10, N, is 3, i.e., K = 2. Thus, the 6 timing control lines CKH are divided into 2 groups, k = 1. At this time, when i = 1, i + kN = 4, that is, the timing control signals of the 1st timing control line CKH1 and the 4th timing control line CKH4 are the same; when i = 2, i + kN = 5, that is, the timing control signals of the 2nd timing control line CKH2 and the 5th timing control line CKH5 are the same; when i = 3, i + kN = 6, that is, the timing control signals of the 3rd timing control line CKH3 and the 6th timing control line CKH6 are the same.

[0046] Optional, continue to refer to Figures 4 to 6 As shown, the voltage polarities of the data signals transmitted by the two signal source lines S electrically connected to any two adjacent multiplexing units 10 are opposite; there are two adjacent multiplexing units 10, and among the N timing control lines CKH electrically connected to one of the multiplexing units 10, at least one timing control line CKH is electrically connected to the other multiplexing unit 10.

[0047] Understandably, the output of each gating switch T in the multiplexing unit 10 is electrically connected to a different column of sub-pixels P via different data lines. This allows the data signal transmitted by the signal source line S to be transmitted to the sub-pixel P via the data lines when the gating switch T is turned on, thereby charging the sub-pixel P. By setting the voltage polarity of the data signals transmitted by any two adjacent signal source lines S to be opposite, the influence between the data signals transmitted on the two adjacent data signal lines can be canceled out, thereby improving the accuracy of the data signals transmitted from each data signal line to each sub-pixel P, and further improving the display effect of the display panel 100.

[0048] For example, refer to Figure 4 As shown, there are two adjacent multiplexing units 10, namely a multiplexing unit 10 electrically connected to signal source line S2 and a multiplexing unit 10 electrically connected to signal source line S3. The multiplexing unit 10 electrically connected to signal source line S2 is electrically connected to the fourth timing control line CKH4, the fifth timing control line CKH5, and the sixth timing control line CKH6, respectively. Furthermore, CKH4 to CKH6 are all electrically connected to the multiplexing unit 10 electrically connected to signal source line S3. This allows any one of the fourth, fifth, and sixth timing control lines CKH4, CKH5, and CKH6 to be enabled. When the gating switch T controlled by it is turned on, the voltage polarity of the data signals transmitted by at least two signal source lines S (i.e., signal source line S2 and signal source line S3) electrically connected by at least two gating switches T controlled by it is opposite. This makes the coupling effect of the data signals transmitted by the signal source lines S on the timing control signals Ckh (i.e., Ckh4, Ckh5 and Ckh6) cancel each other out. This ensures that the effective timing control signal Ckh transmitted by the timing control line CKH can be quickly maintained at a stable effective level (i.e., high level), avoiding charging delay of some sub-pixels P, ensuring balanced charging of each sub-pixel P in the display area AA, thereby improving the display effect of the display panel 100.

[0049] In other embodiments, Figure 7 This is a partial structural schematic diagram of another display panel provided in an embodiment of the present invention, with reference to... Figure 7As shown, there are two adjacent multiplexing units 10, namely a multiplexing unit 10 electrically connected to signal source line S1 and a multiplexing unit 10 electrically connected to signal source line S2. The multiplexing unit 10 electrically connected to signal source line S1 is electrically connected to the first timing control line CKH1, the second timing control line CKH2, and the third timing control line CKH3, respectively. Only the second timing control line CKH2 and the third timing control line CKH3 are connected to the multiplexing unit electrically connected to signal source line S2. Unit 10 is electrically connected such that, when either the second timing control line CKH2 or the third timing control line CKH3 controls the turn-on switch T, the voltage polarities of the data signals transmitted by the at least two signal source lines S (i.e., signal source lines S1 and S2) electrically connected to the at least two turn-on switches T controlled by that timing control line are opposite. This allows the coupling effects of the data signals transmitted by the signal source lines S on the timing control signals Ckh (Ckh2 and Ckh3) to cancel each other out. (Continue to refer to...) Figure 7 As shown, the multiplexing unit 10, electrically connected to signal source line S6, is electrically connected to the first timing control line CKH1, the second timing control line CKH2, and the sixth timing control line CKH6, respectively. Since the timing control signals of the third timing control line CKH1 and the sixth timing control line CKH6 are the same, it does not affect the time-division multiplexing of the three selection switches T within the multiplexing unit 10. Furthermore, the polarity of the data signals transmitted by the signal source lines S is set such that S1, S3, and S5 have the same polarity, and S2, S4, and S6 have the same polarity. In this case, when the selection switch T controlled by the first timing control line CKH1 is turned on, the voltage polarities of the data signals transmitted by at least two signal source lines S (i.e., signal source lines S1 and S6) electrically connected to at least two selection switches T controlled by it are opposite, so that the coupling effect of the data signals transmitted by the signal source lines S on the timing control signal CKH1 can be mutually canceled. Thus, Figure 7 The structure shown allows the effective timing control signal Ckh transmitted by the timing control line CKH in the display panel 100 to be quickly maintained at a stable effective level (i.e., high level), avoiding charging delay of some sub-pixels P, ensuring balanced charging of each sub-pixel P in the display area AA, thereby improving the display effect of the display panel 100.

[0050] Optional, continue to refer to Figure 4 As shown, the N selection switches T of the multiplexing unit 10 are divided into the first selection switch T1 to the Nth selection switch TN; for any multiplexing unit 10, the control terminal of the i-th selection switch Ti is electrically connected to the i-th timing control line CKHi, or the control terminal of the i-th selection switch Ti is electrically connected to the i+kN-th timing control line CKH(i+kN).

[0051] Taking K=2, k=1, M=6, N=3 as an example, refer to Figure 4 As shown, the multiplexing unit 10 includes three selection switches, namely T1, T2, and T3. For any selection unit 10, the control terminal of the i-th selection switch Ti is electrically connected to the i-th timing control line CKH1. For example, in the multiplexing unit 10 electrically connected to the signal source line S1, the control terminal of the first selection switch T1 is electrically connected to the first timing control line CKH1, the control terminal of the second selection switch T2 is electrically connected to the second timing control line CKH2, and the control terminal of the third selection switch T3 is electrically connected to the third timing control line CKH3. Alternatively, in the multiplexing unit 10 electrically connected to the signal source line S2, the control terminal of the first selection switch T1 is electrically connected to the fourth timing control line CKH4, the control terminal of the second selection switch T2 is electrically connected to the fifth timing control line CKH5, and the control terminal of the third selection switch T3 is electrically connected to the sixth timing control line CKH6. It is understandable that the timing control lines CKH1 to CKH6 can be considered to be divided into two groups. The first group of timing control lines CKH includes CKH1 to CKH3, and the second group of timing control lines CKH includes CKH4 to CKH5. The multiplexing unit 10 can be electrically connected to either the first group of timing control lines CKH or the second group of timing control lines CKH. Figure 4 This is merely an illustrative example; in other embodiments, it could also be... Figure 8 The structure shown is not specifically limited here, and the specific connection method can be set according to actual needs. Thus, as long as at least one timing control line CKH controls the turn-on switch T, the voltage polarities of the data signals transmitted by the at least two signal source lines S electrically connected to the at least two turn-on switches T are opposite. This ensures that the coupling effect of the data signals transmitted by the signal source lines S on the effective timing control signal Ckh transmitted by the timing control line CKH can cancel each other out. This ensures that the effective timing control signal Ckh transmitted by the timing control line CKH can be quickly maintained at a stable effective level (e.g., high level), avoiding charging delays for some sub-pixels P, ensuring balanced charging of all sub-pixels P within the display area AA, and thus improving the display effect of the display panel 100.

[0052] Optional, Figure 9 This is a partial structural diagram of another display panel provided in an embodiment of the present invention, as shown below. Figure 9 As shown, multiple multiplexing units 10 are divided into multiple multiplexing unit groups 01, and each multiplexing unit group 01 includes at least two adjacent multiplexing units 10. Within the same multiplexing unit group 01, the control terminal of the i-th selection switch Ti of each multiplexing unit 10 is electrically connected to the i-th timing control line CKHi, or the control terminal of the i-th selection switch Ti of each multiplexing unit is electrically connected to the i+kN-th timing control line CKH(i+kN).

[0053] For example, taking K=2, k=1, M=6, N=3 as an example, Figure 9 Two multiplexing unit groups 01 in multiplexing unit group 01 are shown. One of the multiplexing unit groups 01 includes three multiplexing units 10, which are electrically connected to signal source lines S1, S2 and S3 respectively. In each multiplexing unit 10 in the multiplexing unit group 01, the control terminal of the first selection switch T1 is electrically connected to the first timing control line CKH1, the control terminal of the second selection switch T2 is electrically connected to the second timing control line CKH2, and the control terminal of the third selection switch T3 is electrically connected to the third timing control line CKH3. Another multiplexing unit group 01 includes two multiplexing units 10, which are electrically connected to signal source lines S4 and S5 respectively. In each multiplexing unit 10 of the multiplexing unit group 01, the control terminal of the first selection switch T1 is electrically connected to the fourth timing control line CKH4, the control terminal of the second selection switch T2 is electrically connected to the fifth timing control line CKH5, and the control terminal of the third selection switch T3 is electrically connected to the sixth timing control line CKH6. Thus, since the voltage polarity of the data signals transmitted by the signal source lines S electrically connected to at least two adjacent multiplexing units 10 within each multiplexing unit group 01 is opposite, and these two multiplexing units 10 are electrically connected to the same timing control line CKH, when the selection switch T controlled by each timing control line CKH is turned on, the voltage polarity of the data signals transmitted by the at least two signal source lines S electrically connected to the selection switch T is opposite. This allows the coupling effect of the data signals transmitted by the signal source lines S on the effective timing control signal Ckh transmitted by the timing control line CKH to cancel each other out, ensuring balanced charging of each sub-pixel P within the display area AA, thereby improving the display effect of the display panel 100.

[0054] It should be noted that the number of multiple multiplexing units 10 can be two or more multiplexing unit groups 01, which is not specifically limited here and can be set according to actual needs.

[0055] Figure 10 A schematic diagram is shown illustrating the structure of multiple multiplexing units 10 divided into two groups of multiplexing unit groups 01. Each group of multiplexing unit groups 01 includes multiple multiplexing units 10, and each multiplexing unit 10 is electrically connected to a signal source line S (e.g., S1, S2, S3...Sr, Sr+1, Sr+2...). (Continue to refer to...) Figure 10In one of the multiplexing unit groups 01, the control terminal of the i-th selection switch Ti of each multiplexing unit 10 is electrically connected to the i-th timing control line CKH1. That is, in each multiplexing unit 10 of the multiplexing unit group 01, the control terminal of the first selection switch T1 is electrically connected to the first timing control line CKH1, the control terminal of the second selection switch T2 is electrically connected to the second timing control line CKH2, and the control terminal of the third selection switch T3 is electrically connected to the third timing control line CKH3. In another multiplexing unit group 01, the control terminal of the i-th selection switch Ti of each multiplexing unit is electrically connected to the i+kN-th timing control line CKH(i+kN). That is, in each multiplexing unit 10 of the multiplexing unit group 01, the control terminal of the first selection switch T1 is electrically connected to the fourth timing control line CKH4, the control terminal of the second selection switch T2 is electrically connected to the fifth timing control line CKH5, and the control terminal of the third selection switch T3 is electrically connected to the sixth timing control line CKH6.

[0056] Furthermore, the number of multiplexing units 10 in each multiplexing unit group 01 can be the same or different. This invention does not impose specific limitations on this and can be set according to actual needs.

[0057] In an alternative embodiment, Figure 11 This is a partial structural diagram of another display panel provided in an embodiment of the present invention, as shown below. Figure 11 As shown, the number of multiplexing units 10 in each multiplexing unit group 01 is the same, and for any two adjacent multiplexing unit groups 01, the control terminal of the i-th selection switch Ti of the multiplexing unit 10 in one multiplexing unit group 01 is electrically connected to the i-th timing control line CKHi, and the control terminal of the i-th selection switch Ti of the multiplexing unit 10 in the other multiplexing unit group 01 is electrically connected to the i+kN-th timing control line CKH(i+kN).

[0058] For example, taking K=2, k=1, M=6, N=3 as an example, Figure 11The diagram shows the structure of two multiplexing units 10 in each multiplexing unit group 01. For any two adjacent multiplexing unit groups 01, the control terminal of the i-th selection switch Ti of the multiplexing unit 10 in one of the multiplexing unit groups 01 is electrically connected to the i-th timing control line CKH1. That is, the control terminal of the first selection switch T1 of the multiplexing unit 10 is electrically connected to the first timing control line CKH1, the control terminal of the second selection switch T2 is electrically connected to the second timing control line CKH2, and the control terminal of the third selection switch T3 is electrically connected to the third timing control line CKH3. In another multiplexing unit group 01, the control terminals of the i-th selection switch Ti of the multiplexing unit 10 are all electrically connected to the i+kN-th timing control line CKH(i+kN). That is, the control terminal of the first selection switch T1 of the multiplexing unit 10 is electrically connected to the fourth timing control line CKH4, the control terminal of the second selection switch T2 is electrically connected to the fifth timing control line CKH5, and the control terminal of the third selection switch T3 is electrically connected to the sixth timing control line CKH6. In this way, by setting the number of multiplexing units 10 in each multiplexing unit group 01 to be the same, the number of signal source lines S electrically connected to each multiplexing unit group 01 is the same, thereby making the coupling effect of each multiplexing unit group 01 on the timing control signal Ckh consistent. Furthermore, any two adjacent multiplexing unit groups 01 are electrically connected to different timing control lines CKH, that is, the multiplexing unit groups 01 are alternately electrically connected to two different sets of timing control lines CKH (i.e., the first set of timing control lines is CKH1~CKH3, and the second set of timing control lines is CKH4~CKH6). When the number of multiplexing unit groups 01 electrically connected to each set of timing control lines CKH is the same, it can be ensured that the number of selection switches T electrically connected to each timing control line CKH is consistent. This can avoid the problem of uneven charging of sub-pixels P caused by inconsistent loads of different timing control lines CKH, thereby ensuring that the charging of each sub-pixel P is more balanced, improving the display uniformity of the display panel 100, and thus improving the display quality.

[0059] Optional, Figure 12 This is a partial structural diagram of another display panel provided in an embodiment of the present invention, as shown below. Figure 12As shown, multiple multiplexing units 10 are divided into two multiplexing unit groups 01, namely the first multiplexing unit group 01A and the second multiplexing unit group 01B. In the first multiplexing unit group 01A, the control terminals of the i-th selection switches Ti of the odd-numbered multiplexing units 10 are all electrically connected to the i-th timing control line CKHi, and the control terminals of the i-th selection switches Ti of the even-numbered multiplexing units 10 are all electrically connected to the i+kN timing control line CKH(i+kN). In the second multiplexing unit group 01B, the control terminals of the i-th selection switches Ti of the even-numbered multiplexing units 10 are all electrically connected to the i-th timing control line CKHi, and the control terminals of the i-th selection switches Ti of the odd-numbered multiplexing units 10 are all electrically connected to the i+kN timing control line CKH(i+kN).

[0060] For example, taking K=2, k=1, M=6, N=3 as an example, Figure 12The diagram shows the structure of the first multiplexing unit group 01A and the second multiplexing unit group 01B. In the first multiplexing unit group 01A, the control terminal of the first selection switch T1 of the odd-numbered multiplexing unit 10 is electrically connected to the first timing control line CKH1, the control terminal of the second selection switch T2 is electrically connected to the second timing control line CKH2, and the control terminal of the third selection switch T3 is electrically connected to the third timing control line CKH3. In the even-numbered multiplexing unit 10, the control terminal of the first selection switch T1 is electrically connected to the fourth timing control line CKH4, the control terminal of the second selection switch T2 is electrically connected to the fifth timing control line CKH5, and the control terminal of the third selection switch T3 is electrically connected to the sixth timing control line CKH6. Within the second multiplexing unit group 01B, the control terminal of the first selection switch T1 of the even-numbered multiplexing unit 10 is electrically connected to the first timing control line CKH1, the control terminal of the second selection switch T2 is electrically connected to the second timing control line CKH2, and the control terminal of the third selection switch T3 is electrically connected to the third timing control line CKH3; the control terminal of the first selection switch T1 of the odd-numbered multiplexing unit 10 is electrically connected to the fourth timing control line CKH4, the control terminal of the second selection switch T2 is electrically connected to the fifth timing control line CKH5, and the control terminal of the third selection switch T3 is electrically connected to the sixth timing control line CKH6. Thus, for any one of the timing control lines CKH1 to CKH3, the voltage polarity of the data signals transmitted by the signal source lines S (i.e., S1, S3, S5...) electrically connected to the selector switch T located in the first multiplexing unit group 01A is positive, and the voltage polarity of the data signals transmitted by the signal source lines S (i.e., Sr+1, Sr+3, Sr+5...) electrically connected to the selector switch T located in the second multiplexing unit group 01B is negative. This ensures that when the selector switch T controlled by any one of the timing control lines CKH1 to CKH3 is turned on, the data signals transmitted by the corresponding signal source lines S include both positive and negative signals, thereby reducing the coupling effect on the timing control signal Ckh.Similarly, for any one of the timing control lines CKH4 to CKH6, the voltage polarity of the data signals transmitted by the signal source lines S (i.e., S2, S4, S6...) electrically connected to the selector switch T located in the first multiplexing unit group 01A is negative, and the voltage polarity of the data signals transmitted by the signal source lines S (i.e., Sr, Sr+2, Sr+4...) electrically connected to the selector switch T located in the second multiplexing unit group 01B is positive. This ensures that when the selector switch T controlled by any one of the timing control lines CKH4 to CKH5 is turned on, the data signals transmitted by the corresponding signal source lines S include both positive and negative signals, thereby reducing the coupling effect on the timing control signal Ckh. This, in turn, ensures balanced charging of each sub-pixel P in the display area AA and improves the display effect of the display panel 100.

[0061] Further options are available for reference. Figures 10 to 12 As shown, within each multiplexing unit group 01, the number of multiplexing units 10 is even, such that half of the multiplexing units 10 in each multiplexing unit group 01 are electrically connected to the signal source line S transmitting positive data signals, and the other half are electrically connected to the signal source line S transmitting negative data signals. That is, the number of signal source lines S transmitting positive data signals is the same as the number of signal source lines S transmitting negative data signals. This ensures that the coupling effect of each multiplexing unit group 01 on the effective timing control signal Ckh transmitted on the same timing control line CKH is completely canceled. The effective timing control signal Ckh transmitted on each timing control line CKH is not affected by the data signal transmitted on the signal source line S, thereby making the charging of each sub-pixel P more balanced and improving the display effect of the display panel 100.

[0062] Based on any of the above embodiments, optionally, for any timing control line CKH, when its controlled gating switch T is turned on, the number of positive polarity data signals transmitted by the corresponding signal source line S is the same as the number of negative polarity data signals. In this way, when each timing control line CKH controls the gating switch T to be turned on, the coupling effect of the data signal transmitted by the signal source line S electrically connected to the gating switch T on the timing control signal Ckh is completely canceled, ensuring that the effective timing control signal Ckh transmitted by any timing control line CKH is not affected by the data signal transmitted by the signal source line S. This results in more balanced charging of each sub-pixel P, improving the display effect of the display panel 100.

[0063] Further options are available for reference. Figures 4 to 12As shown, the number of selector switches T controlled by each timing control line CKH is the same. This ensures a consistent load on the timing control lines CKH, avoiding uneven charging of sub-pixels P due to inconsistent loads. This guarantees more balanced charging of each sub-pixel P, improving the display uniformity of the display panel 100 and thus enhancing display quality.

[0064] It should be noted that the number of selector switches T controlled to be turned on for each timing control line CKH can be any value. This embodiment of the invention does not impose a specific limitation on this, and can be set according to actual needs.

[0065] Optional, Figure 13 This is a partial structural diagram of another display panel provided in an embodiment of the present invention, as shown below. Figure 13 As shown, the array of multiple sub-pixels P includes 2N adjacent columns of sub-pixels P, and the voltage polarities of the data signals received by the two adjacent columns of sub-pixels P are opposite; the multiple multiplexing units 10 include an adjacent first multiplexing unit 11 and a second multiplexing unit 12, the first multiplexing unit 11 is electrically connected to the sub-pixel P in the 2N columns of sub-pixels P that receives the positive polarity data signal, and the second multiplexing unit 12 is electrically connected to the sub-pixel P in the 2N columns of sub-pixels P that receives the negative polarity data signal.

[0066] Taking K=2, k=1, M=6, N=3 as an example, Figure 13 It shows 6 adjacent columns of sub-pixels P (e.g.) Figure 13 The diagram shows the structure of sub-pixels P1 through P6 within the dashed box. The voltage polarities of the data signals received by adjacent sub-pixels P are opposite. Odd-numbered sub-pixels P receive positive voltage signals (represented by +), while even-numbered sub-pixels P receive negative voltage signals (represented by -). It is understandable that when the display panel 100 is a liquid crystal display panel, the data signals provided by the signal source lines S of adjacent display frames are usually opposite. This would also reverse the direction of the electric field that controls the rotation of the liquid crystal. Setting the voltage polarities of the data signals received by adjacent sub-pixels P with opposite polarities can prevent liquid crystal polarization and problems such as image retention.

[0067] Furthermore, the first multiplexing unit 11 is electrically connected to the sub-pixels P receiving positive data signals in the first to sixth columns of sub-pixels P, i.e., the first multiplexing unit 11 is electrically connected to the odd-numbered columns of sub-pixels P in the first to sixth columns of sub-pixels P; while the second multiplexing unit 12 is electrically connected to the sub-pixels P receiving negative data signals in the first to sixth columns of sub-pixels P, i.e., the second multiplexing unit 12 is electrically connected to the even-numbered columns of sub-pixels P in the first to sixth columns of sub-pixels P. In this way, the six adjacent columns of sub-pixels P are electrically connected to the two nearest multiplexing units 10, saving the wiring length of the multiplexing unit 10 and the data line, thereby saving wiring space and facilitating the narrow bezel design of the display panel 100. At the same time, it reduces the number of crossovers between wirings and reduces the difficulty of bridge technology due to wiring crossovers.

[0068] Optional, Figure 14 This is a partial structural diagram of another display panel provided in an embodiment of the present invention, as shown below. Figure 14 As shown, the array of multiple sub-pixels P includes a first sub-pixel column P_1, a second sub-pixel column P_2, and a third sub-pixel column P_3; ​​the first sub-pixel column P_1 includes the first sub-pixel P1, the second sub-pixel column P_2 includes the second sub-pixel P2, and the third sub-pixel column P_3 includes the third sub-pixel P3. The emission colors of the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 are all different. M timing control lines CKH include a first type of timing control line CKH_1, a second type of timing control line CKH_2, and a third type of timing control line CKH_3. The output terminal of the selector switch T connected to the first type of timing control line CKH_1 is electrically connected to the first sub-pixel column P_1, the output terminal of the selector switch T connected to the second type of timing control line CKH_2 is electrically connected to the second sub-pixel column P_2, and the output terminal of the selector switch T connected to the third type of timing control line CKH_3 is electrically connected to the third sub-pixel column P_3.

[0069] In this embodiment, the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 can be sub-pixels of any emitting color, and the present invention does not impose specific limitations on this. For example, the first sub-pixel P1 is a red sub-pixel, the second sub-pixel P2 is a green sub-pixel, and the third sub-pixel P3 is a blue sub-pixel.

[0070] Taking K=2, k=1, M=6, N=3 as an example, Figure 14 The diagram illustrates the structure of multiple sub-pixels P arranged in an array. The emission color of each column of sub-pixels P can be the same or different; this embodiment of the invention does not impose a specific limitation on this. Figure 14 This example only illustrates that sub-pixels P in the same column have the same emitted color, but is not limited to this. See also... Figure 14As shown, it can be understood that the same type of timing control line CKH refers to timing control lines CKH with the same timing control signal. That is, the first type of timing control line CKH_1 may include the first timing control line CKH1 and the fourth timing control line CKH4, the second type of timing control line CKH_2 may include the second timing control line CKH2 and the fifth timing control line CKH5, and the third type of timing control line CKH_3 may include the third timing control line CKH3 and the sixth timing control line CKH6.

[0071] Continue to refer to Figure 14 As shown, the output of the selector switch T, controlled by the first type of timing control line CKH_1, is electrically connected to the first sub-pixel column P_1. That is, the first sub-pixel column P_1 can receive data signals for charging when the corresponding selector switch T is turned on by the first timing control line CKH1 or the fourth timing control line CKH4. The output of the selector switch T, controlled by the second type of timing control line CKH_2, is electrically connected to the second sub-pixel column P_2. That is, the second sub-pixel column P_2 can receive data signals for charging when the corresponding selector switch T is turned on by the second timing control line CKH2 or the fifth timing control line CKH5. The output of the selector switch T, controlled by the third type of timing control line CKH_3, is electrically connected to the third sub-pixel column P_3. That is, the third sub-pixel column P_3 can receive data signals for charging when the corresponding selector switch T is turned on by the third timing control line CKH3 and the sixth timing control line CKH6. The specific electrical connection methods between the gating switch T, which is electrically connected to the same column of sub-pixels P via data lines, and the timing control lines CKH of the same type include, but are not limited to, the following: Figure 14 As shown, the settings can be configured according to actual needs. Thus, by electrically connecting the same type of timing control line CKH to sub-pixel columns with the same emission color, the uniformity of charging of sub-pixels P with the same emission color can be ensured, thereby guaranteeing display uniformity.

[0072] Continue to refer to Figure 14 As shown, optionally, for the same type of timing control line CKH, when each timing control line CKH controls the gating switch T to be turned on, the data signal transmitted by the corresponding signal source line S includes positive polarity data signal and negative polarity data signal, and the number of positive polarity data signals and the number of negative polarity data signals are the same.

[0073] Specifically, since the effective timing control signals Ckh transmitted by the same type of timing control line CKH are the same, and the emission colors of the sub-pixels P electrically connected to the corresponding control gating switches T are the same, by setting each timing control line CKH in the same type of timing control line CKH to control the gating switch T to be turned on, the data signals transmitted by the corresponding signal source line S all include positive and negative polarity data signals, and the number of positive and negative polarity data signals is the same. This ensures that the effective timing control signals Ckh transmitted by each timing control line CKH in the same type of timing control line CKH are completely affected by the coupling of the data signals transmitted by the signal source line S. Furthermore, when the number of positive and negative polarity data signals is the same, the coupling effects of data signals with opposite voltage polarities on the timing control signals Ckh can cancel each other out. This ensures that the effective timing control signals Ckh transmitted by the timing control lines CKH can be quickly maintained at a stable effective level (e.g., high level), ensuring that each sub-pixel P in each sub-pixel column with the same emission color is charged evenly, thereby improving the display effect of the display panel 100.

[0074] Based on the same inventive concept, embodiments of the present invention also provide a display device. Figure 15 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention, such as... Figure 15 As shown, the display device 200 includes a display panel 100 provided in any embodiment of the present invention. The display device 200 provided in the embodiments of the present invention can be a mobile phone or any electronic product with display function, including but not limited to the following categories: television, laptop, desktop monitor, tablet computer, digital camera, smart bracelet, smart glasses, vehicle display, medical equipment, industrial control equipment, touch interactive terminal, etc. The embodiments of the present invention do not make any special limitations on these.

[0075] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, combinations, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, the scope of which is determined by the scope of the appended claims.

Claims

1. A display panel, characterized in that, It includes a display area and a non-display area located on one side of the display area. The display area includes multiple sub-pixels arranged in an array, and the non-display area includes multiple multiplexing units, multiple signal source lines, and M timing control lines, where M is an integer greater than 1. The multiplexing unit includes N gating switches. Within the same multiplexing unit, the input terminals of multiple gating switches are electrically connected to the same signal source line, the output terminal of each gating switch is electrically connected to a column of sub-pixels, and the control terminals of the multiple gating switches are electrically connected to different timing control lines. K and N are both integers greater than 1; During the display phase, N timing control lines electrically connected to the same multiplexing unit are used to output valid timing control signals in a time-division manner to control the N gating switches of the multiplexing unit to be turned on in a time-division manner; there is at least one timing control line electrically connected to at least two multiplexing units, and when the gating switch controlled by it is turned on, the voltage polarity of the data signals transmitted by at least two signal source lines electrically connected to the at least two gating switches controlled by it is opposite.

2. The display panel according to claim 1, characterized in that, The timing control signal of the i-th timing control line is the same as that of any i+kN-th timing control line, where 1≤i≤N, 1≤k<K, and k is an integer.

3. The display panel according to claim 2, characterized in that, The voltage polarities of the data signals transmitted on the two signal source lines electrically connected to any two adjacent multiplexing units are opposite. There are two adjacent multiplexing units, and among the N timing control lines electrically connected to one of the multiplexing units, at least one timing control line is electrically connected to the other multiplexing unit.

4. The display panel according to claim 3, characterized in that, The N gating switches of the multiplexing unit are divided into the first gating switch to the Nth gating switch; For any one of the multiplexing units, the control terminal of the i-th gating switch is electrically connected to the i-th timing control line, or the control terminal of the i-th gating switch is electrically connected to the i+kN-th timing control line.

5. The display panel according to claim 4, characterized in that, The multiple multiplexing units are divided into multiple multiplexing unit groups, and each multiplexing unit group includes at least two adjacent multiplexing units; Within the same group of multiplexing units, the control terminal of the i-th selection switch of each multiplexing unit is electrically connected to the i-th timing control line, or the control terminal of the i-th selection switch of each multiplexing unit is electrically connected to the i+kN-th timing control line.

6. The display panel according to claim 5, characterized in that, The number of multiplexing units in each multiplexing unit group is the same, and for any two adjacent multiplexing unit groups, the control terminal of the i-th selection switch of the multiplexing unit in one multiplexing unit group is electrically connected to the i-th timing control line, and the control terminal of the i-th selection switch of the multiplexing unit in the other multiplexing unit group is electrically connected to the i+kN-th timing control line.

7. The display panel according to claim 4, characterized in that, The multiple multiplexing units are divided into two multiplexing unit groups, namely the first multiplexing unit group and the second multiplexing unit group; Within the first multiplexing unit group, the control terminals of the i-th selection switches of the odd-numbered multiplexing units are all electrically connected to the i-th timing control line, and the control terminals of the i-th selection switches of the even-numbered multiplexing units are all electrically connected to the i+kN-th timing control line. In the second multiplexing unit group, the control terminals of the i-th selection switches of the even-numbered multiplexing units are all electrically connected to the i-th timing control line, and the control terminals of the i-th selection switches of the odd-numbered multiplexing units are all electrically connected to the i+kN-th timing control line.

8. The display panel according to claim 5 or 7, characterized in that, Within each of the multiplexing unit groups, the number of multiplexing units is an even number.

9. The display panel according to claim 1, characterized in that, For any of the timing control lines, when the gating switch controlled by it is turned on, the number of positive polarity data signals transmitted by the corresponding signal source line is the same as the number of negative polarity data signals.

10. The display panel according to claim 1, characterized in that, Each of the timing control lines controls the same number of the selected switches to be turned on.

11. The display panel according to claim 1, characterized in that, The gating switch includes an N-channel thin-film transistor.

12. The display panel according to claim 1, characterized in that, The array of sub-pixels includes 2N adjacent columns of sub-pixels, and the voltage polarities of the data signals received by two adjacent columns of sub-pixels are opposite. The plurality of multiplexing units include an adjacent first multiplexing unit and a second multiplexing unit. The first multiplexing unit is electrically connected to the sub-pixel in the 2N columns that receives a positive polarity data signal, and the second multiplexing unit is electrically connected to the sub-pixel in the 2N columns that receives a negative polarity data signal.

13. The display panel according to claim 1, characterized in that, The array of sub-pixels includes a first sub-pixel column, a second sub-pixel column, and a third sub-pixel column; the first sub-pixel column includes the first sub-pixel, the second sub-pixel column includes the second sub-pixel, and the third sub-pixel column includes the third sub-pixel, wherein the first sub-pixel, the second sub-pixel, and the third sub-pixel emit different colors; The M timing control lines include a first type of timing control line, a second type of timing control line, and a third type of timing control line. The output terminal of the gating switch electrically connected to the first type of timing control line is electrically connected to the first sub-pixel column. The output terminal of the gating switch electrically connected to the second type of timing control line is electrically connected to the second sub-pixel column. The output terminal of the gating switch electrically connected to the third type of timing control line is electrically connected to the third sub-pixel column.

14. The display panel according to claim 13, characterized in that, For the same type of timing control line, when each of the timing control lines controls the gating switch to be turned on, the data signal transmitted by the corresponding signal source line includes a positive data signal and a negative data signal, and the number of positive data signals and the number of negative data signals are the same.

15. The display panel according to claim 1, characterized in that, N=2 or N=3 or N=6.

16. A display device, characterized in that, Includes the display panel as described in any one of claims 1-15.

Images