Semiconductor pattern forming process

Abstract

The application provides a semiconductor pattern forming process, comprising the following steps: S0, providing a semiconductor structure from bottom to top of a silicon oxide layer, a silicon nitride layer, a carbon coating layer and a silicon anti-reflection layer; S1, etching the silicon anti-reflection layer, the carbon coating layer and the silicon nitride layer in sequence with the same pattern until the silicon oxide layer is exposed to form a silicon nitride pattern; S2, filling the gap of the silicon nitride pattern with silicon oxide; and S3, removing the silicon nitride pattern to form a silicon oxide pattern, wherein the silicon oxide pattern is formed as large and small islands by filling the silicon oxide and removing the silicon nitride pattern, and the large and small islands formed by the polycrystalline silicon ion implanted in the prior art are prone to top rounding, and the application can prevent the problem of top rounding of the large and small islands.

Description

Technical Field

[0001] This invention relates to the field of integrated circuits, and more particularly to a semiconductor patterning process. Background Technology

[0002] With the continuous miniaturization of chip size, after entering the FinFET technology era, the exposure limit of the 193 immersion lithography machine cannot meet the design requirements for small-sized, short-interval head-to-head pattern exposure. Therefore, the zeroth layer metal channel shearing (MOC) technology, which changes the etching characteristics of the medium by ion implantation, was introduced.

[0003] Traditional MOC (Modular Encapsulation) technology first etches a carbon coating (Spin On Carbon, SOC) until the polysilicon surface is exposed to form channels of varying lengths. Then, ion implantation is performed through the channels defined by the SOC to alter the etching characteristics of the polysilicon. The SOC and the un-implanted polysilicon are then removed, leaving behind islands of varying sizes. However, the resulting islands often exhibit rounded corners due to the influence of the type and dosage of implanted ions and wet cleaning processes, thus increasing the difficulty of controlling subsequent zero-layer metal channel processes.

[0004] Therefore, it is necessary to develop new semiconductor patterning processes to address some of the problems mentioned above in existing technologies. Summary of the Invention

[0005] The purpose of this invention is to provide a semiconductor patterning process so that the tops of large and small islands do not have rounded corners.

[0006] To achieve the above objectives, the semiconductor patterning process of the present invention includes the following steps:

[0007] S0: Provides a semiconductor structure consisting of a silicon oxide layer, a silicon nitride layer, a carbon coating layer, and a silicon anti-reflection layer from bottom to top;

[0008] S1: Etch the silicon antireflective layer, the carbon coating, and the silicon nitride layer sequentially with the same pattern until the silicon oxide layer is exposed to form a silicon nitride pattern;

[0009] S2: Fill the gaps in the silicon nitride pattern with silicon oxide;

[0010] S3: Remove the silicon nitride pattern to form a silicon oxide pattern.

[0011] The beneficial effects of the semiconductor process described in this invention are as follows: S0: Provides a semiconductor structure consisting of a silicon oxide layer, a silicon nitride layer, a carbon coating layer, and a silicon anti-reflection layer from bottom to top; S1: Etches the silicon anti-reflection layer, the carbon coating layer, and the silicon nitride layer sequentially with the same pattern until the silicon oxide layer is exposed to form a silicon nitride pattern; S2: Fills the gaps between the silicon nitride patterns with silicon oxide; S3: Removes the silicon nitride pattern to form a silicon oxide pattern. This invention uses the filling of silicon oxide and the removal of the silicon nitride pattern to form a silicon oxide pattern as large and small islands. In the prior art, the large and small islands formed by ion implantation of polycrystalline silicon are prone to having rounded corners at the top. This invention can reduce the surface roughness of the large and small islands and prevent the problem of rounded corners at the top of the large and small islands.

[0012] Optionally, the step of sequentially etching the silicon antireflective layer, the carbon coating, and the silicon nitride layer with the same pattern until the silicon oxide layer is exposed to form the silicon nitride pattern includes:

[0013] Photoresist is coated and patterned on the top surface of the silicon antireflective layer, and the silicon antireflective layer and the carbon coating are etched sequentially using the patterned photoresist as a mask.

[0014] Optionally, the step of sequentially etching the silicon antireflective layer, the carbon coating, and the silicon nitride layer with the same pattern until the silicon oxide layer is exposed to form the silicon nitride pattern further includes:

[0015] The silicon nitride layer not covered by the remaining carbon coating is etched until the silicon oxide layer is exposed to form a silicon nitride pattern.

[0016] Optionally, the step of filling the gaps in the silicon nitride pattern with silicon oxide further includes: removing the remaining carbon coating.

[0017] Optionally, filling the gaps in the silicon nitride pattern with silicon oxide includes:

[0018] Silicon oxide is deposited using a flowable chemical vapor deposition method to completely fill the gaps in the silicon nitride pattern and cover the top of the silicon nitride pattern.

[0019] Optionally, filling the gaps in the silicon nitride pattern with silicon oxide further includes:

[0020] Polish the silicon oxide until the top surface of the silicon nitride pattern is exposed.

[0021] Optionally, the thickness of the photoresist can be controlled to be 600 Å-1000 Å.

[0022] Optionally, the thickness of the deposited silicon oxide can be controlled to be 900 Å-1100 Å. Attached Figure Description

[0023] Figure 1 This is a schematic flowchart of a semiconductor patterning process in some embodiments of the present invention;

[0024] Figure 2 These are schematic diagrams of the semiconductor structure in some embodiments of the present invention;

[0025] Figure 3 This is a schematic diagram of the structure after photoresist coating in some embodiments of the present invention;

[0026] Figure 4 This is a schematic diagram of the structure forming the photoresist structure in some embodiments of the present invention;

[0027] Figure 5 To Figure 4 A schematic diagram of the structure after etching the silicon antireflective layer;

[0028] Figure 6 This is a schematic diagram of the structure after etching the carbon coating;

[0029] Figure 7 This is a schematic diagram of the structure after etching the silicon nitride layer;

[0030] Figure 8 This is a schematic diagram of the structure obtained after silicon oxide deposition;

[0031] Figure 9 This is a schematic diagram of the structure obtained after grinding the filler layer;

[0032] Figure 10 This is a schematic diagram of the structure obtained after removing the silicon nitride pattern. Detailed Implementation

[0033] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. Unless otherwise defined, the technical or scientific terms used herein should have the ordinary meaning understood by those skilled in the art. The terms "comprising" and similar expressions used herein mean that the element or object preceding the word covers the element or object listed after the word and its equivalents, but does not exclude other elements or objects.

[0034] Figure 1 This is a schematic flowchart of a semiconductor patterning process in some embodiments of the present invention.

[0035] In response to the problems existing in the current technology, referring to Figure 1This invention provides a semiconductor patterning process, including the following steps:

[0036] S0: Provides a semiconductor structure consisting of a silicon oxide layer, a silicon nitride layer, a carbon coating layer, and a silicon anti-reflection layer from bottom to top;

[0037] S1: Etch the silicon antireflective layer, the carbon coating, and the silicon nitride layer sequentially with the same pattern until the silicon oxide layer is exposed to form a silicon nitride pattern;

[0038] S2: Fill the gaps in the silicon nitride pattern with silicon oxide;

[0039] S3: Remove the silicon nitride pattern to form a silicon oxide pattern.

[0040] Figure 2 This is a schematic diagram of the semiconductor structure in some embodiments of the present invention.

[0041] In some embodiments, reference is made to Figure 2 A semiconductor structure is provided, consisting of a silicon oxide layer 12, a silicon nitride layer 21, a carbon coating layer 32, and a silicon anti-reflection layer 42 from bottom to top.

[0042] In some embodiments, the silicon oxide layer is made of silicon dioxide.

[0043] In some embodiments, the material of the carbon coating (Spin-On Carbon, SOC) includes a carbon-containing polymer.

[0044] In some embodiments, the thickness of the carbon coating is 1600 Å to 2400 Å.

[0045] In some embodiments, the material of the silicon anti-reflection coating (SiARC) includes organosiloxanes.

[0046] In some embodiments, the thickness of the silicon antireflective coating is 300 Å to 500 Å.

[0047] In some embodiments, the step of sequentially etching the silicon antireflective layer, the carbon coating, and the silicon nitride layer in the same pattern until the silicon oxide layer is exposed to form the silicon nitride pattern includes:

[0048] Photoresist is coated and patterned on the top surface of the silicon antireflective layer, and the silicon antireflective layer and the carbon coating are etched sequentially using the patterned photoresist as a mask.

[0049] Figure 3 This is a schematic diagram of the structure after photoresist coating in some embodiments of the present invention. Figure 4 This is a schematic diagram of the structure forming the photoresist structure in some embodiments of the present invention.

[0050] In some embodiments, reference is made to Figure 3 and Figure 4 Photoresist 52 is coated on the top surface of the silicon antireflective layer 42, and then the photoresist 52 is exposed and developed to form a photoresist structure 521.

[0051] In some embodiments, reference is made to Figure 3 The thickness of the photoresist 52 is controlled to be 600A-1000A.

[0052] Figure 5 To Figure 4 The diagram shows the structure after etching the silicon antireflective layer.

[0053] In some embodiments, reference is made to Figure 4 and Figure 5 Using the photoresist structure 521 as a mask, the silicon antireflective layer 42 not covered by the photoresist structure 521 is etched in a capacitively coupled plasma reactor (CCP) to form a silicon antireflective layer pattern 421 on the silicon antireflective layer 42.

[0054] Figure 6 This is a schematic diagram of the structure after etching the carbon coating.

[0055] In some embodiments, reference is made to Figure 6 The carbon coating 32 not covered by the silicon antireflective layer pattern 421 is etched to form the carbon coating pattern 321 on the carbon coating 32.

[0056] In some embodiments, the photoresist structure is consumed during the etching of the silicon antireflective layer and the carbon coating.

[0057] In some embodiments, the step of sequentially etching the silicon antireflective layer, the carbon coating, and the silicon nitride layer in the same pattern until the silicon oxide layer is exposed to form the silicon nitride pattern further includes:

[0058] The silicon nitride layer not covered by the remaining carbon coating is etched until the silicon oxide layer is exposed to form a silicon nitride pattern.

[0059] Figure 7 This is a schematic diagram of the structure after etching the silicon nitride layer.

[0060] In some embodiments, reference is made to Figure 6 and Figure 7 The silicon nitride layer 21 not covered by the carbon coating pattern 321 is etched to form the silicon nitride pattern 211.

[0061] In some embodiments, the silicon antireflective layer pattern is consumed during the etching of the carbon coating and the silicon nitride layer.

[0062] In some embodiments, the step of filling the gaps in the silicon nitride pattern with silicon oxide further includes removing any remaining carbon coating.

[0063] In some embodiments, filling the gaps in the silicon nitride pattern with silicon oxide includes:

[0064] Silicon oxide is deposited using a flowable chemical vapor deposition method to completely fill the gaps in the silicon nitride pattern and cover the top of the silicon nitride pattern.

[0065] Figure 8 This is a schematic diagram of the structure obtained after silicon oxide deposition.

[0066] In some embodiments, reference is made to Figure 7 and Figure 8 The carbon coating pattern 321 is removed by in-situ ashing process, and then silicon oxide is deposited by flowable chemical vapor deposition (FCVD) to completely fill the gaps of the silicon nitride pattern 211 and cover the top of the silicon nitride pattern 211 to form a filling layer 111.

[0067] In some embodiments, the thickness of the deposited silicon oxide is controlled to be 900 Å-1100 Å.

[0068] In some embodiments, reference is made to Figure 8 The thickness of the filling layer 111 is a first thickness h1, and the first thickness is controlled to be 900A-1100A, so as to reserve enough thickness for grinding the deposited silicon oxide.

[0069] In some embodiments, the first thickness is 1000 Å.

[0070] In some embodiments, filling the gaps in the silicon nitride pattern with silicon oxide further includes:

[0071] Polish the silicon oxide until the top surface of the silicon nitride pattern is exposed.

[0072] In some embodiments, the filler layer is polished using chemical mechanical polishing (CMP) to expose the top surface of the silicon nitride pattern.

[0073] Figure 9 This is a schematic diagram of the structure obtained after grinding the filler layer. Figure 10 This is a schematic diagram of the structure obtained after removing the silicon nitride pattern.

[0074] In some embodiments, reference is made to Figure 9 and Figure 10 The semiconductor structure is cleaned using a wet cleaning process to remove the silicon nitride pattern 211, so as to form a silicon oxide pattern 1111 on the top surface of the silicon oxide layer 12.

[0075] In some embodiments, the cleaning solution of the wet process includes phosphoric acid.

[0076] The semiconductor patterning process described in this invention can form silicon oxide patterns of different sizes according to different needs, and is not specifically limited herein.

[0077] While embodiments of the present invention have been described in detail above, it will be apparent to those skilled in the art that various modifications and variations can be made to these embodiments. However, it should be understood that such modifications and variations fall within the scope and spirit of the invention as set forth in the claims. Furthermore, the invention described herein may have other embodiments and can be implemented or carried out in various ways.

Claims

1. A semiconductor patterning process, comprising the following steps: S0: Provides a semiconductor structure consisting of a silicon oxide layer, a silicon nitride layer, a carbon coating layer, and a silicon anti-reflection layer from bottom to top; S1: The silicon antireflective layer, the carbon coating, and the silicon nitride layer are etched sequentially with the same pattern until the silicon oxide layer is exposed to form a silicon nitride pattern. This includes: coating and patterning photoresist on the top surface of the silicon antireflective layer; using the patterned photoresist as a mask to etch the silicon antireflective layer not covered by the photoresist to form a silicon antireflective layer pattern; etching the carbon coating not covered by the silicon antireflective layer pattern to form a carbon coating pattern, wherein the photoresist is consumed during the etching of the silicon antireflective layer and the carbon coating; and etching the silicon nitride layer not covered by the remaining carbon coating until the silicon oxide layer is exposed to form a silicon nitride pattern, wherein the silicon antireflective layer pattern is consumed during the etching of the carbon coating and the silicon nitride layer. S2: Fill the gaps in the silicon nitride pattern with silicon oxide; S3: Remove the silicon nitride pattern to form a silicon oxide pattern.

2. The semiconductor patterning process according to claim 1, characterized in that, The step of filling the gaps in the silicon nitride pattern with silicon oxide further includes: removing the remaining carbon coating.

3. The semiconductor patterning process according to claim 1 or 2, characterized in that, The process of filling the gaps in the silicon nitride pattern with silicon oxide includes: Silicon oxide is deposited using a flowable chemical vapor deposition method to completely fill the gaps in the silicon nitride pattern and cover the top of the silicon nitride pattern.

4. The semiconductor patterning process according to claim 3, characterized in that, The process of filling the gaps in the silicon nitride pattern with silicon oxide further includes: Polish the silicon oxide until the top surface of the silicon nitride pattern is exposed.

5. The semiconductor patterning process according to claim 1, characterized in that, The thickness of the photoresist is controlled to be 600 Å-1000 Å.

6. The semiconductor patterning process according to claim 3, characterized in that, The thickness of the deposited silicon oxide is controlled to be 900 Å-1100 Å.

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