A semiconductor package structure and a method of manufacturing the same

Abstract

The application provides a semiconductor packaging structure and a preparation method thereof, and the semiconductor packaging structure comprises a packaging substrate, a first chip welding area and a second chip welding area are defined on the packaging substrate, the first chip welding area and the second chip welding area are adjacent and a first gap exists between the first chip welding area and the second chip welding area, at least one dummy pad is arranged on the packaging substrate, the dummy pad crosses the first gap and covers part of the surface of the first chip welding area and the second chip welding area, a first chip and a second chip are arranged on the packaging substrate, the first chip is provided with a first dummy bump, the second chip is provided with a second dummy bump, the first dummy bump and the second dummy bump are bonded to the dummy pad, and a filling material layer is arranged in the gap between the packaging substrate and the first chip and the second chip. The semiconductor packaging structure and the preparation method thereof can solve the problem that the underfill material cracks due to stress concentration in the existing packaging structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor packaging, and in particular to a semiconductor packaging structure and its fabrication method. Background Technology

[0002] Currently, advanced packaging technologies are making the leads and solder joints more and more dense per unit area, and the size of 2.5D and fan-out packages is getting larger and larger. The reliability of the package is facing serious challenges because the CTE (coefficient of thermal expansion) mismatch between the materials will cause warpage during thermal cycling.

[0003] Because the overall packaging structure cannot directly release the stress caused by warping, such as Figure 1 As shown, stress will be concentrated between the first chip 21 and the second chip 22, which will cause problems such as cracks in the under-fill material layer 130 (which will cause moisture to enter the package and cause corrosion), delamination, and failure of electromagnetic shielding (EMI). Furthermore, the cracks will extend downwards and damage the package substrate 40 (which has through holes, redistribution layers and other structures) bonded to the chip, affecting the electrical connection effect. Summary of the Invention

[0004] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a semiconductor packaging structure and its preparation method, which solves the problem of cracks in the bottom filler caused by stress concentration in existing packaging structures.

[0005] To achieve the above and other related objectives, the present invention provides a semiconductor packaging structure, the semiconductor packaging structure comprising:

[0006] The packaging substrate includes a first surface and a second surface relative to the first surface. The first surface defines a first chip bonding area and a second chip bonding area. The first chip bonding area and the second chip bonding area are adjacent to each other and have a first gap. The first surface is also provided with at least one dummy pad. The dummy pad spans the first gap and covers a portion of the surface of the first chip bonding area and the second chip bonding area.

[0007] A first chip and a second chip, wherein at least one first dummy bump is provided at a first position on the active surface of the first chip, and at least one second dummy bump is provided at a second position on the active surface of the second chip; wherein, the first position is a position on the active surface of the first chip corresponding to the portion covered by the dummy pad in the soldering area of ​​the first chip, and the second position is a position on the active surface of the second chip corresponding to the portion covered by the dummy pad in the soldering area of ​​the second chip, and the first dummy bump and the second dummy bump are bonded to the dummy pad;

[0008] A filler material layer is provided to fill the gap between the packaging substrate and the first chip and the second chip.

[0009] Optionally, the semiconductor packaging structure further includes a third chip; the first surface further defines a third chip bonding area;

[0010] The third chip soldering area is adjacent to the second chip soldering area and there is a second gap;

[0011] At least one of the dummy pads also spans the second second gap and covers a portion of the surface of the second chip soldering area and the third chip soldering area;

[0012] At least one third dummy bump is provided at the third position of the active surface of the third chip. The third position is the position of the active surface of the third chip that corresponds to the portion of the dummy pad covered by the soldering area of ​​the third chip. The second dummy bump and the third dummy bump are bonded to the dummy pad.

[0013] Optionally, the first chip soldering area, the second chip soldering area, and the third chip soldering area are adjacent to each other;

[0014] One of the dummy pads simultaneously covers a portion of the surfaces of the first chip soldering area, the second chip soldering area, and the third chip soldering area;

[0015] The first dummy bump, the second dummy bump, and the third dummy bump are bonded to the dummy pad.

[0016] Optionally, the semiconductor packaging structure further includes:

[0017] A molding compound is formed on the first surface and covers each chip.

[0018] Optionally, the packaging substrate includes an adapter plate with through holes, and the dummy pads are insulated from the through holes.

[0019] Optionally, the packaging substrate includes an adapter plate, the adapter plate having through holes and a redistribution layer, and the dummy pads being insulated from the through holes.

[0020] The present invention also provides a method for fabricating a semiconductor packaging structure, the method comprising:

[0021] An intermediate structure is provided, the intermediate structure including a first temporary carrier board and a packaging substrate located on the upper surface of the first temporary carrier board. The packaging substrate includes a first surface and a second surface relative to the first surface. The first surface defines a first chip bonding area and a second chip bonding area. The first chip bonding area and the second chip bonding area are adjacent to each other and have a first gap. The first surface is also provided with at least one dummy pad. The dummy pad spans the first gap and covers a portion of the surface of the first chip bonding area and a portion of the surface of the second chip bonding area.

[0022] A first chip and a second chip are provided. At least one first dummy bump is provided at a first position on the active surface of the first chip, and at least one second dummy bump is provided at a second position on the active surface of the second chip. The first position is the position on the active surface of the first chip that corresponds to the portion of the dummy pad covered by the dummy pad in the soldering area of ​​the first chip, and the second position is the position on the active surface of the second chip that corresponds to the portion of the dummy pad covered by the dummy pad in the soldering area of ​​the second chip.

[0023] The first chip is bonded to the packaging substrate in the first chip bonding area, the second chip is bonded to the packaging substrate in the second chip bonding area, and the dummy bump is bonded to the dummy pad.

[0024] A filler material layer is filled into the gaps where the first chip and the second chip are bonded to the packaging substrate.

[0025] Optionally, after filling the filler material layer, the preparation method further includes:

[0026] A molding compound is formed on the first surface, the molding compound encapsulating the first chip and the second chip therein;

[0027] Remove the first temporary carrier board.

[0028] Optionally, the method for preparing the intermediate structure includes:

[0029] A substrate is provided, wherein a blind hole is formed therein, and a metal pillar is filled therein;

[0030] A solder pad and a dummy pad are formed on the upper surface of the substrate, wherein the solder pad is connected to the metal pillar and the dummy pad is electrically isolated from the solder pad;

[0031] A second temporary carrier plate is provided to fix the upper surface of the substrate to the second temporary carrier plate;

[0032] Thin the lower surface of the substrate until the metal pillars are exposed;

[0033] Conductive bumps are formed on the lower surface of the substrate, wherein the conductive bumps are connected to the metal pillars;

[0034] Provide the first temporary carrier plate and fix the lower surface of the substrate to the first temporary carrier plate;

[0035] Remove the second temporary carrier board.

[0036] Optionally, after thinning the lower surface of the substrate and before forming conductive bumps on the lower surface of the substrate, the method for preparing the intermediate structure further includes the step of forming a redistribution layer on the lower surface of the substrate, wherein the redistribution layer is connected to the conductive bumps.

[0037] As described above, the semiconductor packaging structure and its fabrication method of the present invention respectively provide dummy bumps in two adjacent chips and corresponding dummy pads on the packaging substrate. The dummy bumps are insulated from the circuits inside the chips, and the dummy pads are insulated from the circuits inside the packaging substrate. When the chips are bonded to the packaging substrate, the dummy pads are also bonded to the dummy bumps respectively, forming a structural reinforcement bridge spanning under the two chips. The structural reinforcement bridge connects the two adjacent chips, which can effectively prevent the bottom filler layer from cracking at the solder joints due to shrinkage and expansion, and further prevent problems such as delamination, electromagnetic shielding failure, and circuit interruption in the packaging structure. Attached Figure Description

[0038] Figure 1 The diagram shows cracks in the filler material layer between adjacent chips caused by warping in a semiconductor package structure.

[0039] Figure 2 The diagram shows a semiconductor package structure where the connection between the chip's microbumps and the solder pads breaks due to the expansion of the filler material layer.

[0040] Figure 3 This diagram illustrates how bonding dummy bumps and dummy pads prevents cracking in the filler layer.

[0041] Figure 4 This diagram illustrates how bonding dummy bumps to dummy pads prevents flip-chip solder joint breakage.

[0042] Figure 5 The flowchart shown is a method for preparing the semiconductor packaging structure described in this invention.

[0043] Figure 6 The image shown is a top view of the semiconductor packaging structure described in this invention.

[0044] Figure 7 The diagram shown is a structural schematic of the intermediate structure described in this invention.

[0045] Figure 8 The diagram shown is a schematic representation of the semiconductor packaging structure described in this invention.

[0046] Figure 9 Displayed as Figure 8 A partial structural diagram of a semiconductor packaging structure.

[0047] Figure 10 The flowchart shown is a method for preparing the intermediate structure described in this invention.

[0048] Figure 11 The diagram shown is a schematic representation of the structure of a substrate with blind holes as described in this invention.

[0049] Figure 12 The diagram shown is a schematic representation of the structure after the formation of the dummy pads as described in this invention.

[0050] Figure 13 The diagram shows the structure of the second temporary carrier plate of the present invention.

[0051] Figure 14 The diagram shows the structure of the substrate after thinning according to the present invention.

[0052] Figure 15 The diagram shown is a schematic representation of the structure after the conductive bumps are formed according to the present invention.

[0053] Figure 16 The diagram shows the structure of the first temporary carrier plate of the present invention.

[0054] Figure 17 The diagram shown is a schematic representation of the structure after removing the second temporary carrier plate as described in this invention.

[0055] Figure 18 The diagram shows the structure of the chip and the packaging substrate after bonding according to the present invention.

[0056] Figure 19 The diagram shown is a schematic representation of the structure after the filling material layer is formed according to the present invention.

[0057] Figure 20 The diagram shown is a structural schematic of the intermediate structure described in this invention.

[0058] Figure 21 The diagram shown is a schematic representation of the semiconductor packaging structure described in this invention.

[0059] Component labeling explanation

[0060] 10 Semiconductor Packaging Structure

[0061] 100 substrate

[0062] 101 Blind Hole

[0063] 102 Welding pads

[0064] 103 Dummy pads

[0065] 104 Conductive bumps

[0066] 110 Second Temporary Carrier

[0067] 120 First Temporary Carrier

[0068] 130 Filler Material Layer

[0069] 140 sealing layer

[0070] 121-128 First chip soldering area to eighth chip soldering area

[0071] 21-24 First Chip to Fourth Chip

[0072] 210 microbumps

[0073] 211 First Dummy Bump

[0074] 221 Second Dummy Bump

[0075] 30 Intermediate Structure

[0076] 40 Packaging substrate Detailed Implementation

[0077] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0078] Please see Figures 1 to 21 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0079] Example 1

[0080] This embodiment provides a semiconductor packaging structure 10, such as Figure 9 As shown, the semiconductor packaging structure 10 includes: a packaging substrate 40, a first chip 21, a second chip 22, and a filler material layer 130. It should be noted that, as... Figure 6 and8 As shown, the packaging substrate 40 can encapsulate N chips (N is greater than or equal to 2), and is not limited to encapsulating two chips. Correspondingly, the packaging substrate 40 is divided into N chip bonding areas that are bonded to the chips. These chip bonding areas are adjacent to each other but do not contact each other. As an example, Figure 6 The packaging substrate 40 includes first chip bonding regions 121 to eighth chip bonding regions 128. Figure 7 The display shows four chip soldering areas; Figure 8 The two adjacent chips within the dashed box are defined as chip 210 and chip 220. Figure 9 The middle structure is shown as a partial structural diagram of a semiconductor package structure 10 having a first chip 210 and a second chip 220. The following is based on... Figure 9 The semiconductor packaging structure 10 described in this embodiment will be introduced.

[0081] like Figure 9 As shown, the surface on which the packaging substrate 40 is bonded to the chip is defined as the first surface, and the opposite surface is defined as the second surface. The packaging substrate 40 has two adjacent but non-contacting regions, namely the first chip bonding region 121 (the region where the first chip 21 is bonded to the packaging substrate 40) and the second chip bonding region 122 (the region where the second chip 22 is bonded to the packaging substrate 40). The first surface is provided with a plurality of solder pads 102. One side of these solder pads 102 is connected to the connection lines of the packaging substrate 40, and the other side is bonded to the microbumps 210 located on the active surface of the chip (the side of the chip with microbumps 210 is defined as the active surface). Therefore, the solder pads 102 and the microbumps 210 serve as channels for electrical connection between the chip and the packaging substrate 40. In addition, the first surface is also provided with dummy pads 103, which are arranged across the first chip bonding region 121 and the second chip bonding region 122 and are insulated from the connection lines in the packaging substrate 40.

[0082] like Figure 9 As shown, the first chip 21 has microbumps 210 on its active surface and a first dummy bump 211 on the side adjacent to the second chip 22; the second chip 22 has microbumps 210 on its active surface and a second dummy bump 221 on the side adjacent to the first chip 21. The first dummy bump 211 and the second dummy bump 221 are insulated from the internal connection lines of the chip.

[0083] like Figure 9 As shown, the filling material layer 130 is filled between the chip and the packaging substrate 40, which can redistribute stress and reduce packaging stress damage.

[0084] In this embodiment, since the dummy pad 103 spans the first chip soldering area 121 and the second chip soldering area 122, connecting the two non-contact areas, the structure of the dummy pad 103 acts as a reinforcing rib for the packaging substrate 40. The dummy pad 103 strengthens the structural strength of the packaging substrate 40 and can effectively prevent the packaging substrate 40 from breaking due to bending stress.

[0085] Since the two sides of the dummy pad 103 are respectively bonded to the first dummy bump 211 and the second dummy bump 221, as Figure 3 As shown, relying on the connection between the first dummy bump 211 and the first chip 21, and the connection between the second dummy bump 221 and the second chip 22, the reinforcement structure formed by the dummy pad 103, the first dummy bump 211, and the second dummy bump 221 can provide a pair of tensile forces (M1 and M1') to the package substrate 40 by means of the dummy bumps when the package substrate 40 is subjected to bending stress, thereby further preventing the package substrate 40 from bending and breaking due to bending stress. In addition, the reinforcing pillar formed by the dummy pad 103 and the first dummy bump 211 can effectively prevent the filler material layer 130 from cracking due to bending stress.

[0086] Because the filler layer 130 can redistribute stress, it should be noted that, for example... Figure 2 As shown, the filler layer 130 shrinks when heated and expands when cooled. The filler layer between the chips, in the direction perpendicular to the surface of the packaging substrate 40, exerts significant stress on the chips, causing cracks to appear at the flip-chip solder joints at the chip edges; as... Figure 4 As shown, the reinforcing pillar composed of the dummy pad 103 and the first dummy bump 211 can generate a pulling force (M2 and M2') to pull the chip and the packaging substrate 40 together when the filling material layer 130 expands, preventing the solder joint from breaking. When the filling material layer 130 contracts, it can support the chip and the packaging substrate 40.

[0087] In some embodiments, the packaging substrate 40 is an adapter board, which can be either a glass adapter board or a silicon-based adapter board. It is provided with multiple through holes and metal wire layers, and may also be provided with a redistribution layer. The through holes, metal wire layers, and redistribution layers together serve as the connection lines of the packaging substrate 40 and are insulated from the dummy pads 103.

[0088] In some embodiments, such as Figure 6The two chips are provided with multiple dummy pads 103 in adjacent areas. The first chip 21 can be provided with multiple first dummy bumps 211 and the second chip 22 can be provided with multiple second dummy bumps 221. A dummy pad 103 can be connected to only one first dummy bump 211 (second dummy bump 221) or to two or more first dummy bumps 211 (second dummy bump 221).

[0089] In some embodiments, such as Figure 6 As shown, due to the design effects of internal circuit capacitance and electromagnetic shielding within the package, not all adjacent chips (for example, Figure 6 The dummy pads must be provided between the second chip soldering area 122 and the sixth chip soldering area 126 shown.

[0090] In some embodiments, such as Figure 6 As shown, when three chips are adjacent to each other, the dummy pad 10 located in the middle of the three chips spans the soldering areas of the three chips (for example, ...). Figure 6 The first chip soldering area 121, the second chip soldering area 122 and the fifth chip soldering area 125 are shown, and are connected to the dummy bumps in the three chip soldering areas.

[0091] In some embodiments, such as Figure 6 As shown, when there are 4 adjacent chips, the dummy pad located in the middle of the 4 chips spans the 4 chip soldering areas (the seventh chip soldering area 127, the fourth chip soldering area 124, the sixth chip soldering area 126, and the eighth chip soldering area 128, respectively) and is connected to the dummy bumps in the 4 chip soldering areas.

[0092] In some embodiments, such as Figure 21 As shown, the semiconductor packaging structure 10 further includes a molding layer 140, the material of which includes, but is not limited to, polyimide, silicone and epoxy resin, wherein the molding layer 140 is formed on the first surface and its upper surface is flush with the upper surface of at least one of the chips.

[0093] In some embodiments, the materials used for dummy pads and dummy bumps include at least one of the following metallic materials: for example, aluminum (Al), copper (Cu), nickel (Ni), tungsten (W), platinum (Pt), gold (Au), tin (Sn), and silver (Ag).

[0094] Example 2

[0095] This embodiment provides a method for fabricating the semiconductor packaging structure 10 as described in Embodiment 1. Figure 5As shown, the method for fabricating the semiconductor package structure 10 includes steps S1) to S4). Specifically, it also includes steps S5) to S6).

[0096] Step S1): As Figure 7 As shown, an intermediate structure 30 is provided, the intermediate structure 30 including a first temporary carrier 120 and a packaging substrate 40 located on the upper surface of the first temporary carrier. The packaging substrate 40 includes a first surface and a second surface relative to the first surface. The first surface defines a first chip bonding area 121 and a second chip bonding area 122. The first chip bonding area 121 and the second chip bonding area 122 are adjacent and there is a first gap between the two areas. The first surface is also provided with at least one dummy pad 103. The dummy pad 103 spans the first gap and covers a portion of the surface of the first chip bonding area 121 and a portion of the surface of the second chip bonding area 122.

[0097] In this embodiment, the first temporary carrier plate 120 may be a glass carrier plate, a ceramic carrier plate, etc., and there is an adhesive material layer between the first temporary carrier plate 120 and the encapsulation substrate 40 to fix the encapsulation substrate on the first temporary carrier plate 120.

[0098] Specifically, when the packaging substrate 40 uses an interposer, the preparation method of the intermediate structure 30 is as follows: Figure 10 As shown, this includes steps S11 to S17.

[0099] Step S11), as follows Figure 11 As shown, a substrate 100 is provided, and a blind hole 101 is formed in the substrate 100. A metal pillar is filled in the blind hole 101.

[0100] In this embodiment, the substrate 100 is, for example, a silicon wafer, but is not limited thereto; it can also be a germanium wafer, a germanium-silicon wafer, an SOI wafer, etc. The blind via 101 can be formed by deep silicon etching. It should be noted that the blind via 101 in this embodiment refers to the through-hole structure formed by electroplating or chemical plating after the copper pillar inside the blind via is formed. Furthermore, the sidewall of the blind via 101 should also have a sidewall insulating layer, a barrier layer, and a seed layer. For the sake of simplicity, the sidewall insulating layer, barrier layer, and seed layer formed on the sidewall of the blind via 101 are not shown in the figure; only the copper pillar inside the blind via 101 is shown.

[0101] Step S12), as Figure 12 As shown, a solder pad 102 and a dummy pad 103 are formed on the upper surface of the substrate 100, wherein the dummy pad 103 is electrically isolated from the solder pad 102.

[0102] In this embodiment, the solder pad 102 is electrically connected to the blind via 101, while the dummy pad 103 is electrically insulated from the blind via 101. When forming the solder pad 102, a metal transition layer is first formed on the upper surface of the substrate 100 using a sputtering process. Then, a photoresist layer with an opening pattern is formed on the upper surface of the metal transition layer. The pad is then grown using chemical plating or electroplating. Finally, the photoresist layer and the metal transition layer not covered by the pad are removed by etching.

[0103] Step S13), as Figure 13 As shown, a second temporary carrier plate 110 is provided to fix the upper surface of the substrate 100 to the second temporary carrier plate 110 to prevent the substrate 100 from breaking or warping in subsequent processes.

[0104] Step S14), as Figure 14 As shown, the lower surface of the substrate 100 is thinned until the metal pillar is exposed.

[0105] In this embodiment, a thinning process is used to thin the lower surface of the substrate 100 until the copper pillar of the blind hole is exposed. During the thinning process, coarse grinding can be used first, followed by fine grinding, to obtain a surface with good flatness.

[0106] Step S15), as Figure 15 As shown, conductive bumps 104 are formed on the lower surface of the substrate 100 to prepare the encapsulation substrate, wherein the conductive bumps 104 are connected to the metal pillars.

[0107] In this embodiment, the conductive bump 104 is electrically connected to the blind via 101. It should be noted that in some embodiments, a redistribution layer (not shown in the figure) is also formed on the lower surface of the substrate 100 for interlayer interconnection. In this case, the conductive bump 104 is formed on the redistribution layer and connected to the blind via 101 through the redistribution layer.

[0108] Step S16), as Figure 16 As shown, a first temporary carrier plate 120 is provided to fix the lower surface of the substrate 100 to the first temporary carrier plate 120 to prevent the substrate 100 from breaking or warping in subsequent processes.

[0109] Step S17), as Figure 17 As shown, the second temporary carrier plate 110 is removed to obtain the intermediate structure 30.

[0110] In this embodiment, firstly, the adhesion of the adhesive material layer between the second temporary carrier plate 110 and the upper surface of the substrate 100 can be reduced by heating and / or light irradiation, and the second temporary carrier plate 110 can be removed. Then, the adhesive material layer can be peeled off by processing methods such as tearing or light irradiation. Of course, the second temporary carrier plate 110 and the substrate 100 can also be peeled off directly by laser peeling process. Laser peeling process directly vaporizes the adhesive material layer, which has high processing precision and leaves few impurities.

[0111] Step S2) Provide a first chip 21 and a second chip 22. At least one first dummy bump 211 is provided at a first position on the active surface of the first chip 21, and at least one second dummy bump 221 is provided at a second position on the active surface of the second chip 22. The first position is the position on the active surface of the first chip that corresponds to the portion of the dummy pad covered by the dummy pad in the soldering area of ​​the first chip, and the second position is the position on the active surface of the second chip that corresponds to the portion of the dummy pad covered by the dummy pad in the soldering area of ​​the second chip.

[0112] In this embodiment, both the first chip 21 and the second chip 22 are provided with microbumps 210. The microbumps 210 are connected to the internal connection lines of the chip, and both are preset with dummy bumps (the first dummy bump 211 and the second dummy bump 221, respectively). The dummy bumps are kept insulated from the internal connection lines of the chip.

[0113] Step S3), as Figure 18 As shown, the first chip 21 is bonded to the packaging substrate 40 in the first chip bonding area 121, the second chip 22 is bonded to the packaging substrate 40 in the second chip bonding area 122, and the first dummy bump and the second dummy bump are bonded to the dummy pad.

[0114] In this embodiment, as Figure 18 As shown, the microbump 210 is bonded to the solder pad 102 in the chip soldering area, and the dummy bumps (211 and 221) are bonded to the dummy pad 103. After the dummy pads and dummy bumps are bonded across the adjacent chip soldering areas, it can effectively prevent the adapter board from cracking, prevent the subsequent filling material layer from cracking, and prevent the connection between the microbump 210 and the solder pad 102 from breaking.

[0115] Step S4), as Figure 19 As shown, a filler material layer 130 is filled into the gap where the first chip 21 and the second chip 22 are bonded to the packaging substrate 40.

[0116] In this embodiment, the filling method of the filling material layer 130 includes, but is not limited to, capillary bottom filling, and the material of the filling material layer 130 includes, but is not limited to, epoxy resin. Its filling and placement between the chip and the packaging substrate 40 enables stress redistribution, thereby reducing packaging stress damage.

[0117] Step S5), as Figure 20 As shown, a molding compound 140 is formed on the first surface, and the molding compound 140 encapsulates the first chip 21 and the second chip 22 therein.

[0118] In this embodiment, the method for forming the molding compound 140 includes, but is not limited to, compression molding, molding, liquid encapsulation, vacuum lamination, and spin coating. The materials used include, but are not limited to, polyimide, silicone, and epoxy resin. Depending on design requirements, after forming the molding compound 140, processes such as backside grinding and CMP (chemical mechanical polishing) may be used to thin the molding compound 140 until the upper surface of one of the chips is exposed.

[0119] Step S6), as Figure 21 As shown, the first temporary carrier plate 120 is removed.

[0120] In this embodiment, the first temporary carrier 120 is removed in the same manner as in step S17) to prepare the semiconductor package structure 10.

[0121] In summary, the semiconductor packaging structure and its fabrication method of the present invention respectively set dummy bumps in two adjacent chips and corresponding dummy pads on the packaging substrate. The dummy bumps are insulated from the circuits inside the chips, and the dummy pads are insulated from the circuits inside the packaging substrate. After the chips are bonded to the packaging substrate, the dummy pads are also bonded to the dummy bumps respectively, forming a structural reinforcement bridge spanning under the two chips. The structural reinforcement bridge connects the two adjacent chips, which can effectively prevent the bottom filler layer from cracking at the solder joints due to shrinkage and expansion, and further prevent problems such as delamination, electromagnetic shielding failure, and circuit interruption in the packaging structure.

[0122] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A semiconductor packaging structure, characterized in that, The semiconductor packaging structure includes: The packaging substrate includes a first surface and a second surface relative to the first surface. The first surface defines a first chip bonding area and a second chip bonding area. The first chip bonding area and the second chip bonding area are adjacent to each other and have a first gap. The first surface is also provided with at least one dummy pad. The dummy pad spans the first gap and covers a portion of the surface of the first chip bonding area and the second chip bonding area. A first chip and a second chip, wherein at least one first dummy bump is provided at a first position on the active surface of the first chip, and at least one second dummy bump is provided at a second position on the active surface of the second chip; wherein, the first position is a position on the active surface of the first chip corresponding to the portion covered by the dummy pad in the soldering area of ​​the first chip, and the second position is a position on the active surface of the second chip corresponding to the portion covered by the dummy pad in the soldering area of ​​the second chip, and the first dummy bump and the second dummy bump are bonded to the dummy pad; A filler material layer is provided to fill the gap between the packaging substrate and the first chip and the second chip.

2. The semiconductor packaging structure according to claim 1, characterized in that, The semiconductor packaging structure further includes a third chip; the first surface also defines a third chip bonding area. The third chip soldering area is adjacent to the second chip soldering area and there is a second gap; At least one of the dummy pads also spans the second gap and covers a portion of the surface of the second chip soldering area and the third chip soldering area; At least one third dummy bump is provided at the third position of the active surface of the third chip. The third position is the position of the active surface of the third chip corresponding to the portion of the dummy pad covered by the soldering area of ​​the third chip. The second dummy bump and the third dummy bump are bonded to the dummy pad.

3. The semiconductor packaging structure according to claim 2, characterized in that, The first chip soldering area, the second chip soldering area, and the third chip soldering area are adjacent to each other; One of the dummy pads simultaneously covers a portion of the surfaces of the first chip soldering area, the second chip soldering area, and the third chip soldering area; The first dummy bump, the second dummy bump, and the third dummy bump are bonded to the dummy pad.

4. The semiconductor packaging structure according to any one of claims 1-3, characterized in that, The semiconductor packaging structure further includes: A molding compound is formed on the first surface and covers each chip.

5. The semiconductor packaging structure according to claim 1, characterized in that, The packaging substrate includes an adapter plate, the adapter plate having through holes, and the dummy pads being insulated from the through holes.

6. The semiconductor packaging structure according to claim 1, characterized in that, The packaging substrate includes an adapter board, which has through holes and a redistribution layer, and the dummy pads are insulated from the through holes and the redistribution layer.

7. A method for fabricating a semiconductor packaging structure, characterized in that, The preparation method includes: An intermediate structure is provided, the intermediate structure including a first temporary carrier board and a packaging substrate located on the upper surface of the first temporary carrier board. The packaging substrate includes a first surface and a second surface relative to the first surface. The first surface defines a first chip bonding area and a second chip bonding area. The first chip bonding area and the second chip bonding area are adjacent to each other and have a first gap. The first surface is also provided with at least one dummy pad. The dummy pad spans the first gap and covers a portion of the surface of the first chip bonding area and a portion of the surface of the second chip bonding area. A first chip and a second chip are provided. At least one first dummy bump is provided at a first position on the active surface of the first chip, and at least one second dummy bump is provided at a second position on the active surface of the second chip. The first position is the position on the active surface of the first chip that corresponds to the portion of the dummy pad covered by the dummy pad in the soldering area of ​​the first chip, and the second position is the position on the active surface of the second chip that corresponds to the portion of the dummy pad covered by the dummy pad in the soldering area of ​​the second chip. The first chip is bonded to the packaging substrate in the first chip bonding area, the second chip is bonded to the packaging substrate in the second chip bonding area, and the first dummy bump and the second dummy bump are bonded to the dummy pad. A filler material layer is filled into the gaps where the first chip and the second chip are bonded to the packaging substrate.

8. The method for preparing a semiconductor packaging structure according to claim 7, characterized in that, After filling the filler material layer, the preparation method further includes: A molding compound is formed on the first surface, the molding compound encapsulating the first chip and the second chip therein; Remove the first temporary carrier board.

9. The method for preparing a semiconductor packaging structure according to claim 7, characterized in that, The method for preparing the intermediate structure includes: A substrate is provided, wherein a blind hole is formed therein, and a metal pillar is filled therein; A solder pad and a dummy pad are formed on the upper surface of the substrate, wherein the solder pad is connected to the metal pillar and the dummy pad is electrically isolated from the solder pad; A second temporary carrier plate is provided to fix the upper surface of the substrate to the second temporary carrier plate; Thin the lower surface of the substrate until the metal pillars are exposed; Conductive bumps are formed on the lower surface of the substrate, wherein the conductive bumps are connected to the metal pillars; Provide the first temporary carrier plate and fix the lower surface of the substrate to the first temporary carrier plate; Remove the second temporary carrier board.

10. The method for preparing a semiconductor packaging structure according to claim 9, characterized in that, After thinning the lower surface of the substrate and before forming conductive bumps on the lower surface of the substrate, the method for preparing the intermediate structure further includes the step of forming a redistribution layer on the lower surface of the substrate, wherein the redistribution layer is connected to the conductive bumps.

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