Electrostatic discharge protection device and method of forming the same

Abstract

An electrostatic discharge protection device and a method of forming the same, wherein the structure comprises: a first well region in the substrate, the first well region having a second conductivity type, the first well region having a first extraction region therein, the first extraction region having a first conductivity type, the first extraction region being electrically connected to the first guard ring; a second well region in the substrate and adjacent to the first well region, the first well region and the second well region being separated from each other, the first well region and the second well region having a discharge region therebetween, the second well region having the first conductivity type; a dielectric layer on the surface of the discharge region, the dielectric layer further extending to the surface of the first extraction region and the second well region; a first conductive contact layer on the surface of the dielectric layer; and a second conductive contact layer on the surface of the first extraction region, the second conductive contact layer being electrically connected to the first conductive contact layer, thereby improving the discharge capability and the turn-on voltage of the device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to an electrostatic discharge protection device and its forming method. Background Technology

[0002] With the development of integrated circuits, high-voltage power integrated circuits have shown great application prospects in automotive electronics, display drivers, and other fields. However, electrostatic discharge (ESD) poses a significant potential threat to high-voltage integrated circuits. Under BCD (Bipolar-CMOS-DMOS) technology, the higher operating voltage and harsher operating environment of the devices make the ESD protection design of high-voltage integrated circuits even more challenging.

[0003] In BCD (Bipolar-CMOS-DMOS) technology, ESD-PNP devices are generally used as protection circuits for high-voltage devices. The main parameters of an ESD-PNP device are determined by the operating voltage and breakdown voltage of the protected device. These two voltages together determine the operating window of the ESD device. The ESD-PNP device needs to be activated within this window and achieve the required discharge capability within that window.

[0004] With the rapid development of integrated circuits, semiconductor manufacturing processes have entered the deep submicron and even nanometer ranges. The shrinking of device dimensions has led to a corresponding narrowing of the design window for electrostatic discharge (ESD) protection devices. Therefore, existing ESD protection devices require further improvement. Summary of the Invention

[0005] The technical problem solved by the present invention is to provide an electrostatic discharge protection device and a method for forming the same, so as to improve the performance of the formed electrostatic discharge protection device.

[0006] To address the aforementioned technical problems, the present invention provides an electrostatic discharge protection device, comprising: a substrate having a first conductivity type; a first well region located within the substrate, the first well region having a second conductivity type, a first lead-out region within the first well region, the first lead-out region having a first conductivity type, and the first lead-out region being electrically connected to a first protective ring; a second well region located within the substrate and adjacent to the first well region, the first well region and the second well region being separate from each other, a discharge region being located between the first well region and the second well region, the second well region having a first conductivity type; a dielectric layer located on the surface of the discharge region, the dielectric layer further extending to a portion of the surfaces of the first lead-out region and the second well region; a first conductive contact layer located on the surface of the dielectric layer; and a second conductive contact layer located on the surface of the first lead-out region, the second conductive contact layer being electrically connected to the first conductive contact layer.

[0007] Optionally, the discharge region contains doped ions, and the conductivity type of the doped ions is a first conductivity type.

[0008] Optionally, it further includes: a buried layer located within the substrate, the buried layer having a second conductivity type, the bottoms of the first well region and the second well region being in contact with the buried layer; a first protective ring located within the substrate and surrounding the first well region and the second well region, the first protective ring having a second conductivity type, the bottom of the first protective ring being in contact with the buried layer, and the first protective ring being electrically connected to the first conductive contact layer and the second conductive contact layer.

[0009] Optionally, it includes: a second protective ring located within the substrate, the second protective ring having a conductivity type opposite to the first protective ring, and the second protective ring being located outside the first protective ring.

[0010] Optionally, the second well region has a second lead-out region, which has a first conductivity type.

[0011] Optionally, the second protection ring is electrically connected to the second well region through the second lead-out region.

[0012] Optionally, the second well region is disposed around the first well region.

[0013] Optionally, the material of the first conductive contact layer includes metal.

[0014] Optionally, a field plate layer may also be provided between the surface of the dielectric layer and the first conductive contact layer.

[0015] Optionally, the material of the field plate layer includes polycrystalline silicon.

[0016] Optionally, the first conductivity type is N-type, and the second conductivity type is P-type.

[0017] Optionally, the material of the dielectric layer includes one or more of silicon oxide, silicon nitride, and silicon oxynitride.

[0018] Optionally, the dielectric layer also extends into the substrate.

[0019] Accordingly, the technical solution of the present invention also provides a method for forming an electrostatic discharge protection device, comprising: providing a substrate having a first conductivity type; forming a first well region and a second well region adjacent to the first well region in the substrate, wherein the first well region has a second conductivity type, the second well region has a first conductivity type, the first conductivity type is different from the second conductivity type, the first well region has a first lead-out region, the first lead-out region has a first conductivity type, the first well region and the second well region are mutually discrete, and a discharge region is formed between adjacent first well regions and second well regions; after forming the first well region and the second well region, forming a dielectric layer on the surface of the discharge region, a portion of the first lead-out region and a portion of the second well region; after forming the dielectric layer, forming a metal interconnect layer, wherein the metal interconnect layer includes an electrically interconnected first conductive contact layer and a second conductive contact layer, the first conductive contact layer being located on the surface of the dielectric layer and the second conductive contact layer being located on the surface of the first lead-out region.

[0020] Optionally, before forming the first well region and the second well region, a buried layer is formed in the substrate, the buried layer having a second conductivity type; after forming the buried layer, a first protective ring is also formed in the substrate, the first protective ring surrounding the first well region and the second well region, the first protective ring having a second conductivity type, and the bottom of the first protective ring contacting the buried layer.

[0021] Optionally, after forming the first protective ring, the first well region, and the second well region, and before forming the dielectric layer, the method further includes: implanting dopant ions into the discharge region, wherein the conductivity type of the dopant ions is a first conductivity type.

[0022] Optionally, the method for forming the dielectric layer includes: forming a dielectric material layer on the surface of the substrate; etching the dielectric material layer until the surface of the substrate is exposed, thereby forming the dielectric layer.

[0023] Optionally, the method for forming the dielectric layer includes: forming a patterned layer on the substrate surface, the patterned layer exposing the surface of the discharge region, a portion of the first lead-out region, and a portion of the surface of the second well region; and after forming the patterned layer, oxidizing the substrate surface to form the dielectric layer.

[0024] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects:

[0025] In the electrostatic discharge (ESD) protection device provided by this invention, a first well region, a first lead-out region, and a second well region constitute a PNP transistor for forming the ESD protection device. The first well region serves as the base, the first lead-out region as the emitter, and the second well region as the collector. A discharge region exists between the first well region and the second well region. A dielectric layer is present on the surface of the discharge region, isolating the first well region from the second well region. A large discharge region exists below the dielectric layer, increasing the discharge path of the device and reducing the discharge path resistance of the ESD protection device. Simultaneously, the first conductive contact layer on the surface of the dielectric layer acts as a field plate, suppressing junction leakage between the discharge region and the first well region (i.e., the base), thereby increasing the turn-on voltage of the ESD protection device.

[0026] Furthermore, the discharge region contains doped ions; the conductivity type of the doped ions is the first conductivity type, and the doped ions increase the doped ion concentration in the discharge region, which is beneficial to increasing the discharge path of the device. Attached Figure Description

[0027] Figure 1 This is a schematic cross-sectional view of an electrostatic discharge protection device.

[0028] Figures 2 to 5 This is a schematic diagram of the structure of each step in the method for forming an electrostatic discharge protection device according to an embodiment of the present invention;

[0029] Figure 6 This is a schematic diagram of the structure of each step in the method for forming an electrostatic discharge protection device according to another embodiment of the present invention. Detailed Implementation

[0030] As described in the background section, the performance of existing electrostatic discharge (ESD) protection devices urgently needs improvement. This paper will now analyze and explain an existing ESD protection device.

[0031] It should be noted that the terms "surface" and "on" in this specification are used to describe the relative spatial position and are not limited to whether there is direct contact.

[0032] Figure 1 This is a schematic diagram of the cross-sectional structure of an electrostatic discharge protection device.

[0033] Please refer to Figure 1The electrostatic discharge protection device includes: a substrate 101, wherein the substrate 101 is P-type and has an N-type buried layer 102; a P-protection ring 103 and an N-protection ring 104 located within the substrate 101, wherein the N-protection ring 104 is located inside the P-protection ring 103 and its bottom contacts the N-type buried layer 102; a device region located inside the N-protection ring 104 and the N-type buried layer 102; and an N-well region 105 located within the device region, wherein the bottom of the N-well region 105 contacts the N-type buried layer 102 and the N-well region 105 has a first P+ lead-out region 106. The first P+ lead-out region 106 is electrically interconnected with the N-guard ring 104; a P-well region 107 is located within the device region and on both sides of the N-well region 105, the bottom of the P-well region 107 is in contact with the N-type buried layer 102, the P-well region 107 has a second P+ lead-out region 108, the second P+ lead-out region 108 is electrically interconnected with the P-guard ring 103; an isolation layer 109 is located within the substrate 101, the isolation layer 109 isolates the P-guard ring 103, the N-guard ring 104, the N-well region 105 and the P-well region 107, and the bottom surface of the isolation layer 109 is higher than the top surface of the N-type buried layer 102.

[0034] The above structure illustrates two PNP transistors used as electrostatic discharge (ESD) protection devices. The first P+ region 106 serves as the emitter, the N-well region 105 as the base, and the P-well region 107 as the collector. The base is led out through the N-type buried layer 102 and the N-guard ring 104, and is electrically interconnected with the emitter. By grounding the base and electrically connecting the collector to the input / output terminals of the solder pads, ESD protection for the integrated circuit can be achieved.

[0035] However, the electrostatic discharge (ESD) protection device controls the turn-on voltage (Vtrig) by adjusting the distance *m* between the P-well and N-well regions. A larger distance *m* results in a higher Vtrig and a higher discharge path resistance (Resd). When the ESD protection device is turned on, a smaller discharge path resistance (Resd) leads to a stronger discharge capability. In BCD technology, due to the higher operating voltage, a higher turn-on voltage is required for the ESD protection device. This leads to a corresponding increase in discharge path resistance, but also a weakening of the discharge capability. To achieve the same discharge capability, the number of transistors needs to be increased, resulting in a larger ESD protection device area, which is detrimental to circuit integration.

[0036] To address the aforementioned problems, this invention provides an electrostatic discharge (ESD) protection device in which a first well region, a first lead-out region, and a second well region constitute a PNP transistor for forming the ESD protection device. The first well region serves as the base, the first lead-out region as the emitter, and the second well region as the collector. A discharge region exists between the first and second well regions, and a dielectric layer is present on the surface of this discharge region. This dielectric layer isolates the first and second well regions. A larger discharge region lies beneath the dielectric layer, increasing the discharge path of the device and reducing the discharge path resistance of the ESD protection device. Simultaneously, the first conductive contact layer on the surface of the dielectric layer acts as a field plate, suppressing junction leakage between the discharge region and the first well region (i.e., the base), thereby increasing the turn-on voltage of the ESD protection device.

[0037] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0038] Figures 2 to 5 This is a schematic diagram of the structure of each step in the method for forming an electrostatic discharge protection device according to an embodiment of the present invention.

[0039] Please refer to Figure 2 A substrate 200 is provided, the substrate 200 having a first conductivity type.

[0040] In this embodiment, the first conductivity type is N-type.

[0041] Subsequently, a first well region and a second well region adjacent to the first well region are formed within the substrate.

[0042] Before forming the first well region and the second well region, a buried layer 201 is formed in the substrate 200, the buried layer 201 having a second conductivity type.

[0043] In this embodiment, the second conductivity type is N-type, and the buried layer 201 is N-type.

[0044] Please refer to Figure 3 A first well region 202 and a second well region 203 adjacent to the first well region 202 are formed in the substrate 201. The first well region 202 has a second conductivity type, and the second well region 203 has a first conductivity type. The first conductivity type is different from the second conductivity type. The first well region 202 has a first lead-out region 204, which has a first conductivity type. The first well region 202 and the second well region 203 are separate from each other, and a discharge region 205 is provided between adjacent first well regions 202 and second well regions 203.

[0045] The first well region 202 serves as the base, the first lead-out region 204 serves as the emitter, and the second well region 203 serves as the collector, which is used to form a PNP type transistor.

[0046] In this embodiment, the second well region 203 is arranged around the first well region 202. In this embodiment, only two PNP transistors are shown, and the two PNP transistors are used as repeating units. An electrostatic discharge protection device may have several such repeating units.

[0047] In another embodiment, the second well region is located on one or both sides of the first well region and is arranged parallel to the first well region. One or two PNP transistors can be used as repeating units to form an electrostatic discharge protection device.

[0048] In this embodiment, before forming the first well region 202 and the second well region 203, an isolation layer 206 is also formed in the substrate 201. The isolation layer 206 exposes a portion of the surface of the substrate 201. After forming the isolation layer 206, dopant ions are implanted into the substrate 200 to form doped regions such as the first well region 202, the second well region 203, the first guard ring, and the second guard ring between adjacent isolation layers 206.

[0049] In this embodiment, after the buried layer 202 is formed, a first protective ring 207 is also formed. The first protective ring 207 is disposed around the first well region 202 and the second well region 203. The first protective ring 207 has a second conductivity type, and the bottom of the first protective ring 207 is in contact with the buried layer 201. Specifically, the conductivity type of the first protective ring 207 is N-type.

[0050] Specifically, the first protective ring 207 includes a third well region (not shown in the figure) located within the substrate 200 and a third lead-out region (not shown in the figure) located within the third well region, the bottom of the third well region being in contact with the buried layer 201.

[0051] In this embodiment, after forming the buried layer 201, a second protective ring 208 is also formed within the substrate 200. The second protective ring 208 has the opposite conductivity type to the first protective ring 207, and is located outside the first protective ring 207. Specifically, the second protective ring 208 has a P-type conductivity.

[0052] Specifically, the second protection ring 208 includes a fourth well region (not shown in the figure) located within the substrate 200 and a fourth lead-out region (not shown in the figure) located within the fourth well region.

[0053] The second well region 203 has a second lead-out region 209, which has a first conductivity type. In this embodiment, the second lead-out region 209 is P-type.

[0054] On the one hand, the first guard ring 207 and the second guard ring 208 are used to reduce substrate noise. On the other hand, the buried layer 201 and the first guard ring 207 are used to extract the current from the first well region 202 (i.e., the base), specifically, through the third extraction region.

[0055] Subsequently, a dielectric layer is formed on the surface of the discharge region 205, a portion of the first lead-out region 204, and a portion of the second well region 203.

[0056] In this embodiment, after forming the first protective ring 207, the first well region 202, and the second well region 203, and before forming the dielectric layer, the method further includes: implanting dopant ions into the discharge region 205, wherein the conductivity type of the dopant ions is a first conductivity type. Specifically, P-type dopant ions are implanted into the discharge region 205. The dopant ions increase the dopant ion concentration in the discharge region 205, which is beneficial for increasing the discharge path of the device.

[0057] In other embodiments, dopant ions may not be injected into the discharge region 205.

[0058] Please refer to Figure 4 After the first well region 202 and the second well region 203 are formed, a dielectric layer 210 is formed on the surface of the discharge region 205, a portion of the first lead-out region 204 and a portion of the second well region 203.

[0059] The dielectric layer 210 is made of one or more of silicon oxide, silicon nitride, and silicon oxynitride. In this embodiment, the dielectric layer 210 is made of silicon oxide.

[0060] In this embodiment, the method for forming the dielectric layer 210 includes: forming a dielectric material layer (not shown in the figure) on the surface of the substrate 200; etching the dielectric material layer until the surface of the substrate 200 is exposed to form the dielectric layer 210.

[0061] Specifically, the dielectric layer 210 can be formed in the same process as the salicide block (SAB) layer during the salicide process, and the dielectric layer 210 and the salicide block layer are made of the same material to reduce the number of process steps.

[0062] In another embodiment, the dielectric layer further extends into the substrate. The method for forming the dielectric layer includes: forming a patterned layer on the surface of the substrate, the patterned layer exposing the surface of the discharge region, a portion of the first lead-out region, and a portion of the surface of the second well region; after forming the patterned layer, oxidizing the surface of the substrate to form the dielectric layer. Specifically, a wet oxidation process is used to form the dielectric layer.

[0063] Please refer to Figure 5 After the dielectric layer 210 is formed, a metal interconnect layer is formed. The metal interconnect layer includes a first conductive contact layer 211 and a second conductive contact layer 212 that are electrically interconnected. The first conductive contact layer 211 is located on the surface of the dielectric layer 210, and the second conductive contact layer 212 is located on the surface of the first lead-out region 204.

[0064] The material of the first conductive contact layer 211 includes metal. In this embodiment, the material of the first conductive contact layer 211 is tungsten.

[0065] In another embodiment, a field plate layer is further provided between the surface of the dielectric layer and the first conductive contact layer. The material of the field plate layer includes polycrystalline silicon.

[0066] It should be noted that, Figure 5 The diagram only shows the first conductive contact layer 211, the second conductive contact layer 212, and the interconnections between the various lead-out regions. The first lead-out region 204 (i.e., the emitter) is electrically connected to the dielectric layer 210 and, through its connection to the first guard ring 207, is electrically connected to the first well region 202 (i.e., the base). Grounding the first well region 202 (i.e., the base) and electrically connecting the second well region 203 (i.e., the collector) to the input / output terminals of the solder pads provides electrostatic discharge protection for the integrated circuit.

[0067] In this embodiment, the second well region 203 is also electrically connected to the second protection ring 208 through the second lead-out region 209 and the fourth lead-out region.

[0068] Thus, the first well region 202, the first lead-out region 204, and the second well region 203 constitute a PNP transistor for forming an electrostatic discharge (ESD) protection device. A discharge region 205 is located between the first well region 202 and the second well region 203. A dielectric layer 210 is present on the surface of the discharge region 205, isolating the first well region 202 and the second well region 203. The larger discharge region 205 beneath the dielectric layer 210 increases the discharge path of the device and reduces the discharge path resistance of the ESD protection device. Simultaneously, the first conductive contact layer 211 on the surface of the dielectric layer 210 acts as a field plate, suppressing junction leakage between the discharge region 205 and the first well region 202 (i.e., the base), thereby increasing the turn-on voltage of the ESD protection device.

[0069] Accordingly, one embodiment of the present invention also provides an electrostatic discharge protection device formed using the above method. Please refer to [link / reference needed]. Figure 5 The system includes: a substrate 200 having a first conductivity type; a first well region 202 located within the substrate 200, the first well region 202 having a second conductivity type, the first well region 202 having a first lead-out region 204 having a first conductivity type, the first lead-out region 204 being electrically connected to the first guard ring 207; and a second well region 203 located within the substrate 200 and adjacent to the first well region 202, the first well region 202 and the second well region 203 being discrete from each other. A discharge region 205 is provided between the first well region 202 and the second well region 203, and the second well region 203 has a first conductivity type; a dielectric layer 210 is located on the surface of the discharge region 205, and the dielectric layer 210 extends to a portion of the surface of the first lead-out region 204 and the second well region 203; a first conductive contact layer 211 is located on the surface of the dielectric layer 210; a second conductive contact layer 212 is located on the surface of the first lead-out region 204, and the second conductive contact layer 212 is electrically connected to the first conductive contact layer 211.

[0070] The first well region 202, the first lead-out region 204, and the second well region 203 constitute a PNP transistor for forming an electrostatic discharge (ESD) protection device. A discharge region 205 is located between the first well region 202 and the second well region 203. A dielectric layer 210 is present on the surface of the discharge region 205, isolating the first well region 202 and the second well region 203. The larger discharge region 205 beneath the dielectric layer 210 increases the discharge path of the device and reduces the discharge path resistance of the ESD protection device. Simultaneously, the first conductive contact layer 211 on the surface of the dielectric layer 210 acts as a field plate, suppressing junction leakage between the discharge region 205 and the first well region 202 (i.e., the base), thereby increasing the turn-on voltage of the ESD protection device.

[0071] The discharge region 205 contains doped ions, and the conductivity type of the doped ions is the first conductivity type. The doped ions increase the doped ion concentration in the discharge region 205, which is beneficial for increasing the discharge path of the device.

[0072] The electrostatic discharge protection device further includes: a buried layer 201 located within the substrate 200, the buried layer 201 having a second conductivity type, the bottoms of the first well region 202 and the second well region 203 both contacting the buried layer 201; and a first protective ring 207 located within the substrate 200 and surrounding the first well region 202 and the second well region 203, the first protective ring 207 having a second conductivity type, the bottom of the first protective ring 207 contacting the buried layer 201, and the first protective ring 207 being electrically connected to the first conductive contact layer 211 and the second conductive contact layer 212.

[0073] The electrostatic discharge protection device includes a second protective ring 208 located within the substrate 200. The second protective ring 208 has an opposite conductivity type to the first protective ring 207, and the second protective ring 208 is located outside the first protective ring 207.

[0074] The second well region 203 has a second lead-out region 209, which has a first conductivity type.

[0075] The second protection ring 208 and the second well region 203 are electrically connected through the second lead-out region 209.

[0076] In this embodiment, the second well region 203 is arranged around the first well region 202.

[0077] The material of the first conductive contact layer 211 includes metal.

[0078] The first conductivity type is N-type, and the second conductivity type is P-type.

[0079] The material of the dielectric layer 210 includes one or more of silicon oxide, silicon nitride, and silicon oxynitride.

[0080] Figure 6 This is a schematic diagram of the steps in a method for forming a semiconductor structure according to another embodiment of the present invention.

[0081] This embodiment provides another method for forming a dielectric layer and a first conductive contact layer. Please refer to [the original text]. Figure 5 Based on this, continue to refer to Figure 6The process includes: after forming the first well region 202 and the second well region 203, forming a dielectric layer 301 on the surface of the discharge region 205, a portion of the first lead-out region 204 and a portion of the second well region 203; after forming the dielectric layer 301, forming a metal interconnect layer, the metal interconnect layer including a first conductive contact layer 302 and a second conductive contact layer 303 electrically interconnected, the first conductive contact layer 302 being located on the surface of the dielectric layer 301 and the second conductive contact layer 303 being located on the surface of the first lead-out region 204.

[0082] The difference between this embodiment and the previous embodiment is that: firstly, the method of forming the dielectric layer 301 is different; secondly, in this embodiment, a field plate layer 304 is also provided between the surface of the dielectric layer 301 and the first conductive contact layer 302.

[0083] Specifically, the dielectric layer 301 also extends into the substrate 200.

[0084] In this embodiment, the method for forming the dielectric layer 301 includes: forming a patterned layer (not shown in the figure) on the surface of the substrate 200, wherein the patterned layer exposes the surface of the discharge region 205, a portion of the first lead-out region 204, and a portion of the surface of the second well region 203; after forming the patterned layer, oxidizing the surface of the substrate 200 to form the dielectric layer 301. Specifically, the dielectric layer 301 is formed using a wet oxidation process.

[0085] The field plate layer 304 is made of polycrystalline silicon. The field plate layer 304 can improve the adhesion between the first conductive contact layer 302 and the dielectric layer 301.

[0086] For the formation methods of other structures in this embodiment, please refer to the description of the previous embodiment, which will not be repeated here.

[0087] Accordingly, another embodiment of the present invention also provides a semiconductor structure formed by the above method. Please refer to [the original text]. Figure 6The system includes: a substrate 200 having a first conductivity type; a first well region 202 located within the substrate 200, the first well region 202 having a second conductivity type, the first well region 202 having a first lead-out region 204 having a first conductivity type, the first lead-out region 204 being electrically connected to the first guard ring 207; and a second well region 203 located within the substrate 200 and adjacent to the first well region 202, the first well region 202 and the second well region 203 being discrete from each other. A discharge region 205 is provided between the first well region 202 and the second well region 203, and the second well region 203 has a first conductivity type; a dielectric layer 301 is located on the surface of the discharge region 205, and the dielectric layer 301 extends to a portion of the surface of the first lead-out region 204 and the second well region 203; a first conductive contact layer 302 is located on the surface of the dielectric layer 301; a second conductive contact layer 303 is located on the surface of the first lead-out region 204, and the second conductive contact layer 303 is electrically connected to the first conductive contact layer 302.

[0088] The structural difference between this embodiment and the previous embodiment is that the dielectric layer 301 extends into the substrate 200; and a field plate layer 304 is also provided between the surface of the dielectric layer 301 and the first conductive contact layer 302.

[0089] In this embodiment, the material of the field plate layer 304 includes polycrystalline silicon.

[0090] In this embodiment, the other structures are the same as in the previous embodiment, and will not be described again here.

[0091] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. An electrostatic discharge protection device, characterized in that, include: Substrate, the substrate having a first conductivity type; A first well region located within the substrate, the first well region having a second conductivity type, a first lead-out region within the first well region having a first conductivity type, and the first lead-out region being electrically connected to a first guard ring; A second well region located within the substrate and adjacent to the first well region, the first well region and the second well region being separate from each other, a discharge region being present between the first well region and the second well region, and the second well region having a first conductivity type; A dielectric layer located on the surface of the discharge region, the dielectric layer further extending to a portion of the surface of the first lead-out region and the second well region, the dielectric layer isolating the first well region and the second well region; The first conductive contact layer is located on the surface of the dielectric layer; A second conductive contact layer is located on the surface of the first lead-out area, and the second conductive contact layer is electrically connected to the first conductive contact layer.

2. The electrostatic discharge protection device as described in claim 1, characterized in that, The discharge region contains doped ions, and the conductivity type of the doped ions is the first conductivity type.

3. The electrostatic discharge protection device as described in claim 1, characterized in that, Also includes: A buried layer located within the substrate, the buried layer having a second conductivity type, the bottoms of both the first well region and the second well region being in contact with the buried layer; A first protective ring is disposed within the substrate and surrounding the first well region and the second well region. The first protective ring has a second conductivity type. The bottom of the first protective ring is in contact with the buried layer, and the first protective ring is electrically connected to the first conductive contact layer and the second conductive contact layer.

4. The electrostatic discharge protection device as described in claim 3, characterized in that, include: The substrate also has a second protective ring, which has the opposite conductivity type to the first protective ring and is located outside the first protective ring.

5. The electrostatic discharge protection device as described in claim 4, characterized in that, The second well region has a second lead-out region, and the second lead-out region has a first conductivity type.

6. The electrostatic discharge protection device as described in claim 5, characterized in that, The second protection ring is electrically connected to the second well region through the second lead-out region.

7. The electrostatic discharge protection device as described in claim 1, characterized in that, The second well region is arranged around the first well region.

8. The electrostatic discharge protection device as described in claim 1, characterized in that, The material of the first conductive contact layer includes metal.

9. The electrostatic discharge protection device as described in claim 1, characterized in that, A field plate layer is also present between the surface of the dielectric layer and the first conductive contact layer.

10. The electrostatic discharge protection device as described in claim 9, characterized in that, The material of the field plate layer includes polycrystalline silicon.

11. The electrostatic discharge protection device as described in claim 1, characterized in that, The first conductivity type is N-type, and the second conductivity type is P-type.

12. The electrostatic discharge protection device as described in claim 1, characterized in that, The material of the dielectric layer includes one or more of silicon oxide, silicon nitride, and silicon oxynitride.

13. The electrostatic discharge protection device as described in claim 1, characterized in that, The dielectric layer also extends into the substrate.

14. A method for forming an electrostatic discharge protection device, characterized in that, include: A substrate is provided, the substrate having a first conductivity type; A first well region and a second well region adjacent to the first well region are formed in the substrate. The first well region has a second conductivity type, and the second well region has a first conductivity type. The first conductivity type is different from the second conductivity type. The first well region has a first lead-out region with a first conductivity type. The first well region and the second well region are separate from each other, and there is a discharge region between adjacent first well regions and second well regions. After the first well region and the second well region are formed, a dielectric layer is formed on the surface of the discharge region, a portion of the first lead-out region and a portion of the second well region, the dielectric layer isolating the first well region and the second well region; After the dielectric layer is formed, a metal interconnect layer is formed. The metal interconnect layer includes a first conductive contact layer and a second conductive contact layer that are electrically interconnected. The first conductive contact layer is located on the surface of the dielectric layer, and the second conductive contact layer is located on the surface of the first lead-out area.

15. The method for forming the electrostatic discharge protection device as described in claim 14, characterized in that, Before forming the first well region and the second well region, a buried layer is formed in the substrate, the buried layer having a second conductivity type; after forming the buried layer, a first protective ring is also formed in the substrate, the first protective ring surrounding the first well region and the second well region, the first protective ring having a second conductivity type, and the bottom of the first protective ring contacting the buried layer.

16. The method for forming the electrostatic discharge protection device as described in claim 15, characterized in that, After forming the first protective ring, the first well region, and the second well region, and before forming the dielectric layer, the method further includes: implanting doped ions into the discharge region, wherein the conductivity type of the doped ions is a first conductivity type.

17. The method for forming the electrostatic discharge protection device as described in claim 14, characterized in that, The method for forming the dielectric layer includes: forming a dielectric material layer on the surface of the substrate; etching the dielectric material layer until the surface of the substrate is exposed to form the dielectric layer.

18. The method for forming the electrostatic discharge protection device as described in claim 14, characterized in that, The method for forming the dielectric layer includes: forming a patterned layer on the surface of the substrate, the patterned layer exposing the surface of the discharge region, a portion of the first lead-out region and a portion of the surface of the second well region; and after forming the patterned layer, oxidizing the surface of the substrate to form the dielectric layer.

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