Display panel

Abstract

A display panel includes a lower substrate, a light emitting diode chip, and an upper substrate. The lower substrate includes a dielectric layer, a first electrode pad, and a second electrode pad. The first electrode pad is on the dielectric layer. The second electrode pad is on the dielectric layer adjacent to the first electrode pad, and the first electrode pad and the second electrode pad are configured to provide different electrical potentials. The light emitting diode chip includes a first electrode and a second electrode on opposite sides, the first electrode electrically connected to the first electrode pad. The upper substrate is on the lower substrate and the light emitting diode chip, the upper substrate including a carrier, an upper bank structure, and a transparent conductive layer. The carrier has a surface facing the lower substrate. The upper bank structure is disposed on the surface. The transparent conductive layer covers the surface of the carrier and the upper bank structure, the transparent conductive layer electrically connected to the second electrode and the second electrode pad.

Description

Technical Field

[0001] Some embodiments of this disclosure relate to a display panel. Background Technology

[0002] Light-emitting diode (LED) displays are among the most common types of displays today. Generally, the manufacturing process for LED displays involves a mass transfer process to transfer a large number of LED chips onto a specific substrate. Next, a transparent conductive layer is formed between the LED chips and the substrate to electrically connect the electrodes of the LED chips to the electrodes on the substrate. When the electrodes of the LED chips cannot be effectively connected to the electrodes on the substrate, the LED chips are prone to failure. Summary of the Invention

[0003] Some embodiments of this disclosure provide a display panel including a lower substrate, a light-emitting diode (LED) chip, and an upper substrate. The lower substrate includes a dielectric layer, a first electrode pad, and a second electrode pad. The first electrode pad is located on the dielectric layer. The second electrode pad is located on the dielectric layer, adjacent to the first electrode pad, and the first and second electrode pads are used to provide different potentials. The LED chip includes a first electrode and a second electrode located on opposite sides, the first electrode being electrically connected to the first electrode pad. The upper substrate is on the lower substrate and the LED chip, and includes a carrier plate, an upper embankment structure, and a transparent conductive layer. The carrier plate has a surface facing the lower substrate. The upper embankment structure is disposed on the surface. The transparent conductive layer covers the surface of the carrier plate and the upper embankment structure, and the transparent conductive layer is electrically connected to the second electrode and the second electrode pad.

[0004] In some embodiments, the side of any of the upper embankment structures forms an angle with the surface of the carrier plate, the angle being less than or equal to 50 degrees.

[0005] In some embodiments, the lower substrate further includes a plurality of lower embankment structures arranged on the dielectric layer, with the lower embankment structures below the upper embankment structures.

[0006] In some embodiments, the display panel further includes a conductive material whose vertical projection on the lower substrate overlaps with multiple vertical projections of the upper embankment structure on the lower substrate, and electrically connects the transparent conductive layer and the second electrode pad.

[0007] In some embodiments, the conductive material is a metal or a conductive adhesive.

[0008] In some implementations, the height of the conductive material is approximately equal to the height of the lower embankment structure.

[0009] In some implementations, the upper embankment structure is made of light-absorbing material.

[0010] In some implementations, the lower embankment structure is made of reflective material.

[0011] In some implementations, the display panel also includes a reflective layer located between the upper embankment structure and the transparent conductive layer.

[0012] In some embodiments, one of the upper embankment structures includes an upper part and a lower part, the lower part of the upper embankment structure is adjacent to the lower embankment structure, the vertical projection of the upper part onto the lower substrate overlaps with the vertical projection of the lower part onto the lower substrate, and the vertical projection of the lower part onto the lower substrate overlaps with the vertical projection of the second electrode pad onto the lower substrate.

[0013] In some embodiments, one of the upper embankment structures comprises an upper part and a lower part, and a second embankment structure of the upper embankment structure is adjacent to the lower embankment structure.

[0014] In summary, some embodiments of this disclosure can be used to reduce the risk of breakage in the transparent conductive layer of a display panel. Specifically, the slope of the transparent conductive layer can be reduced to decrease the risk of breakage. This, in turn, reduces the likelihood of LED chips failing due to breakage in the transparent conductive layer. Attached Figure Description

[0015] Figure 1 A cross-sectional view of a display panel illustrating some embodiments of the present disclosure is shown.

[0016] Figure 2 Show Figure 1 A cross-sectional view of a light-emitting diode crystal.

[0017] Figure 3A Show Figure 1 A bottom view of the upper substrate.

[0018] Figure 3B Show Figure 1 Top view of the lower substrate.

[0019] Figures 4 to 7 A cross-sectional view showing the process of manufacturing a display panel.

[0020] Figure 8 A cross-sectional view of a display panel showing some other embodiments of this disclosure is shown.

[0021] Figure 9 Show Figure 8 A cross-sectional view of a light-emitting diode crystal.

[0022] Figure 10A Show Figure 8 A bottom view of the upper substrate.

[0023] Figure 10B Show Figure 8 Top view of the lower substrate.

[0024] Figure 11 A cross-sectional view of a display panel showing some other embodiments of this disclosure is shown.

[0025] Figure 12 A cross-sectional view of a display panel showing some other embodiments of this disclosure is shown.

[0026] Figure 13 A cross-sectional view of a display panel showing some other embodiments of this disclosure is shown.

[0027] Explanation of reference numerals in the attached figures:

[0028] 10: Display panel

[0029] 10A: Display panel

[0030] 10B: Display panel

[0031] 10C: Display panel

[0032] 100: Lower base plate

[0033] 100': lower base plate

[0034] 110: Dielectric layer

[0035] 112: Dielectric layer

[0036] 120: First electrode pad

[0037] 130: Second electrode pad

[0038] 140: Substrate

[0039] 150: Active Component

[0040] 160: Lower embankment structure

[0041] 170: First through hole component

[0042] 180: Second through hole component

[0043] 200: Light Emitting Diode Chip

[0044] 200B: Light Emitting Diode Chip

[0045] 200G: Light Emitting Diode Chip

[0046] 200R: Light Emitting Diode Chip

[0047] 210: First electrode

[0048] 212: First Floor

[0049] 214: Second layer

[0050] 220: Second electrode

[0051] 222: First Floor

[0052] 224: Second layer

[0053] 230: Epitaxial layer

[0054] 232: N-type semiconductor layer

[0055] 234: Multiple Quantum Wells

[0056] 236: P-type semiconductor layer

[0057] 240: Insulation layer

[0058] 300: Upper base plate

[0059] 310: Carrier board

[0060] 310S: Surface

[0061] 320: Upper embankment structure

[0062] 320S: Side View

[0063] 322: First Embankment Structure

[0064] 324: Second Embankment Structure

[0065] 326: Upper part

[0066] 326S: Side View

[0067] 328: Lower part

[0068] 328S: Side View

[0069] 330: Transparent conductive layer

[0070] 340: Reflective layer

[0071] 400: Conductive material

[0072] 402: Sealant

[0073] 404: Conductive sphere

[0074] 500: Adhesive layer

[0075] a1: included angle

[0076] a2: included angle

[0077] a3: included angle

[0078] D1: First Direction

[0079] H1: Height

[0080] H2: Height

[0081] H4: Height

[0082] H5: Height

[0083] H6: Height

[0084] H7: Height Detailed Implementation

[0085] To enable those skilled in the art to further understand this disclosure, preferred embodiments of the disclosure are described below, and the composition and desired technical effects of the disclosure are explained in detail with reference to the accompanying drawings.

[0086] Some embodiments of this disclosure can be used to reduce the risk of breakage in the transparent conductive layer of a display panel. Specifically, the slope of the transparent conductive layer can be reduced to decrease the risk of breakage. This, in turn, reduces the likelihood of LED chips failing due to breakage in the transparent conductive layer.

[0087] Figure 1 A cross-sectional view of a display panel 10 according to some embodiments of the present disclosure is shown. The display panel 10 includes a lower substrate 100, a light-emitting diode chip 200, and an upper substrate 300. The lower substrate 100 includes a dielectric layer 110, a first electrode pad 120, and a second electrode pad 130. The upper substrate 300 is on the lower substrate 100 and the light-emitting diode chip 200, and the upper substrate 300 includes a carrier plate 310 and a transparent conductive layer 330.

[0088] The lower substrate 100 may be a panel containing driving elements. The lower substrate 100 includes a plurality of dielectric layers 110 stacked from bottom to top, and the dielectric layers 110 may be formed on the substrate 140. In some embodiments, such as Figure 1 As shown, the lower substrate 100 may include an active element 150, such as a thin-film transistor (TFT). In other embodiments, the lower substrate 100 may also include other driving elements such as a microchip, or the active element may not be located in such a position as... Figure 1 As shown, active elements may be located below substrate 140 and drive display panel 10 via double-sided wiring. A first electrode pad 120 is located on dielectric layer 110. A second electrode pad 130 is located on dielectric layer 110, adjacent to the first electrode pad 120, and the first electrode pad 120 and the second electrode pad 130 are used to provide different potentials. In some embodiments, lower substrate 100 includes dielectric layer 112 between dielectric layers 110, and dielectric layer 112 may be made of silicon nitride. Lower substrate 100 also includes a plurality of lower embankment structures 160 arranged on dielectric layer 110.

[0089] The light-emitting diode (LED) chip 200 includes a first electrode 210 and a second electrode 220 located on opposite sides. The first electrode 210 is electrically connected to a first electrode pad 120, and both the first electrode 210 and the second electrode 220 have an epitaxial layer 230. Specifically, the lower substrate 100 may further include a first through-hole 170 and a second through-hole 180. The first through-hole 170 and the second through-hole 180 are located in a dielectric layer 110. The first through-hole 170 is electrically connected to the active element 150 and the first electrode 210 of the LED chip 200. The second through-hole 180 is electrically connected to a ground electrode (not shown) and the second electrode 220 of the LED chip 200A. It should be noted that although... Figure 1 The second vias 180 shown are not interconnected on different dielectric layers 110, but are different from those on the second vias 180. Figure 1 In the cross-section shown, the second through-holes 180 on different dielectric layers 110 are still interconnected.

[0090] The upper substrate 300 may be a substrate that electrically connects the second electrode 220 of the light-emitting diode chip 200 to the second electrode pad 130 of the lower substrate 100. The upper substrate 300 includes a carrier plate 310 having a surface 310S facing the lower substrate 100. A plurality of upper embankment structures 320 are disposed on the surface 310S. A transparent conductive layer 330 covers the surface 310S of the carrier plate 310 and the upper embankment structures 320. The transparent conductive layer 330 is electrically connected to the second electrode 220 and is electrically connected to the second electrode 220 through a conductive material 400. In other words, the transparent conductive layer 330 electrically connects the second electrode 220 and the second electrode pad 130.

[0091] The lower embankment structure 160 of the lower substrate 100 is below the upper embankment structure 320. In some embodiments, the vertical projection of the lower embankment structure 160 onto the lower substrate 100 overlaps with the vertical projection of the upper embankment structure 320 onto the lower substrate 100. More specifically, the upper embankment structure 320 includes a first embankment structure 322 and a second embankment structure 324. The vertical projection of the first embankment structure 322 onto the lower substrate 100 overlaps with multiple vertical projections of the lower embankment structure 160 onto the lower substrate 100, and the vertical projection of the second embankment structure 324 onto the lower substrate 100 overlaps with the vertical projection of the second electrode pad 130 onto the lower substrate 100. The height H1 of the first embankment structure 322 is the same as the height H2 of the second embankment structure 324. The height H4 of the LED chip 200 is equal to the distance between the transparent conductive layer 330 and the first electrode pad 120 on the carrier plate 310, so as to ensure that the LED chip 200 can be electrically connected to the transparent conductive layer 330 and the first electrode pad 120 at the same time.

[0092] The display panel 10 also includes a conductive material 400. The vertical projection of the conductive material 400 onto the lower substrate 100 overlaps with the vertical projection of the upper embankment structure 320 onto the lower substrate 100, and electrically connects the transparent conductive layer 330 and the second electrode pad 130. The height H5 of the conductive material 400 is equal to the distance between the transparent conductive layer 330 and the second electrode pad 130 on the upper embankment structure 320, ensuring that the conductive material 400 can simultaneously electrically connect the transparent conductive layer 330 and the second electrode pad 130. In some embodiments, the conductive material 400 is a metal or a conductive adhesive. For example, Figure 1 In this embodiment, the conductive material 400 is a conductive adhesive, and it is composed of a sealant 402 and conductive balls 404. The conductive balls 404 are uniformly distributed in the sealant 402. The sealant 402 may be an acrylic-epoxy resin, a photoinitiator, a thermosetting agent, a coupling agent, a filler, a combination thereof, or the like. The conductive balls 404 may be spherical objects with nickel and gold layers sequentially coated on their surfaces, and can be used to electrically connect the second electrode pad 130 and the transparent conductive layer 330.

[0093] Because the height H4 of the LED chip 200 is essentially equal to the distance between the transparent conductive layer 330 on the carrier plate 310 and the first electrode pad 120, and the transparent conductive layer 330 is formed only on the surface of the upper embankment structure 320, the slope of the transparent conductive layer 330 is relatively small. The electrical connection between the upper embankment structure 320 and the second electrode pad 130 is through the conductive material 400, making the transparent conductive layer 330 less prone to breakage due to an excessively steep slope, thus preventing the LED chip 200 from failing. In some embodiments, the side 320S of any of the upper embankment structures 320 forms an angle α1 with the surface 310S of the carrier plate 310, where the angle α1 is less than or equal to 50 degrees. When the angle α1 is less than or equal to 50 degrees, the slope of the transparent conductive layer 330 is smaller, making it less prone to breakage. Conversely, when the angle α1 is greater than 50 degrees, the probability of the transparent conductive layer 330 breaking increases.

[0094] In some embodiments, the upper embankment structure 320 and the lower embankment structure 160 may be made of suitable materials, and their shapes are designed to enhance the visual experience of the display panel 10. In some embodiments, the upper embankment structure 320 and the lower embankment structure 160 may be made of different materials. For example, the lower embankment structure 160 may be a reflective material to reflect light emitted from the side of the light-emitting diode chip 200 upwards, thereby improving the upward light emission efficiency of the display panel 10. The upper embankment structure 320 may be a light-absorbing material to absorb ambient light incident from the outside of the display panel 10, thereby reducing interference caused by ambient light to the display panel 10. Furthermore, the upper embankment structure 320 may be an inverted trapezoid, and the lower embankment structure 160 may be a regular trapezoid. For example, the width of the upper embankment structure 320 gradually decreases towards the lower substrate 100, while the width of the lower embankment structure 160 gradually increases towards the lower substrate 100. Therefore, the sloping sides of the trapezoidal shape of the lower embankment structure 160 help to reflect light emitted from the side of the LED chip 200 upwards. The inverted trapezoidal shape of the upper embankment structure 320 has a larger upper surface, which also allows for more effective absorption of ambient light incident from outside the display panel 10. In some embodiments, the upper embankment structure 320 may be formed of a black organic material with an optical density of not less than 1.0, for example, an optical density of 2.0. The lower embankment structure 160 may be formed of a white organic material with a reflectivity of not less than 50%, for example, a reflectivity greater than or equal to 70%. The upper embankment structure 320 and the lower embankment structure 160 may also be made of compressible materials. In some embodiments, the compression ratio of the materials of the upper embankment structure 320 and the lower embankment structure 160 is between 80% and 90%. Therefore, before the upper substrate 300 and the lower substrate 100 are assembled together, the combined thickness of the upper embankment structure 320 and the lower embankment structure 160 is relatively large. After the upper substrate 300 and the lower substrate 100 are assembled together, the thickness of the upper embankment structure 320 and the lower embankment structure 160 is compressed, allowing the transparent conductive layer 330 of the upper substrate 300 to reliably contact the conductive material 400.

[0095] The display panel 10 also includes an adhesive layer 500. The adhesive layer 500 is located between the upper substrate 300 and the lower substrate 100 to bond the upper substrate 300 and the lower substrate 100 and provide support. In some embodiments, the adhesive layer 500 may be made of a sealant doped with a small amount of support material. The sealant of the adhesive layer 500 may be an acrylic-epoxy resin, a photoinitiator, a thermosetting agent, a coupling agent, a filler, a combination thereof, or the like, to bond the upper substrate 300 and the lower substrate 100. The support material may be an object that provides support, such as fibers or silicon balls, and the size of the support material may be selected according to the target height between the upper substrate 300 and the lower substrate 100.

[0096] Figure 2 Show Figure 1 A cross-sectional view of a light-emitting diode (LED) chip 200. The LED chip 200 includes a first electrode 210, a second electrode 220, an epitaxial layer 230, and an insulating layer 240. The first electrode 210 includes a first layer 212 and a second layer 214, with the second layer 214 between the first layer 212 and the epitaxial layer 230. The first layer 212 and the second layer 214 of the first electrode 210 may be made of conductors. In some embodiments, the first layer 212 may be made of nickel, tin, gold, or a combination thereof. The second layer 214 may be made of aluminum. The second electrode 220 may be made of a transparent conductive layer, such as indium tin oxide (ITO), such that when the LED chip 200 emits light upwards (i.e., towards...), it... Figure 1 and Figure 2 Light can still penetrate the second electrode 220 (in the direction of the second electrode 220). The epitaxial layer 230 is located between the first electrode 210 and the second electrode 220. The width of the epitaxial layer 230 can become narrower as it approaches the second electrode 220; that is, the epitaxial layer 230 can be trapezoidal. The epitaxial layer 230 may include an N-type semiconductor layer 232, a multiple-quantum-well (MQW) layer 234, and a P-type semiconductor layer 236. In some embodiments, the N-type semiconductor layer 232 and the P-type semiconductor layer 236 may be N-type doped gallium nitride and P-type doped gallium nitride, respectively. An insulating layer 240 is located on the sidewall of the epitaxial layer 230 and covers a portion of the second electrode 220. In some embodiments, the insulating layer 240 may be an oxide layer.

[0097] Figure 3A Show Figure 1 A bottom view of the upper substrate 300. Figure 3B Show Figure 1 A top view of the lower substrate 100. Figure 3AIn the upper substrate 300, the upper embankment structures 320 are arranged along the first direction D1 on the surface 310S of the carrier plate 310. Multiple upper embankment structures 320 (e.g., but not limited to three) can form a unit, and each unit of upper embankment structure 320 has a large space between it. This large space is used to accommodate the light-emitting diode chip 200. A transparent conductive layer 330 covers the surface 310S of the carrier plate 310 and the upper embankment structures 320.

[0098] exist Figure 3B In the lower substrate 100, lower embankment structures 160 are arranged along a first direction D1 on the dielectric layer 110, and the distance between each lower embankment structure 160 is approximately the same. Each lower embankment structure 160 can correspond to one of the upper embankment structures 320. A light-emitting diode (LED) chip 200 can be located between two adjacent lower embankment structures 160, and the LED chip 200 can be accommodated within the space between the upper embankment structures 320. In some embodiments, the LED chip 200 can include LED chips 200R, 200B, and 200G that emit different colors of light, and the LED chips 200R, 200B, and 200G can also be arranged along the first direction D1 and each located between two adjacent lower embankment structures 160. A conductive material 400 can also be located between two adjacent lower embankment structures 160, and the conductive material 400 corresponds to one of the upper embankment structures 320. The adhesive layer 500 is located on the periphery of the lower substrate 100, and can therefore be used to bond the lower substrate 100 and the upper substrate 300.

[0099] Figures 4 to 7 A cross-sectional view showing the process of manufacturing the display panel 10. Figure 4 In the middle, a lower substrate 100' is provided.

[0100] exist Figure 5 In this process, a lower embankment structure 160 is formed on the lower substrate 100' to form the lower substrate 100, and the lower embankment structure 160 does not cover the first electrode pad 120 and the second electrode pad 130. Details of the lower substrate 100 are as follows: Figure 1 As mentioned above, it will not be repeated here.

[0101] exist Figure 6 In this process, the light-emitting diode chip 200 is transferred onto the first electrode pad 120, so that the first electrode pad 120 of the lower substrate 100 is connected to the first electrode 210 of the light-emitting diode chip 200.

[0102] exist Figure 7In this process, a conductive material 400 is formed on the second electrode pad 130 of the lower substrate 100, and an adhesive layer 500 is formed around the lower substrate 100. Then, an upper substrate 300 is placed on the lower substrate 100, so that the second electrode pad 130 of the lower substrate 100 is connected to the second electrode 220 of the light-emitting diode chip 200 through the conductive material 400 and the transparent conductive layer 330 to form a display panel 10. Since the transparent conductive layer 330 has been formed on the upper substrate 300 beforehand, when the upper substrate 300 is placed directly on the lower substrate 100, the second electrode pad 130 and the second electrode 220 can be connected simultaneously without forming additional material around the light-emitting diode chip 200 for electrical connection, thus avoiding the formation of additional material that could cause the light-emitting diode chip 200 to detach.

[0103] Figure 8 A cross-sectional view of a display panel 10A according to other embodiments of the present disclosure is shown. The display panel 10A and... Figure 1 The display panel is similar to the display panel 10, but the difference lies in the structure of the light-emitting diode chip 200 in the display panel 10A, the position of the transparent conductive layer 330, and the position of the conductive material 400. Specifically, Figure 8 The first electrode 210 of the LED chip 200 of the display panel 10A is electrically connected to the first electrode pad 120 through the transparent conductive layer 330, and the second electrode 220 of the LED chip 200 of the display panel 10A is in direct contact with and electrically connected to the second electrode pad 130. Figure 1 The first electrode 210 of the LED chip 200 in the display panel 10 directly contacts and is electrically connected to the first electrode pad 120, and the second electrode 220 of the LED chip 200 in the display panel 10 is electrically connected to the second electrode pad 130 through the transparent conductive layer 330. Furthermore, Figure 8 The vertical projection of the second embankment structure 324 of the upper embankment structure 320 of the display panel 10A onto the lower substrate 100 overlaps with the vertical projection of the first electrode pad 120 onto the lower substrate 100. Figure 1 The vertical projection of the second embankment structure 324 of the upper embankment structure 320 onto the lower substrate 100 overlaps with the vertical projection of the second electrode pad 130 onto the lower substrate 100. In some embodiments, at least one upper embankment structure 320 and the lower embankment structure 160 are in direct contact.

[0104] Figure 9 Show Figure 8A cross-sectional view of a light-emitting diode (LED) chip 200. The LED chip 200 includes a first electrode 210, a second electrode 220, an epitaxial layer 230, and an insulating layer 240. The first electrode 210 may be made of a transparent conductive layer, such as indium tin oxide (ITO), so that when the LED chip 200 emits light upwards (i.e., towards...), it... Figure 8 and Figure 9 The first electrode 210 is positioned so that light can still penetrate it. The second electrode 220 includes a first layer 222 and a second layer 224, with the second layer 224 located between the first layer 222 and the epitaxial layer 230. The first layer 222 and the second layer 224 of the second electrode 220 may be made of conductors. In some embodiments, the first layer 222 may be made of nickel, tin, gold, or a combination thereof. The second layer 224 may be made of aluminum. The epitaxial layer 230 is located between the first electrode 210 and the second electrode 220. The width of the epitaxial layer 230 may increase as it gets closer to the first electrode 210, i.e., the epitaxial layer 230 may be an inverted trapezoid. The epitaxial layer 230 may include an N-type semiconductor layer 232, a multiple-quantum-well (MQW) layer 234, and a P-type semiconductor layer 236. In some embodiments, the N-type semiconductor layer 232 and the P-type semiconductor layer 236 may be N-type doped gallium nitride and P-type doped gallium nitride, respectively. An insulating layer 240 is located on the sidewall of the epitaxial layer 230 and covers a portion of the first electrode 210. In some embodiments, the insulating layer 240 may be an oxide layer.

[0105] Figure 10A Show Figure 8 A bottom view of the upper substrate 300. Figure 10B Show Figure 8 A top view of the lower substrate 100. Figure 10A In the upper substrate 300, the upper embankment structures 320 are arranged along a first direction D1 on the surface 310S of the carrier plate 310. Multiple upper embankment structures 320 (e.g., but not limited to three) can form a unit, and each unit of upper embankment structure 320 has a large space between it. This large space is used to accommodate the light-emitting diode chip 200. A transparent conductive layer 330 covers the surface 310S of the carrier plate 310 and the upper embankment structures 320. Figure 10A Unlike the upper substrate 300, Figure 3A The transparent conductive layer 330 of the upper substrate 300 is responsible for connecting the second electrode 220 of the light-emitting diode chip 200 to the second electrode pad 130 (i.e., the ground electrode), so the transparent conductive layer 330 can cover the entire upper embankment structure 320. On the other hand, Figure 10AThe transparent conductive layer 330 of the upper substrate 300 is responsible for connecting the first electrode 210 of the light-emitting diode chip 200 to the first electrode pad 120 and the active element 150. Therefore, the upper substrate 300 includes a plurality of transparent conductive layers 330, each transparent conductive layer 330 covering a portion of the upper embankment structure 320 and the space for accommodating the light-emitting diode chip 200. The transparent conductive layer 330 may also not cover a portion of the upper embankment structure 320.

[0106] exist Figure 10B In the lower substrate 100, lower embankment structures 160 are arranged along a first direction D1 on the dielectric layer 110, and the distance between each lower embankment structure 160 is approximately the same. Each lower embankment structure 160 corresponds to one of the upper embankment structures 320. A light-emitting diode (LED) chip 200 may be located between two adjacent lower embankment structures 160, and the LED chip 200 may be accommodated within the space between the upper embankment structures 320 and contact the transparent conductive layer 330. In some embodiments, the LED chip 200 may include LED chips 200R, 200B, and 200G that emit different colors of light, and the LED chips 200R, 200B, and 200G may also be arranged along the first direction D1 and each located between two adjacent lower embankment structures 160. A conductive material 400 may also be located between two adjacent lower embankment structures 160, and the conductive material 400 corresponds to one of the upper embankment structures 320. The adhesive layer 500 is located on the periphery of the lower substrate 100, and can therefore be used to bond the lower substrate 100 and the upper substrate 300.

[0107] Figure 11 A cross-sectional view of the display panel 10B according to other embodiments of the present disclosure is shown. The display panel 10B and... Figure 1 The display panel is similar to 10, the difference between the two is that... Figure 11 The conductive material 400 of the display panel 10B is metal, while Figure 1 The conductive material 400 of the display panel 10 is conductive adhesive.

[0108] Figure 12 A cross-sectional view of a display panel 10C according to other embodiments of the present disclosure is shown. The display panel 10C and... Figure 1 The display panel is similar to 10, the difference between the two is that... Figure 11One of the upper embankment structures 320 of the display panel 10B includes an upper portion 326 and a lower portion 328, with the lower portion 328 of the upper embankment structure 320 adjacent to the lower embankment structure 160. The vertical projection of the upper portion 326 onto the lower substrate 100 overlaps with the vertical projection of the lower portion 328 onto the lower substrate 100, and the vertical projection of the lower portion 328 onto the lower substrate 100 overlaps with the vertical projection of the second electrode pad 130 onto the lower substrate 100. The side surface 326S of the upper portion 326 of the upper embankment structure 320 and the side surface 328S of the lower portion 328 of the upper embankment structure 320 are not interconnected, and the transparent conductive layer 330 covers the upper portion 326 and the lower portion 328 of the upper embankment structure 320. The side 326S of the upper part 326 of the upper embankment structure 320 forms an angle α2 with the surface 310S of the carrier plate 310, and the side 328S of the lower part 328 of the upper embankment structure 320 forms an angle α3 with the surface 310S of the carrier plate 310. The angles α2 and α3 are less than or equal to 50 degrees. In some embodiments, the height H7 of the lower surface of the lower part 328 relative to the lower substrate 100 is less than the height H6 of the lower surface of the upper part 326 relative to the lower substrate 100. Therefore, the lower part 328 can be closer to the second electrode pad 130, so that the electrical connection between the transparent conductive layer 330 and the second electrode pad 130 can be completed without the need for a conductive material 400.

[0109] Figure 13 A cross-sectional view of a display panel 10D according to other embodiments of this disclosure is shown. The display panel 10D and... Figure 1 Similar to the display panel 10, the difference lies in that the display panel 10D also includes a reflective layer 340, located between the upper embankment structure 320 and the transparent conductive layer 330. The reflective layer 340 can be used to reflect the light emitted from the side of the light-emitting diode chip 200 upwards, further improving the upward light emission efficiency of the display panel 10. In some embodiments, the reflective layer 340 may be made of metal.

[0110] In summary, some embodiments of this disclosure can reduce the risk of open circuits in the transparent conductive layer of a display panel. For example, the display panel may include an upper substrate and a lower substrate. The transparent conductive layer may be formed only on the upper embankment structure of the upper substrate and electrically connected to the lower substrate via an additional conductive material. Therefore, the angle between the sidewall of the upper embankment structure of the upper substrate and the carrier surface of the upper substrate can be designed to be smaller to reduce the risk of open circuits in the transparent conductive layer. In this way, the light-emitting diode chips in the display panel are less likely to fail due to open circuits in the transparent conductive layer.

[0111] Although this disclosure has been presented above with reference to embodiments, it is not intended to limit this disclosure. Any person skilled in the art may make some changes and modifications without departing from the concept and scope of this disclosure. Therefore, the scope of protection of this disclosure shall be determined by the claims.

Claims

1. A display panel, comprising: A lower substrate, the lower substrate comprising: One dielectric layer; A first electrode pad is located on the dielectric layer; and A second electrode pad is located on the dielectric layer, adjacent to the first electrode pad, and the first electrode pad and the second electrode pad are used to provide different potentials; A light-emitting diode (LED) chip, the LED chip comprising a first electrode and a second electrode located on opposite sides, the first electrode being electrically connected to a first electrode pad; and An upper substrate is provided on the lower substrate and the light-emitting diode chip. The upper substrate includes: A carrier plate having a surface facing the lower substrate; Multiple upper embankment structures are set on this surface; and A transparent conductive layer covers the surface of the carrier plate and the upper embankment structure, and the transparent conductive layer electrically connects the second electrode and the second electrode pad.

2. The display panel of claim 1, wherein one side of any of the upper embankment structures forms an angle with the surface of the carrier plate, the angle being less than or equal to 50 degrees.

3. The display panel as claimed in claim 1 further comprises a conductive material, wherein a vertical projection of the conductive material on the lower substrate overlaps with a plurality of vertical projections of the upper embankment structures on the lower substrate, and electrically connects the transparent conductive layer and the second electrode pad.

4. The display panel as claimed in claim 3, wherein the conductive material is a metal or a conductive adhesive.

5. The display panel of claim 3, wherein the lower substrate further comprises a plurality of lower embankment structures arranged on the dielectric layer, the lower embankment structures being below the upper embankment structures.

6. The display panel of claim 5, wherein a height of the conductive material is approximately equal to a plurality of heights of the lower embankment structures.

7. The display panel of claim 5, wherein the lower embankment structure is made of a reflective material.

8. The display panel of claim 5, wherein one of the upper embankment structures comprises an upper portion and a lower portion, the lower portion of one of the upper embankment structures is adjacent to the lower embankment structures, a vertical projection of the upper portion onto the lower substrate overlaps with a vertical projection of the lower portion onto the lower substrate, and the vertical projection of the lower portion onto the lower substrate overlaps with a vertical projection of the second electrode pad onto the lower substrate.

9. The display panel of claim 1, wherein the upper embankment structures are light-absorbing materials.

10. The display panel of claim 1, further comprising a reflective layer located between the upper embankment structures and the transparent conductive layer.

Images