Vertical MOSFET and LED monolithic integrated chip and preparation method

Abstract

The present invention relates to a vertical MOSFET and LED monolithic integrated chip and a preparation method thereof, wherein the structure comprises epitaxially growing MOSFET and LED structures on a substrate material that can be used for GaN growth in sequence, and preparing a gate dielectric layer and a metal electrode layer required for MOSFET and LED through a semiconductor process flow. The present invention epitaxies a MOSFET structure and an LED structure once on a surface of a material that can be used for GaN growth, and the drain electrode of the MOSFET is shared with the p-electrode of the LED device, so that the MOSFET structure and the LED structure are connected in series, and the current passing through the MOSFET, that is, the current flowing through the LED, is regulated by the MOSFET gate, so as to achieve the purpose of MOSFET regulating the light emission of the LED, and form a vertical MOSFET-LED integrated chip.

Description

Technical Field

[0001] The invention belongs to the field of semiconductor optoelectronic technology and relates to a vertical MOSFET and LED monolithic integrated chip. Background Art

[0002] Large-scale optoelectronic integrated circuits have attracted extensive research in recent years. Compared with traditional off-chip packaging methods, this on-chip optoelectronic integration can reduce the parasitic capacitance and parasitic resistance of circuit connections, obtain higher-speed, more efficient, and more reliable devices, and can effectively reduce the size, weight, and manufacturing cost of the devices. GaN materials are widely used in the optoelectronic field due to their wide bandgap, high electron mobility, high thermal conductivity, and high stability. They are one of the most promising materials for optoelectronic integration. GaN materials have been widely used in the field of LED lighting and display, and their application in field-effect transistors has also developed rapidly, such as MOSFET, HEMT, etc. The realization of monolithic integration of LEDs and field-effect transistors will be of great significance to intelligent lighting, display, sensing, and visible light communication.

[0003] Traditional integration of LED and field effect transistor is mainly divided into two methods: selective epitaxy and selective etching. Selective epitaxy refers to growing FET epitaxial structure and LED epitaxial structure separately, and selectively growing the structure that needs epitaxy through mask. Selective etching refers to epitaxy of FET structure and LED structure at one time, and then selectively etching the top structure; such as LED-on-FET structure, selectively etching the LED structure above FET to expose the FET structure, forming a horizontal cascade HEMT-LED (MOSFET-LED).

[0004] The above methods are all lateral connections between field effect transistors and LEDs, which not only have the problem of uneven current expansion, but also cannot meet the needs of higher resolution displays. How to further improve the performance and density of the device is of great significance to large-scale and high-density optoelectronic integration. Summary of the invention

[0005] Purpose of the invention: On one hand, a vertical MOSFET and LED monolithic integrated chip is provided to solve the above problems existing in the prior art. On the other hand, a method for preparing the above integrated chip is provided.

[0006] Technical solution:

[0007] According to one aspect of the present application, a vertical MOSFET and LED monolithic integrated chip is provided, wherein a MOSFET and LED structure, as well as a gate dielectric layer and a metal electrode layer are sequentially prepared on the upper surface of a GaN grown substrate material, and the chip is characterized in that:

[0008] The MOSFET structure includes a buffer layer, a current expansion layer, a drift layer and a channel layer stacked in sequence from bottom to top.

[0009] The LED structure is stacked from bottom to top. + -GaN electronic layer, InGaN / GaN multiple quantum well layer, p-AlGaN electronic barrier layer and p + -GaN vacancy layer,

[0010] The drain electrode of the MOSFET structure is shared with the p-electrode of the LED structure, so that the MOSFET structure and the LED structure are connected in series. The current passing through the MOSFET structure is regulated by the gate of the MOSFET structure, so as to achieve the purpose of regulating the light emission of the LED by the MOSFET structure.

[0011] The method for preparing the vertical MOSFET and LED monolithic integrated chip comprises the following steps:

[0012] S1, growing a MOSFET structure and an LED structure on the surface of a substrate;

[0013] S2, using ICP technology, photoresist as mask, passing Cl2 and BCl3 mixed gas, anisotropic etching p + -GaN hole layer, p-AlGaN electron blocking layer, InGaN / GaN multi-quantum well layer and part of n + -GaN electronics;

[0014] S3, using ICP technology, photoresist as mask, etch MOSFET structure to n + -GaN drift layer, the MOSFET source structure formed vertically penetrates the n + -GaN electron layer, p-GaN channel layer, n-GaN drift layer and part of n + -GaN current spreading layer;

[0015] S4, using EBE evaporated metal Ni as an etching mask, using ICP technology, selectively etching the MOSFET structure to the n-GaN drift layer, the formed MOSFET gate trench structure vertically penetrates the n-GaN layer. + -GaN electronic layer and p-GaN channel layer, after etching the gate trench, the obtained sample was wet treated with tetramethylammonium hydroxide solution;

[0016] S5, using ALD to deposit Al2O3 as a gate dielectric layer on the top surface of the MOSFET structure, the surface of the gate trench, and the surface of the LED structure;

[0017] S6. Using RIE technology and photoresist as a mask, MOSFET source and LED anode holes are etched on the device surface where the gate dielectric layer is deposited. Using EBE technology, Ti / Al / Ni / Au metal electrodes are evaporated in the etched contact holes and on the surface of the gate groove.

[0018] Beneficial effects: The present invention grows a MOSFET structure and an LED structure on a substrate material for growing GaN to achieve epitaxial growth of a single material. Compared with the traditional selective epitaxial method, this method can greatly reduce the complexity of growth; compared with the selective etching method, this method avoids the influence of damage to the material surface caused by etching on the device performance; the drain of the MOSFET structure of the vertical MOSFET-LED device is shared with the p-electrode of the LED structure, and the current input into the LED is controlled by adjusting the gate voltage, thereby adjusting the luminous intensity of the LED to achieve vertical integration of the MOSFET and LED structures. This vertical MOSFET-LED device not only optimizes the problem of uneven current expansion in the lateral structure, but also greatly reduces the area and cost of the integrated device, which is of great significance to intelligent lighting, display, sensing and visible light communication. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 This is a schematic diagram of Embodiment 1 of the present invention.

[0020] Figure 2 It is an equivalent schematic diagram of the first embodiment of the present invention.

[0021] Figure 3 This is a schematic diagram of Embodiment 2 of the present invention.

[0022] Figure 4 This is an equivalent schematic diagram of the second embodiment of the present invention. DETAILED DESCRIPTION

[0023] like Figure 1 and Figure 2 As shown, the technical principle and technical details of Example 1 are described. It should be noted that since the structures in Example 1 and Example 2 can be made of different materials, or have multiple implementation methods, the reference numerals of Example 1 and Example 2 are numbered separately.

[0024] Embodiment 1

[0025] Example 1-1: A vertical MOSFET and LED monolithic integrated chip of a III-nitride semiconductor, in which the drain electrode of the MOSFET is shared with the p-electrode of the LED, so that the MOSFET structure and the LED structure are connected in series, and the current passing through the MOSFET, that is, the current flowing through the LED, is regulated by the MOSFET gate, thereby achieving the purpose of controlling the LED light emission.

[0026] Specifically, a vertical MOSFET and LED monolithic integrated chip of group III nitride semiconductor is provided, which includes a substrate material that can be used for GaN growth, and a MOSFET and LED structure and a gate dielectric layer and a metal electrode layer corresponding to the device are sequentially prepared on the upper surface. The MOSFET structure includes a buffer layer, a current expansion layer, a drift layer, and a channel layer stacked in sequence from bottom to top; the LED structure includes n + -GaN electronic layer, InGaN / GaN multi-quantum well layer, p-AlGaN electronic barrier layer, p + -GaN vacancy layer.

[0027] In a preferred embodiment, the substrate material for growing GaN includes sapphire, Si, a self-supporting GaN substrate, SiC, Ga2O3, and an AlN substrate.

[0028] In a preferred embodiment, in the MOSFET structure, the buffer layer includes n - -GaN, the current spreading layer includes n + -GaN or n + -AlGaN, the drift layer comprises n-GaN or n-AlGaN, and the channel layer comprises p-GaN or p-AlGaN. Further preferably, the Al x Ga 1-x The Al component in N is adjustable, where 0≤x≤1.

[0029] In a preferred embodiment, in the MOSFET structure, the buffer layer thickness is set to 0.5-10 um, the current spreading thickness is set to 0.1-4 um, the drift layer thickness is set to 0.5-20 um, and the channel layer thickness is set to 0.05-1 um.

[0030] In a preferred embodiment, in the MOSFET structure, n + -The electron concentration in the GaN current spreading layer is set to 1*10 17 -1*10 19 cm -3 , the electron concentration in the n-GaN drift layer is set to 1*10 14 -1*10 16 cm -3 , the hole concentration in the p-GaN channel layer is set to 1*10 15 -1*10 18 cm -3 , n + -The electron concentration in the GaN current spreading layer is set to 1*10 17 -1*10 19 cm -3 .

[0031] In a preferred embodiment, in the LED structure, the size of the LED is set to 0.1-1000 um.

[0032] In a preferred embodiment, in the LED structure, n + The thickness of the p-GaN electron layer is set to 2-4um, the thickness of the InGaN / GaN multi-quantum well layer is set to 10-250nm, and the thickness of the p-AlGaN electron barrier layer is set to 5-100nm. + -GaN hole layer thickness is set to 10 to 1000nm. Further preferably, the In x Ga 1-x The In component x in N is adjustable, where 0≤x≤1.

[0033] In a preferred embodiment, the gate dielectric layer is one or more of SiO2, Si3N4, Al2O3, HfO2 and the like.

[0034] In a preferred embodiment, in the MOSFET metal electrode layer, the source electrode, drain electrode and gate electrode of the MOSFET are one or more of Cr, Ti, Al, Ni, Au, Pt, Pd, V, etc.

[0035] The steps of preparing the above integrated chip include:

[0036] A1. Growing a MOSFET structure and an LED structure on the surface of a sapphire substrate 101. The MOSFET structure includes n - -GaN buffer layer 102, n + -GaN drift layer 103, n-GaN barrier layer 104, p-GaN channel layer 105, the LED structure includes n-GaN drift layer 103, n-GaN barrier layer 104, p-GaN channel layer 105, and ... + -GaN electron layer 106, InGaN / GaN multi-quantum well layer 107, p-AlGaN electron barrier layer 108, p-GaN hole layer 109. In the MOSFET structure, n - -GaN buffer layer 2 has a thickness of 2um and an electron concentration of 1*10 16 cm -3 , n + -GaN drift layer 3 has a thickness of 1um and an electron concentration of 1*10 19 cm -3 , the thickness of n-GaN barrier layer 4 is 4um, and the electron concentration is 2*10 16 cm -3 , the thickness of the p-GaN channel layer 5 is 350nm, and the hole concentration is 1*10 18 cm -3 .

[0037] A2. In the LED structure, the LED size is set to 100um, the thickness of the InGaN / GaN multi-quantum well layer 107 is 350nm, the thickness of the p-AlGaN electron blocking layer 108 is 100nm, and the thickness of the p-GaN hole layer 109 is 500nm, where x in the InxGa1-xN in the multi-quantum well layer 107 is set to 0.28.

[0038] A2. Using ICP technology, photoresist as mask, introducing a mixed gas of Cl2 and BCl3, anisotropically etching p + -GaN hole layer 109, p-AlGaN electron blocking layer 108, InGaN / GaN multi-quantum well layer 107 and part of n-AlGaN electron blocking layer 108 + -GaN electronics.

[0039] A3. Using ICP technology, photoresist is used as a mask to etch the MOSFET structure to n + -GaN drift layer, the MOSFET source structure formed vertically penetrates the n + -GaN electron layer 106, p-GaN channel layer 105 and n-GaN drift layer 104 and part of n + -GaN current spreading layer 103. Using RTA rapid annealing technology, the obtained sample was rapidly annealed at 700°C for 15 minutes in an atmosphere of N2:O2=4:1.

[0040] A4. Using EBE-evaporated metal Ni as an etching mask, ICP technology is used to selectively etch the MOSFET structure to the n-GaN drift layer 104. The formed MOSFET gate trench structure vertically penetrates the n-GaN layer. + -GaN electron layer 106 and p-GaN channel layer 105, such as Figure 4 After the gate trench is etched, the obtained sample is wet treated with a tetramethylammonium hydroxide solution, the concentration of the tetramethylammonium hydroxide solution is 10%, the wet treatment temperature is 85°, and the wet treatment time is 90 minutes.

[0041] A5. ALD is used to deposit Al2O3 as a gate dielectric layer 110 on the top surface of the MOSFET structure, the surface of the gate trench, and the surface of the LED structure.

[0042] A6. Using RIE technology and photoresist as a mask, MOSFET source and LED anode holes are etched on the device surface where the gate dielectric layer is deposited. Using EBE technology, Ti / Al / Ni / Au metal electrodes 111 are evaporated in the etched contact holes and on the surface of the gate grooves.

[0043] Example 1-2: The difference between a III-nitride semiconductor vertical MOSFET and LED monolithic integrated chip described in Example 1-1 is that:

[0044] The MOSFET structure is a stack of n - -GaN buffer layer 202, n + -AlGaN drift layer 203, n-AlGaN barrier layer 204, p-AlGaN channel layer 205, wherein Al x Ga 1-x The Al composition x in N is set to 0.2. The preparation method is carried out according to Example 1.

[0045] Embodiment 2

[0046] like Figure 3 and Figure 4 As shown, a vertical MOSFET and LED monolithic integrated chip based on TJ junction is proposed, including: setting a TJ tunneling junction structure on an LED epitaxial wafer, etching to form a through-TJ tunneling junction, InGaN / GaN multi-quantum well 204 and part of n + - Multiple orderly arranged basic units of GaN203, which can be used as multi-quantum well LEDs and vertically structured GaN MOSFETs.

[0047] The vertical structure of the GaN MOSFET drain electrode is set in the LED p + -GaN6 is shared with the p-electrode, a source electrode is set on the top of the vertical GaN MOSFET, and a gate dielectric layer 210 and a gate electrode metal layer are set on the side wall of the MOSFET. The TJ tunneling junction is set on the LED epitaxial wafer, which is conducive to the current expansion on the p-GaN surface in the LED. At the same time, this structure can be used to prepare MOSFET devices. The MOSFET drain electrode prepared by this structure is shared with the p-electrode of the LED device, so that the MOSFET structure and the LED structure are connected in series, and the current flowing into the LED device is controlled by the MOSFET gate electrode, so as to achieve the purpose of controlling the light emission of the LED and realize the monolithic integration of MOSFET and LED.

[0048] The thickness of the u-GaN buffer layer is set to 1-4um; + -GaN electron thickness is set to 2-4um; InGaN / GaN multi-quantum well thickness is set to 50-250nm; p-AlGaN electron barrier thickness is set to 5-100nm; + -GaN hole layer thickness is set to 10-1000nm, where In x Ga 1-x In N / GaN multiple quantum wells, 0≤x≤1.

[0049] In a preferred embodiment, the TJ tunnel junction comprises p ++ -GaN tunneling layer, n ++ -GaN tunneling layer and n + -GaN electronic layer.

[0050] In a further preferred embodiment, the p ++ -GaN tunneling layer thickness is set to 5-50nm, and doping concentration is set to 1*10 18 -1*10 21 cm -3 ;n ++ -GaN tunneling thickness is set to 5-50nm, and doping concentration is set to 1*10 18 -1*10 21 cm -3 ;n + -GaN electron layer thickness is set to 100-1000nm, and doping concentration is set to 1*10 17 -1*10 19 cm -3 .

[0051] In a preferred embodiment, the size of the orderly arranged basic units is set to 0.01-1000um.

[0052] In a preferred embodiment, the MOSFET sidewall inclination angle is less than 90°.

[0053] In a preferred embodiment, the gate dielectric layer is one or more of SiO2, Si3N4, Al2O3, HfO2, etc.

[0054] In a preferred embodiment, the drain electrode, source electrode and gate electrode of the GaN MOSFET are one or more of Cr, Ti, Al, Ni, Au, Pt, Pd, V and the like.

[0055] In the present technical solution, the LED epitaxial wafer includes a u-GaN buffer layer 202 grown from bottom to top on a sapphire substrate 201, and the thickness of the u-GaN buffer layer 202 is set to 2 um; + -GaN electron layer 203, its thickness is set to 2um; InGaN / GaN multi-quantum well layer 204, its thickness is set to 250nm, p-AlGaN electron blocking layer 205, its thickness is set to 50nm; p-GaN hole layer 206, its thickness is set to 350nm. x Ga 1-x In the N / GaN MQW, x is set to 0.28.

[0056] In a further embodiment, the substrate material for GaN growth may also be Si, a self-supporting GaN substrate, SiC, Ga2O3, or an AlN substrate.

[0057] In this embodiment, the TJ tunnel junction includes p ++ -GaN tunneling layer 207, the thickness of which is set to 15 nm; n ++ -GaN tunneling layer 208, the thickness of which is set to 20nm and n + - GaN electronic layer 209, the thickness of which is set to 200 nm.

[0058] In a further embodiment, the size of the orderly arranged basic unit is set to 100um, the side wall inclination angle of the MOSFET is less than 90°, the gate dielectric layer is Al2O3, and the drain electrode, source electrode and gate electrode of the GaN MOSFET are Ti / Al / Ni / Au.

[0059] In this embodiment, a TJ tunneling junction is grown on the LED epitaxial structure to simultaneously realize the two functions of LED light emission and MOSFET control. Compared with the traditional MOSFET-LED integrated device, this method can not only expand the p-GaN surface current through the TJ tunneling junction and improve the uniformity of the injected current, but also the structure can be used to prepare MOSFET to achieve the function of controlling the MicroLED current. The MOSFET drain electrode is shared with the p-electrode of the LED device, so that the MOSFET structure and the LED structure are connected in series. The MOSFET gate electrode can regulate the current passing through the MOSFET, that is, the current flowing into the LED, to achieve the purpose of controlling the LED light emission and realize the monolithic integration of MOSFET and LED. This monolithic integrated MOSFET-LED device has a simple growth structure and preparation process, which is of great significance in production and manufacturing.

[0060] The preferred embodiments of the present invention are described in detail above; however, the present invention is not limited to the specific details in the above embodiments. Within the technical concept of the present invention, various equivalent transformations can be made to the technical solutions of the present invention, and these equivalent transformations all belong to the protection scope of the present invention.

Claims

1. A method for preparing a vertical MOSFET and LED monolithic integrated chip, characterized in that: A vertical MOSFET and LED monolithic integrated chip includes a MOSFET structure and an LED structure, as well as a gate dielectric layer and a metal electrode layer, which are sequentially prepared on the upper surface of a GaN-grown substrate material; the MOSFET structure includes a buffer layer, a current expansion layer, a drift layer and a channel layer which are sequentially stacked from bottom to top; the LED structure includes n + -GaN electronic layer, InGaN / GaN multiple quantum well layer, p-AlGaN electronic barrier layer and p + -GaN hole layer; the drain electrode of the MOSFET structure is shared with the p-electrode of the LED structure, so that the MOSFET structure and the LED structure are connected in series, and the current passing through the MOSFET structure is regulated by the gate of the MOSFET structure, so as to achieve the purpose of regulating the light emission of the LED by the MOSFET structure; The method comprises the following steps: S1, growing a MOSFET structure and an LED structure on the surface of a substrate; S2, using ICP technology, photoresist as mask, passing Cl2 and BCl3 mixed gas, anisotropic etching p + -GaN hole layer, p-AlGaN electron blocking layer, InGaN / GaN multi-quantum well layer and part of n + -GaN electronic layer; S3, using ICP technology, photoresist as mask, etch MOSFET structure to n + -GaN current extension layer, forming the MOSFET source structure vertically penetrating the n + -GaN electron layer, p-GaN channel layer, n-GaN drift layer and part of n + -GaN current spreading layer; S4, using EBE evaporated metal Ni as an etching mask, using ICP technology, selectively etching the MOSFET structure to the n-GaN drift layer, the formed MOSFET gate trench structure vertically penetrates the n-GaN layer. + -GaN electronic layer and p-GaN channel layer, after etching the gate trench, the obtained sample was wet treated with tetramethylammonium hydroxide solution; S5, using ALD to deposit Al2O3 as a gate dielectric layer on the top surface of the MOSFET structure, the surface of the gate trench, and the surface of the LED structure; S6. Using RIE technology and photoresist as a mask, MOSFET source and LED anode holes are etched on the device surface where the gate dielectric layer is deposited. Using EBE technology, Ti / Al / Ni / Au metal electrode layers are evaporated in the etched contact holes and on the surface of the gate grooves.

2. The method for preparing a vertical MOSFET and LED monolithic integrated chip according to claim 1, characterized in that: In the MOSFET structure, the buffer layer thickness is set to 0.5-10 μm, the current spreading layer thickness is set to 0.1-4 μm, the drift layer thickness is set to 0.5-20 μm, and the channel layer thickness is set to 0.05-1 μm.

3. The method for preparing a vertical MOSFET and LED monolithic integrated chip according to claim 1, characterized in that: In the LED structure, n + The thickness of the p-GaN electron layer is set to 2~4μm, the thickness of the InGaN / GaN multi-quantum well layer is set to 10~250nm, the thickness of the p-AlGaN electron barrier layer is set to 5-100nm, and the p + -GaN vacancy layer thickness is set to 10~1000nm.

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