semiconductor diode

Abstract

This invention belongs to the field of semiconductor power device technology, and specifically discloses a semiconductor diode, including an n-type semiconductor layer; an anode metal layer located on the n-type semiconductor layer; a plurality of alternately spaced n-type pillars and p-type pillars located within the n-type semiconductor layer; a p-type body region located at the top of the p-type pillars; a low-carrier region, wherein the p-type body region within the low-carrier region forms a p-type Schottky diode with the anode metal layer; and a high-carrier region, wherein a p-type contact region is provided within the p-type body region within the high-carrier region, and the p-type contact region forms an ohmic contact with the anode metal layer.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor power device technology, and in particular relates to a semiconductor diode. Background Technology

[0002] Traditional semiconductor diodes have a large chip area and low current density. Currently, a superjunction structure is usually added to semiconductor diodes to increase chip current density and reduce chip area. However, conventional superjunction semiconductor diodes store too many minority carriers per unit area, and the voltage change is caused by the two-dimensional depletion effect. At the same time, the reverse recovery softness is too low, resulting in too large overshoot voltage during the reverse recovery process. Summary of the Invention

[0003] In view of this, the object of the present invention is to provide a semiconductor diode to reduce voltage spikes caused by the two-dimensional depletion effect in a semiconductor diode with a superjunction structure.

[0004] To achieve the above-mentioned objectives of this invention, this invention provides a semiconductor diode, comprising:

[0005] n-type semiconductor layer;

[0006] An anode metal layer located above the n-type semiconductor layer;

[0007] A plurality of alternately spaced n-type pillars and p-type pillars are located within the n-type semiconductor layer;

[0008] The p-shaped body region located at the top of the p-shaped column;

[0009] A low-carrier region, wherein the p-type body region within the low-carrier region forms a p-type Schottky diode with the anode metal layer;

[0010] The high carrier region includes a p-type contact region within the p-type body region, which forms an ohmic contact with the anode metal layer.

[0011] Optionally, the n-type pillar in the high-carrier region and the anode metal layer form an n-type Schottky diode.

[0012] Optionally, the low-carrier region is located at the edge of the active region of the semiconductor diode, and the high-carrier region is located in the middle region of the active region of the semiconductor diode.

[0013] Optionally, the width of the p-shaped body region is greater than the width of the p-shaped column.

[0014] The semiconductor diode of the present invention has a low-carrier region and a high-carrier region. During the reverse recovery process, the carriers in the low-carrier region are extracted first, and then the carriers in the high-carrier region are extracted. This allows the reverse breakdown voltage to gradually increase and avoids voltage jumps caused by two-dimensional depletion. Furthermore, an n-type Schottky diode is formed in the high-carrier region to inject majority carriers into the semiconductor diode, which can reduce the minority carrier storage quantity of the pn junction below the ohmic contact region and reduce the peak reverse recovery current. Attached Figure Description

[0015] To more clearly illustrate the technical solutions of exemplary embodiments of the present invention, the accompanying drawings used in describing the embodiments are briefly introduced below.

[0016] Figure 1 This is a cross-sectional structural schematic diagram of the first embodiment of the semiconductor diode provided by the present invention. Detailed Implementation

[0017] The technical solution of the present invention will be fully described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Furthermore, to clearly illustrate the specific implementation of the present invention, the schematic diagrams in the accompanying drawings are enlarged to show the thickness of the layers and regions described in the present invention, and the sizes of the figures do not represent actual dimensions.

[0018] Figure 1 This is a cross-sectional structural schematic diagram of the first embodiment of the semiconductor diode provided by the present invention, as shown below. Figure 1 As shown, the semiconductor diode of the present invention includes an n-type semiconductor layer 20, which is typically formed on an n-type substrate 10.

[0019] A plurality of alternating n-type pillars 22 and p-type pillars 21 are located within the n-type semiconductor layer 20, forming a charge-balanced superjunction structure between the n-type pillars 22 and the p-type pillars 21. A p-type body region 23 is located at the top of the p-type pillar 21, preferably with a width greater than the width of the p-type pillar 21.

[0020] The anode metal layer 25 and the insulating layer 26 located above the n-type semiconductor layer 20 serve as electrical insulation.

[0021] The semiconductor diode of the present invention includes two regions: a low-carrier region 31 and a high-carrier region 32. Within the low-carrier region 31, a p-type body region 23 contacts the anode metal layer 25 to form a p-type Schottky diode structure. Within the high-carrier region 32, a p-type contact region 24 is provided within the p-type body region 23, and the p-type contact region 24 contacts the anode metal layer 25 to form an ohmic contact structure. Preferably, the low-carrier region 31 is located at the edge region of the active region of the semiconductor diode, and the high-carrier region 32 is located in the middle region of the active region of the semiconductor diode. The low-carrier region 31 can be located in a portion of the edge region of the active region, or the entire edge region can be the low-carrier region 31. For example, the low-carrier region 31 can be located on one or both sides of the high-carrier region 32, or the low-carrier region 31 can surround the high-carrier region 32. For example... Figure 1 The diagram only shows the structure at the adjacent positions of the low carrier region 31 and the high carrier region 32, and does not show the structure of the low carrier region 31 and the high carrier region 32 from a global perspective.

[0022] In the reverse recovery process, the semiconductor diode of the present invention first extracts the carriers in the low carrier region and then extracts the carriers in the high carrier region. This allows the reverse breakdown voltage to gradually increase and avoids voltage jumps caused by two-dimensional depletion.

[0023] In the semiconductor diode of the present invention, within the high carrier region 32, the n-type pillar 22 can be made to contact the anode metal layer 25 to form an n-type Schottky diode. This can inject majority carriers into the semiconductor diode, reduce the minority carrier storage quantity of the pn junction below the ohmic contact region, and reduce the reverse recovery peak current.

[0024] The above specific implementation methods and embodiments are specific support for the technical concept of the present invention, and should not be used to limit the scope of protection of the present invention. Any equivalent changes or modifications made on the basis of the technical solution based on the technical concept proposed by the present invention shall still fall within the scope of protection of the technical solution of the present invention.

Claims

1. A semiconductor diode, characterized in that, include: n-type semiconductor layer; An anode metal layer located above the n-type semiconductor layer; A plurality of alternately spaced n-type pillars and p-type pillars are located within the n-type semiconductor layer; The p-shaped body region located at the top of the p-shaped column; A low-carrier region, wherein the p-type body region within the low-carrier region forms a p-type Schottky diode with the anode metal layer; A high carrier region, wherein a p-type contact region is provided within the p-type body region of the high carrier region, and the p-type contact region forms an ohmic contact with the anode metal layer; The low-carrier region is located at the edge of the active region of the semiconductor diode, and the high-carrier region is located in the middle region of the active region of the semiconductor diode.

2. The semiconductor diode as described in claim 1, characterized in that, The n-type pillars in the high-carrier region and the anode metal layer form an n-type Schottky diode.

3. The semiconductor diode as described in claim 1, characterized in that, The width of the p-shaped body region is greater than the width of the p-shaped column.

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