Super junction devices and methods of manufacturing the same

Abstract

The application discloses a super-junction device, which comprises at least two layers of trench filling type PN sub-columns, and has a blocking layer in at least a part of the super-junction structure; in the area with the blocking layer, a third epitaxial sub-layer of a first conductive type is formed between the upper and lower layers of the PN sub-columns; the blocking layer is located between the upper and lower layers of the second conductive type sub-columns; the second conductive type column with the blocking layer comprises at least one layer of the blocking layer; the breakdown voltage of each layer of the PN sub-columns above the blocking layer is a first voltage; the voltage at which the blocking layer is completely depleted is a second voltage; the second voltage is less than the first voltage; the third epitaxial sub-layer of the upper and lower layers of the first conductive type sub-columns forms a connecting layer, and the connecting layer is increased with ion implantation impurities of the first conductive type. The application further discloses a manufacturing method of the super-junction device. The application can reduce the Cds of the device when the Vds is very small, improve the Cgd and the reverse recovery characteristics of the body diode of the device, and also reduce the on-resistance.

Description

Technical Field

[0001] This invention relates to the field of semiconductor integrated circuit manufacturing, and in particular to a super junction device; this invention also relates to a method for manufacturing a super junction device. Background Technology

[0002] A superjunction structure is a structure consisting of alternating N-type and P-type pillars. If a superjunction structure replaces the N-type drift region in a vertical double-diffused metal-oxide-semiconductor (VDMOS) device, providing a conduction path in the on-state (only the N-type pillars provide the path, the P-type pillars do not), and withstands reverse bias in the off-state, a superjunction metal-oxide-semiconductor field-effect transistor (MOSFET) is formed. In the on-state, only the N-type pillars provide the conduction path, the P-type pillars do not provide a conduction path; the reverse bias voltage is shared by both the P-type and N-type pillars. Superjunction MOSFETs can significantly reduce the on-resistivity of a device by using a low-resistivity epitaxial layer, while maintaining the same reverse breakdown voltage as traditional VDMOS devices.

[0003] By forming trenches in an N-type epitaxial layer and filling the trenches with a P-type epitaxial layer, alternating P-type and N-type pillars, i.e., PN pillars, are formed, which is a manufacturing method for superjunctions that can be mass-produced.

[0004] To manufacture devices with higher reverse-bias breakdown voltage or lower specific on-resistance, a smaller PN pillar pitch or a deeper PN pillar is required. When using trench-filled P-type epitaxy, these requirements lead to two problems: First, a high trench aspect ratio makes trench etching problematic, especially since etching residue at the bottom of the trench cannot be completely cleaned after etching, causing device failure. Second, a large trench aspect ratio makes epitaxial filling more difficult, resulting in epitaxial voids or excessively long filling times, increasing manufacturing costs. Therefore, one approach in these situations is to divide the formation of the P-pillars into multiple or two stages, reducing the aspect ratio of each P-pillar (i.e., P-subpillar). This makes trench etching, cleaning, and filling processes feasible and cost-effective.

[0005] In existing methods, P-type sub-pillars formed one or more times are stacked vertically to form P-type pillars, thus achieving a fully superjunction high-voltage device. However, when the source-drain voltage (Vds) is very low, all P-type and N-type pillars undergo lateral depletion, resulting in high source-drain capacitance (Cds) or output capacitance (Coss), especially at very low Vds. Simultaneously, the lateral depletion of all P-type and N-type pillars at very low Vds leads to poor reverse recovery softness of the body diode or susceptibility to oscillation. These problems worsen as the step size decreases, reducing the Vds at which the P-type and N-type pillars are completely laterally depleted, further deteriorating the reverse recovery softness of the body diode. Furthermore, due to the smaller step size, the number of PN pillar units (superjunction units) increases for the same chip area, increasing the contact area of ​​the PN pillars in the superjunction structure, thus significantly increasing both Cds and Coss. Summary of the Invention

[0006] The technical problem to be solved by this invention is to provide a superjunction device that can reduce the source-drain capacitance (Cds) and thus reduce the output capacitance (Coss) when the source-drain voltage is very low. It can also achieve partial depletion of the superjunction structure thickness at a certain source-drain voltage, thereby improving the gate-drain capacitance and the reverse recovery characteristics of the body diode. Furthermore, it can maintain a high breakdown voltage and reduce the on-resistance. To this end, this invention also provides a method for manufacturing the superjunction device.

[0007] To solve the above-mentioned technical problems, the superjunction structure of the superjunction device provided by the present invention includes at least two layers of PN subpillars, and each layer of PN subpillars is formed by alternating arrangement of first conductivity type subpillars and second conductivity type subpillars.

[0008] The structure of each PN sub-pillar includes: a second conductivity type sub-pillar composed of a first epitaxial sub-layer of the second conductivity type filling a trench, wherein the trench forms a second epitaxial sub-layer of the first conductivity type, and the first conductivity type sub-pillar is composed of the second epitaxial sub-layer between each second conductivity type sub-pillar.

[0009] The superjunction structure has a blocking layer in at least a portion of its regions.

[0010] In the region having the blocking layer, a third epitaxial sublayer of a first conductivity type is formed between the upper and lower layers of the PN subpillars of the blocking layer; in the longitudinal direction, the bottom surface of the second conductivity type subpillar of the PN subpillar at the top of the blocking layer is located above or below the top surface of the third epitaxial sublayer, and the blocking layer is composed of the second epitaxial sublayer and the third epitaxial sublayer below the bottom surface of the second conductivity type subpillar of the top PN subpillar, or the third epitaxial sublayer; the first conductivity type subpillars and the third epitaxial sublayers of each layer of PN subpillars are stacked to form an electrically connected first conductivity type pillar, and the second conductivity type pillars of each layer of PN subpillars and the blocking layer are stacked to form a second conductivity type pillar with a blocking layer.

[0011] The second conductive type column with a blocking layer includes at least one blocking layer, which is located between two adjacent layers of the second conductive type sub-columns.

[0012] The breakdown voltage of each PN sub-pillar located above the blocking layer is the first voltage.

[0013] The voltage at which the blocking layer is completely depleted is the second voltage.

[0014] The process structure of the blocking layer is configured to satisfy the requirement that the second voltage is less than the first voltage. Before the reverse bias voltage borne by the superjunction structure is less than the second voltage, the second conductor type sub-pillars of each layer of PN sub-pillars located below the blocking layer in the region having the blocking layer are all floating structures. After the reverse bias voltage borne by the superjunction structure is greater than the second voltage and before it is less than the first voltage, the depletion region of the superjunction structure in the region having the blocking layer extends from the top of the blocking layer to the PN sub-pillars at the bottom of the blocking layer, causing the PN sub-pillars at the bottom of the blocking layer to begin to bear voltage.

[0015] The third epitaxial sublayer superimposed on the first conductivity type pillar serves as a connecting layer. First conductivity type ion implantation impurities are added to the formation region of the connecting layer, making the first conductivity type doping concentration of the connecting layer greater than the first conductivity type doping concentration of the third epitaxial sublayer in the blocking layer. This reduces the doping concentration difference between the connecting layer and the first conductivity type subpillars above and below the connecting layer, thereby lowering the on-resistance.

[0016] A further improvement is that the resistivity of the blocking layer is higher than or equal to the resistivity of the first conductivity type sub-pillar of the top layer of the blocking layer of the PN sub-pillar.

[0017] The thickness of each blocking layer is required to ensure that the areal density of the first conductivity type impurities in each blocking layer is less than or equal to 1E12cm³. -2 .

[0018] A further improvement is that, in the second conductive type pillar with the blocking layer, the blocking layer is at least disposed between the first PN sub-pillar and the second PN sub-pillar, wherein the first PN sub-pillar is the bottommost PN sub-pillar.

[0019] A further improvement is that the superjunction device includes an active region, a transition region, and a termination region.

[0020] The superjunction structure is provided in the active region, the transition region and the terminal region.

[0021] A further improvement is that the region having the blocking layer is located in part or all of the active region.

[0022] A further improvement is that the region having the blocking layer is also included in part or all of the transition region and the terminal region.

[0023] First conductivity type ion implantation impurities are added only in the formation region of the connection layer located in the active region;

[0024] No first conductivity type ion implantation impurities are added in the formation region of the connection layer located in the transition region and the terminal region. The first conductivity type doping concentration of the connection layer located in the transition region and the terminal region is equal to the first conductivity type doping concentration of the third epitaxial sublayer in the blocking layer, so as to improve the breakdown voltage capability of the transition region and the terminal region.

[0025] A further improvement is that the process conditions for adding ion implantation impurities of the first conductivity type in the connecting layer include: an implantation energy of 60 keV to 1000 keV and an implantation dose of 3E11cm. -2 ~2E12cm -2 .

[0026] A further improvement is that, when the number of PN sub-pillars is three or more, in each of the second conductive type pillars with a blocking layer, a blocking layer of one or more is provided between the second PN sub-pillar and the top PN sub-pillar.

[0027] A further improvement is that the resistivity of the first conductive type sub-pillar of each PN sub-pillar is the same, the resistivity of each blocking layer is 2 to 10 times the resistivity of the first conductive type sub-pillar of each PN sub-pillar, and the size of each blocking layer is 2 micrometers to 5 micrometers.

[0028] A further improvement is that the resistivity of the first conductivity type sub-pillar of each PN sub-pillar is the same, the resistivity of each blocking layer is equal to the resistivity of the first conductivity type sub-pillar of each PN sub-pillar, and the size of each blocking layer is less than or equal to 1 micrometer.

[0029] A further improvement is that the first conductivity type is N-type and the second conductivity type is P-type; or, the first conductivity type is P-type and the second conductivity type is N-type.

[0030] To solve the above-mentioned technical problems, the manufacturing method of the superjunction device provided by the present invention includes a superjunction structure comprising at least two or more PN subpillars, wherein at least a portion of the superjunction structure has a blocking layer, the blocking layer being composed of a third epitaxial sublayer of a first conductivity type; in the forming region of the blocking layer, the blocking layer is located between the second conductivity type subpillars of the upper and lower PN subpillars, and the forming process steps of the superjunction structure include:

[0031] Step 1: Form the PN sub-pillar of the current layer on the front layer structure using the PN sub-pillar formation process; when the current layer is the first layer, the front layer structure includes a semiconductor substrate and a first epitaxial layer with a first conductivity type doped on the surface of the semiconductor substrate.

[0032] The process steps for forming the PN sub-pillar include:

[0033] A second epitaxial sublayer of the first conductivity type is formed.

[0034] A trench is formed in the second epitaxial sublayer.

[0035] The second epitaxial sublayer is filled with a first epitaxial sublayer of a second conductivity type, and the first epitaxial sublayer of the second conductivity type filled in the trench forms a second conductivity type sub-pillar. The second epitaxial sublayers between the second conductivity type sub-pillars form a first conductivity type sub-pillar. The first conductivity type sub-pillar and the second conductivity type sub-pillar are arranged alternately to form the PN sub-pillar.

[0036] Step 2: If the blocking layer needs to be formed on the surface of the second conductivity type sub-pillar of the PN sub-pillar in the current layer, the steps include: forming the third epitaxial sub-layer on the surface of the PN sub-pillar in the current layer; performing first conductivity type ion implantation in a selected region of the third epitaxial sub-layer, the selected region being the formation region of the connecting layer, to increase the first conductivity type doping concentration of the connecting layer; then using the previous layer structure, the PN sub-pillar of the current layer, and the third epitaxial sub-layer as the new previous layer structure, and then repeating Step 1.

[0037] If the blocking layer does not need to be formed on the surface of the second conductivity type sub-pillar of the PN sub-pillar in the current layer and the current layer is not the top layer, then the previous layer structure and the PN sub-pillar of the current layer are used as the new previous layer structure, and then step one is repeated.

[0038] If the blocking layer does not need to be formed on the surface of the second conductivity type sub-pillar of the PN sub-pillar in the current layer and the current layer is the top layer, then the formation process of the superjunction structure is completed.

[0039] In the region having the blocking layer, in the longitudinal direction, the bottom surface of the second conductivity type sub-pillar of the PN sub-pillar at the top of the blocking layer is located above or below the top surface of the third epitaxial sub-layer. The blocking layer is composed of the second epitaxial sub-layer and the third epitaxial sub-layer below the bottom surface of the second conductivity type sub-pillar of the top PN sub-pillar, or the third epitaxial sub-layer. The first conductivity type sub-pillars and the third epitaxial sub-layers of each layer of PN sub-pillars are stacked to form an electrically connected first conductivity type pillar, and the second conductivity type sub-pillars of each layer of PN sub-pillars and the blocking layer are stacked to form a second conductivity type pillar with a blocking layer.

[0040] The second conductive type column with a blocking layer includes at least one blocking layer, which is located between two adjacent layers of the second conductive type sub-columns.

[0041] The breakdown voltage of each PN sub-pillar located above the blocking layer is the first voltage.

[0042] The voltage at which the blocking layer is completely depleted is the second voltage.

[0043] The process structure of the blocking layer is configured to satisfy the requirement that the second voltage is less than the first voltage. Before the reverse bias voltage borne by the superjunction structure is less than the second voltage, the second conductor type sub-pillars of each layer of PN sub-pillars located below the blocking layer in the region having the blocking layer are all floating structures. After the reverse bias voltage borne by the superjunction structure is greater than the second voltage and before it is less than the first voltage, the depletion region of the superjunction structure in the region having the blocking layer extends from the top of the blocking layer to the PN sub-pillars at the bottom of the blocking layer, causing the PN sub-pillars at the bottom of the blocking layer to begin to bear voltage.

[0044] The third epitaxial sublayer superimposed on the first conductivity type pillar serves as the connecting layer. The first conductivity type ion implantation impurities added to the connecting layer make the first conductivity type doping concentration of the connecting layer greater than the first conductivity type doping concentration of the third epitaxial sublayer in the blocking layer, thereby reducing the doping concentration difference between the connecting layer and the first conductivity type subpillars above and below the connecting layer, and thus reducing the on-resistance.

[0045] A further improvement is that the resistivity of the blocking layer is higher than or equal to the resistivity of the first conductivity type sub-pillar of the top layer of the blocking layer of the PN sub-pillar.

[0046] The thickness of each blocking layer is required to ensure that the areal density of the first conductivity type impurities in each blocking layer is less than or equal to 1E12cm³. -2 .

[0047] A further improvement is that, in the second conductive type pillar with the blocking layer, the blocking layer is at least disposed between the first PN sub-pillar and the second PN sub-pillar, wherein the first PN sub-pillar is the bottommost PN sub-pillar.

[0048] A further improvement is that the superjunction device includes an active region, a transition region, and a termination region;

[0049] The superjunction structure is provided in the active region, the transition region and the terminal region.

[0050] A further improvement is that the region having the blocking layer is located in part or all of the active region.

[0051] A further improvement is that the region having the blocking layer is also included in part or all of the transition region and the terminal region.

[0052] First conductivity type ion implantation impurities are added only in the formation region of the connection layer located in the active region.

[0053] No first conductivity type ion implantation impurities are added in the formation region of the connection layer located in the transition region and the terminal region. The first conductivity type doping concentration of the connection layer located in the transition region and the terminal region is equal to the first conductivity type doping concentration of the third epitaxial sublayer in the blocking layer, so as to improve the breakdown voltage capability of the transition region and the terminal region.

[0054] A further improvement is that the process conditions for adding ion implantation impurities of the first conductivity type in the connecting layer include: an implantation energy of 60 keV to 1000 keV and an implantation dose of 3E11cm. -2 ~2E12cm -2 .

[0055] A further improvement is that, when the number of PN sub-pillars is three or more, in each of the second conductive type pillars with a blocking layer, a blocking layer of one or more is provided between the second PN sub-pillar and the top PN sub-pillar.

[0056] A further improvement is that the resistivity of the first conductive type sub-pillar of each PN sub-pillar is the same, the resistivity of each blocking layer is 2 to 10 times the resistivity of the first conductive type sub-pillar of each PN sub-pillar, and the size of each blocking layer is 2 micrometers to 5 micrometers.

[0057] A further improvement is that the resistivity of the first conductivity type sub-pillar of each PN sub-pillar is the same, the resistivity of each blocking layer is equal to the resistivity of the first conductivity type sub-pillar of each PN sub-pillar, and the size of each blocking layer is less than or equal to 1 micrometer.

[0058] A further improvement is that the first conductivity type is N-type and the second conductivity type is P-type; or, the first conductivity type is P-type and the second conductivity type is N-type.

[0059] This invention sets the superjunction structure in the superjunction device as a superposition structure of multiple PN subpillars, and the second conductivity type subpillar of each PN subpillar adopts a trench-filled structure. This can reduce the manufacturing difficulty of the superjunction structure and further reduce the step size of the superjunction unit.

[0060] Based on this, the present invention, taking into account the characteristic that each layer of PN subpillars is formed in layers, sets a first conductivity type blocking layer between the second conductivity type subpillars of at least a portion of the PN subpillars. The blocking layer can be depleted before the PN subpillar at the top of the blocking layer breaks down. However, before the blocking layer is depleted, the second conductivity type subpillars of the PN subpillars at the bottom of the blocking layer are all floating structures. The floating second conductivity type subpillars are not connected to the external potential, but are surrounded by the surrounding first conductivity type subpillars and the blocking layer. In this way, there is no potential difference between the floating second conductivity type subpillars and the surrounding first conductivity type subpillars and the blocking layer, so the PN subpillars at the bottom of the blocking layer will not be depleted. This prevention of depletion of the PN subpillars at the bottom of the blocking layer will give the device the following beneficial effects:

[0061] When the reverse bias voltage of the superjunction structure, such as the source-drain voltage (Vds) of the superjunction device, is very small, such as around 5V to 10V, depletion will only occur on the PN sub-pillars above the blocking layer. Therefore, the contact area of ​​the depleted P-type and N-type pillars in the entire superjunction structure will be reduced. The area of ​​the source-drain capacitance of the device is proportional to the contact area of ​​the depleted P-type and N-type pillars in the superjunction structure, which can reduce the source-drain capacitance (Cds). As the source-drain capacitance is a component of the output capacitance, it can also reduce the output capacitance (Coss).

[0062] When the reverse bias voltage of the superjunction structure, such as Vds, is a smaller voltage than the second voltage, such as less than 200V to 300V, only the PN sub-pillars above the blocking layer will be completely depleted, while the PN sub-pillars at the bottom of the blocking layer will not be depleted. That is, the carriers of the floating second conductivity type sub-pillars and the surrounding first conductivity type sub-pillars of the PN sub-pillars at the bottom of the blocking layer will not be completely swept out by the transverse electric field. In other words, they will be retained or partially retained, which can improve the reverse recovery characteristics of the device body diode.

[0063] Meanwhile, since the PN subpillars at the bottom of the blocking layer of the superjunction structure will not be laterally depleted at a lower voltage, and since the gate-drain capacitance (Cgd) of the device is inversely proportional to the thickness of the depleted superjunction structure, the gate-drain capacitance (Cgd) of the device will increase at a lower voltage, such as when Vds is small. This results in better electromagnetic interference (EMC) performance of the superjunction device during use.

[0064] Since the resistivity of the third epitaxial sublayer, which is set according to the process requirements of the blocking layer, is relatively high, it affects the on-resistance of the device. To address this, the present invention adds first-conductivity type ion implantation impurities to the third epitaxial sublayer that forms the first conductivity type pillar. This increases the doping concentration of the connecting layer, reduces or even makes the difference between the doping concentration of the connecting layer and the doping concentration of the first conductivity type sub-pillars above and below it equal. This eliminates the adverse effect of the introduction of the blocking layer on the on-resistance of the device, and ultimately reduces the on-resistance of the device. Attached Figure Description

[0065] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:

[0066] Figure 1 This is a schematic diagram of the structure of the superjunction device according to the first embodiment of the present invention;

[0067] Figure 2 This is a schematic diagram of the superjunction device according to the second embodiment of the present invention;

[0068] Figures 3A-3C This is a schematic diagram of the device structure in each step of the manufacturing method of the superjunction device according to an embodiment of the present invention. Detailed Implementation

[0069] like Figure 1The diagram shown is a schematic representation of the superjunction device according to a first embodiment of the present invention. The superjunction structure 301 of the superjunction device according to the first embodiment of the present invention includes at least two layers of PN subpillars, each layer of PN subpillars being formed by alternating arrangements of first conductivity type subpillars and second conductivity type subpillars. The structure of each layer of PN subpillars includes: the second conductivity type subpillar is composed of a first epitaxial sublayer of the second conductivity type filling a trench, the trench being formed in the second epitaxial sublayer of the first conductivity type, and the first conductivity type subpillar is composed of the second epitaxial sublayer between each of the second conductivity type subpillars.

[0070] Figure 1 In the superjunction structure 301, there are two layers of PN subpillars, the first layer of PN subpillars is marked with 301a and the second layer of PN subpillars is marked with 301b. The entire superjunction structure is marked with 301.

[0071] The first layer of PN sub-pillars 301a is located between lines A1A2 and B1B2. In the first layer of PN sub-pillars 301a, the first conductivity type sub-pillar is marked with 204a, and the second conductivity type sub-pillar is marked with 205a.

[0072] The second layer of PN sub-pillars 301a is located between lines A1A2 and B1B2. In the second layer of PN sub-pillars 301b, the first conductivity type sub-pillar is marked with 204b, and the second conductivity type sub-pillar is marked with 205b.

[0073] The superjunction structure 301 has a blocking layer in at least a portion of its region, and the region where the blocking layer is formed is shown in dashed box 206.

[0074] In the region having the blocking layer, a third epitaxial sublayer 302 of the first conductivity type is formed between the upper and lower PN subpillars of the blocking layer.

[0075] In the vertical direction, the bottom surface of the second conductivity type sub-pillar of the PN sub-pillar at the top of the blocking layer is located above or below the top surface of the third epitaxial sub-layer 302. The blocking layer is composed of the second epitaxial sub-layer and the third epitaxial sub-layer 302 below the bottom surface of the second conductivity type sub-pillar of the PN sub-pillar at the top, or the third epitaxial sub-layer 302. Figure 1In this embodiment, the bottom surface of the second conductivity type sub-pillar 205b of the second PN sub-pillar 301b is located below the third epitaxial sub-layer 302. Therefore, the blocking layer is entirely composed of the third epitaxial sub-layer 302 located below the bottom surface of the second conductivity type sub-pillar 205b of the second PN sub-pillar 301b. In other embodiments, the bottom surface of the second conductivity type sub-pillar 205b of the second PN sub-pillar 301b can be located above the third epitaxial sub-layer 302. In this case, the blocking layer is composed of the second epitaxial sub-layer located below the bottom surface of the second conductivity type sub-pillar 205b of the second PN sub-pillar 301b and the third epitaxial sub-layer 302. The second epitaxial sub-layer located below the bottom surface of the second conductivity type sub-pillar 205b is the second epitaxial sub-layer that constitutes the first conductivity type sub-pillar 204a.

[0076] The first conductive type sub-pillar of each PN sub-pillar and the third epitaxial sub-layer 302 are superimposed to form an electrically connected first conductive type pillar, and the second conductive type sub-pillar of each PN sub-pillar and the blocking layer are superimposed to form a second conductive type pillar with a blocking layer.

[0077] The second conductive type column with a blocking layer includes at least one blocking layer, which is located between two adjacent layers of the second conductive type sub-columns. Figure 1 Since the entire PN sub-pillar consists of two layers, each of the second conductive type pillars with a blocking layer includes one blocking layer.

[0078] The breakdown voltage of each PN sub-pillar located above the blocking layer is the first voltage.

[0079] The voltage at which the blocking layer is completely depleted is the second voltage.

[0080] The process structure of the blocking layer is configured to meet the requirement that the second voltage is less than the first voltage. Before the reverse bias voltage borne by the superjunction structure 301 is less than the second voltage, the second conductor type sub-pillars of each layer of PN sub-pillars located below the blocking layer in the region having the blocking layer are all floating structures. After the reverse bias voltage borne by the superjunction structure 301 is greater than the second voltage and before it is less than the first voltage, the depletion region of the superjunction structure 301 in the region having the blocking layer extends from the top of the blocking layer to the PN sub-pillars at the bottom of the blocking layer, causing the PN sub-pillars at the bottom of the blocking layer to begin to bear voltage.

[0081] The third epitaxial sublayer 302 superimposed on the first conductivity type pillar serves as a connecting layer 206a. First conductivity type ion implantation impurities are added to the formation region of the connecting layer 206a, making the first conductivity type doping concentration of the connecting layer 206a greater than the first conductivity type doping concentration of the third epitaxial sublayer 302 in the blocking layer. This reduces the difference in doping concentration between the connecting layer 206a and the first conductivity type subpillars above and below the connecting layer 206a, thereby reducing the on-resistance. Figure 1 In the above and below layers of the connecting layer 206a, the first conductivity type sub-pillars are the first conductivity type sub-pillar 204a of the first layer and the first conductivity type sub-pillar 204b of the second layer, respectively. After the first conductivity type ion implantation, the doping concentration of the connecting layer 206a is close to or even equal to the doping concentration of the first conductivity type sub-pillar 204a of the first layer and the first conductivity type sub-pillar 204b of the second layer. In this way, the on-resistance of the device can be avoided after the insertion of the third epitaxial sub-layer 302.

[0082] In the first embodiment of the present invention, the resistivity of the blocking layer is higher than or equal to the resistivity of the first conductivity type sub-pillar of the PN sub-pillar on top of the blocking layer.

[0083] The thickness of each blocking layer is required to ensure that the areal density of the first conductivity type impurities in each blocking layer is less than or equal to 1E12cm³. -2 In other words, if the resistivity of the blocking layer is reduced, the thickness of the blocking layer needs to be reduced in order to achieve a surface density of impurities of the first conductivity type in the blocking layer that is less than or equal to 1E12cm³. -2 .

[0084] In the second conductive type pillar with a blocking layer, the blocking layer is at least disposed between the first PN sub-pillar and the second PN sub-pillar, wherein the first PN sub-pillar is the bottommost PN sub-pillar.

[0085] Superjunction devices consist of an active region, a transition region, and a termination region.

[0086] The superjunction structure 301 is provided in the active region, the transition region and the terminal region.

[0087] The region having the blocking layer is located in part or all of the active region.

[0088] The region containing the blocking layer is also included in part or all of the transition region and the terminal region.

[0089] In some preferred embodiments, a first conductivity type ion implantation impurity is added only in the formation region of the interconnect layer 206a located in the active region.

[0090] No first conductivity type ion implantation impurities are added in the formation region of the connection layer 206a located in the transition region and the terminal region. The first conductivity type doping concentration of the connection layer 206a located in the transition region and the terminal region is equal to the first conductivity type doping concentration of the third epitaxial sublayer 302 in the blocking layer, so as to improve the breakdown voltage capability of the transition region and the terminal region.

[0091] The process conditions for adding ion implantation impurities of the first conductivity type in the connecting layer 206a include: implantation energy of 60 keV to 1000 keV and implantation dose of 3E11 cm⁻¹. -2 ~2E12cm -2 When the first conductivity type is N-type, the first conductivity type ion-implanted impurity of the connecting layer 206a includes phosphorus.

[0092] In some preferred embodiments, the resistivity of the first conductive type sub-pillars of each PN sub-pillar is the same, the resistivity of each blocking layer is 2 to 10 times the resistivity of the first conductive type sub-pillar of each PN sub-pillar, and the size of each blocking layer is 2 micrometers to 5 micrometers.

[0093] In some preferred embodiments, the resistivity of the first conductivity type sub-pillars in each PN sub-pillar layer is the same, the resistivity of each blocking layer is equal to the resistivity of the first conductivity type sub-pillars in each PN sub-pillar layer, and the thickness of each blocking layer is less than or equal to 1 micrometer. Thus, even if the resistivity of the blocking layer decreases (i.e., the doping concentration increases), the areal density of the first conductivity type impurities in the blocking layer can still be less than or equal to 1E12cm³ by reducing the thickness of the blocking layer. -2 The thickness of the blocking layer can be achieved by controlling the etching process of the trenches corresponding to the second conductivity type sub-pillar 205b in the second PN sub-pillar 301b.

[0094] In the first embodiment of the present invention, the first conductivity type is N-type and the second conductivity type is P-type. In other embodiments, the first conductivity type can also be P-type and the second conductivity type can be N-type.

[0095] The superjunction device further includes a front-side structure formed on the front side of the superjunction structure, the front-side structure of the superjunction device including:

[0096] The second conductivity type of well region 207 is formed on the surface of the second conductivity type sub-pillar of the corresponding topmost PN sub-pillar. Figure 1The topmost PN sub-pillar is the second-layer PN sub-pillar 301b, and each well region 207 is formed in the top surface region of the second conductivity type sub-pillar 205b. After the well region 207 is formed, the effective thickness of the superjunction structure 301 will decrease, and the top surface will decrease from line C1C2 to line D1D2.

[0097] A gate structure formed by stacking a gate dielectric layer 208 and a gate conductive material layer 209. Figure 1 In this embodiment, the gate structure is a planar gate. The gate dielectric layer 208 is a gate oxide layer, and the gate conductive material layer 209 is a polysilicon gate. The surface of the well region 207 covered by the gate structure is used to form a conductive channel. In other embodiments, the gate structure may also be a trench gate.

[0098] A source region 210, which is heavily doped with a first conductivity type and self-aligned with the side of the gate structure, is formed on the surface of the well region 207.

[0099] In some preferred embodiments, in order to reduce on-resistance, a first conductivity type doped anti-JFET region 211 is also formed between the well regions 207.

[0100] An interlayer film 212 covers the surfaces of the gate structure, the source region 210, and the JFET region 211. Contact holes 213 are formed on the top of both the gate structure and the source region 210, passing through the interlayer film 212.

[0101] The gate structure is connected to a gate patterned from the front metal layer 215 via a top contact hole 213.

[0102] The bottom of the contact hole 213 at the top of the source region 210 will also pass through the source region 210 and contact the well region 207, and a heavily doped well contact region 214 of the second conductivity type will also be formed at the bottom of the contact hole 213 corresponding to the source region 210. The source region 210 and the well region 207 are simultaneously connected to the source electrode composed of the front metal layer 215 through the contact hole at the top.

[0103] Typically, a first epitaxial layer 202 and a second epitaxial layer 203 are spaced between the superjunction structure 301 and the bottom semiconductor substrate 201. The semiconductor substrate 201 is heavily doped with a first conductivity type, and both the first epitaxial layer 202 and the second epitaxial layer 203 are doped with a first conductivity type. The resistivity of the first epitaxial layer 202 is less than or equal to the resistivity of the second epitaxial layer 203, and the resistivity of the second epitaxial layer 203 is less than or equal to the resistivity of the first conductivity type pillar of the superjunction structure 301.

[0104] The semiconductor substrate 201 can be directly used as a drain region after the back side is thinned, or the drain region can be formed by further implantation of heavily doped ions of the first conductivity type on the back side after the back side is thinned.

[0105] A drain electrode composed of a back metal layer 216 is formed on the back side of the drain region.

[0106] As can be seen from the above, the first embodiment of the present invention discloses a specially designed PN pillar, i.e., a superjunction structure, in which at least two different PN subpillars are stacked longitudinally to form the PN pillar of the device. Between the first layer P-type subpillar 205a and the second layer P-type subpillar 205b, at least a portion of the region has an N-type blocking layer. The resistivity of this blocking layer is higher than that of the N-type sub-pillar. The second PN sub-pillar 301b, above the first PN sub-pillar 301a, achieves lateral depletion when Vds is reverse biased, and depletes longitudinally along with the N-type blocking layer. The electric field strength in the second PN sub-pillar 301b increases with Vds. Before reaching the breakdown voltage of the second PN sub-pillar 301b, the N-type impurities in the intermediate blocking layer are completely depleted, thereby causing the first P-type sub-pillar 205a to begin to deplete. The P-type sub-pillar 205a and N-type sub-pillar 204a of the first PN sub-pillar 301a deplete each other and share the reverse bias voltage Vds with the second PN sub-pillar 301b, so that the breakdown voltage of the device is not significantly reduced due to the addition of the N-type blocking layer.

[0107] In the first embodiment of the present invention, the superjunction structure 301 in the superjunction device is set as a superposition structure of multiple PN sub-pillars, and the second conductivity type sub-pillars of each PN sub-pillar adopt a trench-filled structure. This can reduce the manufacturing difficulty of the superjunction structure 301 and further reduce the step size of the superjunction unit.

[0108] Based on this, the first embodiment of the present invention, taking into account the characteristic that each layer of PN sub-pillars is formed in layers, provides a blocking layer of the first conductivity type between the second conductivity type sub-pillars of at least a portion of the PN sub-pillars. The blocking layer can be depleted before the PN sub-pillar at the top of the blocking layer breaks down. However, before the blocking layer is depleted, the second conductivity type sub-pillars of the PN sub-pillars at the bottom of the blocking layer are all floating structures. The floating second conductivity type sub-pillars are not connected to the external potential, but are surrounded by the surrounding first conductivity type sub-pillars and the blocking layer. In this way, there is no potential difference between the floating second conductivity type sub-pillars and the surrounding first conductivity type sub-pillars and the blocking layer, so the PN sub-pillars at the bottom of the blocking layer will not be depleted. This non-depletion of the PN sub-pillars at the bottom of the blocking layer will give the device the following beneficial effects:

[0109] When the reverse bias voltage of the superjunction structure 301, such as the source-drain voltage (Vds) of the superjunction device, is very small, such as around 5V to 10V, depletion will only occur on the PN sub-pillars above the blocking layer. Therefore, the contact area of ​​the depleted P-type and N-type pillars in the entire superjunction structure 301 will be reduced. The area of ​​the source-drain capacitance of the device is proportional to the contact area of ​​the depleted P-type and N-type pillars in the superjunction structure 301, which can reduce the source-drain capacitance (Cds). As the source-drain capacitance is a component of the output capacitance, it can also reduce the output capacitance (Coss).

[0110] When the reverse bias voltage of the superjunction structure 301, such as Vds, is a smaller voltage than the second voltage, such as less than 200V to 300V, only the PN sub-pillars above the blocking layer will be completely depleted, while the PN sub-pillars at the bottom of the blocking layer will not be depleted. That is, the carriers of the floating second conductivity type sub-pillars and the surrounding first conductivity type sub-pillars of the PN sub-pillars at the bottom of the blocking layer will not be completely swept out by the transverse electric field. In other words, they will be retained or partially retained, which can improve the reverse recovery characteristics of the device body diode.

[0111] Meanwhile, since the PN subpillars at the bottom of the blocking layer of the superjunction structure 301 will not be laterally depleted at a lower voltage, and since the gate-drain capacitance (Cgd) of the device is inversely proportional to the thickness of the depleted superjunction structure 301, the gate-drain capacitance (Cgd) of the device will increase at a lower voltage, such as when Vds is small. This results in better electromagnetic interference (EMC) performance of the superjunction device during use.

[0112] Since the resistivity of the third epitaxial sublayer 302, which is set according to the process requirements of the blocking layer, is relatively high, it affects the on-resistance of the device. Therefore, in the first embodiment of the superjunction device of the present invention, first conductivity type ion implantation impurities are added to the third epitaxial sublayer 302 of the connecting layer 206a that constitutes the first conductivity type pillar. This increases the doping concentration of the connecting layer 206a, reduces or even makes the difference between the doping concentration of the connecting layer 206a and the doping concentration of the first conductivity type sub-pillars above and below it equal, thereby eliminating the adverse effect of the introduction of the blocking layer on the on-resistance of the device and finally reducing the on-resistance of the device.

[0113] like Figure 2 The diagram shown is a structural schematic of the superjunction device according to the second embodiment of the present invention. The difference between the superjunction device of the second embodiment of the present invention and the superjunction device of the first embodiment of the present invention is as follows:

[0114] The superjunction structure 301 of the superjunction device in the second embodiment of the present invention includes three layers of PN subpillars. The third layer of PN subpillars is denoted by 301c. The first conductivity type subpillar of the third layer of PN subpillars 301c is denoted by 204c, and the second conductivity type subpillar is denoted by 205c. Figure 2 In this embodiment, the second conductive type sub-pillar 205c is in direct contact with the second conductive type sub-pillar 205b of the bottom layer. In other embodiments, a blocking layer can also be directly disposed between the second conductive type sub-pillar 205c and the second conductive type sub-pillar 205b of the bottom layer.

[0115] In some embodiments, the number of PN sub-pillars can be greater than three. In this case, in each of the second conductive type pillars with a blocking layer, one or more blocking layers are provided between the second PN sub-pillar and the top PN sub-pillar. Providing zero blocking layers indicates direct contact between the upper and lower layers of the second conductive type pillars. Increasing the number of PN sub-pillars can increase the withstand voltage of the device.

[0116] like Figures 3A to 3B The diagram shown is a schematic representation of the device structure in each step of the manufacturing method of the superjunction device according to an embodiment of the present invention. In the manufacturing method of the superjunction device according to an embodiment of the present invention, the superjunction structure 301 includes at least two or more PN subpillars. At least a portion of the superjunction structure 301 has a blocking layer, which is composed of a third epitaxial sublayer 302 of a first conductivity type. In the forming region of the blocking layer, the blocking layer is located between the second conductivity type subpillars of the upper and lower PN subpillars. The forming process steps of the superjunction structure 301 include:

[0117] Step 1: Form the PN sub-pillar of the current layer on the front layer structure using the PN sub-pillar formation process; when the current layer is the first layer, the front layer structure includes a semiconductor substrate 201 and a first epitaxial layer 202 with a first conductivity type doped on the surface of the semiconductor substrate 201.

[0118] A second epitaxial layer 203 is also formed on the surface of the first epitaxial layer 202. The semiconductor substrate 201 is heavily doped with a first conductivity type, and both the first epitaxial layer 202 and the second epitaxial layer 203 are doped with a first conductivity type. The resistivity of the first epitaxial layer 202 is less than or equal to the resistivity of the second epitaxial layer 203, and the resistivity of the second epitaxial layer 203 is less than or equal to the resistivity of the first conductivity type pillar of the superjunction structure 301.

[0119] The process steps for forming the PN sub-pillar include:

[0120] A second epitaxial sublayer of the first conductivity type is formed.

[0121] A trench is formed in the second epitaxial sublayer. A hard mask layer can be used in the formation of the trench, the hard mask layer comprising a first oxide layer, a second nitride layer and a third oxide layer stacked sequentially.

[0122] The second epitaxial sublayer is filled with a first epitaxial sublayer of a second conductivity type, and the first epitaxial sublayer of the second conductivity type filled in the trench forms a second conductivity type sub-pillar. The second epitaxial sublayers between the second conductivity type sub-pillars form a first conductivity type sub-pillar. The first conductivity type sub-pillar and the second conductivity type sub-pillar are arranged alternately to form the PN sub-pillar.

[0123] Figure 3A This shows a structural diagram after the formation of the first layer of PN sub-pillars 301a. Figure 3A In this process, a second epitaxial layer 203 is also formed on the surface of the first epitaxial layer 202. The PN sub-pillars 301a of the first layer include alternating first conductivity type sub-pillars 204a and second conductivity type sub-pillars 205a.

[0124] Step 2: If the blocking layer needs to be formed on the surface of the second conductivity type sub-pillar of the PN sub-pillar in the current layer, including: Figure 3B As shown, the third epitaxial sublayer 302 is formed on the surface of the PN subpillar of the current layer.

[0125] Ion implantation of the first conductivity type is performed in a selected region of the third epitaxial sublayer 302, which is the formation region of the connecting layer 206a, to increase the doping concentration of the first conductivity type of the connecting layer 206a. Figure 3B In the process, the formation area of ​​the connecting layer 206a is defined by the pattern of photoresist 303, and then ion implantation of the first conductivity type, as indicated by mark 304, is performed.

[0126] In some preferred embodiments, the process conditions for adding ion implantation impurities of the first conductivity type to the interconnect layer 206a include: an implantation energy of 60 keV to 1000 keV and an implantation dose of 3E11 cm⁻¹. -2 ~2E12cm -2 When the first conductivity type is N-type, the impurities implanted by the first conductivity type ion implantation of the connecting layer 206a include phosphorus.

[0127] Then, the previous layer structure, the PN sub-pillar of the current layer, and the third epitaxial sub-layer 302 are used as the new previous layer structure, and then step one is repeated.

[0128] If the blocking layer does not need to be formed on the surface of the second conductivity type sub-pillar of the PN sub-pillar in the current layer and the current layer is not the top layer, then the previous layer structure and the PN sub-pillar of the current layer are used as the new previous layer structure, and then step one is repeated.

[0129] If the blocking layer does not need to be formed on the surface of the second conductivity type sub-pillar of the PN sub-pillar in the current layer and the current layer is the top layer, then the formation process of the superjunction structure 301 is completed.

[0130] like Figure 3B As shown, after the formation of the first layer PN sub-pillar 301a, the third epitaxial sub-layer 302 will be formed. Figure 3C As shown, step one is then repeated to form the second layer of PN sub-pillars 301b. The second layer of PN sub-pillars 301b consists of alternating first conductivity type sub-pillars 204b and second conductivity type sub-pillars 205b.

[0131] Correspondence formation Figure 1 The superjunction device of the first embodiment of the present invention shown completes the formation process of the superjunction structure 301 after the formation of the second layer PN subpillar 301b. If it is necessary to form... Figure 2 The superjunction device of the second embodiment of the present invention shown requires repeating step one to form the third PN sub-pillar 301c. More PN sub-pillars can be obtained by repeating step one.

[0132] In the region having the blocking layer, in the longitudinal direction, the bottom surface of the second conductivity type sub-pillar of the PN sub-pillar at the top of the blocking layer is located above or below the top surface of the third epitaxial sub-layer 302, and the blocking layer is composed of the second epitaxial sub-layer and the third epitaxial sub-layer 302 below the bottom surface of the second conductivity type sub-pillar of the top PN sub-pillar. Figure 3B In the second layer, the second conductivity type sub-pillar 205b of the PN sub-pillar 301b is located below the top surface of the third epitaxial sub-layer 302. The blocking layer is composed of the third epitaxial sub-layer 302 at the bottom of the second conductivity type sub-pillar 205b. The forming region of the blocking layer is shown in the dashed box 206.

[0133] The first conductive type sub-pillar of each PN sub-pillar and the third epitaxial sub-layer 302 are superimposed to form an electrically connected first conductive type pillar, and the second conductive type sub-pillar of each PN sub-pillar and the blocking layer are superimposed to form a second conductive type pillar with a blocking layer.

[0134] The second conductive type column with a blocking layer includes at least one blocking layer, which is located between two adjacent layers of the second conductive type sub-columns.

[0135] The breakdown voltage of each PN sub-pillar located above the blocking layer is the first voltage.

[0136] The voltage at which the blocking layer is completely depleted is the second voltage.

[0137] The process structure of the blocking layer is configured to meet the requirement that the second voltage is less than the first voltage. Before the reverse bias voltage borne by the superjunction structure 301 is less than the second voltage, the second conductor type sub-pillars of each layer of PN sub-pillars located below the blocking layer in the region having the blocking layer are all floating structures. After the reverse bias voltage borne by the superjunction structure 301 is greater than the second voltage and before it is less than the first voltage, the depletion region of the superjunction structure 301 in the region having the blocking layer extends from the top of the blocking layer to the PN sub-pillars at the bottom of the blocking layer, causing the PN sub-pillars at the bottom of the blocking layer to begin to bear voltage.

[0138] The third epitaxial sublayer 302 superimposed on the first conductivity type pillar serves as the connecting layer 206a. The first conductivity type ion implantation impurities added to the connecting layer 206a make the first conductivity type doping concentration of the connecting layer 206a greater than the first conductivity type doping concentration of the third epitaxial sublayer 302 in the blocking layer, thereby reducing the doping concentration difference between the connecting layer 206a and the first conductivity type subpillars above and below the connecting layer 206a, and thus reducing the on-resistance.

[0139] In the method of this invention embodiment, the resistivity of the blocking layer is higher than or equal to the resistivity of the first conductivity type sub-pillar of the PN sub-pillar on top of the blocking layer.

[0140] The thickness of each blocking layer is required to ensure that the areal density of the first conductivity type impurities in each blocking layer is less than or equal to 1E12cm³. -2 .

[0141] In the second conductive type pillar with a blocking layer, the blocking layer is at least disposed between the first PN sub-pillar and the second PN sub-pillar, wherein the first PN sub-pillar is the bottommost PN sub-pillar.

[0142] Superjunction devices include an active region, a transition region, and a termination region;

[0143] The superjunction structure 301 is provided in the active region, the transition region and the terminal region.

[0144] In some embodiments, the region having the blocking layer is located in part or all of the active region.

[0145] The region containing the blocking layer is also included in part or all of the transition region and the terminal region.

[0146] In some preferred embodiments, a first conductivity type ion implantation impurity is added only in the formation region of the interconnect layer 206a located in the active region.

[0147] No first conductivity type ion implantation impurities are added in the formation region of the connection layer 206a located in the transition region and the terminal region. The first conductivity type doping concentration of the connection layer 206a located in the transition region and the terminal region is equal to the first conductivity type doping concentration of the third epitaxial sublayer 302 in the blocking layer, so as to improve the breakdown voltage capability of the transition region and the terminal region.

[0148] In some embodiments, when the number of PN sub-pillars is three or more, each of the second conductive type pillars with a blocking layer has one or more blocking layers between the second PN sub-pillar and the top PN sub-pillar. The presence of zero blocking layers indicates that the corresponding upper and lower layers of the second conductive type pillars are in direct contact.

[0149] In some embodiments, the resistivity of the first conductivity type sub-pillars of each PN sub-pillar is the same, and the resistivity of each blocking layer is 2 to 10 times that of the first conductivity type sub-pillar of each PN sub-pillar. Each blocking layer has a resistivity of 2 micrometers to 5 micrometers. A higher resistivity of the blocking layer corresponds to a lower doping concentration, provided that the areal density of the first conductivity type impurities in the blocking layer is less than or equal to 1E¹² cm⁻¹. -2 Under certain conditions, the thickness of the blocking layer can be increased.

[0150] In some embodiments, the resistivity of the first conductivity type subpillars of each PN subpillar layer is the same, and the resistivity of each blocking layer is equal to the resistivity of the first conductivity type subpillars of each PN subpillar layer. Each blocking layer is less than or equal to 1 micrometer. Because the resistivity of the blocking layer is equal to the resistivity of the first conductivity type subpillars of each layer, the third epitaxial sublayer can directly utilize the second epitaxial sublayer of the top layer of the blocking layer. However, due to the low resistivity of the blocking layer, the doping concentration will be relatively high. To ensure that the areal density of the first conductivity type impurities in the blocking layer is less than or equal to 1E12cm², [further details are needed]. -2 Under certain conditions, the thickness of the blocking layer needs to be controlled to be less than 1 micrometer, which can be achieved by etching the trench on the top of the blocking layer.

[0151] In the method of this embodiment, the first conductivity type is N-type and the second conductivity type is P-type. In other embodiments, the first conductivity type can also be P-type and the second conductivity type can be N-type.

[0152] After forming the superjunction structure 301, a process is also included to form the front structure of the superjunction device on the surface of the superjunction structure 301; and after the front structure of the superjunction device is completed, a process is also included to form the back structure of the superjunction device.

[0153] To form Figure 1 Taking the superjunction device of the first embodiment of the present invention as an example, the process steps for forming the front structure of the superjunction device include:

[0154] A second conductivity type well region 207 is formed, and each well region 207 is formed on the surface of the second conductivity type sub-pillar of the corresponding topmost PN sub-pillar. Figure 1 The topmost PN sub-pillar is the second-layer PN sub-pillar 301b, and each well region 207 is formed in the top surface region of the second conductivity type sub-pillar 205b. After the well region 207 is formed, the effective thickness of the superjunction structure 301 will decrease, and the top surface will decrease from line C1C2 to line D1D2.

[0155] A gate structure is formed by stacking a gate dielectric layer 208 and a gate conductive material layer 209. Figure 1 In this embodiment, the gate structure is a planar gate. The gate dielectric layer 208 is a gate oxide layer, and the gate conductive material layer 209 is a polysilicon gate. The surface of the well region 207 covered by the gate structure is used to form a conductive channel. In other embodiments, the gate structure may also be a trench gate.

[0156] Source-drain injection is performed to form a first conductivity type heavily doped source region 210 on the surface of the well region 207 and self-aligned on the side of the gate structure.

[0157] In some preferred embodiments, to reduce on-resistance, a JFET-resistant region 211 doped with a first conductivity type is also formed between the well regions 207. The JFET-resistant region 211 is typically formed by photolithography and ion implantation after the formation of the superjunction structure and before the formation of the well regions 207, or by photolithography and ion implantation after the formation of the well regions 207 and before the formation of the gate structure.

[0158] An interlayer film 212 is formed, which covers the surfaces of the gate structure, the source region 210, and the JFET region 211.

[0159] Contact holes 213 are formed on the top of both the gate structure and the source region 210, extending through the interlayer film 212. The steps for forming the contact holes 213 include: first, performing photolithography to define the contact holes; then, performing etching to form the openings of the contact holes 213 extending through the interlayer film 212; and finally, filling the openings of the contact holes 213 with a metal layer to form the contact holes 213.

[0160] The gate structure is connected to a gate patterned from the front metal layer 215 via a top contact hole 213.

[0161] The bottom of the contact hole 213 at the top of the source region 210 will also pass through the source region 210 and contact the well region 207. Preferably, after the opening of the contact hole 213 is formed and before metal filling, a step of implanting heavily doped ions of the second conductivity type is included to form a heavily doped well contact region 214 of the second conductivity type at the bottom of the contact hole 213 corresponding to the source region 210. The source region 210 and the well region 207 are simultaneously connected to the source electrode composed of the front metal layer 215 through the top contact hole 213.

[0162] The process steps for forming the back-side structure of the superjunction device include:

[0163] The semiconductor substrate 201 is thinned on the back side, and the thinned semiconductor substrate 201 is used directly as the drain region, or the drain region is formed by further implantation of heavily doped ions of the first conductivity type on the back side after the back side is thinned.

[0164] A drain electrode composed of a back metal layer 216 is formed on the back side of the drain region.

[0165] The following section uses a 600V N-type superjunction MOSFET as an example and combines specific parameters to further explain in detail the manufacturing method of the superjunction device according to the embodiments of the present invention:

[0166] Since the superjunction device is an N-type device, the first conductivity type is N-type, the second conductivity type is P-type, the first conductor type sub-pillar is an N-type sub-pillar, and the second conductivity type sub-pillar is a P-type sub-pillar. Figure 3A In the first layer of PN subpillars, the top width of the P-type subpillar 205a is 3 micrometers, and the side tilt angle of the P-type subpillar 205a is 89 degrees; the top width of the N-type subpillar 204a is 2 micrometers. The step size of the first layer of PN subpillars is 5 micrometers. Since the superjunction structure is formed by aligning and stacking multiple layers of PN subpillars, the step size of each superjunction structure is also 5 micrometers.

[0167] In step one, forming the first layer of the PN sub-pillars includes:

[0168] The provided semiconductor substrate 201 is an N-type substrate with a resistivity of 0.001 to 0.003 ohm·cm and a typical thickness of about 725 micrometers.

[0169] The thickness of the first epitaxial layer 202 deposited on the semiconductor substrate 201 is 5μm-10μm.

[0170] The second epitaxial layer 203 and the second epitaxial sublayer corresponding to the N-type subpillar 204a are deposited on the first epitaxial layer 202.

[0171] The hard mask layer is deposited on the second epitaxial sublayer corresponding to the N-type subpillar 204a. The hard mask layer includes a first oxide layer, a second nitride layer and a third oxide layer stacked in sequence, namely oxide film-silicon nitride film-oxide film.

[0172] Next, the trench formation area is defined by photolithography; then etching is performed. The etching first removes the oxide-silicon nitride-oxide film in the trench formation area, and uses the oxide-silicon nitride-oxide film outside the trench formation area as a hard mask to etch the material of the second epitaxial sublayer, such as silicon, to form the trench. The bottom of the trench reaches the bottom of the second epitaxial sublayer.

[0173] The resistivity of the first epitaxial layer 202 is chosen to be lower than that of the second epitaxial layer 203, typically 0.5 to 1 times the resistivity of the second epitaxial layer 203. Using a lower resistivity reduces the on-resistance of the device, while using the same resistivity simplifies the epitaxial deposition process.

[0174] The second epitaxial layer 203 and the second epitaxial sublayer corresponding to the N-type sub-pillar 204a can have the same resistivity or different resistivity. For example, the resistivity of the second epitaxial layer 203 can be chosen such that it is 0.5-1 times that of the second epitaxial sublayer corresponding to the N-type sub-pillar 204a. The thickness of the second epitaxial layer 203 has a certain influence on the characteristics of the body diode and the on-resistance of the device, and can be set between 5-15 micrometers. When there are some requirements for the avalanche resistance of the device, it can generally be set to 10-15 micrometers.

[0175] The second epitaxial sublayer corresponding to the N-type subpillar 204a, together with the subsequently formed P-type subpillar 205a, forms a PN subpillar in a superjunction structure. The thickness of the second epitaxial sublayer corresponding to the N-type subpillar 204a can be set to 20 micrometers, and the resistivity can be set according to the step size of the subsequent superjunction structure. For a superjunction structure with a step size of 5 micrometers, the resistivity of the second epitaxial sublayer corresponding to the N-type subpillar 204a can be set to 0.5-0.8 ohm·cm.

[0176] In a preferred embodiment, the resistivity of the first epitaxial layer 202, the second epitaxial layer 203, and the second epitaxial sublayer corresponding to the N-type subpillar 204a is set to be the same, such as 0.523 ohm-cm. 0.523 ohm-cm corresponds to a doping impurity concentration of approximately 1E16 / cm. 3 The thickness of the first epitaxial layer 202 is 5 micrometers, the thickness of the second epitaxial layer 203 is 5 μm, and the thickness of the second epitaxial sublayer corresponding to the N-type subpillar 204a is 20 μm.

[0177] Figure 3A In the process, after the etching to form the trench is completed, the third oxide layer and the second nitride layer in the hard mask layer outside the trench are etched away by drying or wet etching, leaving the bottom first oxide layer as a hard mask for the first epitaxial sublayer, such as silicon, corresponding to the trench filling P-type subpillar 205a. Then, the first epitaxial sublayer is formed to completely fill the trench. Chemical mechanical polishing (CMP) is used to remove all the material, such as silicon, from the surface of the first epitaxial sublayer, and then the first oxide layer is etched away, so that the first epitaxial sublayer completely fills only the trench and forms the P-type subpillar 205a. The second epitaxial sublayer between the P-type subpillars 205a serves as the N-type subpillar 204a. The P-type subpillars 205a and the N-type subpillars 204a are arranged alternately to form the first layer of PN subpillars. The charge of the PN subpillars is balanced, or the difference in charge is less than 5% of the total charge of the N-pillars and also less than 5% of the total charge of the P-pillars.

[0178] like Figure 3B As shown, after forming the first PN sub-pillar 301a, a pretreatment process is performed, which includes cleaning and may also include a sacrificial oxidation process. After the pretreatment, a third epitaxial sublayer 302 is deposited on the first PN sub-pillar 301a. The thickness and resistivity of the third epitaxial sublayer 302 can be designed according to the parameters of the N-type sub-pillar 204b of the subsequent second PN sub-pillar 301b. For example, the resistivity of the third epitaxial sublayer 302 is generally set to 2-5 times the resistivity of the N-type sub-pillar 204b. Typically, the doping concentration of the third epitaxial sublayer 302 should not be too high, and the thickness of the third epitaxial sublayer 302 should be set to ensure that the areal density of the impurity concentration of the third epitaxial sublayer 302 is less than or equal to 1E12 / cm². 2 Here, we take the example where the thickness of the blocking layer is directly equal to the thickness of the third epitaxial sublayer 302. In some preferred embodiments, the configuration is as follows: assuming the resistivity of the N-type subpillar 204b is 0.523 ohm-cm, the corresponding impurity concentration is 1E16 / cm². 3 Therefore, the resistivity of the third epitaxial sublayer 302 can be set to 1.57 ohm-cm, corresponding to an impurity concentration of 3E15 / cm. 3The thickness can be selected to be 3 micrometers, so that the impurity areal density of the third epitaxial sublayer 302 is 0.9E12 / cm. 2 In some embodiments, the third epitaxial sublayer 302 can also be configured with a lower doping concentration and a thinner thickness. For example, the resistivity of the third epitaxial sublayer 302 can be set to 4.48 ohm·cm, corresponding to an impurity concentration of 1E15 / cm3, and the thickness can be set to 2 micrometers. This minimizes the overall impact on the device's BVdss. Alternatively, it can be configured with a lower impurity concentration and a thicker thickness, which makes the blocking layer effect more obvious. That is, the voltage Vds at which the first PN subpillar 301a begins to bear voltage is larger, thereby providing greater improvement to the device's Cds, Coss, and the reverse recovery characteristics of the body diode.

[0179] like Figure 3B As shown, a photolithography process is performed to form a photoresist pattern 303 to select the ion implantation region. Then, using the photoresist pattern 303 as a mask, ion implantation of the first conductivity type, indicated by mark 304, is performed. The implanted impurity can be phosphorus, and implantation energies of 60keV-1000keV and implantation doses of 3E11-2E12 / cm² are used. 2 This reduces the difference in impurity concentration of the first conductivity type in the implanted region, i.e., the connecting layer 206a, from the impurity concentration of the first conductivity type subpillars in other layers, thereby improving the Rdson performance of the device. Preferably, the first conductivity type ion implantation corresponding to the mark 304 here is only performed on the active region of the device. For the terminal region and transition region, the first conductivity type ion implantation is not performed. That is, the photoresist pattern 303 will completely cover the terminal region and transition region. In this way, the overall impurity mass of the first conductivity type impurities in the terminal region of the device is reduced, which facilitates the depletion of impurities and increases the voltage that the terminal region and transition region can withstand.

[0180] like Figure 3C As shown, step one is then repeated to form the second PN sub-pillar 301b, which includes a P-type sub-pillar 205b and an N-type sub-pillar 204b. The P-type sub-pillar 205b is placed above the P-type sub-pillar 205a. The bottom of the P-type sub-pillar 205b may or may not contact the third epitaxial sublayer 302. If it contacts the third epitaxial sublayer 302, it is necessary to ensure that the third epitaxial sublayer 302 is not etched through and maintains a thickness of at least 1 micrometer. If it does not contact the third epitaxial sublayer 302, the impurity quality of the second epitaxial sublayer, the N-type sub-pillar 204b located between the P-type sub-pillars 205b and 205a, above the third epitaxial sublayer 302 must be considered. That is, the surface density of the N-type impurities between the P-type sub-pillars 205b and 205a must be less than or equal to 1E12 / cm². 2 .

[0181] The resistivity of the N-type sub-pillar 204b is set to be the same as that of the first-layer N-type sub-pillar 204a; in some embodiments, the resistivity of the N-type sub-pillar 204b can also be set to be different from that of the first-layer N-type sub-pillar 204a. The thickness of the second epitaxial sublayer of the N-type sub-pillar 204b can be set to 20-25 micrometers. Considering that alignment marks formed on the epitaxial layer below the second epitaxial sublayer of the N-type sub-pillar 204b can still be identified by associated equipment, such as lithography machines and overlay precision testing machines, after the second epitaxial sublayer of the N-type sub-pillar 204b is deposited, the thickness of the second epitaxial sublayer of the N-type sub-pillar 204b is generally thinner than 25 micrometers, preferably 20 micrometers.

[0182] P-type sub-pillars 205b and N-type sub-pillars 204b are adjacent to each other and alternately arranged to form the second layer of PN sub-pillars 301b. The charge of the second layer of PN sub-pillars 301b is balanced or the difference in charge is less than 5% of the total charge of N-type sub-pillars 204b and also less than 5% of the total charge of P-type sub-pillars 205b.

[0183] for Figure 1 The superjunction device of the first embodiment of the present invention shown has a front structure forming process after the second PN sub-pillar 301b is formed. This process includes: forming a P-type well region 207 using the same process as existing methods, depositing a gate dielectric layer 208 and a gate conductive material layer 209, forming an N+ doped source region 210, forming an interlayer film 212, a contact hole 213, a well contact region 214 formed by P-type heavy doping implantation at the bottom of the contact hole 213 of the source region 210, forming a front metal layer 215, and patterning the front metal layer 215.

[0184] To further reduce on-resistance, N-type phosphorus impurities can be implanted into the N-type region between the P-type well regions 207 to form a JFET-resistant implantation region 211. This N-type JFET-resistant implantation region 211 can be achieved by photolithography and ion implantation after the formation of the second PN subpillar 301b, or it can be achieved by photolithography and implantation after the well region 207 process is completed, before the gate conductive material layer 209, such as polysilicon gate deposition.

[0185] After the front process is completed, the following back process is also performed:

[0186] The semiconductor substrate 201 is subjected to back-side thinning, and a back-side metal layer 216 is deposited on the back side of the semiconductor substrate 20. The back-side metal layer 216 can be TiNiAg, and the thickness can be set to Ti. Ni is Ag is

[0187] After following the steps above, you will obtain... Figure 1 The superjunction device of the first embodiment of the present invention is shown.

[0188] In the method of this embodiment of the invention, by adding an N-shaped blocking layer, as shown in the dashed box 206, between the P-shaped sub-pillar 205b of the second layer PN sub-pillar 301b and the P-shaped sub-pillar 205a of the first layer PN sub-pillar 301a, the P-shaped sub-pillar 205a of the first layer is surrounded by an N-shaped region, forming a floating P-shaped sub-pillar 205a, thereby achieving the following effect:

[0189] Since the floating P-type sub-pillar 205a of this superjunction device does not participate in voltage bearing at very small Vds, such as 5V to 10V, and the PN sub-pillar 301a of the first layer does not contribute to Cds in this Vds range, the value of Cds will decrease at very small Vds, which will reduce the Coss of the device.

[0190] Because the N-type blocking layer is not depleted at lower Vds, for example, below 300V, when the superjunction device is used in a circuit with a power supply voltage below 300V, the carriers of the first-layer PN sub-pillar 301a will not be swept out at lower Vds due to the lateral depletion of the first-layer PN sub-pillar 301ad. In other words, they will be retained or partially retained. Therefore, the reverse recovery characteristics of the body diode of the device will be significantly improved.

[0191] Meanwhile, since the P-type sub-pillar 205a of the first-layer PN sub-pillar 301a is in a floating state under small Vds, the first-layer PN sub-pillar 301a is not laterally depleted. Therefore, under small Vds, the Cgd of the device will be larger than that without a blocking layer, thus making the superjunction device perform better in electromagnetic interference during use.

[0192] The interconnect layer 206, outside the high resistivity blocking layer, includes selective ion implantation with photolithography, which improves the on-resistivity of the device so that the on-resistivity of the device is not increased by the introduction of the high resistivity blocking layer, or is only minimally affected.

[0193] The method of this invention can also be used to obtain superjunction structures with more layers of the PN subpillar, for example, it can obtain... Figure 2 The superjunction device of the second embodiment of the present invention shown only requires the following further improvement:

[0194] like Figure 2As shown, after the formation of the second PN sub-pillar 301b, the formation process of the PN sub-pillar, i.e., step one, is repeated to form the third PN sub-pillar 301c. The third PN sub-pillar 301c is composed of alternating N-type sub-pillars 204c and P-type sub-pillars 205c. The depth of the third PN sub-pillar 301c is also 20 micrometers, and the width and trench tilt angle of the third PN sub-pillar 301c are the same as those of the second PN sub-pillar 301b. The P-type sub-pillar 205c of the third PN sub-pillar 301c rests on the P-type sub-pillar 205b of the bottom second PN sub-pillar 301b. In this way, the superimposed structure of the second PN sub-pillar 301b and the third PN sub-pillar 301c at the top of the blocking layer can withstand a voltage of approximately 600V. The floating P-type sub-pillar 205a of the first PN sub-pillar 301a can help to significantly improve the reverse recovery characteristics of the body diode of this type of small-step, low-Rsp device.

[0195] By further modifying the thickness of the third PN sub-pillar 301c, a superjunction device with different withstand voltages according to the second embodiment of the present invention can be obtained. For example, the thickness of the third PN sub-pillar 301c can be set to 10 micrometers, and the width and trench tilt angle of the third PN sub-pillar 301c are the same as those of the second PN sub-pillar 301b. The P-type sub-pillar 205c of the third PN sub-pillar 301c rests on the P-type sub-pillar 205b of the bottom second PN sub-pillar 301b. In this way, the superimposed structure of the second PN sub-pillar 301b and the third PN sub-pillar 301c at the top of the blocking layer can withstand a voltage of approximately 400V to 500V. The floating first p-type pillar can help to significantly improve the reverse recovery characteristics of the body diode of this type of small-step, low-Rsp device.

[0196] exist Figure 2 A further improvement on the device of the second embodiment of the present invention shown is that the superjunction structure can be stacked with one or more PN sub-pillars on top of the third PN sub-pillar 301c, thus obtaining a superjunction device with a higher voltage, while achieving excellent bulk diode flexibility and EMC characteristics.

[0197] exist Figure 2 A further improvement to the device of the second embodiment of the present invention shown is that an N-type blocking layer is also added between the P-type sub-pillar 205b of the second layer and the P-type sub-pillar 205c of the third layer, so that the P-type sub-pillar 205b of the second layer also becomes floating.

[0198] The present invention has been described in detail above through specific embodiments, but these are not intended to limit the invention. Many modifications and improvements can be made by those skilled in the art without departing from the principles of the invention, and these should also be considered within the scope of protection of the present invention.

Claims

1. A superjunction device, characterized in that, The superjunction structure includes at least two layers of PN subpillars, each layer of which is composed of alternating first conductivity type subpillars and second conductivity type subpillars; The structure of each PN sub-pillar includes: a second conductivity type sub-pillar composed of a first epitaxial sub-layer of the second conductivity type filling a trench, wherein the trench is formed in the second epitaxial sub-layer of the first conductivity type, and the first conductivity type sub-pillar is composed of the second epitaxial sub-layer between each second conductivity type sub-pillar; The superjunction structure has a blocking layer in at least a portion of its regions; In the region having the blocking layer, a third epitaxial sublayer of a first conductivity type is formed between the upper and lower layers of the PN subpillars of the blocking layer; in the longitudinal direction, the bottom surface of the second conductivity type subpillar of the PN subpillar at the top of the blocking layer is located above or below the top surface of the third epitaxial sublayer, and the blocking layer is composed of the second epitaxial sublayer and the third epitaxial sublayer below the bottom surface of the second conductivity type subpillar of the top PN subpillar, or the third epitaxial sublayer; the first conductivity type subpillars and the third epitaxial sublayers of each layer of PN subpillars are stacked to form an electrically connected first conductivity type pillar, and the second conductivity type pillars of each layer of PN subpillars and the blocking layer are stacked to form a second conductivity type pillar with a blocking layer; The second conductivity type pillar with a blocking layer includes at least one blocking layer, and the blocking layer is located between two adjacent PN sub-pillars of the second conductivity type pillar; The breakdown voltage of each PN sub-pillar located above the blocking layer is the first voltage; The voltage at which the blocking layer is completely depleted is the second voltage; The process structure of the blocking layer is configured to satisfy the requirement that the second voltage is less than the first voltage. Before the reverse bias voltage borne by the superjunction structure is less than the second voltage, the second conductivity type sub-pillars of each PN sub-pillar located below the blocking layer in the region having the blocking layer are all floating structures. After the reverse bias voltage borne by the superjunction structure is greater than the second voltage and before it is less than the first voltage, the depletion region of the superjunction structure in the region having the blocking layer extends from the top of the blocking layer to the PN sub-pillar at the bottom of the blocking layer, and the PN sub-pillar at the bottom of the blocking layer begins to bear voltage. The third epitaxial sublayer superimposed on the first conductivity type pillar serves as a connecting layer. First conductivity type ion implantation impurities are added to the formation region of the connecting layer, making the first conductivity type doping concentration of the connecting layer greater than the first conductivity type doping concentration of the third epitaxial sublayer in the blocking layer. This reduces the doping concentration difference between the connecting layer and the first conductivity type subpillars above and below the connecting layer, thereby lowering the on-resistance.

2. The superjunction device as described in claim 1, characterized in that: The resistivity of the blocking layer is higher than or equal to the resistivity of the first conductivity type sub-pillar of the top layer of the blocking layer of the PN sub-pillar; The thickness of each blocking layer is required to ensure that the areal density of the first conductivity type impurities in each blocking layer is less than or equal to 1E12cm³. -2 .

3. The superjunction device as described in claim 2, characterized in that: In the second conductive type pillar with a blocking layer, the blocking layer is at least disposed between the first PN sub-pillar and the second PN sub-pillar, wherein the first PN sub-pillar is the bottommost PN sub-pillar.

4. The superjunction device as described in claim 3, characterized in that: Superjunction devices include an active region, a transition region, and a termination region; The superjunction structure is provided in the active region, the transition region and the terminal region.

5. The superjunction device as described in claim 4, characterized in that: The region having the blocking layer is located in part or all of the active region.

6. The superjunction device as described in claim 5, characterized in that: The region containing the blocking layer is also included in part or all of the transition region and the terminal region; First conductivity type ion implantation impurities are added only in the formation region of the connection layer located in the active region; No first conductivity type ion implantation impurities are added in the formation region of the connection layer located in the transition region and the terminal region. The first conductivity type doping concentration of the connection layer located in the transition region and the terminal region is equal to the first conductivity type doping concentration of the third epitaxial sublayer in the blocking layer, so as to improve the breakdown voltage capability of the transition region and the terminal region.

7. The superjunction device as described in claim 6, characterized in that: The process conditions for adding ion implantation impurities of the first conductivity type in the connecting layer include: implantation energy of 60 keV to 1000 keV and implantation dose of 3E11cm. -2 ~2E12cm -2 .

8. The superjunction device as described in claim 3, characterized in that: When the number of PN sub-pillars is greater than or equal to 3, in each of the second conductive type pillars with blocking layers, a blocking layer is provided between the second layer of the PN sub-pillar and the top layer of the PN sub-pillar, either without a blocking layer or with at least one blocking layer.

9. The superjunction device as described in claim 8, characterized in that: The resistivity of the first conductive type sub-pillar of each PN sub-pillar is the same, the resistivity of each blocking layer is 2 to 10 times that of the first conductive type sub-pillar of each PN sub-pillar, and the size of each blocking layer is 2 micrometers to 5 micrometers.

10. The superjunction device as described in claim 8, characterized in that: The resistivity of the first conductivity type sub-pillar of each PN sub-pillar is the same, the resistivity of each blocking layer is equal to the resistivity of the first conductivity type sub-pillar of each PN sub-pillar, and the blocking layer of each layer is less than or equal to 1 micrometer.

11. The superjunction device according to any one of claims 1 to 10, characterized in that: The first conductivity type is N-type, and the second conductivity type is P-type; or, the first conductivity type is P-type, and the second conductivity type is N-type.

12. A method for manufacturing a superjunction device, characterized in that, The superjunction structure includes at least two PN subpillars, and at least a portion of the superjunction structure has a blocking layer, which is composed of a third epitaxial sublayer of a first conductivity type; in the region where the blocking layer is formed, the blocking layer is located between the upper and lower PN subpillars of a second conductivity type, and the superjunction structure formation process includes: Step 1: Form the PN sub-pillar of the current layer on the front layer structure using the PN sub-pillar formation process; when the current layer is the first layer, the front layer structure includes a semiconductor substrate and a first epitaxial layer with a first conductivity type doped on the surface of the semiconductor substrate; The process steps for forming the PN sub-pillar include: Forming a second epitaxial sublayer of the first conductivity type; Trenches are formed in the second epitaxial sublayer; The second epitaxial sublayer is filled with a first epitaxial sublayer of a second conductivity type, and the first epitaxial sublayer of the second conductivity type filled in the trench forms a second conductivity type sub-pillar. The second epitaxial sublayers between the second conductivity type sub-pillars form a first conductivity type sub-pillar. The first conductivity type sub-pillars and the second conductivity type sub-pillars are arranged alternately to form the PN sub-pillar. Step 2: If the blocking layer needs to be formed on the surface of the second conductivity type sub-pillar of the PN sub-pillar in the current layer, the steps include: forming the third epitaxial sub-layer on the surface of the PN sub-pillar in the current layer; performing first conductivity type ion implantation in a selected region of the third epitaxial sub-layer, the selected region being the formation region of the connecting layer, to increase the first conductivity type doping concentration of the connecting layer; then using the previous layer structure, the PN sub-pillar of the current layer, and the third epitaxial sub-layer as the new previous layer structure, and then repeating Step 1. If the blocking layer does not need to be formed on the surface of the second conductivity type sub-pillar of the PN sub-pillar in the current layer and the current layer is not the top layer, then the previous layer structure and the PN sub-pillar of the current layer are used as the new previous layer structure, and then step one is repeated. If the blocking layer does not need to be formed on the surface of the second conductivity type sub-pillar of the PN sub-pillar in the current layer and the current layer is the top layer, then the formation process of the superjunction structure is completed. In the region having the blocking layer, in the longitudinal direction, the bottom surface of the second conductivity type sub-pillar of the PN sub-pillar at the top of the blocking layer is located above or below the top surface of the third epitaxial sub-layer. The blocking layer is composed of the second epitaxial sub-layer and the third epitaxial sub-layer below the bottom surface of the second conductivity type sub-pillar of the top PN sub-pillar, or the third epitaxial sub-layer. The first conductivity type sub-pillars and the third epitaxial sub-layers of each layer of PN sub-pillars are stacked to form an electrically connected first conductivity type pillar, and the second conductivity type pillars of each layer of PN sub-pillars and the blocking layer are stacked to form a second conductivity type pillar with a blocking layer. The second conductivity type pillar with a blocking layer includes at least one blocking layer, and the blocking layer is located between two adjacent PN sub-pillars of the second conductivity type pillar; The breakdown voltage of each PN sub-pillar located above the blocking layer is the first voltage; The voltage at which the blocking layer is completely depleted is the second voltage; The process structure of the blocking layer is configured to satisfy the requirement that the second voltage is less than the first voltage. Before the reverse bias voltage borne by the superjunction structure is less than the second voltage, the second conductivity type sub-pillars of each PN sub-pillar located below the blocking layer in the region having the blocking layer are all floating structures. After the reverse bias voltage borne by the superjunction structure is greater than the second voltage and before it is less than the first voltage, the depletion region of the superjunction structure in the region having the blocking layer extends from the top of the blocking layer to the PN sub-pillar at the bottom of the blocking layer, and the PN sub-pillar at the bottom of the blocking layer begins to bear voltage. The third epitaxial sublayer superimposed on the first conductivity type pillar serves as the connecting layer. The first conductivity type ion implantation impurities added to the connecting layer make the first conductivity type doping concentration of the connecting layer greater than the first conductivity type doping concentration of the third epitaxial sublayer in the blocking layer, thereby reducing the doping concentration difference between the connecting layer and the first conductivity type subpillars above and below the connecting layer, and thus reducing the on-resistance.

13. The method for manufacturing a superjunction device as described in claim 12, characterized in that: The resistivity of the blocking layer is higher than or equal to the resistivity of the first conductivity type sub-pillar of the top layer of the blocking layer of the PN sub-pillar; The thickness of each blocking layer is required to ensure that the areal density of the first conductivity type impurities in each blocking layer is less than or equal to 1E12cm³. -2 .

14. The method for manufacturing a superjunction device as described in claim 13, characterized in that: In the second conductive type pillar with a blocking layer, the blocking layer is at least disposed between the first PN sub-pillar and the second PN sub-pillar, wherein the first PN sub-pillar is the bottommost PN sub-pillar.

15. The method for manufacturing a superjunction device as described in claim 14, characterized in that: Superjunction devices include an active region, a transition region, and a termination region; The superjunction structure is provided in the active region, the transition region and the terminal region.

16. The method for manufacturing a superjunction device as described in claim 15, characterized in that: The region having the blocking layer is located in part or all of the active region.

17. The method for manufacturing a superjunction device as described in claim 16, characterized in that: The region containing the blocking layer is also included in part or all of the transition region and the terminal region; First conductivity type ion implantation impurities are added only in the formation region of the connection layer located in the active region; No first conductivity type ion implantation impurities are added in the formation region of the connection layer located in the transition region and the terminal region. The first conductivity type doping concentration of the connection layer located in the transition region and the terminal region is equal to the first conductivity type doping concentration of the third epitaxial sublayer in the blocking layer, so as to improve the breakdown voltage capability of the transition region and the terminal region.

18. The method for manufacturing a superjunction device as described in claim 12 or 17, characterized in that: The process conditions for adding ion implantation impurities of the first conductivity type in the connecting layer include: implantation energy of 60 keV to 1000 keV and implantation dose of 3E11cm. -2 ~2E12cm -2 .

19. The method for manufacturing a superjunction device as described in claim 14, characterized in that: When the number of PN sub-pillars is greater than or equal to 3, in each of the second conductive type pillars with blocking layers, a blocking layer is provided between the second layer of the PN sub-pillar and the top layer of the PN sub-pillar, either without a blocking layer or with at least one blocking layer.

20. The method for manufacturing a superjunction device as described in claim 19, characterized in that: The resistivity of the first conductive type sub-pillar of each PN sub-pillar is the same, the resistivity of each blocking layer is 2 to 10 times the resistivity of the first conductive type sub-pillar of each PN sub-pillar, and the resistivity of each blocking layer is 2 micrometers to 5 micrometers. Alternatively, the resistivity of the first conductivity type sub-pillar of each PN sub-pillar is the same, the resistivity of each blocking layer is equal to the resistivity of the first conductivity type sub-pillar of each PN sub-pillar, and the blocking layer of each layer is less than or equal to 1 micrometer.

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