Superjunction Devices and Their Manufacturing Methods

Abstract

This invention discloses a superjunction device comprising at least two layers of trench-filled PN subpillars. At least a portion of the second conductivity type pillars of the superjunction structure have floating layers doped with a first conductivity type. In the first to second-top layers of the second conductivity type subpillars with floating layers, at least one layer of the second conductivity type subpillars has a floating layer. The floating layer is surrounded by the same layer of second conductivity type subpillars and consists of first conductivity type ion implantation regions with the trench of the layer above the floating layer as a self-alignment condition. The floating layer remains surrounded by the same layer of second conductivity type subpillars after lateral and longitudinal diffusion. To this end, this invention also discloses a method for manufacturing the superjunction device. This invention can improve the reverse recovery characteristics of the body diode of the device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor integrated circuit manufacturing, and in particular to a super junction device; this invention also relates to a method for manufacturing a super junction device. Background Technology

[0002] A superjunction structure is a structure consisting of alternating N-type and P-type pillars. If a superjunction structure replaces the N-type drift region in a vertical double-diffused metal-oxide-semiconductor (VDMOS) device, providing a conduction path in the on-state (only the N-type pillars provide the path, the P-type pillars do not), and withstands reverse bias in the off-state, a superjunction metal-oxide-semiconductor field-effect transistor (MOSFET) is formed. In the on-state, only the N-type pillars provide the conduction path, the P-type pillars do not provide a conduction path; the reverse bias voltage is shared by both the P-type and N-type pillars. Superjunction MOSFETs can significantly reduce the on-resistivity of a device by using a low-resistivity epitaxial layer, while maintaining the same reverse breakdown voltage as traditional VDMOS devices.

[0003] By forming trenches in an N-type epitaxial layer and filling the trenches with a P-type epitaxial layer, alternating P-type and N-type pillars, i.e., PN pillars, are formed, which is a manufacturing method for superjunctions that can be mass-produced.

[0004] To manufacture devices with higher reverse-bias breakdown voltage or lower specific on-resistance, a smaller PN pillar pitch or a deeper PN pillar is required. When using trench-filled P-type epitaxy, these requirements lead to two problems: First, a high trench aspect ratio makes trench etching problematic, especially since etching residue at the bottom of the trench cannot be completely cleaned after etching, causing device failure. Second, a large trench aspect ratio makes epitaxial filling more difficult, resulting in epitaxial voids or excessively long filling times, increasing manufacturing costs. Therefore, one approach in these situations is to divide the formation of the P-pillars into multiple or two stages, reducing the aspect ratio of each P-pillar (i.e., P-subpillar). This makes trench etching, cleaning, and filling processes feasible and cost-effective.

[0005] However, when the step size decreases, for example to 4-7 micrometers, the PN pillars are completely depleted at very low Vds under reverse bias. This causes the body diode to switch from forward conduction to reverse cutoff, resulting in the rapid sweeping out of the device at very low Vds, such as 10-30V. This worsens the reverse recovery softness of the device, making it prone to oscillations. These problems worsen as the step size decreases, and the Vds at which the P-type and N-type pillars are completely depleted laterally further deteriorate, further worsening the reverse recovery softness of the body diode. Summary of the Invention

[0006] The technical problem to be solved by the present invention is to provide a superjunction device that can improve the reverse recovery characteristics of the body diode. To this end, the present invention also provides a method for manufacturing a superjunction device.

[0007] To solve the above-mentioned technical problems, the superjunction structure of the superjunction device provided by the present invention includes at least two layers of PN subpillars, and each layer of PN subpillars is formed by alternating arrangement of first conductivity type subpillars and second conductivity type subpillars.

[0008] The structure of each PN sub-pillar includes: a second conductivity type sub-pillar composed of a first epitaxial sub-layer of the second conductivity type filling a trench, wherein the trench forms a second epitaxial sub-layer of the first conductivity type, and the first conductivity type sub-pillar is composed of the second epitaxial sub-layer between each second conductivity type sub-pillar.

[0009] The first conductivity type sub-pillars of each layer of PN sub-pillars are stacked to form a first conductivity type pillar, and the second conductivity type sub-pillars of each layer of PN sub-pillars are stacked to form a second conductivity type pillar.

[0010] The superjunction structure has a floating layer doped with a first conductivity type in at least a portion of the second conductivity type pillars.

[0011] The floating layer is formed in at least one or more of the second conductive type sub-pillars from the first layer of the second conductive type pillar having the floating layer to the second conductive type sub-pillar of the next top layer.

[0012] The floating layer is surrounded by the second conductivity type sub-pillars of the same layer. The floating layer is composed of a first conductivity type ion implantation region with the trench of the upper layer of the floating layer as the self-alignment condition. The first conductivity type ion implantation process of the floating layer ensures that the floating layer remains surrounded by the second conductivity type sub-pillars of the same layer after lateral and longitudinal diffusion.

[0013] A further improvement is that the resistivity of the floating layer is higher than or equal to the resistivity of the first conductivity type sub-pillar of the layer above the floating layer.

[0014] A further improvement is that the resistivity of the first conductive type sub-pillars of each PN sub-pillar is the same; the resistivity of the floating layer is 2 to 10 times the resistivity of the first conductive type sub-pillars of each PN sub-pillar.

[0015] A further improvement is that the thickness of the floating layer is 1 micrometer to 3 micrometers.

[0016] A further improvement is that the first conductivity type ion implantation region of the floating layer is implanted by a single implantation or multiple implantations.

[0017] A further improvement is that the process conditions for a single implantation of the first conductivity type ion implantation region of the floating layer include: an implantation energy of 1000 keV and an implantation dose of 1E12cm. -2 ~2E12cm -2 ;

[0018] The process conditions for multiple implantation of the first conductivity type ion implantation region of the floating layer include: the first implantation energy is 2000 keV, and the first implantation dose is 5E11cm. -2 ~1E12cm -2 The second injection energy was 1000 keV, and the second injection dose was 5E11cm. -2 ~1E12cm -2 .

[0019] A further improvement is that the side angle of the groove in the layer above the floating layer is greater than or equal to 89 degrees and less than or equal to 90 degrees.

[0020] A further improvement is that the top opening width of the trench in the layer above the floating layer is smaller than the top opening width of the deep trench in the same layer of the floating layer.

[0021] A further improvement is that the bottom of the trench in the upper layer of the floating layer also passes through the top of the second conductive type sub-pillar in the same layer of the floating layer, and the depth of the trench in the upper layer of the floating layer passing through the second conductive type sub-pillar in the same layer of the floating layer is 1 micrometer to 4 micrometers.

[0022] A further improvement is that the first conductivity type is N-type and the second conductivity type is P-type; or, the first conductivity type is P-type and the second conductivity type is N-type.

[0023] To solve the above-mentioned technical problems, the manufacturing method of the superjunction device provided by the present invention includes a superjunction structure comprising at least two layers of PN subpillars, each layer of PN subpillars being formed by alternating arrangement of first conductivity type subpillars and second conductivity type subpillars; the first conductivity type subpillars of each layer of PN subpillars are stacked to form a first conductivity type pillar, and the second conductivity type subpillars of each layer of PN subpillars are stacked to form a second conductivity type pillar.

[0024] The superjunction structure has a floating layer doped with a first conductivity type in at least a portion of the second conductivity type pillars; the formation process steps of the superjunction structure include:

[0025] Step 1: Provide a front layer structure and form a second epitaxial sublayer of the first conductivity type of the current layer on the front layer structure.

[0026] When the current layer is the first layer, the front layer structure includes a semiconductor substrate and a first epitaxial layer with a first conductivity type doped on the surface of the semiconductor substrate.

[0027] When the current layer is the second layer or above, the front layer structure includes the lower layer PN sub-pillar, and the top surface of the front layer structure is the top surface of the lower layer PN sub-pillar.

[0028] Step 2: Form trenches in selected regions of the second epitaxial sublayer.

[0029] When the preceding structure has the lower PN sub-pillar, the bottom surface of the trench exposes the surface of the second conductivity type sub-pillar of the lower PN sub-pillar.

[0030] Step 3: If the preceding structure includes the lower PN sub-pillar and the second conductivity type sub-pillar of the lower PN sub-pillar needs to form the floating layer, then it includes:

[0031] Using the trench as a self-alignment condition, first conductivity type ion implantation is performed in the second conductivity type sub-pillar of the lower PN sub-pillar to form the floating layer. The first conductivity type ion implantation of the floating layer ensures that the floating layer remains surrounded by the second conductivity type sub-pillar of the same layer after lateral and longitudinal diffusion; then proceed to the subsequent step four.

[0032] If the floating layer is not required, proceed directly to step four.

[0033] Step 4: Fill the trench with a first epitaxial sublayer of the second conductivity type. The first epitaxial sublayer filled in the trench forms the second conductivity type subpillar of the current layer. The second epitaxial sublayer between the second conductivity type subpillars serves as the first conductivity type subpillar. The first conductivity type subpillar and the second conductivity type subpillar are arranged alternately to form the PN subpillar of the current layer.

[0034] If the PN sub-pillar of the current layer is not the top layer, then the PN sub-pillar of the current layer is merged into the previous layer structure, and steps one to four are repeated; if the PN sub-pillar of the current layer is the top layer, then the formation process of the superjunction structure is completed.

[0035] The floating layer is formed in at least one or more of the second conductive type sub-pillars from the first layer of the second conductive type pillar having the floating layer to the second conductive type sub-pillar of the next top layer.

[0036] A further improvement is that the resistivity of the floating layer is higher than or equal to the resistivity of the first conductivity type sub-pillar of the layer above the floating layer.

[0037] A further improvement is that the resistivity of the first conductive type sub-pillars of each PN sub-pillar is the same; the resistivity of the floating layer is 2 to 10 times the resistivity of the first conductive type sub-pillars of each PN sub-pillar.

[0038] A further improvement is that the thickness of the floating layer is 1 micrometer to 3 micrometers.

[0039] A further improvement is that, in step three, the first conductivity type ion implantation of the floating layer is carried out by single implantation or multiple implantation.

[0040] A further improvement is that the process conditions for a single implantation of the first conductivity type ion implantation region of the floating layer include: an implantation energy of 1000 keV and an implantation dose of 1E12cm. -2 ~2E12cm -2 ;

[0041] The process conditions for multiple implantation of the first conductivity type ion implantation region of the floating layer include: the first implantation energy is 2000 keV, and the first implantation dose is 5E11cm. -2 ~1E12cm -2 The second injection energy was 1000 keV, and the second injection dose was 5E11cm. -2 ~1E12cm -2 .

[0042] A further improvement is that the side angle of the groove in the layer above the floating layer is greater than or equal to 89 degrees and less than or equal to 90 degrees.

[0043] A further improvement is that, in step two, if the front layer structure includes the lower PN sub-pillar, the top opening width of the trench in the current layer is smaller than the top opening width of the deep trench in the same layer of the floating layer.

[0044] A further improvement is that, in step two, if the front layer structure includes the lower PN sub-pillar, the bottom of the trench in the current layer also passes through the top of the second conductive type sub-pillar in the same layer of the floating layer, and the depth of the trench in the current layer passing through the second conductive type sub-pillar in the same layer of the floating layer is 1 micrometer to 4 micrometers.

[0045] A further improvement is that the first conductivity type is N-type and the second conductivity type is P-type; or, the first conductivity type is P-type and the second conductivity type is N-type.

[0046] This invention sets the superjunction structure in the superjunction device as a superposition structure of multiple PN sub-pillars, and the second conductivity type sub-pillars of each PN sub-pillar adopt a trench-filled structure. This can reduce the manufacturing difficulty of the superjunction structure and further reduce the step size of the superjunction unit.

[0047] Based on this, the present invention takes into account the characteristic that each layer of PN sub-pillars is formed in layers. A floating layer of the first conductivity type is set in the second conductivity type sub-pillar of at least a portion of the PN sub-pillars. The floating layer is completely surrounded by the second conductivity type sub-pillars of the same layer. Therefore, the floating layer is surrounded by second conductivity type impurities and is in a floating state. When the superjunction structure is reverse biased, the regions outside the floating layer in the first conductivity type pillar and the second conductivity type pillar will be electrically connected to the corresponding potential, causing the superjunction structure to be reverse biased. The charge carriers in the superjunction structure that are electrically connected will be quickly and completely swept out due to the lateral depletion of the PN pillars under a very small reverse bias voltage, i.e., Vds. However, since the floating layer is not connected to the external potential, the charge carriers in the floating layer will not be quickly swept out under the action of the lateral electric field under a very small reverse bias voltage. This can improve the reverse recovery characteristics of the body diode of the device. Attached Figure Description

[0048] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:

[0049] Figure 1 This is a schematic diagram of the structure of the superjunction device according to the first embodiment of the present invention;

[0050] Figure 2 This is a schematic diagram of the superjunction device according to the second embodiment of the present invention;

[0051] Figure 3 This is a schematic diagram of the superjunction device according to the third embodiment of the present invention;

[0052] Figures 4A-4C This is a schematic diagram of the device structure in each step of the manufacturing method of the superjunction device according to an embodiment of the present invention. Detailed Implementation

[0053] like Figure 1 The diagram shown is a structural schematic of a superjunction device according to the first embodiment of the present invention. The superjunction structure 301 of the superjunction device according to the first embodiment of the present invention includes at least two layers of PN subpillars, and each layer of PN subpillars is formed by alternating arrangement of first conductivity type subpillars and second conductivity type subpillars.

[0054] The structure of each PN sub-pillar includes: a second conductivity type sub-pillar composed of a first epitaxial sub-layer of the second conductivity type filling a trench, wherein the trench forms a second epitaxial sub-layer of the first conductivity type, and the first conductivity type sub-pillar is composed of the second epitaxial sub-layer between each second conductivity type sub-pillar.

[0055] The first conductivity type sub-pillars of each layer of PN sub-pillars are stacked to form a first conductivity type pillar, and the second conductivity type sub-pillars of each layer of PN sub-pillars are stacked to form a second conductivity type pillar.

[0056] Figure 1 In the superjunction structure 301, there are two layers of PN subpillars, the first layer of PN subpillars is marked with 301a and the second layer of PN subpillars is marked with 301b. The entire superjunction structure is marked with 301.

[0057] The first layer of PN sub-pillars 301a is located between lines A1A2 and B1B2. In the first layer of PN sub-pillars 301a, the first conductivity type sub-pillar is marked with 204a, and the second conductivity type sub-pillar is marked with 205a.

[0058] The second layer of PN sub-pillars 301a is located between lines A1A2 and B1B2. In the second layer of PN sub-pillars 301b, the first conductivity type sub-pillar is marked with 204b, and the second conductivity type sub-pillar is marked with 205b.

[0059] The superjunction structure 301 has a floating layer 206 doped with a first conductivity type in at least a portion of the second conductivity type pillar.

[0060] The floating layer 206 is formed in at least one layer of second conductive type sub-pillars, from the first layer of the second conductive type pillar having the floating layer 206 to the next layer of the second conductive type sub-pillars. The second conductive type sub-pillars of the first layer are also the second conductive type pillars 205a in the first layer of the PN sub-pillars 301a. Figure 1 In the corresponding first embodiment of the present invention, since there are only two PN sub-pillars in total, the first layer is also the second top layer, so the floating layer 206 is only provided in the second conductivity type sub-pillar 205a of the first layer.

[0061] The floating layer 206 is surrounded by the second conductivity type sub-pillars of the same layer. The floating layer 206 is composed of a first conductivity type ion implantation region with the trench of the upper layer of the floating layer 206 as the self-alignment condition. The first conductivity type ion implantation process of the floating layer 206 ensures that the floating layer 206 remains surrounded by the second conductivity type sub-pillars of the same layer after lateral and longitudinal diffusion.

[0062] In the first embodiment of the present invention, the resistivity of the floating layer 206 is higher than or equal to the resistivity of the first conductivity type sub-pillar of the layer above the floating layer 206.

[0063] The resistivity of the first conductivity type sub-pillars in each layer of PN sub-pillars is the same; the resistivity of the floating layer 206 is 2 to 10 times the resistivity of the first conductivity type sub-pillars in each layer of PN sub-pillars. In some embodiments, the resistivity of the floating layer 206 can also be 1 to 3 times the resistivity of the first conductivity type sub-pillars in each layer of PN sub-pillars.

[0064] In some embodiments, the thickness of the floating layer 206 is 1 micrometer to 3 micrometers.

[0065] In some embodiments, the process conditions for single-stage implantation of the first conductivity type ion implantation region of the floating layer 206 include: an implantation energy of 1000 keV and an implantation dose of 1E12cm. -2 ~2E12cm -2 .

[0066] In some embodiments, the first conductivity type ion implantation region of the floating layer 206 may be implanted multiple times. The process conditions for multiple implantations of the first conductivity type ion implantation region of the floating layer 206 include: a first implantation energy of 2000 keV and a first implantation dose of 5E11cm⁻¹. -2 ~1E12cm -2The second injection energy was 1000 keV, and the second injection dose was 5E11cm. -2 ~1E12cm -2 .

[0067] The side slope angle of the trench in the layer above the floating layer 206 is greater than or equal to 89 degrees and less than or equal to 90 degrees. The more vertical the side slope of the trench in the layer above the floating layer 206, the less impact the first conductivity type ion implantation of the floating layer 206 has on the side slope of the trench.

[0068] In the first embodiment of the present invention, the top opening width of the trench in the first layer is equal to the top opening width of the trench in the second layer.

[0069] In the first embodiment of the present invention, the first conductivity type is N-type and the second conductivity type is P-type. In other embodiments, the first conductivity type can also be P-type and the second conductivity type can be N-type.

[0070] The superjunction device further includes a front-side structure formed on the front side of the superjunction structure, the front-side structure of the superjunction device including:

[0071] The second conductivity type of well region 207 is formed on the surface of the second conductivity type sub-pillar of the corresponding topmost PN sub-pillar. Figure 1 The topmost PN sub-pillar is the second-layer PN sub-pillar 301b, and each well region 207 is formed in the top surface region of the second conductivity type sub-pillar 205b. After the well region 207 is formed, the effective thickness of the superjunction structure 301 will decrease, and the top surface will decrease from line C1C2 to line D1D2.

[0072] A gate structure formed by stacking a gate dielectric layer 208 and a gate conductive material layer 209. Figure 1 In this embodiment, the gate structure is a planar gate. The gate dielectric layer 208 is a gate oxide layer, and the gate conductive material layer 209 is a polysilicon gate. The surface of the well region 207 covered by the gate structure is used to form a conductive channel. In other embodiments, the gate structure may also be a trench gate.

[0073] A source region 210, which is heavily doped with a first conductivity type and self-aligned with the side of the gate structure, is formed on the surface of the well region 207.

[0074] In some preferred embodiments, in order to reduce on-resistance, a first conductivity type doped anti-JFET region 211 is also formed between the well regions 207.

[0075] An interlayer film 212 covers the surfaces of the gate structure, the source region 210, and the JFET region 211. Contact holes 213 are formed on the top of both the gate structure and the source region 210, passing through the interlayer film 212.

[0076] The gate structure is connected to a gate patterned from the front metal layer 215 via a top contact hole 213.

[0077] The bottom of the contact hole 213 at the top of the source region 210 will also pass through the source region 210 and contact the well region 207, and a heavily doped well contact region 214 of the second conductivity type will also be formed at the bottom of the contact hole 213 corresponding to the source region 210. The source region 210 and the well region 207 are simultaneously connected to the source electrode composed of the front metal layer 215 through the contact hole at the top.

[0078] Typically, a first epitaxial layer 202202 and a second epitaxial layer 203 are spaced between the superjunction structure 301 and the bottom semiconductor substrate 201201. The semiconductor substrate 201201 is heavily doped with a first conductivity type, and both the first epitaxial layer 202202 and the second epitaxial layer 203 are doped with a first conductivity type. The resistivity of the first epitaxial layer 202202 is less than or equal to the resistivity of the second epitaxial layer 203, and the resistivity of the second epitaxial layer 203 is less than or equal to the resistivity of the first conductivity type pillar of the superjunction structure 301.

[0079] The semiconductor substrate 201201 can be directly used as a drain region after the back side is thinned, or the drain region can be formed by further implantation of heavily doped ions of the first conductivity type on the back side after the back side is thinned.

[0080] A drain electrode composed of a back metal layer 216 is formed on the back side of the drain region.

[0081] In the first embodiment of the present invention, the superjunction structure 301 in the superjunction device is set as a superposition structure of multiple PN sub-pillars, and the second conductivity type sub-pillars of each PN sub-pillar adopt a trench-filled structure. This can reduce the manufacturing difficulty of the superjunction structure 301 and further reduce the step size of the superjunction unit.

[0082] Based on this, the first embodiment of the present invention, taking into account the characteristic that each layer of PN sub-pillars is formed in layers, sets a floating layer 206 of the first conductivity type in the second conductivity type sub-pillars of at least a portion of the PN sub-pillars. The floating layer 206 is completely surrounded by the second conductivity type sub-pillars of the same layer, so the surrounding area of ​​the floating layer 206 is all second conductivity type impurities, and it is in a floating state. When the superjunction structure 301 is reverse biased, the areas outside the floating layer 206 in the first conductivity type pillars and the second conductivity type pillars will be electrically connected to the corresponding potential, causing the superjunction structure 301 to be reverse biased. The charge carriers electrically connected in the superjunction structure 301 will be quickly and completely swept out under a very small reverse bias voltage, i.e., Vds, due to the lateral depletion of the PN pillars. However, since the floating layer 206 is not connected to the external potential, the charge carriers in the floating layer 206 will not be quickly swept out under the action of the lateral electric field under a very small reverse bias voltage. This can improve the reverse recovery characteristics of the body diode of the device.

[0083] like Figure 2 The diagram shown is a structural schematic of the superjunction device according to the second embodiment of the present invention. The difference between the superjunction device of the second embodiment of the present invention and the superjunction device of the first embodiment of the present invention is as follows:

[0084] In the superjunction structure 301 of the superjunction device in the second embodiment of the present invention, the bottom of the trench of the upper layer of the floating layer 206 also passes through the top of the second conductive type sub-pillar of the same layer of the floating layer 206, and the depth of the trench of the upper layer of the floating layer 206 passing through the second conductive type sub-pillar of the same layer of the floating layer 206 is 1 micrometer to 4 micrometers.

[0085] That is, Figure 2 The bottom surface of the trench in the second layer is located below line B1B2, which helps ensure that the floating layer 206 is completely surrounded by the second conductive type sub-pillar 205a of the first layer. First, vertically, it ensures that the floating layer 206 does not spread upward to the top of line B1B2; second, since the sides of the trench in the second layer typically have an angle of less than 90 degrees, the width of the bottom opening of the trench in the second layer decreases with increasing depth, provided that the top opening width of the trench in the second layer remains unchanged. This also helps ensure that the floating layer 206 does not spread laterally to the outside of the second conductive type sub-pillar 205a of the first layer.

[0086] like Figure 3 The diagram shown is a structural schematic of the superjunction device according to the third embodiment of the present invention. The difference between the superjunction device of the third embodiment of the present invention and the superjunction device of the second embodiment of the present invention is as follows:

[0087] In the superjunction structure 301 of the superjunction device in the third embodiment of the present invention, the top opening width of the trench of the upper layer of the floating layer 206 is smaller than the top opening width of the deep trench of the same layer of the floating layer 206.

[0088] Reducing the width of the top opening of the trench in the layer above the floating layer 206 is more conducive to ensuring that the floating layer 206 does not spread laterally to the outside of the second conductive type sub-pillar 205a in the first layer.

[0089] like Figures 4A to 4C The diagram shown is a schematic representation of the device structure in each step of the manufacturing method of the superjunction device according to an embodiment of the present invention. In the manufacturing method of the superjunction device according to an embodiment of the present invention, the superjunction structure 301 includes at least two layers of PN subpillars, each layer of PN subpillars being formed by alternating arrangement of first conductivity type subpillars and second conductivity type subpillars; the first conductivity type subpillars of each layer of PN subpillars are stacked to form a first conductivity type pillar, and the second conductivity type subpillars of each layer of PN subpillars are stacked to form a second conductivity type pillar.

[0090] The superjunction structure 301 has a floating layer 206 doped with a first conductivity type in at least a portion of the second conductivity type pillars; the formation process steps of the superjunction structure 301 include:

[0091] Step 1: Provide a front layer structure and form a second epitaxial sublayer of the first conductivity type of the current layer on the front layer structure.

[0092] like Figure 4A As shown, when the current layer is the first layer, the front layer structure includes a semiconductor substrate 201 and a first epitaxial layer 202 with a first conductivity type doped on the surface of the semiconductor substrate 201. A second epitaxial layer 203 is also formed on the surface of the first epitaxial layer 202. The semiconductor substrate 201 is heavily doped with the first conductivity type, and both the first epitaxial layer 202 and the second epitaxial layer 203 are doped with the first conductivity type. The resistivity of the first epitaxial layer 202 is less than or equal to the resistivity of the second epitaxial layer 203, and the resistivity of the second epitaxial layer 203 is less than or equal to the resistivity of the first conductivity type pillar of the superjunction structure 301.

[0093] When the current layer is the second layer or above, the front layer structure includes the lower layer PN sub-pillar, and the top surface of the front layer structure is the top surface of the lower layer PN sub-pillar.

[0094] Step 2: Form trenches in selected regions of the second epitaxial sublayer.

[0095] When the preceding structure has the lower PN sub-pillar, the bottom surface of the trench exposes the surface of the second conductivity type sub-pillar of the lower PN sub-pillar.

[0096] A hard mask layer can be used in the formation of the trench, the hard mask layer comprising a first oxide layer, a second nitride layer and a third oxide layer stacked in sequence.

[0097] Step 3: If the preceding structure includes the lower PN sub-pillar and the second conductivity type sub-pillar of the lower PN sub-pillar needs to form the floating layer 206, then it includes:

[0098] Using the trench as a self-alignment condition, first conductivity type ions are implanted into the second conductivity type sub-pillar of the lower PN sub-pillar to form the floating layer 206. The first conductivity type ion implantation of the floating layer 206 ensures that the floating layer 206 remains surrounded by the second conductivity type sub-pillar of the same layer after lateral and longitudinal diffusion; then proceed to the next step four.

[0099] If the floating layer 206 is not required, proceed directly to step four.

[0100] Step 4: Fill the trench with a first epitaxial sublayer of the second conductivity type. The first epitaxial sublayer filled in the trench forms the second conductivity type subpillar of the current layer. The second epitaxial sublayer between the second conductivity type subpillars serves as the first conductivity type subpillar. The first conductivity type subpillar and the second conductivity type subpillar are arranged alternately to form the PN subpillar of the current layer.

[0101] If the PN sub-pillar of the current layer is not the top layer, then the PN sub-pillar of the current layer is merged into the previous layer structure, and steps one to four are repeated; if the PN sub-pillar of the current layer is the top layer, then the formation process of the superjunction structure 301 is completed.

[0102] Figure 4A This shows a structural diagram after the formation of the first layer of PN sub-pillars 301a. Figure 4A In this process, a second epitaxial layer 203 is also formed on the surface of the first epitaxial layer 202. The PN sub-pillars 301a of the first layer include alternating first conductivity type sub-pillars 204a and second conductivity type sub-pillars 205a. The floating layer 206 does not need to be formed at the bottom of the second conductivity type sub-pillars 205a.

[0103] Figure 4B The diagram shows the structure after step two of the forming process is completed in the cyclic steps of forming the second layer of the PN sub-pillar 301b. It can be seen that the steps for forming the second layer of the PN sub-pillar 301b include:

[0104] First, step one is performed to form the second epitaxial sublayer of the first conductivity type sub-pillar 204b of the second PN sub-pillar 301b.

[0105] Then, step two is performed to form the trench 302. A hard mask layer 303 is used in forming the trench 302. In some preferred embodiments, the upper PN sub-pillar of the floating layer 206 is... Figure 4B The side slope angle of the trench in the current layer is greater than or equal to 89 degrees and less than or equal to 90 degrees.

[0106] Since the floating layer 206 needs to be formed in the second conductivity type sub-pillar 205a of the first layer PN sub-pillar 301a, which is the lower layer PN sub-pillar corresponding to the current layer, step three needs to be performed after the trench 302 is formed. That is, the first conductivity type ion implantation corresponding to the mark 304 and the floating layer 206 self-aligned by the trench 302 are formed while retaining the hard mask layer 303.

[0107] In some embodiments, the first conductivity type ion implantation of the floating layer 206 is performed in a single implantation. Preferably, the process conditions for single implantation of the first conductivity type ion implantation region of the floating layer 206 include: an implantation energy of 1000 keV and an implantation dose of 1E12cm. -2 ~2E12cm -2 ;

[0108] In other embodiments, the first conductivity type ion implantation of the floating layer 206 employs multiple implantations. Preferably, the process conditions for multiple implantations of the first conductivity type ion implantation region of the floating layer 206 include: a first implantation energy of 2000 keV and a first implantation dose of 5E11 cm⁻¹. -2 ~1E12cm -2 The second injection energy was 1000 keV, and the second injection dose was 5E11cm. -2 ~1E12cm -2 .

[0109] Next, in step four, the trench 302 is filled with the first epitaxial sublayer of the second conductivity type, forming the second conductivity type sub-pillar 205b of the second PN sub-pillar 301b.

[0110] For the superjunction device structure of the first embodiment of the present invention, since only two layers of the PN subpillars are required, a superjunction structure 301 with two superimposed layers is formed after the second layer of the PN subpillars 301b is formed. If more layers of the PN subpillars need to be formed, steps one to four need to be repeated for each additional layer of the PN subpillars.

[0111] The floating layer 206 is formed in at least one layer of the second conductive type sub-pillars from the first layer of the second conductive type pillar having the floating layer 206 to the second conductive type sub-pillar of the next top layer.

[0112] The resistivity of the floating layer 206 is higher than or equal to the resistivity of the first conductivity type sub-pillar of the layer above the floating layer 206.

[0113] In some embodiments, the resistivity of the first conductivity type sub-pillars of each PN sub-pillar layer is the same; the resistivity of the floating layer 206 is 2 to 10 times the resistivity of the first conductivity type sub-pillars of each PN sub-pillar layer.

[0114] The thickness of the floating layer 206 is 1 micrometer to 3 micrometers.

[0115] When it is necessary to form the superjunction device of the first embodiment of the present invention, in step two, when the current layer is the second layer, the top opening width of the trench 302 of the second layer is the same as the top opening width of the trench of the first layer; the bottom surface of the trench 302 of the second layer only needs to expose the surface of the second conductivity type sub-pillar 205a of the first layer.

[0116] When forming the superjunction device according to the second embodiment of the present invention, in step two, when the current layer is the second layer, the top opening width of the trench 302 in the second layer is the same as the top opening width of the trench in the first layer; the trench 302 in the second layer needs to penetrate part of the thickness of the second conductive type sub-pillar 205a in the first layer, which is more conducive to the floating layer 206 being completely surrounded by the second conductive type sub-pillar 205a in the first layer. Preferably, the depth of the trench in the current layer penetrating the second conductive type sub-pillar in the same layer as the floating layer 206 is 1 micrometer to 4 micrometers.

[0117] When forming the superjunction device according to the third embodiment of the present invention, in step two, when the current layer is the second layer, the top opening width of the trench 302 in the second layer is set to be the same as the top opening width of the trench in the first layer. Simultaneously, the trench 302 in the second layer needs to penetrate a portion of the thickness of the second conductive type sub-pillar 205a in the first layer. This is more conducive to the floating layer 206 being completely surrounded by the second conductive type sub-pillar 205a in the first layer. Preferably, the depth of the trench in the current layer penetrating the second conductive type sub-pillar in the same layer as the floating layer 206 is 1 micrometer to 4 micrometers.

[0118] In the method of this embodiment, the first conductivity type is N-type and the second conductivity type is P-type. In other embodiments, the first conductivity type can also be P-type and the second conductivity type can be N-type.

[0119] After forming the superjunction structure 301, a process is also included to form the front structure of the superjunction device on the surface of the superjunction structure 301; and after the front structure of the superjunction device is completed, a process is also included to form the back structure of the superjunction device.

[0120] To form Figure 1 Taking the superjunction device of the first embodiment of the present invention as an example, the process steps for forming the front structure of the superjunction device include:

[0121] A second conductivity type well region 207 is formed, and each well region 207 is formed on the surface of the second conductivity type sub-pillar of the corresponding topmost PN sub-pillar. Figure 1 The topmost PN sub-pillar is the second-layer PN sub-pillar 301b, and each well region 207 is formed in the top surface region of the second conductivity type sub-pillar 205b. After the well region 207 is formed, the effective thickness of the superjunction structure 301 will decrease, and the top surface will decrease from line C1C2 to line D1D2.

[0122] A gate structure is formed by stacking a gate dielectric layer 208 and a gate conductive material layer 209. Figure 1 In this embodiment, the gate structure is a planar gate. The gate dielectric layer 208 is a gate oxide layer, and the gate conductive material layer 209 is a polysilicon gate. The surface of the well region 207 covered by the gate structure is used to form a conductive channel. In other embodiments, the gate structure may also be a trench gate.

[0123] Source-drain injection is performed to form a first conductivity type heavily doped source region 210 on the surface of the well region 207 and self-aligned on the side of the gate structure.

[0124] In some preferred embodiments, to reduce on-resistance, a JFET-resistant region 211 doped with a first conductivity type is also formed between the well regions 207. The JFET-resistant region 211 is typically formed by photolithography and ion implantation after the formation of the superjunction structure and before the formation of the well regions 207, or by photolithography and ion implantation after the formation of the well regions 207 and before the formation of the gate structure.

[0125] An interlayer film 212 is formed, which covers the surfaces of the gate structure, the source region 210, and the JFET region 211.

[0126] Contact holes 213 are formed on the top of both the gate structure and the source region 210, extending through the interlayer film 212. The steps for forming the contact holes 213 include: first, performing photolithography to define the contact holes; then, performing etching to form the openings of the contact holes 213 extending through the interlayer film 212; and finally, filling the openings of the contact holes 213 with a metal layer to form the contact holes 213.

[0127] The gate structure is connected to a gate patterned from the front metal layer 215 via a top contact hole 213.

[0128] The bottom of the contact hole 213 at the top of the source region 210 will also pass through the source region 210 and contact the well region 207. Preferably, after the opening of the contact hole 213 is formed and before metal filling, a step of implanting heavily doped ions of the second conductivity type is included to form a heavily doped well contact region 214 of the second conductivity type at the bottom of the contact hole 213 corresponding to the source region 210. The source region 210 and the well region 207 are simultaneously connected to the source electrode composed of the front metal layer 215 through the top contact hole 213.

[0129] The process steps for forming the back-side structure of the superjunction device include:

[0130] The semiconductor substrate 201 is thinned on the back side, and the thinned semiconductor substrate 201 is used directly as the drain region, or the drain region is formed by further implantation of heavily doped ions of the first conductivity type on the back side after the back side is thinned.

[0131] A drain electrode composed of a back metal layer 216 is formed on the back side of the drain region.

[0132] The following section uses a 600V N-type superjunction MOSFET as an example and combines specific parameters to further explain in detail the manufacturing method of the superjunction device according to the embodiments of the present invention:

[0133] Since the superjunction device is an N-type device, the first conductivity type is N-type, the second conductivity type is P-type, the first conductor type sub-pillar is an N-type sub-pillar, and the second conductivity type sub-pillar is a P-type sub-pillar. Figure 4A In the first layer of PN sub-pillars, the top width of the P-type sub-pillar 205a is 3 micrometers, and the side tilt angle of the P-type sub-pillar 205a is 89 degrees; the top width of the N-type sub-pillar 204a is 2 micrometers. The step size of the first layer of PN sub-pillars is 5 micrometers. Since the superjunction structure is formed by aligning and stacking multiple layers of PN sub-pillars, the step size of each superjunction structure is also 5 micrometers. The side tilt angle of the P-type pillar is 89 degrees.

[0134] In step one, forming the first layer of the PN sub-pillars includes:

[0135] The provided semiconductor substrate 201 is an N-type substrate with a resistivity of 0.001 to 0.003 ohm·cm and a typical thickness of about 725 micrometers.

[0136] The thickness of the first epitaxial layer 202 deposited on the semiconductor substrate 201 is 5μm-10μm.

[0137] The second epitaxial layer 203 and the second epitaxial sublayer corresponding to the N-type subpillar 204a are deposited on the first epitaxial layer 202.

[0138] The hard mask layer is deposited on the second epitaxial sublayer corresponding to the N-type subpillar 204a. The hard mask layer includes a first oxide layer, a second nitride layer and a third oxide layer stacked in sequence, namely oxide film-silicon nitride film-oxide film.

[0139] Next, the trench formation area is defined by photolithography; then etching is performed. The etching first removes the oxide-silicon nitride-oxide film in the trench formation area, and uses the oxide-silicon nitride-oxide film outside the trench formation area as a hard mask to etch the material of the second epitaxial sublayer, such as silicon, to form the trench. The bottom of the trench reaches the bottom of the second epitaxial sublayer.

[0140] The resistivity of the first epitaxial layer 202 is chosen to be lower than that of the second epitaxial layer 203, typically 0.5 to 1 times the resistivity of the second epitaxial layer 203. Using a lower resistivity reduces the on-resistance of the device, while using the same resistivity simplifies the epitaxial deposition process.

[0141] The second epitaxial layer 203 and the second epitaxial sublayer corresponding to the N-type sub-pillar 204a can have the same resistivity or different resistivity. For example, the resistivity of the second epitaxial layer 203 can be chosen such that it is 0.5-1 times that of the second epitaxial sublayer corresponding to the N-type sub-pillar 204a. The thickness of the second epitaxial layer 203 has a certain influence on the characteristics of the body diode and the on-resistance of the device, and can be set between 5-15 micrometers. When there are some requirements for the avalanche resistance of the device, it can generally be set to 10-15 micrometers.

[0142] The second epitaxial sublayer corresponding to the N-type subpillar 204a, together with the subsequently formed P-type subpillar 205a, forms a PN subpillar in a superjunction structure. The thickness of the second epitaxial sublayer corresponding to the N-type subpillar 204a can be set to 20 micrometers, and the resistivity can be set according to the step size of the subsequent superjunction structure. For a superjunction structure with a step size of 5 micrometers, the resistivity of the second epitaxial sublayer corresponding to the N-type subpillar 204a can be set to 0.5-0.8 ohm·cm.

[0143] In a preferred embodiment, the resistivity of the first epitaxial layer 202, the second epitaxial layer 203, and the second epitaxial sublayer corresponding to the N-type subpillar 204a is set to be the same, such as 0.523 ohm-cm. 0.523 ohm-cm corresponds to a doping impurity concentration of approximately 1E16 / cm. 3 The thickness of the first epitaxial layer 202 is 5 micrometers, the thickness of the second epitaxial layer 203 is 5 μm, and the thickness of the second epitaxial sublayer corresponding to the N-type subpillar 204a is 20 μm.

[0144] Figure 4A In the process, after the etching to form the trench is completed, the third oxide layer and the second nitride layer in the hard mask layer outside the trench are etched away by drying or wet etching, leaving the bottom first oxide layer as a hard mask for the first epitaxial sublayer, such as silicon, corresponding to the trench filling P-type subpillar 205a. Then, the first epitaxial sublayer is formed to completely fill the trench. Chemical mechanical polishing (CMP) is used to remove all the material, such as silicon, from the surface of the first epitaxial sublayer, and then the first oxide layer is etched away, so that the first epitaxial sublayer completely fills only the trench and forms the P-type subpillar 205a. The second epitaxial sublayer between the P-type subpillars 205a serves as the N-type subpillar 204a. The P-type subpillars 205a and the N-type subpillars 204a are arranged alternately to form the first layer of PN subpillars. The charge of the PN subpillars is balanced, or the difference in charge is less than 5% of the total charge of the N-pillars and also less than 5% of the total charge of the P-pillars.

[0145] like Figure 4B As shown, after forming the first PN subpillar 301a, a pretreatment is performed, which includes cleaning and may also include a sacrificial oxidation process; then, the second epitaxial sublayer of the N-type subpillar 204b of the second PN subpillar 301b is deposited, with a resistivity of 0.523 ohm-cm and a corresponding impurity concentration of 1E16 / cm. 3 The thickness is 20 micrometers. Photolithography is then performed, forming trenches 302 with an opening width of 3 micrometers and a side tilt angle greater than or equal to 89 degrees. After trench 302 is formed, under the protection of photoresist or a hard mask layer 303, P-type ions corresponding to marker 304 are implanted into the top region of the first layer of P-type sub-pillars 205a at the bottom of trench 302. The implanted impurity is phosphorus, and the energy is a single implantation. For example, for a tilt angle of 89 degrees, phosphorus can be implanted in a single step with an implantation energy of 1000 keV and an implantation dose of 1E12 / cm². 2 ~2E12 / cm 2 It can also be a combination of phosphorus injections with different energies, for example: the first injection energy is 2000 keV and the injection dose is 5E11 / cm. 2 ~1E12 / cm2 The second injection had an injection energy of 1000 keV and an injection dose of 5 E11 / cm. 2 ~1E12 / cm 2 In this condition setting, the resistivity of the floating layer 206 formed by injection should not be lower than the resistivity of the N-type sub-pillar 204b of the second layer, which is generally recommended to be 1-3 times. At the same time, it should be ensured that after lateral and longitudinal diffusion, it is still surrounded by the P-type sub-pillar 205a of the bottom first layer of the device, and does not directly contact the N-type pillar.

[0146] The N-type impurity ion implantation in the floating layer 206 here needs to be optimized in conjunction with the process conditions in the flow, under the following comprehensive conditions:

[0147] First, after injection, a local N-type region, namely the floating layer 206, is formed. The resistivity of this region, i.e., the impurity concentration, must be higher than or equal to the impurity concentration of the N-type sub-pillar 204b in the second layer. After subsequent diffusion in the N-type injection process, the floating layer 206 formed by this N-type injection is still completely surrounded by P-type impurities. Therefore, a higher energy injection is required, while the injection dose should not be too high.

[0148] In the method of this embodiment, the trenches 302 of the first and second layers are both 20 micrometers deep and tilted at an angle of 89 degrees. With a top width of 3 micrometers, the bottom width is 2.28 micrometers. Since N-type impurity injection is completed through the bottom of the trench, only by appropriately setting the phosphorus injection conditions and subsequent thermal processes can the N-type region be controlled to be surrounded by P-type impurities, meaning the floating layer 206 is surrounded by the P-type sub-pillars 205a of the first layer.

[0149] like Figure 4C As shown, after removing the photoresist or part of the dielectric film of the hard mask layer 303, a P-type epitaxial layer is filled in the trench 302 to form P-type sub-pillars 205b and N-type sub-pillars 204b. The second layer of P-type sub-pillars 205b is placed above the first layer of P-type sub-pillars 205a. The first layer of P-type sub-pillars 205a surrounds the floating layer 206. The P-type sub-pillars 205b and N-type sub-pillars 204b are adjacent and alternately arranged to form the second layer of PN sub-pillars 301b. The charge of the second layer of PN sub-pillars 301b is balanced or the difference in charge is less than 5% of the total charge of the N-type sub-pillars 204b and also less than 5% of the total charge of the P-type sub-pillars 205b.

[0150] for Figure 1The superjunction device of the first embodiment of the present invention shown, after the formation of the second PN sub-pillar 301b, can proceed with the formation process of the front structure of the superjunction device, including: forming a P-type well region 207 using the same process as existing methods, depositing a gate dielectric layer 208 and a gate conductive material layer 209, forming an N+ doped source region 210, forming an interlayer film 212, a contact hole 213, a well contact region 214 formed by P-type heavy doping implantation at the bottom of the contact hole 213 of the source region 210, forming a front metal layer 215 and patterning the front metal layer 215. The gate dielectric layer 208 can be... The oxide layer, wherein the gate conductive material layer 209 can have a thickness of The polycrystalline silicon gate; the source / drain implantation process of the source region 210 is as follows: the implanted impurity is As, the implantation energy is 60keV, and the implantation dose is 5E15 / cm. 2 The interlayer membrane 212 includes BPSG.

[0151] To further reduce on-resistance, N-type phosphorus impurities can be implanted into the N-type region between the P-type well regions 207 to form a JFET-resistant implantation region 211. This N-type JFET-resistant implantation region 211 can be achieved by photolithography and ion implantation after the formation of the second PN subpillar 301b, or it can be achieved by photolithography and implantation after the well region 207 process is completed, before the gate conductive material layer 209, such as polysilicon gate deposition.

[0152] After the front process is completed, the following back process is also performed:

[0153] The semiconductor substrate 201 is subjected to back-side thinning, and a back-side metal layer 216 is deposited on the back side of the semiconductor substrate 20. The back-side metal layer 216 can be TiNiAg, and the thickness can be set to Ti. Ni is Ag is

[0154] After following the steps above, you will obtain... Figure 1 The superjunction device of the first embodiment of the present invention is shown.

[0155] The method of this invention involves etching the trench 302 of the second-layer PN sub-pillar 301b, and then forming an N-type region in the first-layer P-type sub-pillar 205a through ion implantation. This N-type region is surrounded by the P-type pillar region, forming a floating N-type region, namely the floating layer 206, thereby improving the reverse recovery softness of the device's bulk diode.

[0156] The method in the embodiments of the present invention can be further improved in various ways, including:

[0157] In some embodiments, in order to make the formed N-type region, i.e., the floating layer 206, easily surrounded by the P-type region, i.e., the P-type sub-pillar 205a of the first layer, the top opening width of the groove 302 of the second layer PN sub-pillar 301b, i.e., the groove 302 of the second layer, is set to 2.5 micrometers. Thus, with an inclination angle of 89 degrees and a depth of 20 micrometers, the bottom width is 1.78 micrometers. Compared with the top width of the groove of the first layer PN sub-pillar 301a of 3.0 micrometers, it is easier for the N-type region to be completely surrounded by the P-type region.

[0158] In some embodiments, to facilitate the formation of an N-type region being surrounded by a P-type region, the depth of the trench 302 during etching of the second layer is increased to penetrate the top of the P-type sub-pillar 205a of the first layer's PN sub-pillar 301a, for example, to a depth of 3 μm. This results in a trench 302 depth of 23 μm. Based on the side angle of the trench 303, at an angle of 89 degrees, the width of the trench 302 at 20 μm (line B1B2) is 2.28 μm, and at a depth of 23 μm (inside the first layer's PN sub-pillar 301a), the width is 2.16 μm. Thus, the N-type implantation is set at 60-200 keV, with a dose of 1E12-2E12 / cm². 2 As long as the thermal process after injection is not too long, for example, the thermal process should not exceed 1150 degrees and 30 minutes, it is easy to obtain the N-type region surrounded by the P-type region by setting the process parameters.

[0159] In some embodiments, after the second PN sub-pillar 301b is formed, steps one and four can be repeated to form the third PN sub-pillar. During the formation of the third PN sub-pillar, the floating layer 206 can also be formed in the P-shaped sub-pillar of the second PN sub-pillar 301b.

[0160] The present invention has been described in detail above through specific embodiments, but these are not intended to limit the invention. Many modifications and improvements can be made by those skilled in the art without departing from the principles of the invention, and these should also be considered within the scope of protection of the present invention.

Claims

1. A superjunction device, characterized in that, The superjunction structure includes at least two layers of PN subpillars, each layer of which is composed of alternating first conductivity type subpillars and second conductivity type subpillars; The structure of each PN sub-pillar includes: a second conductivity type sub-pillar consisting of a first epitaxial sub-layer of the second conductivity type filling a trench, wherein the trench is formed in the second epitaxial sub-layer of the first conductivity type, and the first conductivity type sub-pillar consisting of the second epitaxial sub-layer between each second conductivity type sub-pillar; The first conductivity type sub-pillars of each layer of PN sub-pillars are stacked to form a first conductivity type pillar, and the second conductivity type sub-pillars of each layer of PN sub-pillars are stacked to form a second conductivity type pillar; The superjunction structure has a floating layer doped with a first conductivity type in at least a portion of the second conductivity type pillars; The floating layer is formed in at least one or more of the second conductive type sub-pillars from the first layer of the second conductive type pillar having the floating layer to the second conductive type sub-pillar of the next top layer; The floating layer is surrounded by the second conductivity type sub-pillars of the same layer. The floating layer is composed of a first conductivity type ion implantation region with the trench of the upper layer of the floating layer as the self-alignment condition. The first conductivity type ion implantation process of the floating layer ensures that the floating layer remains surrounded by the second conductivity type sub-pillars of the same layer after lateral and longitudinal diffusion.

2. The superjunction device as described in claim 1, characterized in that: The resistivity of the floating layer is higher than or equal to the resistivity of the first conductivity type sub-pillar of the layer above the floating layer.

3. The superjunction device as described in claim 2, characterized in that: The resistivity of the first conductive type sub-pillars of each PN sub-pillar layer is the same; the resistivity of the floating layer is 2 to 10 times the resistivity of the first conductive type sub-pillars of each PN sub-pillar layer.

4. The superjunction device as described in claim 1, characterized in that: The thickness of the floating layer is 1 micrometer to 3 micrometers.

5. The superjunction device as described in claim 1, characterized in that: The first conductivity type ion implantation region of the floating layer is implanted by a single implantation or multiple implantations.

6. The superjunction device as described in claim 5, characterized in that: The process conditions for a single-implantation ion implantation region of the first conductivity type of the floating layer include: an implantation energy of 1000 keV and an implantation dose of 1E12 cm⁻¹. -2 ~2E12cm -2 ; The process conditions for multiple implantation of the first conductivity type ion implantation region of the floating layer include: the first implantation energy is 2000 keV, and the first implantation dose is 5E11cm. -2 ~1E12cm -2 The second injection energy was 1000 keV, and the second injection dose was 5E11cm. -2 ~1E12cm -2 .

7. The superjunction device as described in claim 1, characterized in that: The side angle of the trench in the layer above the floating layer is greater than or equal to 89 degrees and less than or equal to 90 degrees.

8. The superjunction device as described in claim 1, characterized in that: The top opening width of the groove in the layer above the floating layer is smaller than the top opening width of the groove in the same layer of the floating layer.

9. The superjunction device as described in claim 1, characterized in that: The bottom of the trench in the upper layer of the floating layer also passes through the top of the second conductive type sub-pillar in the same layer of the floating layer, and the depth of the trench in the upper layer of the floating layer passing through the second conductive type sub-pillar in the same layer of the floating layer is 1 micrometer to 4 micrometers.

10. The superjunction device according to any one of claims 1 to 9, characterized in that: The first conductivity type is N-type, and the second conductivity type is P-type; or, the first conductivity type is P-type, and the second conductivity type is N-type.

11. A method for manufacturing a superjunction device, characterized in that, The superjunction structure includes at least two layers of PN subpillars, each layer of PN subpillars being formed by alternating arrangement of first conductivity type subpillars and second conductivity type subpillars; the first conductivity type subpillars of each layer of PN subpillars are stacked to form a first conductivity type pillar, and the second conductivity type pillars of each layer of PN subpillars are stacked to form a second conductivity type pillar; The superjunction structure has a floating layer doped with a first conductivity type in at least a portion of the second conductivity type pillars; the formation process steps of the superjunction structure include: Step 1: Provide a front-layer structure and form a second epitaxial sublayer of the first conductivity type of the current layer on the front-layer structure; When the current layer is the first layer, the front layer structure includes a semiconductor substrate and a first epitaxial layer with a first conductivity type doped on the surface of the semiconductor substrate; When the current layer is the second layer or above, the front layer structure includes the lower layer PN sub-pillar and the top surface of the front layer structure is the top surface of the lower layer PN sub-pillar; Step 2: Form trenches in selected regions of the second epitaxial sublayer; When the preceding structure has the lower PN sub-pillar, the bottom surface of the trench will expose the surface of the second conductivity type sub-pillar of the lower PN sub-pillar; Step 3: If the preceding structure includes the lower PN sub-pillar and the second conductivity type sub-pillar of the lower PN sub-pillar needs to form the floating layer, then it includes: Using the trench as a self-alignment condition, first conductivity type ion implantation is performed in the second conductivity type sub-pillar of the lower PN sub-pillar to form the floating layer. The first conductivity type ion implantation of the floating layer ensures that the floating layer remains surrounded by the second conductivity type sub-pillar of the same layer after lateral and longitudinal diffusion; then proceed to the subsequent step four. If the floating layer is not required, proceed directly to step four. Step 4: Fill the trench with a first epitaxial sublayer of the second conductivity type. The first epitaxial sublayer filled in the trench forms the second conductivity type sub-pillar of the current layer. The second epitaxial sublayer between the second conductivity type sub-pillars serves as the first conductivity type sub-pillar. The first conductivity type sub-pillar and the second conductivity type sub-pillar are arranged alternately to form the PN sub-pillar of the current layer. If the PN sub-pillar of the current layer is not the top layer, then the PN sub-pillar of the current layer is merged into the previous layer structure, and steps one to four are repeated; if the PN sub-pillar of the current layer is the top layer, then the formation process of the superjunction structure is completed. The floating layer is formed in at least one or more of the second conductive type sub-pillars from the first layer of the second conductive type pillar having the floating layer to the second conductive type sub-pillar of the next top layer.

12. The method for manufacturing a superjunction device as described in claim 11, characterized in that: The resistivity of the floating layer is higher than or equal to the resistivity of the first conductivity type sub-pillar of the layer above the floating layer.

13. The method for manufacturing a superjunction device as described in claim 12, characterized in that: The resistivity of the first conductive type sub-pillars of each PN sub-pillar layer is the same; the resistivity of the floating layer is 2 to 10 times the resistivity of the first conductive type sub-pillars of each PN sub-pillar layer.

14. The method for manufacturing a superjunction device as described in claim 11, characterized in that: The thickness of the floating layer is 1 micrometer to 3 micrometers.

15. The method for manufacturing a superjunction device as described in claim 11, characterized in that: In step three, the first conductivity type ion implantation of the floating layer is performed using a single implantation or multiple implantations.

16. The method for manufacturing a superjunction device as described in claim 15, characterized in that: The process conditions for a single-implantation ion implantation region of the first conductivity type of the floating layer include: an implantation energy of 1000 keV and an implantation dose of 1E12 cm⁻¹. -2 ~2E12cm -2 ; The process conditions for multiple implantation of the first conductivity type ion implantation region of the floating layer include: the first implantation energy is 2000 keV, and the first implantation dose is 5E11cm. -2 ~1E12cm -2 The second injection energy was 1000 keV, and the second injection dose was 5E11cm. -2 ~1E12cm -2 .

17. The method for manufacturing a superjunction device as described in claim 11, characterized in that: The side angle of the trench in the layer above the floating layer is greater than or equal to 89 degrees and less than or equal to 90 degrees.

18. The method for manufacturing a superjunction device as described in claim 11, characterized in that: In step two, if the front layer structure includes the lower PN sub-pillar, the top opening width of the trench in the front layer is smaller than the top opening width of the trench in the same layer of the floating layer.

19. The method for manufacturing a superjunction device as described in claim 11, characterized in that: In step two, if the front layer structure includes the lower PN sub-pillar, and the bottom of the trench in the current layer also passes through the top of the second conductive type sub-pillar in the same layer of the floating layer, the depth of the trench in the current layer passing through the second conductive type sub-pillar in the same layer of the floating layer is 1 micrometer to 4 micrometers.

20. The method for manufacturing a superjunction device according to any one of claims 11 to 19, characterized in that: The first conductivity type is N-type, and the second conductivity type is P-type; or, the first conductivity type is P-type, and the second conductivity type is N-type.

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