Half-bridge power devices and their fabrication methods, chips

Abstract

This application proposes a half-bridge power device and its fabrication method and chip. The half-bridge power device forms two insulating regions by setting three trenches from the surface of the first substrate to the surface of the buried oxide layer and filling them with insulating material. In each insulating region, the first substrate, P-body region, first N+ region and second N+ region are equivalent to forming a MOSFET, which is led out through a metal layer. At the same time, the two equivalent MOSFETs are connected by a conductive dielectric to form an equivalent half-bridge power device. The two MOSFETs are insulated from each other by an insulating layer. There is no current path between the high-voltage drain metal layer and the low-voltage P-body region, which reduces the back gate effect and thus reduces noise and power consumption.

Description

Technical Field

[0001] This application belongs to the field of semiconductor technology, and in particular relates to a half-bridge power device and its fabrication method and chip. Background Technology

[0002] The half-bridge is one of the most commonly used switching circuit topologies in modern electronic power products, such as... Figure 1 As shown, it consists of a low-side switch Q2 (source at low potential) and a high-side switch Q1 (source at high potential) connected in the circuit. Traditional half-bridge circuits require connecting two separate MOSFETs. If the upper and lower bridge arm MOSFETs can be integrated, the circuit integration can be improved, achieving high performance and low cost.

[0003] Because a half-bridge circuit requires two complementary switches to be turned on or off, the two sources need different voltage biases. The substrate of a MOSFET is typically connected to its corresponding source; if integrated on the same substrate, a back-gate effect will occur, generating unnecessary noise during high-side switching and unnecessary power consumption within the substrate. Summary of the Invention

[0004] The purpose of this application is to provide a half-bridge power device that aims to solve the problem of back-gate effect in traditional half-bridge integrated structures.

[0005] A first aspect of this application provides a half-bridge power device, comprising:

[0006] A first substrate, a second substrate, and a buried oxide layer are stacked along a first direction;

[0007] Along the first direction, a first trench, a second trench, and a third trench are formed between the upper surface of the first substrate and the upper surface of the buried oxide layer. The first trench, the second trench, and the third trench are sequentially spaced along the second direction and filled with insulating material. The first trench and the third trench are located on both sides of the half-bridge power device, and the first direction and the second direction intersect.

[0008] Along the second direction, a P-body region, a first N+ region, and a second N+ region are disposed in the first substrate between adjacent trenches;

[0009] Along the first direction, a metal layer and a dielectric layer are stacked on the first substrate between adjacent trenches. The metal layer between adjacent trenches includes a source metal layer, a gate metal layer, and a drain metal layer that are sequentially spaced along the second direction. The gate metal layer contacts the first N+ region and the second N+ region through the dielectric layer. The drain metal layer contacts the second N+ region. The drain metal layer and the source metal layer on both sides of the second trench are connected by a conductive dielectric.

[0010] Optionally, the half-bridge power device further includes:

[0011] An insulating portion extends and connects to a corresponding trench, and the insulating portion covers the gap between the gate metal layer and the drain metal layer;

[0012] The insulating part and the insulating material in the trench are made of silicon dioxide or silicon nitride.

[0013] Optionally, the half-bridge power device further includes:

[0014] A third substrate is stacked on the buried oxide layer, opposite to the second substrate, along the first direction.

[0015] Optionally, the second and third substrates are silicon substrates;

[0016] The first substrate is a P-type substrate;

[0017] The dielectric layer and the buried oxide layer are made of silicon dioxide.

[0018] Optionally, each of the grooves is a V-shaped groove or a trapezoidal groove.

[0019] A second aspect of this application provides a method for fabricating a half-bridge power device, comprising:

[0020] A third substrate, a buried oxide layer, a second substrate, and a first substrate are stacked in the opposite direction to the first direction to form a third substrate;

[0021] Along the first direction, a first trench, a second trench, and a third trench are formed between the upper surface of the first substrate and the upper surface of the buried oxide layer. The first trench, the second trench, and the third trench are arranged at intervals along the second direction. The first trench and the third trench are located on both sides of the half-bridge power device, and the first direction and the second direction intersect.

[0022] The first trench, the second trench, and the third trench are filled with insulating material;

[0023] Along the second direction, a P-body region, a first N+ region, and a second N+ region are formed in the first substrate between adjacent trenches;

[0024] Along the first direction, a metal layer and a dielectric layer are stacked on the first substrate between adjacent trenches. The metal layer between adjacent trenches includes a source metal layer, a gate metal layer and a drain metal layer that are sequentially spaced along the second direction. The gate metal layer contacts the first N+ region and the second N+ region through the dielectric layer. The drain metal layer contacts the second N+ region. The drain metal layer and the source metal layer on both sides of the second trench are connected by a conductive dielectric.

[0025] Optionally, the step of stacking the third substrate, the buried oxide layer, the second substrate, and the first substrate in the opposite direction to the first direction specifically includes:

[0026] A second substrate and a first buried oxide layer are stacked along a first direction, and a second buried oxide layer and a third substrate are stacked in the opposite direction of the first direction;

[0027] The first buried oxide layer and the second buried oxide layer are annealed and bonded to form a second substrate, a buried oxide layer and a third substrate stacked together;

[0028] A first substrate is formed by stacking on the surface of the second substrate.

[0029] Optionally, the method for fabricating the half-bridge power device further includes:

[0030] An insulating portion is formed along a second direction, the insulating portion extending and connected to a corresponding trench, and the insulating portion covering the gap between the gate metal layer and the drain metal layer;

[0031] The insulating part and the insulating material in the trench are made of silicon dioxide or silicon nitride.

[0032] Optionally, the second and third substrates are silicon substrates;

[0033] The first substrate is a P-type substrate;

[0034] The dielectric layer and the buried oxide layer are made of silicon dioxide.

[0035] A third aspect of this application provides a chip including the half-bridge power device described above.

[0036] The beneficial effects of this application embodiment compared with the prior art are as follows: The above-mentioned half-bridge power device forms two insulating regions by setting three trenches from the surface of the first substrate to the surface of the buried oxide layer and filling them with insulating material. The first substrate, P-body region, first N+ region and second N+ region in each insulating region are equivalent to forming a MOS transistor and led out through a metal layer. At the same time, the two equivalent MOS transistors are connected by a conductive dielectric to form an equivalent half-bridge power device. The two MOS transistors are insulated from each other by an insulating layer. There is no current path between the high voltage drain metal layer and the low voltage P-body region, which weakens the back gate effect and thus reduces noise impact and power consumption. Attached Figure Description

[0037] Figure 1 This is a circuit diagram of a traditional half-bridge circuit;

[0038] Figure 2 This is a schematic diagram of the cross-section of a traditional NMOS transistor;

[0039] Figure 3 A cross-sectional schematic diagram of a half-bridge power device provided in an embodiment of this application;

[0040] Figure 4 This is a schematic diagram of a first process for fabricating a half-bridge power device according to an embodiment of this application;

[0041] Figure 5 for Figure 4 A schematic cross-sectional view of the half-bridge power device corresponding to step S20 in the fabrication method of the half-bridge power device shown.

[0042] Figure 6 for Figure 4 A schematic diagram of the specific process of step S10 in the fabrication method of the half-bridge power device shown;

[0043] Figure 7 for Figure 6 A schematic cross-sectional view of the half-bridge power device corresponding to step S11 in the fabrication method of the half-bridge power device shown.

[0044] Figure 8 for Figure 6 A schematic cross-sectional view of the half-bridge power device corresponding to step S12 in the fabrication method of the half-bridge power device shown.

[0045] Figure 9 for Figure 6 A schematic cross-sectional view of the half-bridge power device corresponding to step S13 in the fabrication method of the half-bridge power device shown.

[0046] Figure 10 This is a schematic diagram of a second process for fabricating a half-bridge power device according to an embodiment of this application. Detailed Implementation

[0047] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.

[0048] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0049] It should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0050] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0051] The first aspect of this application provides a half-bridge power device for reducing the back-gate effect between the upper and lower arms of the half-bridge.

[0052] Among them, such as Figure 2 As shown, for an NMOS transistor, the first substrate 10 is typically connected to the lowest potential of the circuit, with VBS ≤ 0 (i.e., there is no potential difference between the P-body region 41 and the second substrate 20). The threshold voltage of the MOS transistor changes depending on the potential difference between its source (S1, which is a metal directly contacting the P-body region 41, and the two are at the same potential) and the first substrate 10. This variation effect is called the "back gate effect".

[0053] Taking an NMOS transistor as an example, as VGS increases, the gate metal layer 81 attracts electrons from inside the first substrate 10 to move towards the surface of the first substrate 10, and a depletion layer is generated on the surface of the first substrate 10. When VGS rises to a certain voltage—the threshold voltage—inversion occurs on the surface of the first substrate 10 under the gate metal layer 81, and the NMOS transistor begins to conduct between the source and drain.

[0054] The threshold voltage is related to the amount of charge in the depletion layer. The more charge in the depletion layer, the more difficult it is to turn on the NMOS transistor, and the higher the threshold voltage—that is, the voltage required to turn on the NMOS. When there is current in the first substrate 10, VBS < 0 due to the voltage drop, the potential difference between the gate metal layer 81 and the first substrate 10 increases, the thickness of the depletion layer also increases, and the amount of charge in the depletion layer increases, thus causing the threshold voltage to increase. Therefore, the first substrate 10 and the gate metal layer 81 have similar functions, also controlling the change in drain current. Therefore, we call it the "back gate" function.

[0055] When a MOSFET is used in a half-bridge power device, since the drain of the high-voltage switch is generally input with a high voltage, a weak current will exist in the first substrate 10, causing VBS < 0 and resulting in a back-gate effect.

[0056] To mitigate the back-gate effect, in this embodiment, as follows: Figure 3 As shown, the half-bridge power device includes:

[0057] A first substrate 10, a second substrate 20, and a buried oxide layer 30 are stacked along the first direction X.

[0058] Along the first direction X, a first trench 31, a second trench 32, and a third trench 33 are formed between the upper surface of the first substrate 10 and the upper surface of the buried oxide layer 30. The first trench 31, the second trench 32, and the third trench 33 are arranged sequentially at intervals along the second direction Y and are filled with insulating material. The first trench 31 and the third trench 33 are located on both sides of the half-bridge power device, and the first direction X and the second direction Y intersect.

[0059] Along the second direction Y, a P-body region 41, a first N+ region 51 and a second N+ region 61 are disposed in the first substrate 10 between adjacent trenches;

[0060] Along the first direction X, a metal layer and a dielectric layer 101 are stacked on the first substrate 10 between adjacent trenches. The metal layer between adjacent trenches includes a source metal layer 91, a gate metal layer 81 and a drain metal layer 71 that are sequentially spaced along the second direction Y. The gate metal layer 81 is in contact with the first N+ region 51 and the second N+ region 61 through the dielectric layer 101, and the drain metal layer 71 is in contact with the second N+ region 61. The drain metal layer 71 and the source metal layer 91 on both sides of the second trench 32 are connected by a conductive dielectric.

[0061] By trenching and filling the SOI substrate with insulating material, the SOI substrate is divided into two insulating regions. Within each region, the first substrate 10, P-body region 41, first N+ region 51, and second N+ region 61 correspond to the gate, source, and drain of a MOS transistor. Simultaneously, the gate, source, and drain are electrically led out through the gate metal layer 81, source metal layer 91, and drain metal layer 71, respectively, effectively forming two NMOS transistors. These two NMOS transistors are connected by a conductive dielectric to form an equivalent half-bridge component, for example... Figure 2 In the middle, the left insulating area forms a low-voltage switch Q2, and the right insulating area forms a high-voltage switch Q1. The connection between the two switches is the half-bridge output port, and the drain of the high-voltage switch Q1 is the half-bridge input port. At the same time, the gates of the two switches receive drive signals VGS_HS and VGS_LS, thereby performing half-bridge inverter conversion on the input power supply.

[0062] In order to reduce the back-gate effect caused by the weak current generated from the drain of the high-voltage switch Q1 to the P-body region 41 of the low-voltage switch Q2, trenches were formed in the SOI substrate and filled with insulating material, thereby dividing the SOI substrate into two insulating regions. The first trench 31 and the third trench 33 are used to achieve electrical isolation between the half-bridge power devices and the outside world. At the same time, the second trench 32 is used to achieve electrical isolation between the drain of the high-voltage switch Q1 and the first P-body region 41 of the low-voltage switch Q2. There is no current path between the drain metal layer 71 of the high-voltage switch Q1 and the P-body region 41 of the low-voltage switch Q2, which weakens the back-gate effect. There is no substrate noise caused by crosstalk propagation between substrates, and the substrate loss in radio frequency integrated circuits is reduced in practical applications, thereby achieving the purpose of reducing noise impact and power consumption.

[0063] Meanwhile, the lateral isolation of the second trench 32 can also reduce the parasitic capacitance between the driver and the switch, as well as between the switching nodes, in the half-bridge power circuit, enabling the transistor to operate at a faster frequency.

[0064] In practical applications, the resulting half-bridge switching topology can integrate a complete high-end power supply circuit system on a single unit by embedding transistor logic circuits and passive components (resistors, capacitors) on the substrate.

[0065] The first substrate 10 can be a crystalline silicon substrate. The first substrate 10 can also be formed from other semiconductor materials, such as silicon-germanium. Furthermore, the first substrate 10 can be a bulk substrate. The first substrate 10 can be lightly doped with p-type impurities, such as boron or indium; optionally, the first substrate 10 is a p-type substrate.

[0066] The insulating material used to achieve electrical isolation can be the same type of material as the buried oxide layer 30 or a different material, such as silicon, silicon nitride, etc. To simplify the process and reduce costs, the insulating material in the trench can optionally be silicon dioxide or silicon nitride.

[0067] In order to further provide electrical isolation for the half-bridge power devices and avoid signal crosstalk between metal layers, the half-bridge power devices may optionally include:

[0068] An insulating portion extends and connects to the corresponding trench, and the insulating portion covers the gap between the gate metal layer 81 and the drain metal layer 71.

[0069] The insulating material in the insulating part and the trench is silicon dioxide or silicon nitride.

[0070] The insulating portion can be formed before or after the metal layer fabrication process. The insulating portion is an extension of the insulating material in the trench, for example... Figure 2 As shown, the insulating portion includes a first insulating portion 102 extending along the second groove 32 and a second insulating portion 103 extending along the third groove 33.

[0071] By insulating the gaps between the gate metal layer 81, the gate metal layer 81 and the drain metal layer 71, electrical crosstalk between the metal layers is reduced. When the half-bridge power device is smaller, the spacing between the gate metal layer 81, the gate metal layer 81 and the drain metal layer 71 is smaller, and the gate metal layer 81, the gate metal layer 81 and the drain metal layer 71 still have good electrical insulation.

[0072] To simplify the process, both are made of the same insulating material. Optionally, the insulating material can be silicon dioxide or silicon nitride.

[0073] The insulating section and trench form two open insulating regions, housing two NMOS transistors in a relatively sealed space, with reserved grounding positions and bridging positions for conductive media, giving the half-bridge power device good internal and external electrical isolation.

[0074] The trenches are generated using a trench process to achieve electrical isolation between high and low voltage switches. The shape of the trenches can be selected according to requirements; to simplify the process, each trench can optionally be a V-shaped trench or a trapezoidal trench.

[0075] Among these, while ensuring the performance of a single switching transistor, the insulation area formed by the buried oxide layer 30 can be minimized as much as possible. At the same time, while ensuring the trench isolation effect, the trench width can be minimized as much as possible to reduce the unit size.

[0076] The dielectric layer 101 and the buried oxide layer 30 can be made of corresponding dielectric materials, such as silicon or silicon dioxide. Optionally, to simplify the process, the dielectric layer 101 and the buried oxide layer 30 are made of silicon dioxide.

[0077] To support the buried oxide layer 30, the half-bridge power device may optionally include:

[0078] Along the first direction X, a third substrate 40 is stacked on the buried oxide layer 30 opposite to the second substrate 20. The buried oxide layer 30 is formed by ion implantation or chemical bonding on the third substrate 40. The second substrate 20 is used to support the first substrate 10. The second substrate 20 and the third substrate 40 have the same function. To simplify the process, they are made of the same material. Also, depending on the type of SiO substrate, the second substrate 20 and the third substrate 40 can optionally be silicon substrates.

[0079] Electrical connection is achieved through a conductive medium. Optionally, to simplify the process, the conductive medium, the drain metal layer of the low-voltage switch Q2, and the source metal layer of the high-voltage switch Q1 are integrated into one piece, and are made of the same material, namely metal.

[0080] The beneficial effects of this application embodiment compared with the prior art are as follows: The above-mentioned half-bridge power device forms two insulating regions by setting three trenches from the surface of the first substrate 10 to the surface of the buried oxide layer 30 and filling them with insulating material. The first substrate 10, P-body region 41, first N+ region 51 and second N+ region 61 in each insulating region are equivalent to forming a MOS transistor, which is led out through a metal layer. At the same time, the two equivalent MOS transistors are connected by a conductive dielectric to form an equivalent half-bridge power device. The two MOS transistors are insulated from each other by an insulating layer. There is no current path between the high voltage drain metal layer 71 and the low voltage P-body region 41, which weakens the back gate effect and thus reduces noise impact and power consumption.

[0081] Corresponding to the structure of half-bridge power devices, such as Figure 4 As shown, a second aspect of this application provides a method for fabricating a half-bridge power device, comprising the following steps:

[0082] Step S10: A third substrate 40, a buried oxide layer 30, a second substrate 20 and a first substrate 10 are stacked in the opposite direction along the first direction X to form a third substrate 40, a buried oxide layer 30, a second substrate 20 and a first substrate 10.

[0083] In this embodiment, the first substrate 10, the second substrate 20, the buried oxide layer 30 and the third substrate 40 constitute an SOI substrate. The SOI substrate can be formed by a process of heating and bonding with oxide chemical bonds or by an ion implantation process.

[0084] Optionally, such as Figure 6 As shown, step S10 specifically includes:

[0085] Step S11, as follows Figure 7 As shown, a second substrate 20 and a first buried oxide layer 311 are stacked along the first direction X, and a second buried oxide layer 312 and a third substrate 40 are stacked in the opposite direction of the first direction X.

[0086] Step S12, as follows Figure 8 As shown, the first buried oxide layer 311 and the second buried oxide layer 312 are annealed and bonded to form a second substrate 20, a buried oxide layer 30 and a third substrate 40 stacked together;

[0087] Step S13, as follows Figure 9 As shown, a first substrate 10 is formed by stacking on the surface of the second substrate 20.

[0088] The second substrate 20 and the first buried oxide layer 311 can be generated by ion implantation or epitaxy, and the third substrate 40 and the second buried oxide layer 312 can be generated by ion implantation or epitaxy. The first buried oxide layer 311 and the second buried oxide layer 312 are arranged opposite to each other and bonded by annealing to form a stacked second substrate 20, buried oxide layer 30 and third substrate 40. If the second substrate 20 and the third substrate 40 are thick, in order to simplify the Trench process, the second substrate 20 needs to be thinned. This can be done by physical grinding and polishing or by chemical mechanical thinning. Then, the first substrate 10 is generated on the second substrate 20 by ion implantation or epitaxy.

[0089] The second substrate 20 is used to support the first substrate 10. The second substrate 20 and the third substrate 40 have the same function. To simplify the process, they are made of the same material. Also, based on the type of SiO substrate, the second substrate 20 and the third substrate 40 can optionally be silicon substrates.

[0090] Step S20, along the first direction X, such as Figure 5As shown, a first trench 31, a second trench 32, and a third trench 33 are formed between the upper surface of the first substrate 10 and the upper surface of the buried oxide layer 30. The first trench 31, the second trench 32, and the third trench 33 are arranged sequentially at intervals along the second direction Y. The first trench 31 and the third trench 33 are located on both sides of the half-bridge power device, and the first direction X and the second direction Y intersect.

[0091] Step S30: Fill the first trench 31, the second trench 32 and the third trench 33 with insulating material;

[0092] Step S40: Along the second direction Y, a P-body region 41, a first N+ region 51, and a second N+ region 61 are formed in the first substrate 10 between adjacent trenches;

[0093] Step S50: Along the first direction X, a metal layer and a dielectric layer 101 are stacked on the first substrate 10 between adjacent trenches. The metal layer between adjacent trenches includes a source metal layer 91, a gate metal layer 81 and a drain metal layer 71 that are sequentially spaced along the second direction Y. The gate metal layer 81 is in contact with the first N+ region 51 and the second N+ region 61 through the dielectric layer 101, and the drain metal layer 71 is in contact with the second N+ region 61. The drain metal layer 71 and the source metal layer 91 on both sides of the second trench 32 are connected by a conductive dielectric.

[0094] In this embodiment, by trenching the SOI substrate and filling it with insulating material, the SOI substrate is divided into two insulating regions. Within each region, the first substrate 10, P-body region 41, first N+ region 51, and second N+ region 61 correspond to the gate, source, and drain of a MOS transistor. Simultaneously, the gate, source, and drain are electrically led out through the gate metal layer 81, source metal layer 91, and drain metal layer 71, respectively, effectively forming two NMOS transistors. These two NMOS transistors are connected across a conductive dielectric to form an equivalent half-bridge component, for example... Figure 2 In the middle, the left insulating area forms a low-voltage switch Q2, and the right insulating area forms a high-voltage switch Q1. The connection between the two switches is the half-bridge output port, and the drain of the high-voltage switch Q1 is the half-bridge input port. At the same time, the gates of the two switches receive drive signals VGS_HS and VGS_LS, thereby performing half-bridge inverter conversion on the input power supply.

[0095] In order to reduce the back-gate effect caused by the weak current generated from the drain of the high-voltage switch Q1 to the P-body region 41 of the low-voltage switch Q2, trenches were formed in the SOI substrate and filled with insulating material, thereby dividing the SOI substrate into two insulating regions. The first trench 31 and the third trench 33 are used to achieve electrical isolation between the half-bridge power devices and the outside world. At the same time, the second trench 32 is used to achieve electrical isolation between the drain of the high-voltage switch Q1 and the first P-body region 41 of the low-voltage switch Q2. There is no current path between the drain metal layer 71 of the high-voltage switch Q1 and the P-body region 41 of the low-voltage switch Q2, which weakens the back-gate effect. There is no substrate noise caused by crosstalk propagation between substrates, and the substrate loss in radio frequency integrated circuits is reduced in practical applications, thereby achieving the purpose of reducing noise impact and power consumption.

[0096] Meanwhile, the lateral isolation of the second trench 32 can also reduce the parasitic capacitance between the driver and the switch, as well as between the switching nodes, in the half-bridge power circuit, enabling the transistor to operate at a faster frequency.

[0097] In practical applications, the resulting half-bridge switching topology can integrate a complete high-end power supply circuit system on a single unit by embedding transistor logic circuits and passive components (resistors, capacitors) on the substrate.

[0098] The first substrate 10 can be a crystalline silicon substrate. The first substrate 10 can also be formed from other semiconductor materials, such as silicon-germanium. Furthermore, the first substrate 10 can be a bulk substrate. The first substrate 10 can be lightly doped with p-type impurities, such as boron or indium; optionally, the first substrate 10 is a p-type substrate.

[0099] The insulating material used to achieve electrical isolation can be the same type of material as the buried oxide layer 30 or a different material, such as silicon, silicon nitride, etc. To simplify the process and reduce costs, the insulating material in the trench can optionally be silicon dioxide or silicon nitride.

[0100] In order to further provide electrical isolation for the half-bridge power devices and avoid signal crosstalk between metal layers, optionally, such as Figure 10 As shown, the fabrication method of the half-bridge power device also includes:

[0101] Step S60: An insulating portion is formed along the second direction Y. The insulating portion extends and connects with the corresponding trench. The insulating portion covers the gap between the gate metal layer 81 and the drain metal layer 71.

[0102] The insulating material in the insulating part and the trench is silicon dioxide or silicon nitride.

[0103] The insulating portion can be formed before or after the metal layer fabrication process. The insulating portion is an extension of the insulating material in the trench, for example... Figure 2 As shown, the insulating portion includes a first insulating portion 102 extending along the second groove 32 and a second insulating portion 103 extending along the third groove 33.

[0104] By insulating the gaps between the gate metal layer 81, the gate metal layer 81 and the drain metal layer 71, electrical crosstalk between the metal layers is reduced. When the half-bridge power device is smaller, the spacing between the gate metal layer 81, the gate metal layer 81 and the drain metal layer 71 is smaller, and the gate metal layer 81, the gate metal layer 81 and the drain metal layer 71 still have good electrical insulation.

[0105] To simplify the process, both are made of the same insulating material. Optionally, the insulating material can be silicon dioxide or silicon nitride.

[0106] The insulating section and trench form two open insulating regions, housing two NMOS transistors in a relatively sealed space, with reserved grounding positions and bridging positions for conductive media, giving the half-bridge power device good internal and external electrical isolation.

[0107] The trenches are generated using a trench process to achieve electrical isolation between high and low voltage switches. The shape of the trenches can be selected according to requirements; to simplify the process, each trench can optionally be a V-shaped trench or a trapezoidal trench.

[0108] Among these, while ensuring the performance of a single switching transistor, the insulation area formed by the buried oxide layer 30 can be minimized as much as possible. At the same time, while ensuring the trench isolation effect, the trench width can be minimized as much as possible to reduce the unit size.

[0109] The dielectric layer 101 and the buried oxide layer 30 can be made of corresponding dielectric materials, such as silicon or silicon dioxide. Optionally, to simplify the process, the dielectric layer 101 and the buried oxide layer 30 are made of silicon dioxide.

[0110] Electrical connection is achieved through a conductive medium. Optionally, to simplify the process, the conductive medium, the drain metal layer of the low-voltage switch Q2, and the source metal layer of the high-voltage switch Q1 are integrated into one piece, and are made of the same material, namely metal.

[0111] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0112] This application also proposes a chip that includes a half-bridge power device. The specific structure of the half-bridge power device is as described in the above embodiments. Since this chip adopts all the technical solutions of all the above embodiments, it has at least all the beneficial effects brought about by the technical solutions of the above embodiments, which will not be described in detail here.

[0113] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A half-bridge power device, characterized by include: A first substrate, a second substrate, and a buried oxide layer are stacked along a first direction; Along the first direction, a first trench, a second trench, and a third trench are formed between the upper surface of the first substrate and the upper surface of the buried oxide layer. The first trench, the second trench, and the third trench are sequentially spaced along the second direction and filled with insulating material. The first trench and the third trench are located on both sides of the half-bridge power device, and the first direction and the second direction intersect. Along the second direction, a P-body region, a first N+ region, and a second N+ region are disposed in the first substrate between adjacent trenches; Along the first direction, a metal layer and a dielectric layer are stacked on the first substrate between adjacent trenches. The metal layer between adjacent trenches includes a source metal layer, a gate metal layer, and a drain metal layer that are sequentially spaced along the second direction. The gate metal layer contacts the first N+ region and the second N+ region through the dielectric layer. The drain metal layer contacts the second N+ region. The drain metal layer and the source metal layer on both sides of the second trench are connected by a conductive dielectric.

2. The half bridge power device of claim 1, wherein, The half-bridge power device also includes: An insulating portion extends and connects to a corresponding trench, and the insulating portion covers the gap between the gate metal layer and the drain metal layer; The insulating part and the insulating material in the trench are made of silicon dioxide or silicon nitride.

3. The half bridge power device of claim 1, wherein, The half-bridge power device also includes: A third substrate is stacked on the buried oxide layer, opposite to the second substrate, along the first direction.

4. The half bridge power device of claim 3, wherein, The second and third substrates are silicon substrates; The first substrate is a P-type substrate; The dielectric layer and the buried oxide layer are made of silicon dioxide.

5. The half bridge power device of claim 1, wherein, Each of the grooves is either a V-shaped groove or a trapezoidal groove.

6. A method of manufacturing a half-bridge power device, characterized by include: A third substrate, a buried oxide layer, a second substrate, and a first substrate are stacked in the opposite direction to the first direction to form a third substrate; Along the first direction, a first trench, a second trench, and a third trench are formed between the upper surface of the first substrate and the upper surface of the buried oxide layer. The first trench, the second trench, and the third trench are arranged alternately along the second direction. The first trench and the third trench are located on both sides of the half-bridge power device, and the first direction and the second direction intersect. The first trench, the second trench, and the third trench are filled with insulating material; Along the second direction, a P-body region, a first N+ region, and a second N+ region are formed in the first substrate between adjacent trenches; Along the first direction, a metal layer and a dielectric layer are stacked on the first substrate between adjacent trenches. The metal layer between adjacent trenches includes a source metal layer, a gate metal layer and a drain metal layer that are sequentially spaced along the second direction. The gate metal layer contacts the first N+ region and the second N+ region through the dielectric layer. The drain metal layer contacts the second N+ region. The drain metal layer and the source metal layer on both sides of the second trench are connected by a conductive dielectric.

7. The method of fabricating a half bridge power device of claim 6, wherein, The step of stacking the third substrate, buried oxide layer, second substrate, and first substrate in the opposite direction of the first direction specifically includes: A second substrate and a first buried oxide layer are stacked along a first direction, and a second buried oxide layer and a third substrate are stacked in the opposite direction of the first direction; The first buried oxide layer and the second buried oxide layer are annealed and bonded to form a second substrate, a buried oxide layer and a third substrate stacked together; A first substrate is formed by stacking on the surface of the second substrate.

8. The method of fabricating a half bridge power device of claim 6, wherein, The method for fabricating the half-bridge power device further includes: An insulating portion is formed along a second direction, the insulating portion extending and connected to a corresponding trench, and the insulating portion covering the gap between the gate metal layer and the drain metal layer; The insulating part and the insulating material in the trench are made of silicon dioxide or silicon nitride.

9. The method for fabricating a half-bridge power device as described in claim 6, characterized in that, The second and third substrates are silicon substrates; The first substrate is a P-type substrate; The dielectric layer and the buried oxide layer are made of silicon dioxide.

10. A chip, characterized in that, Includes the half-bridge power device as described in any one of claims 1 to 5.

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