A SiC VDMOSFET device with integrated HJD and its fabrication method

Abstract

This invention relates to a SiC VDMOSFET device with integrated heterojunction diode (HJD) and its fabrication method, comprising: a metallized drain, an N+ substrate layer, an N- epitaxial layer, a P-base region, a P+ implantation region, an N+ implantation region, an N-doped region, a P+ polysilicon region, a gate dielectric layer, an N+ polysilicon gate, and a metallized source. The P-base region, P+ implantation region, and N-doped region have the same depth. The contact interface between the source and the P+ implantation region, N+ implantation region, and P+ polysilicon region is an ohmic contact, and the interface between the P+ polysilicon region and the N-doped region is a heterojunction contact. This invention integrates a heterojunction diode structure within the device, improving cell area utilization, further reducing the turn-on voltage while reducing the gate capacitance, turn-on time, and device switching losses.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, specifically to a SiC VDMOSFET device with integrated HJD and its fabrication method. Background Technology

[0002] Silicon carbide (SiC) has a wider bandgap, a larger critical breakdown electric field, and higher thermal conductivity than silicon, giving SiC devices better radiation resistance, lower on-resistance, and lower energy loss. In summary, SiC devices offer significant advantages in high-power, high-temperature, high-radiation environments, as well as energy efficiency and environmental friendliness.

[0003] Metal-oxide-semiconductor field-effect transistors (MOSFETs) possess a range of advantages, including high integration density, good thermal stability, and strong radiation resistance, making them widely used in power electronic systems. SiC MOSFETs, as a new type of third-generation semiconductor device, are currently the most favored silicon carbide power semiconductor device in industry due to their low on-state resistance, fast switching speed, and simple drive circuitry. Vertical double-diffused metal-oxide-semiconductor field-effect transistors (VDMOSFETs) are another widely used type of MOSFET.

[0004] In power electronic systems, SiC MOSFETs primarily function as electronic switches. When the MOSFET is in the off state, there is a reverse leakage current between the drain and source. Without an anti-parallel diode, this leakage current could damage other components in the circuit. Furthermore, when SiC MOSFETs are used for AC circuit rectification, since the MOSFET can only conduct under forward voltage, an anti-parallel diode is needed to provide a conduction path under reverse voltage, thereby achieving current rectification. Therefore, a diode is typically connected in anti-parallel externally or integrated internally within the SiC MOSFET to improve the performance of the SiC MOSFET's body diode, thus increasing the SiC MOSFET's operating efficiency.

[0005] Connecting a reverse-parallel diode outside the SiC MOSFET can significantly improve the performance of the SiC MOSFET body diode, but it increases the circuit footprint, raises the device packaging cost, and introduces parasitic capacitance and inductance, resulting in a slower response speed of the reverse diode. Therefore, existing technologies integrate Schottky barrier diodes (SBDs) and junction barrier Schottky diodes (JBSs) inside the SiC MOSFET. However, the internally integrated SBDs and JBSs still have a large turn-on voltage and have high design complexity and manufacturing cost, so further technological improvements are needed. Summary of the Invention

[0006] To address the aforementioned problems in the prior art, this invention provides a SiCVD MOSFET device with integrated HJD and its fabrication method. The technical problem to be solved by this invention is achieved through the following technical solution:

[0007] A SiC VDMOSFET device with integrated HJD (High-Jet Discharge) includes a metallized drain, an N+ substrate layer, and an N- epitaxial layer stacked sequentially from bottom to top. The metallized drain and the N+ substrate layer have an ohmic contact. The N- epitaxial layer contains a first P-base region, a second P-base region, a first P+ implantation region, a second P+ implantation region, a first N+ implantation region, a second N+ implantation region, a first N-doped region, and a second N-doped region.

[0008] The first P-base region and the second P-base region are separated by the N-epitaxial layer;

[0009] The first P+ injection region is located on the side of the first P-base region that is away from the second P-base region; the second P+ injection region is located on the side of the second P-base region that is away from the first P-base region.

[0010] The first N+ injection region is disposed within the first P-base region, and the second N+ injection region is disposed within the second P-base region;

[0011] The first N-doped region is disposed on the side of the first P+ implanted region away from the first P-base region; the second N-doped region is disposed on the side of the second P+ implanted region away from the second P-base region.

[0012] A first P+ polysilicon region is disposed on the first N-doped region, and a heterojunction contact is formed between the first N-doped region and the first P+ polysilicon region. A second P+ polysilicon region is disposed on the second N-doped region, and a heterojunction contact is formed between the second N-doped region and the second P+ polysilicon region.

[0013] In one embodiment of the present invention, the first P-base region and the second P-base region are symmetrically arranged, and the first P-base region and the second P-base region have the same width and depth.

[0014] In one embodiment of the present invention, the first P+ injection region and the second P+ injection region are symmetrically arranged, and the first P+ injection region and the second P+ injection region have the same width and depth.

[0015] In one embodiment of the present invention, the first N-doped region and the second N-doped region are symmetrically arranged, the first N-doped region and the second N-doped region have the same width and depth, and the doping concentration of the first N-doped region and the second N-doped region is greater than the doping concentration of the N-epitaxial layer.

[0016] In one embodiment of the present invention, the first N-doped region and the second N-doped region are symmetrically arranged, and the first N-doped region and the second N-doped region have the same width and depth;

[0017] The upper surface of the first N+ injection region is flush with the upper surface of the first P-base region, and the lower surface of the first N+ injection region is located within the first P-base region; the upper surface of the second N+ injection region is flush with the upper surface of the second P-base region, and the lower surface of the second N+ injection region is located within the second P-base region.

[0018] In one embodiment of the present invention, one side of the first N+ injection region is in contact with the first P+ injection region, and the other side of the first N+ injection region is disposed within the first P- base region; one side of the second N+ injection region is in contact with the second P+ injection region, and the other side of the second N+ injection region is disposed within the second P- base region.

[0019] The first P+ injection region is in contact with the side of the first P- base region; the second P+ injection region is in contact with the side of the second P- base region;

[0020] The first N-doped region is in contact with the side of the first P+ implanted region, and the second N-doped region is in contact with the side of the second P+ implanted region;

[0021] The depths of the first P-base region, the second P-base region, the first P+ implantation region, the second P+ implantation region, the first N-doped region, and the second N-doped region are all the same.

[0022] In one embodiment of the present invention, a step is provided at one end of the first P+ implantation region near the first N- doped region, and a step is provided at one end of the second P+ implantation region near the second N- doped region;

[0023] The upper surfaces of the first N-doped region and the second N-doped region are lower than the upper surfaces of the first P+ implanted region and the second P+ implanted region. The upper surface of the first N-doped region is flush with the platform of the step of the first P+ implanted region, and the upper surface of the second N-doped region is flush with the platform of the step of the second P+ implanted region.

[0024] In one embodiment of the present invention, the SiC VDMOSFET device further includes a ring-shaped gate dielectric layer and an N+ polysilicon gate, wherein,

[0025] The gate dielectric layer is disposed on the first N+ implantation region, the first P-base region, the N-epitaxy layer, the second P-base region, and the second N+ implantation region;

[0026] The N+ polysilicon gate is disposed within the annular region of the gate dielectric layer, and the width of the N+ polysilicon gate is less than the distance between the outer side of the first N+ implantation region and the outer side of the second N+ implantation region.

[0027] In one embodiment of the present invention, the SiC VDMOSFET device further includes a metallized source, which is disposed above the first P+ polysilicon region, the first P+ implantation region, the first N+ implantation region, the gate dielectric layer, the second N+ implantation region, the second P+ implantation region, and the second P+ polysilicon region, and forms an ohmic contact.

[0028] The present invention also provides a method for fabricating a SiC VDMOSFET device with integrated HJD, used to fabricate the SiC VDMOSFET device described in any of the above embodiments, the fabrication method comprising:

[0029] Step 1: Select an N+ substrate layer;

[0030] Step 2: Form the N- epitaxial layer on the N+ substrate layer using an epitaxial growth method;

[0031] Step 3: Ion implantation is performed on the surface of the N-epitaxial layer to form the first P-base region and the second P-base region;

[0032] Step 4: Ion implantation is performed on the surfaces of the first P-based region and the second P-based region to form the first P+ implantation region and the second P+ implantation region respectively;

[0033] Step 5: Ion implantation is performed on the surfaces of the first P-base region and the second P-base region to form a first N+ implantation region, a second N+ implantation region, a first N-doped region, and a second N-doped region.

[0034] Step 6: First, etch the first P+ implantation region, the second P+ implantation region, the first N-doped region, and the second N-doped region. Then, deposit a gate dielectric layer on the first N+ implantation region, the first P-base region, the N-epilithial layer, the second P-base region, and the second N+ implantation region. Finally, deposit polysilicon on the etched first N-doped region, the second N-doped region, and the gate dielectric layer to form the first P+ polysilicon region, the second P+ polysilicon region, and the N+ polysilicon gate.

[0035] Step 7: Continue to deposit the gate dielectric layer to form a ring-shaped gate dielectric layer, and form a metallized drain on the lower surface of the N+ substrate layer. Form a metallized source on the first P+ polysilicon region, the first P+ implantation region, the first N+ implantation region, the gate dielectric layer, the second N+ implantation region, the second P+ implantation region, and the second P+ polysilicon region.

[0036] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0037] The contact between the P+ polysilicon region and the N- epitaxial layer in this invention is a heterojunction contact, that is, an HJD structure is integrated inside the SiC VDMOSFET device, replacing the SBD or JBS structure integrated inside a typical SiC VDMOSFET device. Since the potential barrier height in the valence band between the 4H-SiC and the polysilicon junction is very large and the potential barrier height in the conduction band is very low, in the HJDMOSFET, the electron current can move towards the source, while the hole current cannot move towards the drain. Therefore, it works as a unipolar device and has excellent reverse recovery characteristics. Thus, the HJD structure has a lower turn-on voltage, a smaller reverse recovery charge Qrr, and a smaller switching loss energy.

[0038] The first P+ injection region and the second P+ injection region provided in the P-base region of the present invention have a shielding effect, which can protect the heterojunction interface from the influence of high electric field and improve the withstand voltage capability of the device.

[0039] In this invention, the concentrations of the first N-doped region and the second N-doped region in the P-base region are slightly higher than those in the N-epitaxial layer, which serves to further reduce the turn-on voltage of the heterojunction diode.

[0040] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0041] Figure 1 This is a schematic diagram of the structure of a SiC VDMOSFET device with integrated HJD provided in an embodiment of the present invention;

[0042] Figures 2a-2f This is a schematic diagram illustrating the process of fabricating a SiC VDMOSFET device with integrated HJD according to an embodiment of the present invention.

[0043] Symbol explanation:

[0044] 1-N+ substrate layer; 2-N-epitaxial layer; 3-first P-base region; 4-second P-base region; 5-first P+ implantation region; 6-second P+ implantation region; 7-first N+ implantation region; 8-second N+ implantation region; 9-gate dielectric layer; 10-N+ polysilicon gate; 11-first N-doped region; 12-second N-doped region; 13-first P+ polysilicon region; 14-second P+ polysilicon region; 15-metallized drain; 16-metallized source. Detailed Implementation

[0045] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0046] Example 1

[0047] Please see Figure 1 , Figure 1 This is a schematic diagram of a SiC VDMOSFET device with integrated HJD provided in an embodiment of the present invention. The embodiment of the present invention provides a SiC VDMOSFET device with integrated HJD, which includes a metallized drain 15, an N+ substrate layer 1, and an N- epitaxial layer 2 stacked sequentially from bottom to top. The metallized drain 15 and the N+ substrate layer 1 have an ohmic contact. The N- epitaxial layer 2 contains a first P-base region 3, a second P-base region 4, a first P+ implantation region 5, a second P+ implantation region 6, a first N+ implantation region 7, a second N+ implantation region 8, a first N-doped region 11, and a second N-doped region 12.

[0048] The first P-base region 3 and the second P-base region 4 are separated by an N-epitaxial layer 2;

[0049] The first P+ injection region 5 is located on the side of the first P-base region 3 away from the second P-base region 4; the second P+ injection region 6 is located on the side of the second P-base region 4 away from the first P-base region 3;

[0050] The first N+ injection region 7 is located within the first P-base region 3, and the second N+ injection region 8 is located within the second P-base region 4;

[0051] The first N-doped region 11 is disposed on the side of the first P+ implantation region 5 away from the first P-base region 3; the second N-doped region 12 is disposed on the side of the second P+ implantation region 6 away from the second P-base region 4;

[0052] A first P+ polysilicon region 13 is provided on the first N-doped region 11, and a heterojunction contact is formed between the first N-doped region 11 and the first P+ polysilicon region 13. A second P+ polysilicon region 14 is provided on the second N-doped region 12, and a heterojunction contact is formed between the second N-doped region 12 and the second P+ polysilicon region 14.

[0053] The gate dielectric layer 9 is disposed on the first N+ implantation region 7, the first P-base region 3, the N-epitaxy layer 2, the second P-base region 4, and the second N+ implantation region 8;

[0054] The N+ polysilicon gate 10 is disposed in the annular region of the gate dielectric layer 9, and the width of the N+ polysilicon gate is less than the distance between the outer side of the first N+ implantation region 7 and the outer side of the second N+ implantation region 8.

[0055] In this invention, the first N-doped region 11 and the first P+ polysilicon region 13 form a heterojunction contact, and the second N-doped region 12 and the second P+ polysilicon region 14 also form a heterojunction contact. This means that an HJD (hetero-junction diode) structure is integrated within the SiC VDMOSFET device, replacing the SBD or JBS structure typically integrated within SiC VDMOSFET devices. Because the potential barrier height between the SiC and polysilicon junctions in the valence band of the HJD is very high, the HJD provided in this invention... In a MOSFET, electron current can move towards the source, while hole current cannot move towards the drain. Therefore, only electrons conduct electricity, making it a unipolar device. During reverse recovery, there is no recombination process between electrons and holes; only a small number of electrons need to be removed from the N-region, resulting in a fast recovery speed and excellent reverse recovery characteristics. This leads to a smaller reverse recovery charge Qrr and lower switching loss energy. SiC and polysilicon have lower potential barriers in the conduction band. When the source is positive, electrons can more easily cross the barrier of the HJD, making the HJD more conductive than a pin diode. Therefore, the HJD structure has a lower turn-on voltage.

[0056] In this invention, a first P+ injection region and a second P+ injection region are provided in the first P-base region and the second P-base region. In the off state, the depletion region generated in the first P+ injection region and the second P+ injection region can protect the p+ polysilicon region from the influence of high drain voltage and enable it to operate stably under high voltage. Therefore, the first P+ injection region and the second P+ injection region have a shielding effect, which can protect the heterojunction interface from the influence of high electric field and improve the breakdown voltage capability of the device.

[0057] In this embodiment, the first P-base region 3 and the second P-base region 4 are symmetrically arranged, and the first P-base region 3 and the second P-base region 4 have the same width and depth.

[0058] In this embodiment, the first P+ injection region 5 and the second P+ injection region 6 are symmetrically arranged, and the first P+ injection region 5 and the second P+ injection region 6 have the same width and depth.

[0059] In this embodiment, the first N-doped region 11 and the second N-doped region 12 are symmetrically arranged, and the first N-doped region 11 and the second N-doped region 12 have the same width and depth. The doping concentration of the first N-doped region 11 and the second N-doped region 12 is greater than the doping concentration of the N-epitaxial layer 2.

[0060] The concentrations of the first N-doped region and the second N-doped region in the first P-base region and the second P-base region of the present invention are slightly higher than those of the N-epitaxial layer. Therefore, the barrier of the HJD formed with the P+ polysilicon region will be relatively low, thereby reducing the turn-on voltage of the body diode.

[0061] In this embodiment, the first N-doped region 11 and the second N-doped region 12 are symmetrically arranged, and the first N-doped region 11 and the second N-doped region 12 have the same width and depth;

[0062] The upper surface of the first N+ injection region 7 is flush with the upper surface of the first P-base region 3, and the lower surface of the first N+ injection region 7 is located within the first P-base region 3; the upper surface of the second N+ injection region 8 is flush with the upper surface of the second P-base region 4, and the lower surface of the second N+ injection region 8 is located within the second P-base region 4.

[0063] In this embodiment, one side of the first N+ injection region 7 is in contact with the first P+ injection region 5, and the other side of the first N+ injection region 7 is disposed within the first P- base region 3. One side of the second N+ injection region 8 is in contact with the second P+ injection region 6, and the other side of the second N+ injection region 8 is disposed within the second P- base region 4.

[0064] The first P+ injection region 5 is in contact with the side of the first P- base region 3; the second P+ injection region 6 is in contact with the side of the second P- base region 4.

[0065] The first N-doped region 11 is in contact with the side of the first P+ implanted region 5, and the second N-doped region 12 is in contact with the side of the second P+ implanted region 6.

[0066] The first P-base region 3, the second P-base region 4, the first P+ implantation region 5, the second P+ implantation region 6, the first N-doped region 11, and the second N-doped region 12 all have the same depth.

[0067] In this embodiment, a step is provided at one end of the first P+ implantation region 5 near the first N- doped region 11, and a step is provided at one end of the second P+ implantation region 6 near the second N- doped region 12;

[0068] The upper surfaces of the first N-doped region 11 and the second N-doped region 12 are lower than the upper surfaces of the first P+ implanted region 5 and the second P+ implanted region 6. The upper surface of the first N-doped region 11 is flush with the platform of the step of the first P+ implanted region 5, and the upper surface of the second N-doped region 12 is flush with the platform of the step of the second P+ implanted region 6.

[0069] In summary, please refer to Figure 1 The N-epitaxial layer 2 is provided with a first P-base region 3 and a second P-base region 4, and the first P-base region 3 and the second P-base region 4 are provided with a first P+ implantation region 5, a second P+ implantation region 6, a first N+ implantation region 7, a second N+ implantation region 8, a first N-doped region 11, and a second N-doped region 12.

[0070] There are two P-base regions, the first P-base region 3 and the second P-base region 4. The first P-base region 3 and the second P-base region 4 are located at the leftmost and rightmost horizontal positions of the N-epitaxial layer 2, respectively. The upper left part of the first P-base region 3 and the upper right part of the second P-base region 4 are etched into a groove shape. The first P-base region 3 and the second P-base region 4 are symmetrically arranged and have the same width and depth.

[0071] There are two P+ implantation regions: the first P+ implantation region 5 and the second P+ implantation region 6. The first P+ implantation region 5 is located in the middle region of the first P-base region 3, and its left boundary is close to the first N-doped region 11, and its right boundary is close to the first N+ implantation region 7. The second P+ implantation region 6 is located in the middle region of the second P-base region 4, and its left boundary is close to the second N+ implantation region 8, and its right boundary is close to the second N-doped region 12.

[0072] The first P+ injection region 5 and the second P+ injection region 6 have the same shape, the same horizontal height, the same width and depth, and the depth of the first P+ injection region 5 and the second P+ injection region 6 is the same as that of the first P-base region 3 and the second P-base region 4.

[0073] There are two N+ injection regions, namely the first N+ injection region 7 and the second N+ injection region 8. The first N+ injection region 7 is located to the right of the first P+ injection region 5, and the second N+ injection region 8 is located to the left of the second P+ injection region 6. The first N+ injection region 7 and the second N+ injection region 8 are located within the first P-base region 3 and the second P-base region 4, respectively.

[0074] There are two N-doped regions 11 and 12. The first N-doped region 11 is located at the leftmost horizontal level at the lower end of the first P-base region 3, and the second N-doped region 12 is located at the rightmost horizontal level at the lower end of the second P-base region 4.

[0075] The first N-doped region 11 and the second N-doped region 12 have the same horizontal height, the same width and depth, and the depth of the first N-doped region 11 and the second N-doped region 12 is the same as that of the first P-base region 3 and the second P-base region 4.

[0076] The horizontal order from left to right at the top of the N-epitaxial layer 2 is as follows: first N-doped region 11, first P+ implanted region 5, first N+ implanted region 7, first P-base region 3, N-epitaxial layer 2, second P-base region 4, second N+ implanted region 8, second P+ implanted region 6, and second N-doped region 12.

[0077] There are two P+ polysilicon regions 13 and 14. The first P+ polysilicon region 13 is located above the leftmost side of the N-epitaxial layer, and the right side of the first P+ polysilicon region 13 is perpendicularly aligned with the right side of the first N-doped region 11. The second P+ polysilicon region 14 is located above the rightmost side of the N-epitaxial layer, and the left side of the second P+ polysilicon region 14 is perpendicularly aligned with the left side of the second N-doped region 12. The contacts between the first P+ polysilicon region 13 and the second P+ polysilicon region 14 and the first N-doped region 11 and the second N-doped region 12, respectively, are heterojunction contacts.

[0078] The N+ polysilicon gate 10 is located above the first N+ implantation region 11, the first P-base region 3, the N-epilithial layer 2, the second P-base region 4, and the second N+ implantation region 8; the width of the N+ polysilicon gate 10 is less than the horizontal distance from the left boundary of the first N+ implantation region 7 to the right boundary of the second N+ implantation region 8.

[0079] The N+ polysilicon gate 10 is surrounded by the gate dielectric layer 9, meaning that all structures in contact with the N+ polysilicon gate 10 are isolated by the gate dielectric layer 9.

[0080] The metallized source 16 is in direct contact with the first P+ polysilicon region 13, the first P+ implantation region 5, the first N+ implantation region 7, the gate dielectric layer 9, the second N+ implantation region 8, the second P+ implantation region 6, and the second P+ polysilicon region 14 from left to right at the bottom horizontal position. The metallized source 16 is in ohmic contact with the P+ implantation region 5 / 6, the N+ implantation region 7 / 8, and the P+ polysilicon region 13 / 14.

[0081] Optionally, the metal materials for the metallized drain and metallized source are titanium, nickel, molybdenum or tungsten.

[0082] Optionally, the thickness of the N+ substrate layer is 1–100 μm.

[0083] For example, the thickness of the N+ substrate is 3 μm, and the doping concentration is 5 × 10⁻⁶. 18 cm -3 .

[0084] Optionally, the thickness of the N-epitaxial layer is 10–500 μm.

[0085] For example, the thickness of the N-epitaxial layer is 30 μm, and the doping concentration is 3 × 10⁻⁶. 15 cm -3 .

[0086] Optionally, both the N+ substrate layer 1 and the N- epitaxial layer 2 are made of 4H-SiC material.

[0087] Optionally, the thickness of the first P-base region 3 and the second P-base region 4 is 0.5 to 5 μm.

[0088] For example, the thickness of the first P-base region 3 and the second P-base region 4 is 0.8 μm, the width is 4 μm, and the doping concentration is 2 × 10⁻⁶. 17 cm -3 .

[0089] Optionally, the thickness of the first N+ injection region 7 and the second N+ injection region 8 is 0.1 to 2 μm.

[0090] For example, the thickness of the first N+ implantation region 7 and the second N+ implantation region 8 are 0.2 μm, the width is 1 μm, and the doping concentration is 1 × 10⁻⁶. 19 cm -3 .

[0091] For example, the thickness of the first P+ implantation region 5 and the second P+ implantation region 6 are 0.8 μm, the width is 1.5 μm, and the doping concentration is 1 × 10⁻⁶. 19 cm -3 .

[0092] Optionally, the channel length in the first P-base region 3 and the second P-base region 4 is 0.1 to 5 μm.

[0093] For example, the channel length in the first P-base region 3 and the second P-base region 4 is 0.5 μm.

[0094] Optionally, the thickness of the first P+ polysilicon region 13 and the second P+ polysilicon region 14 is 0.1 to 5 μm.

[0095] For example, the width of the first P+ polysilicon region 13 and the height of the second P+ polysilicon region 14 are 1 μm and 0.3 μm, respectively, and the doping concentration is 1 × 10⁻⁶. 20 cm -3 .

[0096] Optionally, the thickness of the N+ polysilicon gate is 0.1–5 μm.

[0097] For example, the N+ polysilicon gate 10 has a width of 2.5 μm, a height of 0.5 μm, and a doping concentration of 1 × 10⁻⁶. 20 cm -3 .

[0098] Optionally, the thickness of the gate dielectric layer 9 surrounding the N+ polysilicon gate 10 is 0.1–2 μm.

[0099] For example, the gate dielectric layer 9 is a SiO2 layer with a thickness of 0.1 μm.

[0100] For example, the thickness of the first N-doped region 11 and the second N-doped region 12 are 0.8 μm, the width is 1 μm, and the doping concentration is 2 × 10⁻⁶. 16 cm -3 .

[0101] The contact between the P+ polysilicon region and the N- epitaxial layer in this invention is a heterojunction contact, that is, an HJD structure is integrated inside the SiC VDMOSFET device, replacing the SBD or JBS structure integrated inside a typical SiC VDMOSFET device. Since the potential barrier height in the valence band between the 4H-SiC and the polysilicon junction is very large and the potential barrier height in the conduction band is very low, in the HJDMOSFET, the electron current can move towards the source, while the hole current cannot move towards the drain. Therefore, it works as a unipolar device and has excellent reverse recovery characteristics. Thus, the HJD structure has a lower turn-on voltage, a smaller reverse recovery charge Qrr, and a smaller switching loss energy.

[0102] The first P+ injection region and the second P+ injection region provided in the P-base region of the present invention have a shielding effect, which can protect the heterojunction interface from the influence of high electric field and improve the withstand voltage capability of the device.

[0103] In this invention, the concentrations of the first N-doped region and the second N-doped region in the P-base region are slightly higher than those in the N-epitaxial layer, which serves to further reduce the turn-on voltage of the heterojunction diode.

[0104] Example 2

[0105] Please see Figures 2a-2f , Figures 2a-2f This is a schematic diagram illustrating the fabrication process of a SiCVD MOSFET device with integrated HJD according to an embodiment of the present invention. The present invention provides a method for fabricating a SiC VD MOSFET device with integrated HJD, which is used to fabricate the SiC VD MOSFET device described in Embodiment 1. The fabrication method includes:

[0106] Step 1: Select N+ substrate layer 1.

[0107] The N+ substrate is made of SiC material.

[0108] Step 2, as follows Figure 2a As shown, an N- epitaxial layer 2 is formed on an N+ substrate layer 1 by epitaxial growth.

[0109] Specifically, first, a thickness of 3 μm and a doping concentration of 5 × 10⁻⁶ were tested. 18 cm -3 The SiC N+ substrate 1 was subjected to RCA standard cleaning, and then a 30 μm thick epitaxial growth with a doping concentration of 3 × 10⁻⁶ was grown on the N+ substrate 1. 15 cm -3 The N-epitaxial layer 2 of SiC material.

[0110] Step 3, as follows Figure 2b As shown, ion implantation is performed on the surface of the N-epipolar layer 2 to form the first P-base region 3 and the second P-base region 4.

[0111] Specifically, a SiO2 layer is deposited on the surface of N-epitaxial layer 2, and photoresist is coated on it. Masks are placed at 4 μm intervals on both sides of N-epitaxial layer 2. After exposure, development, etching and photoresist removal, aluminum ions are implanted into N-epitaxial layer 2 to a depth of 0.8 μm and a doping concentration of 2 × 10⁻⁶. 17 cm -3 After implantation, annealing is performed, followed by removal of the first SiO2 layer, ultimately forming the first P-base region 3 and the second P-base region 4 on both sides of the N-epitaxial layer 2.

[0112] Step 4, as follows Figure 2c As shown, ion implantation is performed on the surfaces of the first P-base region 3 and the second P-base region 4 to form the first P+ implantation region 5 and the second P+ implantation region 6 respectively.

[0113] Specifically, a SiO2 layer is deposited on the surface of the N-epitaxial layer 2, the first P-base region 3, and the second P-base region 4. Photoresist is then applied, and 1.5 μm long masks are placed at four points on the leftmost side of the first P-base region 3 (spaced 1 μm apart), the rightmost side of the first P-base region 3 (spaced 1.5 μm apart), and the leftmost side of the second P-base region 4 (spaced 1.5 μm apart), and the rightmost side of the second P-base region 4 (spaced 1 μm apart). After exposure, development, etching, and photoresist removal, aluminum ion implantation is performed to a depth of 0.8 μm and a doping concentration of 1 × 10⁻⁸. 19 cm -3 After implantation, annealing is performed, and then the second SiO2 layer is removed. Finally, the first P+ implantation region 5 is formed in the middle region of the first P-base region 3, and the second P+ implantation region 6 is formed in the middle region of the second P-base region 4.

[0114] Step 5, as follows Figure 2d As shown, ion implantation is performed on the surfaces of the first P-base region 3 and the second P-base region 4 to form the first N+ implantation region 7, the second N+ implantation region 8, the first N-doped region 11, and the second N-doped region 12.

[0115] Specifically, a SiO2 layer is deposited on the upper surfaces of the N-epitaxial layer 2, the first P-base region 3, the second P-base region 4, the first P+ implantation region 5, and the second P+ implantation region 6. Photoresist is then applied. Masks with a length of 1 μm are placed on the right side of the first P+ implantation region 5 and the left side of the second P+ implantation region 6. After exposure, development, etching, and photoresist removal, phosphorus ion implantation is performed on the first P-base region 3 and the second P-base region 4 to a depth of 0.2 μm and a doping concentration of 1 × 10⁻⁶. 19 cm -3 After implantation, annealing is performed, and then the third SiO2 layer is removed. Finally, the first N+ implantation region 7 is formed on the right side of the first P+ implantation region 5, and the second N+ implantation region 8 is formed on the left side of the second P+ implantation region 6.

[0116] A SiO2 layer was deposited on the upper surfaces of the N-epitaxial layer 2, the first P-base region 3, the second P-base region 4, the first P+ implantation region 5, the second P+ implantation region 6, the first N+ implantation region 7, and the second N+ implantation region 8. Masks with a length of 1 μm were placed on the left side of the first P+ implantation region 5 and the right side of the second P+ implantation region 6. After exposure, development, etching, and resist removal, phosphorus ion implantation was performed on the first P-base region 3 and the second P-base region 4 to a depth of 0.8 μm and a doping concentration of 2 × 10⁻⁶. 16 cm -3 After implantation, annealing is performed, and then the fourth SiO2 layer is removed. Finally, the first N-doped region 11 is formed on the left side of the first P+ implantation region 5, and the second N-doped region 12 is formed on the right side of the second P+ implantation region 6.

[0117] Step 6, as follows Figure 2eAs shown, the first P+ implantation region 5, the second P+ implantation region 6, the first N-doped region 11, and the second N-doped region 12 are first etched. Then, a gate dielectric layer is deposited on the first N+ implantation region 7, the first P-base region 3, the N-epitaxial layer 2, the second P-base region 4, and the second N+ implantation region 8. Finally, polysilicon is deposited on the etched first N-doped region 11, the second N-doped region 12, and the gate dielectric layer to form the first P+ polysilicon region 13, the second P+ polysilicon region 14, and the N+ polysilicon gate 10.

[0118] Specifically, a SiO2 layer is deposited on the upper surface of the N-epitaxial layer 2, the first P-base region 3, the second P-base region 4, the first P+ implantation region 5, the second P+ implantation region 6, the first N+ implantation region 7, the second N+ implantation region 8, the first N-doped region 11, and the second N-doped region 12. Photoresist is then applied, and a 1μm long mask is placed at a 1μm interval to the left of the first N+ implantation region and a 1μm interval to the right of the second N+ implantation region. After exposure, development, etching, and photoresist removal, the fifth SiO2 layer is removed, ultimately forming a groove-shaped structure.

[0119] A SiO2 layer is deposited on the upper surface of the N-epitaxial layer 2, the first P-base region 3, the second P-base region 4, the first P+ implantation region 5, the second P+ implantation region 6, the first N+ implantation region 7, the second N+ implantation region 8, the first N-doped region 11, the second N-doped region 12, the first P+ polysilicon region 13, and the second P+ polysilicon region 14. A photoresist is then coated onto the surface of the device. A mask is placed between the first N+ implantation region 7 and the second N+ implantation region 8. After exposure, development, etching, and photoresist removal, an N+ polysilicon layer is first deposited on the device surface. A SiO2 layer is deposited on the N+ polysilicon, and photoresist is applied. The mask is placed directly above the first N-doped region 11 and the second N-doped region 12. After exposure, development, etching and photoresist removal, a P+ polysilicon layer is deposited on the device surface. The sixth SiO2 layer is removed, and finally, the gate dielectric layer 9, the N+ polysilicon gate 10, the first P+ polysilicon region 13 and the second P+ polysilicon region 14 are formed on the upper surface. The first P+ polysilicon region 13 and the second P+ polysilicon region 14 are heterojunction contacts with the first N-doped region 11 and the second N-doped region 12.

[0120] Step 7, as follows Figure 2f As shown, a gate dielectric layer is deposited to form an annular gate dielectric layer 9, and a metallized drain 15 is formed on the lower surface of the N+ substrate layer 1. A metallized source 16 is formed on the first P+ polysilicon region 13, the first P+ implantation region 5, the first N+ implantation region 7, the gate dielectric layer 9, the second N+ implantation region 8, the second P+ implantation region 6, and the second P+ polysilicon region 14.

[0121] Specifically, a SiO2 layer is first deposited on the upper surface of the device, and photoresist is applied. A mask is used to leave a gap on the upper surface of the N+ polysilicon gate 10. After exposure, development, etching and removal of the photoresist, titanium metal is deposited on the bottom of the device to form a metallized drain 15 and on the upper surface of the device to form a metallized source 16. The metallized drain 15 is in ohmic contact with the N+ substrate layer, and the metallized source 16 is in ohmic contact with the first P+ implantation region 5, the second P+ implantation region 6, the first N+ implantation region 7, the second N+ implantation region 8, the first P+ polysilicon region 13 and the second P+ polysilicon region 14. Finally, surface planarization is performed to complete the process design.

[0122] In the description of this invention, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0123] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0124] Although the invention has been described herein in conjunction with various embodiments, those skilled in the art will understand and implement other variations of the disclosed embodiments by reviewing the accompanying drawings, disclosure, and appended claims in carrying out the claimed invention. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality. A single processor or other unit can implement several functions listed in the claims. While different dependent claims may recite certain measures, this does not mean that these measures cannot be combined to produce good results.

[0125] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, any modifications made without departing from the inventive concept should be considered within the scope of protection of the present invention.

Claims

1. An integrated HJD SiC VDMOSFET device, characterized by, The SiC VDMOSFET device includes a metallized drain (15), an N+ substrate layer (1), and an N- epitaxial layer (2) stacked sequentially from bottom to top. The metallized drain (15) and the N+ substrate layer (1) are in an ohmic contact. The N- epitaxial layer (2) contains a first P-base region (3), a second P-base region (4), a first P+ implantation region (5), a second P+ implantation region (6), a first N+ implantation region (7), a second N+ implantation region (8), a first N-doped region (11), and a second N-doped region (12). The first P-base region (3) and the second P-base region (4) are spaced apart by the N-epipolar layer (2); The first P+ injection region (5) is located on the side of the first P-base region (3) away from the second P-base region (4); the second P+ injection region (6) is located on the side of the second P-base region (4) away from the first P-base region (3); The first N+ injection region (7) is disposed within the first P-base region (3), and the second N+ injection region (8) is disposed within the second P-base region (4); The first N-doped region (11) is disposed on the side of the first P+ implanted region (5) away from the first P-base region (3); the second N-doped region (12) is disposed on the side of the second P+ implanted region (6) away from the second P-base region (4); A first P+ polysilicon region (13) is provided on the first N-doped region (11), and the first N-doped region (11) and the first P+ polysilicon region (13) are in a heterojunction contact. A second P+ polysilicon region (14) is provided on the second N-doped region (12), and the second N-doped region (12) and the second P+ polysilicon region (14) are in a heterojunction contact.

2. The SiC VDMOSFET device with integrated HJD according to claim 1, characterized in that, The first P-base region (3) and the second P-base region (4) are symmetrically arranged, and the first P-base region (3) and the second P-base region (4) have the same width and depth.

3. The SiC VDMOSFET device with integrated HJD according to claim 1, characterized in that, The first P+ injection region (5) and the second P+ injection region (6) are symmetrically arranged, and the first P+ injection region (5) and the second P+ injection region (6) have the same width and depth.

4. The SiC VDMOSFET device with integrated HJD according to claim 1, characterized in that, The first N-doped region (11) and the second N-doped region (12) are symmetrically arranged, and the first N-doped region (11) and the second N-doped region (12) have the same width and depth. The doping concentration of the first N-doped region (11) and the second N-doped region (12) is greater than the doping concentration of the N-epipolar layer (2).

5. The SiC VDMOSFET device with integrated HJD according to claim 1, characterized in that, The first N-doped region (11) and the second N-doped region (12) are symmetrically arranged, and the first N-doped region (11) and the second N-doped region (12) have the same width and depth; The upper surface of the first N+ injection region (7) is flush with the upper surface of the first P-base region (3), and the lower surface of the first N+ injection region (7) is located within the first P-base region (3); the upper surface of the second N+ injection region (8) is flush with the upper surface of the second P-base region (4), and the lower surface of the second N+ injection region (8) is located within the second P-base region (4).

6. The SiC VDMOSFET device with integrated HJD according to claim 1, characterized in that, One side of the first N+ injection region (7) is in contact with the first P+ injection region (5), and the other side of the first N+ injection region (7) is disposed in the first P-base region (3). One side of the second N+ injection region (8) is in contact with the second P+ injection region (6), and the other side of the second N+ injection region (8) is disposed in the second P-base region (4). The first P+ injection region (5) is in contact with the side of the first P- base region (3); the second P+ injection region (6) is in contact with the side of the second P- base region (4); The first N-doped region (11) is in contact with the side of the first P+ implanted region (5), and the second N-doped region (12) is in contact with the side of the second P+ implanted region (6); The first P-base region (3), the second P-base region (4), the first P+ implantation region (5), the second P+ implantation region (6), the first N-doped region (11), and the second N-doped region (12) all have the same depth.

7. The SiC VDMOSFET device with integrated HJD according to claim 1, characterized in that, The first P+ implantation region (5) has a step at one end near the first N-doped region (11), and the second P+ implantation region (6) has a step at one end near the second N-doped region (12); The upper surfaces of the first N-doped region (11) and the second N-doped region (12) are lower than the upper surfaces of the first P+ implanted region (5) and the second P+ implanted region (6). The upper surface of the first N-doped region (11) is flush with the platform of the step of the first P+ implanted region (5), and the upper surface of the second N-doped region (12) is flush with the platform of the step of the second P+ implanted region (6).

8. The SiC VDMOSFET device with integrated HJD according to claim 1, characterized in that, It also includes a ring-shaped gate dielectric layer (9) and an N+ polysilicon gate (10), wherein, The gate dielectric layer (9) is disposed on the first N+ implantation region (7), the first P-base region (3), the N-epitaxy layer (2), the second P-base region (4) and the second N+ implantation region (8); The N+ polysilicon gate (10) is disposed in the annular region of the gate dielectric layer (9), and the width of the N+ polysilicon gate (10) is less than the distance between the side surface outside the first N+ injection region (7) and the side surface outside the second N+ injection region (8).

9. The SiC VDMOSFET device with integrated HJD according to claim 8, characterized in that, It also includes a metallized source (16), which is disposed on the first P+ polysilicon region (13), the first P+ implantation region (5), the first N+ implantation region (7), the gate dielectric layer (9), the second N+ implantation region (8), the second P+ implantation region (6) and the second P+ polysilicon region (14), and forms an ohmic contact.

10. A method for fabricating a SiC VDMOSFET device with integrated HJD, characterized in that, The method for fabricating the SiC VDMOSFET device according to any one of claims 1 to 9 comprises: Step 1: Select an N+ substrate layer (1); Step 2: The N- epitaxial layer (2) is formed on the N+ substrate layer (1) by epitaxial growth; Step 3: Ion implantation is performed on the surface of the N-epilithial layer (2) to form the first P-base region (3) and the second P-base region (4); Step 4: Ion implantation is performed on the surfaces of the first P-base region (3) and the second P-base region (4) to form the first P+ implantation region (5) and the second P+ implantation region (6) respectively; Step 5: Ion implantation is performed on the surfaces of the first P-base region (3) and the second P-base region (4) to form the first N+ implantation region (7), the second N+ implantation region (8), the first N-doped region (11), and the second N-doped region (12); Step 6: First, etch the first P+ implantation region (5), the second P+ implantation region (6), the first N-doped region (11), and the second N-doped region (12). Then, deposit a gate dielectric layer on the first N+ implantation region (7), the first P-base region (3), the N-epilithial layer (2), the second P-base region (4), and the second N+ implantation region (8). Then, deposit polysilicon on the etched first N-doped region (11), the second N-doped region (12), and the gate dielectric layer to form the first P+ polysilicon region (13), the second P+ polysilicon region (14), and the N+ polysilicon gate (10). Step 7: Continue to deposit the gate dielectric layer to form an annular gate dielectric layer (9), and form a metallized drain (15) on the lower surface of the N+ substrate layer (1), and form a metallized source (16) on the first P+ polysilicon region (13), the first P+ implantation region (5), the first N+ implantation region (7), the gate dielectric layer (9), the second N+ implantation region (8), the second P+ implantation region (6) and the second P+ polysilicon region (14).

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