Semiconductor structure and method of manufacturing the same

Abstract

The embodiment of the present disclosure relates to the field of semiconductor, and provides a semiconductor structure and a manufacturing method thereof, the semiconductor structure comprising: a substrate; an oxide semiconductor layer located on a part of the surface of the substrate, the oxide semiconductor layer having doping ions for pinning oxygen vacancies; a doping layer located at least between the oxide semiconductor layer and the substrate, and the doping layer having doping ions; a gate electrode located on a part of the surface of the oxide semiconductor layer away from the substrate; and source-drain doping regions located in the oxide semiconductor layer on both sides of the gate electrode. At least the carrier mobility in the semiconductor structure can be improved.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductors, and in particular to a semiconductor structure and a method for manufacturing the same. Background Technology

[0002] Thin-film transistors (TFTs) are the core components of active-matrix flat panel display technology and are widely used in the display field. Currently, silicon-based TFTs are the most mature industrialized technology in flat panel display technology, mainly including amorphous silicon and polycrystalline silicon TFTs. With the development of flat panel display technology towards larger areas, higher resolutions, and flexible rollable designs, and the emergence of many new flat panel display technologies, higher demands are being placed on the performance of TFTs.

[0003] Oxide semiconductor layers, such as indium gallium zinc oxide (IGZO), indium tin oxide (ITO), indium tungsten oxide (IWO), indium zinc oxide (IZO), and indium aluminum zinc oxide (IAZO), are amorphous oxides with higher electron mobility than amorphous silicon. Applying oxide semiconductor layers to the channel materials of next-generation thin-film transistors (TFTs) can significantly improve the charge-discharge rate of the pixel electrodes, increase pixel response speed, and achieve faster refresh rates. This results in semiconductor structures with higher energy efficiency and overall higher performance. However, some challenges still exist with this semiconductor structure. Summary of the Invention

[0004] This disclosure provides a semiconductor structure and a method for manufacturing the same, which can at least improve the carrier mobility in the semiconductor structure.

[0005] According to some embodiments of this disclosure, one aspect of this disclosure provides a semiconductor structure, including: a substrate; an oxide semiconductor layer located on a portion of the surface of the substrate, the oxide semiconductor layer having dopant ions for pinning oxygen vacancies; a doped layer located at least between the oxide semiconductor layer and the substrate, the doped layer having the dopant ions; a gate located on a portion of the surface of the oxide semiconductor layer away from the substrate; and source / drain doped regions located within the oxide semiconductor layer on both sides of the gate.

[0006] In some embodiments, the doping ion includes one or more of fluorine ions or hydrogen ions.

[0007] In some embodiments, the material of the doped layer includes silicon nitride.

[0008] In some embodiments, the thickness of the doped layer is 10-30 nm.

[0009] In some embodiments, the substrate includes: a substrate and at least one fin located on the substrate, the substrate further having an isolation layer covering a portion of the side surface of the fin, and the top surface of the fin being higher than the top surface of the isolation layer; the oxide semiconductor layer being located at least on the top surface of the fin and on the side surface above the isolation layer, and the doped layer being located on the top and side surface of the fin.

[0010] In some embodiments, the at least one fin includes a plurality of fins spaced apart along a preset direction; the oxide semiconductor layer and the gate both span the plurality of fins along the preset direction.

[0011] According to some embodiments of this disclosure, another aspect of this disclosure provides a method for manufacturing a semiconductor structure, comprising: providing a substrate; forming an oxide semiconductor layer and a doped layer, the oxide semiconductor layer being located on a portion of the surface of the substrate, the doped layer being located at least between the oxide semiconductor layer and the substrate, and the doped layer having doped ions; forming a gate located on a portion of the oxide semiconductor layer away from the substrate; forming source / drain doped regions located within the oxide semiconductor layer on both sides of the gate; and performing an annealing process to diffuse some of the doped ions in the doped layer into the oxide semiconductor layer, the doping being used to pin oxygen vacancies in the oxide semiconductor layer.

[0012] In some embodiments, before forming the gate, the process further includes treating the surface of the oxide semiconductor layer using a plasma processing technique.

[0013] In some embodiments, the substrate forming step includes: providing an initial substrate; patterning a portion of the initial substrate to form at least one fin, with the remaining portion of the initial substrate below the at least one fin serving as a substrate, the substrate and the at least one fin constituting the substrate.

[0014] In some embodiments, the steps of forming the source / drain doped regions and performing the annealing process include: doping the oxide semiconductor layers on opposite sides of the gate; and after performing the doping process, performing the annealing process to activate ions in the doped layers and to allow a portion of the doped ions in the doped layers to diffuse into the oxide semiconductor layers.

[0015] The technical solutions provided in this disclosure have at least the following advantages:

[0016] The semiconductor structure provided in this disclosure includes: a substrate; an oxide semiconductor layer located on a portion of the substrate surface, wherein the oxide semiconductor layer has dopant ions for pinning oxygen vacancies; a doped layer located at least between the oxide semiconductor layer and the substrate, and wherein the doped layer has dopant ions; a gate located on a portion of the oxide semiconductor layer surface away from the substrate; and source / drain doped regions located within the oxide semiconductor layer on both sides of the gate. The semiconductor structure provided in this disclosure includes a doped layer located at least between the oxide semiconductor layer and the substrate, and the oxide semiconductor layer has dopant ions for pinning oxygen vacancies. The dopant ions pinn more oxygen vacancies in the oxide semiconductor layer, increasing the number of oxygen vacancies that serve as carrier migration tracks in the oxide semiconductor layer, thereby improving the carrier mobility in the oxide semiconductor layer. This maintains the carrier concentration and thermal stability in the oxide semiconductor layer during annealing, and improves the carrier mobility in the semiconductor structure. Furthermore, this disclosure also increases the channel area of ​​the oxide semiconductor layer while keeping the channel length constant, thus maintaining device performance. Attached Figure Description

[0017] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or the conventional technology, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of a semiconductor structure;

[0019] Figure 2 This is a schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure;

[0020] Figure 3 This is a cross-sectional view of a semiconductor structure provided in an embodiment of the present disclosure;

[0021] Figure 4 This is a schematic diagram of a semiconductor structure provided in another embodiment of the present disclosure;

[0022] Figure 5 This is a cross-sectional view of a semiconductor structure provided in another embodiment of the present disclosure;

[0023] Figure 6 This is a schematic diagram of a semiconductor structure provided in another embodiment of the present disclosure;

[0024] Figure 7 This is a cross-sectional view of a semiconductor structure provided in another embodiment of the present disclosure;

[0025] Figure 8 This is a schematic diagram of a semiconductor structure provided in another embodiment of the present disclosure;

[0026] Figures 9 to 18 This is a schematic diagram of the structure corresponding to each step in the manufacturing method of the semiconductor structure provided in the embodiments of this disclosure. Detailed Implementation

[0027] As can be seen from the background technology, current semiconductor structures have the problem of needing to improve carrier mobility.

[0028] refer to Figure 1 , Figure 1 This is a schematic diagram of a semiconductor structure. The semiconductor structure includes: a substrate 10; an oxide semiconductor layer 20 located on a portion of the surface of the substrate 10; a gate 30 located on a portion of the surface of the oxide semiconductor layer 20 away from the substrate 10; source / drain doped regions 21 located within the oxide semiconductor layer 20 on both sides of the gate 30; and source / drain electrodes 40 located on both sides of the gate 30 and also on a portion of the surface of the oxide semiconductor layer 20 away from the substrate 10. Furthermore, an insulating layer 50 is provided between the gate 30 and the source / drain electrodes 40, covering the sides of the gate 30 and the source / drain electrodes 40 and electrically isolating the gate 30 and the source / drain electrodes 40. A gate oxide layer 60 is also provided between the gate 30 and the oxide semiconductor layer 20, and an isolation layer 70 is also provided between the substrate 10 and the oxide semiconductor layer 20.

[0029] Analysis revealed that in the aforementioned semiconductor structure, the oxide semiconductor layer 20, such as indium gallium zinc oxide (IGZO), indium tin oxide (ITO), indium tungsten oxide (IWO), indium zinc oxide (IZO), or indium aluminum zinc oxide (IAZO), serves as the channel of the semiconductor structure. During operation, carrier movement generates current within the oxide semiconductor layer 20. Due to the limited number of oxygen vacancies serving as carrier migration orbitals in the oxide semiconductor layer 20, the carrier concentration is low, resulting in low carrier mobility and consequently, low overall carrier mobility within the semiconductor structure. Providing a semiconductor structure that increases the number of oxygen vacancies serving as carrier migration orbitals in the oxide semiconductor layer 20 could mitigate this problem.

[0030] This disclosure provides a semiconductor structure including: a substrate; an oxide semiconductor layer located on a portion of the substrate surface, the oxide semiconductor layer having dopant ions for pinning oxygen vacancies; a doped layer located at least between the oxide semiconductor layer and the substrate, and the doped layer having dopant ions; a gate located on a portion of the oxide semiconductor layer surface away from the substrate; and source / drain doped regions located within the oxide semiconductor layer on both sides of the gate. Thus, the dopant ions in the doped layer can pin more oxygen vacancies in the oxide semiconductor layer. These oxygen vacancies can all serve as migration tracks for charge carriers, maintaining the concentration and thermal stability of charge carriers in the oxide semiconductor layer during annealing, improving the carrier mobility in the oxide semiconductor layer, thereby improving the carrier mobility in the semiconductor structure and optimizing the performance of the semiconductor structure.

[0031] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the various embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been presented in the various embodiments of the present disclosure to enable the reader to better understand the present disclosure. However, the technical solutions claimed in the present disclosure can be implemented even without these technical details and various changes and modifications based on the following embodiments.

[0032] Figures 2 to 8 This is a schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure.

[0033] Figure 2 This is a schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure. Figure 3 for Figure 2 A schematic diagram of the cross-sectional structure viewed along the AA1 direction. (Reference) Figures 2 to 3 The semiconductor structure includes: a substrate 100; an oxide semiconductor layer 110 located on a portion of the surface of the substrate 100, the oxide semiconductor layer 110 having doped ions for pinning oxygen vacancies; a doped layer 120 located at least between the oxide semiconductor layer 110 and the substrate 100, and the doped layer 120 having doped ions; a gate 130 located on a portion of the surface of the oxide semiconductor layer 110 away from the substrate 100; and source / drain doped regions 111 located within the oxide semiconductor layer 110 on both sides of the gate 130.

[0034] In some embodiments, the substrate 100 may be an active region. The material of the substrate 100 may include single-crystal silicon (Si), single-crystal germanium (Ge), or silicon-germanium (GeSi), silicon carbide (SiC); it may also be silicon-on-insulator (SOI), germanium-on-insulator (GOI); or it may be a glass substrate or other materials, such as gallium arsenide or other group III-V compounds. In the embodiments of this disclosure, the material of the substrate 100 may be single-crystal silicon (Si) or a glass substrate.

[0035] The oxide semiconductor layer 110, such as indium gallium zinc oxide (IGZO), indium tin oxide (ITO), indium tungsten oxide (IWO), indium zinc oxide (IZO), and indium aluminum zinc oxide (IAZO), such as IGZO, contains indium, gallium, and zinc. Using oxide semiconductor materials in the oxide semiconductor layer 110 as a channel in a semiconductor structure can improve the performance of the semiconductor structure. Compared to amorphous silicon channel layers, the carrier mobility of a channel layer using oxide semiconductor materials is 20-30 times that of amorphous silicon, and the oxide semiconductor layer can also improve the charge and discharge rate of the semiconductor structure, thereby improving the energy efficiency of the semiconductor structure.

[0036] The source / drain doping region 111 needs to be doped. If N-type doping is required, N-type ions, such as nitrogen ions or phosphorus ions, can be implanted. If P-type doping is required, P-type ions, such as boron ions or aluminum ions, can be implanted.

[0037] refer to Figure 2 The doped layer 120 may be located solely between the oxide semiconductor layer 110 and the substrate 100. Dopant ions in the doped layer 120 can be pinned into the adjacent oxide semiconductor layer 110 through high-temperature annealing. By pinning more oxygen vacancies in the oxide semiconductor layer 110, these vacancies can serve as migration tracks for charge carriers, thus increasing the number of carrier migration tracks and consequently increasing the carrier mobility in the oxide semiconductor layer 110.

[0038] In some embodiments, the dopant ions may include one or more of fluoride ions or hydrogen ions. When the dopant ions are fluoride ions or hydrogen ions, the dopant ions in the doped layer 120 can more easily diffuse into the oxide semiconductor layer 110 to pin oxygen vacancies that can be used as carrier migration orbitals, which can further enhance the effect of the dopant ions on increasing the carrier mobility of the semiconductor structure.

[0039] In some embodiments, the material of the doped layer 120 may include silicon nitride. Silicon nitride has high hardness and density, good process compatibility, and can effectively introduce dopant ions, such as H and F, without damaging device performance. Using silicon nitride as the material of the doped layer 120 allows the doped layer 120 to meet the requirements of carrying dopant ions for pinning oxygen vacancies in the oxide semiconductor layer 110, while improving the mechanical strength and insulation properties of the semiconductor structure and enhancing the stability of the semiconductor structure.

[0040] In some embodiments, the thickness of the doped layer 120 can be 10-30 nm. For example, the thickness of the doped layer 120 can be 10 nm, 12 nm, 16 nm, 18 nm, 24 nm, etc. If the thickness of the doped layer 120 is small, fewer dopant ions can diffuse into the oxide semiconductor layer 110 to pin oxygen vacancies, resulting in fewer oxygen vacancies in the oxide semiconductor layer 110, which is not conducive to improving the carrier mobility of the semiconductor structure. If the thickness of the doped layer 120 is large, it may cause some waste, increase the manufacturing cost of the semiconductor structure, and also increase the size of the semiconductor structure, which is not conducive to the development of semiconductor structures towards miniaturization and micro-miniaturization. Therefore, the thickness of the doped layer 120 can be selected within a suitable range. When the thickness of the doped layer 120 is 10-30 nm, the doped layer 120 can provide enough dopant ions to effectively improve the carrier mobility of the semiconductor structure without causing waste.

[0041] In some embodiments, the material of the gate 130 may include one or more of polycrystalline silicon or tungsten.

[0042] Figure 4 This is a schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure. Figure 5 for Figure 4 A schematic diagram of the cross-sectional structure viewed along the AA1 direction.

[0043] refer to Figures 4 to 5 In some embodiments, the semiconductor structure may further include a gate oxide layer 140, which is located between the gate 130 and the oxide semiconductor layer 110. The material of the gate oxide layer 140 may include silicon oxide or aluminum oxide, etc. The gate oxide layer 140 can improve the electronic conductivity of the semiconductor structure, making electron conduction in the semiconductor structure smoother. Furthermore, the gate oxide layer 140 can control the current, preventing excessive current from causing device overheating or short circuits. It can form a charge channel to control the flow of electrons in the device, thereby improving device stability, increasing device efficiency, and protecting the device from environmental factors to a certain extent. In addition, the gate oxide layer 140 also has a certain degree of surface activity and can serve as a surface-active layer in the semiconductor structure, which can be used to receive or place other substances.

[0044] In some embodiments, the semiconductor structure may have source and drain electrodes 150, which are located on both sides of the gate 130 and on a portion of the oxide semiconductor layer 110 away from the substrate 100. The material of the source and drain electrodes 150 may include one or more of polysilicon or tungsten.

[0045] In some embodiments, the semiconductor structure may further include an insulating layer 160, which is located between the gate 130 and the source / drain 150, covering the sides of the gate 130 and the source / drain 150. The material of the insulating layer 160 may include silicon nitride. The insulating layer 160 serves to isolate the gate 130 and the source / drain 150. The oxide semiconductor layer 110 located directly below the insulating layer 160 along a direction perpendicular to the surface of the substrate 100 may also be a source / drain doped region 111.

[0046] In some embodiments, the semiconductor structure may further include an isolation layer 170, which is located on the surface of the substrate 100, and a doped layer 120 is located at least on the portion of the isolation layer 170 away from the substrate 100. The material of the isolation layer 170 may include one or more of silicon nitride, silicon oxide, and silicon oxynitride. The isolation layer 170 can isolate the substrate 100 from the oxide semiconductor layer 110, reducing leakage current in the semiconductor structure and improving the stability of the semiconductor structure.

[0047] Figure 6 This is a schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure. Figure 7 for Figure 6 A schematic diagram of the cross-sectional structure viewed along the AA1 direction. (Reference) Figures 6 to 7 In some embodiments, the substrate 100 may include a substrate 101 and at least one fin 102 located on the substrate 101. The substrate 101 may also have an isolation layer 170 covering a portion of the side surface of the fin 102, with the top surface of the fin 102 higher than the top surface of the isolation layer 170. An oxide semiconductor layer 110 is located at least on the top surface of the fin 102 and on the side surface above the isolation layer 170, and a doped layer 120 is located on the top and side surfaces of the fin 102. Thus, without increasing the length of the oxide semiconductor layer 110 serving as a channel in the semiconductor structure, the contact area between the oxide semiconductor layer 110 serving as a channel and the gate 130 can be increased, reducing the contact resistance in the semiconductor structure. Furthermore, the control capability of the gate 130 over the oxide semiconductor layer 110 can be improved, effectively suppressing short-channel effects, reducing subthreshold leakage current, reducing gate leakage current, and improving the performance of the semiconductor structure.

[0048] In some embodiments, at least one fin 102 may include a plurality of fins 102 spaced apart along a predetermined direction; the oxide semiconductor layer 110 and the gate 130 may both span the plurality of fins 102 along the predetermined direction. The plurality of fins 102 spaced apart along the predetermined direction can further increase the contact area between the oxide semiconductor layer 110 and the gate 130, further improve the control capability of the gate 130 over the oxide semiconductor layer 110, and further improve the performance of the semiconductor structure.

[0049] refer to Figure 8 In some embodiments, the semiconductor structure may also include a filler layer 180. The filler layer 180 covers the top and side surfaces of structures such as the doped layer 120, gate 130, source / drain 150, and insulating layer 160, with the top surface of the filler layer 180 covering the top surfaces of the gate 130 and the source / drain 150. The filler layer 180 enables the semiconductor structure to have higher mechanical strength, improves the stability of the semiconductor structure, and protects the components in the semiconductor structure from damage by the external environment.

[0050] In some embodiments, the material of the filler layer 180 may include one or more of silicon oxide or silicon nitride.

[0051] The semiconductor structure provided in this disclosure includes a substrate; an oxide semiconductor layer located on a portion of the substrate surface, the oxide semiconductor layer having doped ions for pinning oxygen vacancies; a doped layer located at least between the oxide semiconductor layer and the substrate, and the doped layer having doped ions; a gate located on a portion of the oxide semiconductor layer surface away from the substrate; and source / drain doped regions located within the oxide semiconductor layer on both sides of the gate. This structure can improve carrier mobility in the semiconductor structure and optimize the performance of the semiconductor structure.

[0052] Accordingly, another embodiment of this disclosure also provides a method for manufacturing a semiconductor structure, which can be used to form the above-mentioned semiconductor structure. The semiconductor structure provided by another embodiment of this disclosure will be described in detail below with reference to the accompanying drawings. For parts that are the same as or corresponding to the previous embodiment, please refer to the corresponding descriptions of the foregoing embodiments; detailed descriptions will not be repeated below.

[0053] Figures 9 to 18 This is a schematic diagram of the structure corresponding to each step in the manufacturing method of the semiconductor structure provided in the embodiments of this disclosure, and Figures 9 to 18 These are cross-sectional schematic diagrams of the semiconductor structure corresponding to each step in the manufacturing method of the semiconductor structure provided in the embodiments of this disclosure. It is understood that the cross-sectional schematic diagrams do not show all the structures in the semiconductor structure.

[0054] refer to Figures 9 to 13 Provides a base of 100.

[0055] In some embodiments, the step of forming the substrate 100 may include: providing an initial substrate 200; patterning a portion of the initial substrate 200 to form at least one fin 102, with the remaining initial substrate 200 below the at least one fin 102 serving as a substrate 101, the substrate 101 and the at least one fin 102 constituting the substrate 100.

[0056] Specifically, the process for providing the substrate 100, which includes a substrate 101 and at least one fin 102, can be a self-aligned double patterning (SADP) process.

[0057] refer to Figure 9 An initial substrate 200 is provided, on which a protective layer 191, a hard mask layer 192, a sacrificial layer 193, and a photoresist layer 194 are sequentially stacked. The protective layer 191 may be made of silicon oxide, and the hard mask layer 192 may be made of silicon nitride. The photoresist layer 194 covers a portion of the surface of the sacrificial layer 193 and has a pre-defined pattern.

[0058] refer to Figure 10 The photoresist layer 194 is used as a mask to etch the sacrificial layer 193, so that the preset pattern in the photoresist layer 194 is transferred to the sacrificial layer 193. After etching, the photoresist layer 194 is removed.

[0059] refer to Figure 11 A mask layer 195 is formed covering the sides of the sacrificial layer 193, and then the sacrificial layer 193 is removed. The method for forming the mask layer 195 may include: first forming the mask layer 195 on the surface of the hard mask layer 192 and on the top and side surfaces of the sacrificial layer 193 using atomic layer deposition (ALD), and then removing part of the mask layer 195 by an etch-back process, so that the remaining mask layer 195 only covers the side surfaces of the sacrificial layer 193.

[0060] refer to Figure 12 The hard mask layer 192 is etched using mask layer 195 as a mask, and then mask layer 195 is removed after etching. At this point, the etching pattern in the hard mask layer 192 has a higher density than the preset pattern in the photoresist layer 194, which allows for a higher density of the fins 102 formed in subsequent steps. This further increases the contact area between the oxide semiconductor layer 110 and the gate 130, further enhances the control capability of the gate 130 over the oxide semiconductor layer 110, and further improves the performance of the semiconductor structure. The protective layer 191 located between the initial substrate 200 and the hard mask layer 192 protects the initial substrate 200, preventing over-etching during the etching of the hard mask layer 192 using mask layer 195, thus preventing damage to the initial substrate 200.

[0061] refer to Figure 13The protective layer 191 and the initial substrate 200 are etched using a hard mask layer 192 as a mask, such that the initial substrate 200 includes a substrate 101 and at least one fin 102. Due to the process characteristics of wet etching, the initial substrate 200 closer to the protective layer 191 comes into contact with the etching environment before the initial substrate 200 farther away from the protective layer 191, and the width of the fin 102 gradually decreases in the direction away from the substrate 101.

[0062] refer to Figure 14 An initial isolation layer 270 is formed. The initial isolation layer 270 may cover the top surface of the substrate 101, the side surface of the fin 102, and the side surface of the protective layer 191 and the hard mask layer 192. The material of the initial isolation layer 270 may include one or more of silicon nitride, silicon oxide, or silicon oxynitride.

[0063] refer to Figure 15 The hard mask layer, protective layer, and part of the initial isolation layer are etched away to form an isolation layer 170. The isolation layer 170 can cover the top surface of the substrate and part of the side surface of the fin 102, and the top surface of the fin 102 is higher than the top surface of the isolation layer 170. The isolation layer 170 can isolate the substrate 100 from the oxide semiconductor layer 110, reduce the occurrence of leakage current in the semiconductor structure, and improve the stability of the semiconductor structure.

[0064] In some embodiments, the hard mask layer 192 and the protective layer 191 may be removed before forming the isolation layer 170.

[0065] refer to Figure 16 An oxide semiconductor layer 110 and a doped layer 120 are formed. The oxide semiconductor layer 110 is located on a portion of the surface of the substrate 100, and the doped layer 120 is located at least between the oxide semiconductor layer 110 and the substrate 100, and the doped layer 120 contains doped ions. The steps of forming the oxide semiconductor layer 110 and the doped layer 120 may include: first forming the doped layer 120, which at least covers a portion of the surface of the substrate 100, and the doped layer 120 may cover the entire top and side surfaces of the fins 102; then forming the oxide semiconductor layer 110, which covers a portion of the surface of the doped layer 120 away from the substrate 100, and the oxide semiconductor layer 110 may span multiple fins 102 along a predetermined direction. Since the oxide semiconductor layer 110 does not cover the entire surface of the substrate 100, when forming the oxide semiconductor layer 110, an initial oxide semiconductor layer covering the entire surface of the substrate 100 may be formed first, and then a portion of the initial oxide semiconductor layer may be removed to form the oxide semiconductor layer 110.

[0066] In some embodiments, before forming the gate 130, the process may further include treating the surface of the oxide semiconductor layer 110 using a plasma processing technique. This increases the number of oxygen vacancies in the oxide semiconductor layer 110 that serve as carrier migration orbitals, thereby increasing the carrier concentration and carrier mobility of the oxide semiconductor layer 110, thus increasing the carrier mobility of the semiconductor structure and optimizing its performance.

[0067] refer to Figure 17 A gate 130 is formed on a portion of the oxide semiconductor layer 110 away from the substrate 100.

[0068] In some embodiments, a gate oxide layer 140 may be formed before the gate 130 is formed. The gate oxide layer 140 is located on a portion of the oxide semiconductor layer 110 away from the substrate 100, and the gate 130 is located on a portion of the gate oxide layer 140 away from the substrate 100. The material of the gate oxide layer 140 may include silicon oxide or aluminum oxide, etc., and the gate oxide layer 140 can improve the electronic conductivity of the semiconductor structure.

[0069] Continue to refer to Figure 17 Source / drain doped regions 111 are formed within the oxide semiconductor 110 on both sides of the gate 130. The source / drain doped regions 111 require doping treatment. If N-type doping is required, N-type ions, such as nitrogen ions or phosphorus ions, can be implanted. If P-type doping is required, P-type ions, such as boron ions or aluminum ions, can be implanted.

[0070] Continue to refer to Figure 17 Annealing is performed to allow some of the doped ions in the doped layer 120 to diffuse into the oxide semiconductor layer 110, pinning oxygen vacancies in the oxide semiconductor layer 110. Pinning oxygen vacancies in the oxide semiconductor layer 110 increases the number of oxygen vacancies that can serve as carrier migration tracks, thereby increasing the carrier mobility of the semiconductor structure.

[0071] In some embodiments, the annealing temperature can be between 150°C and 350°C. For example, the annealing temperature can be 350°C, 320°C, 300°C, 290°C, 270°C, 250°C, 210°C, 200°C, 150°C, etc. If the annealing temperature is too high, the carrier concentration in the oxide semiconductor layer 110 may decrease, affecting the performance of the semiconductor structure; if the annealing temperature is too low, the effect of dopant ions pinning oxygen vacancies in the oxide semiconductor layer 110 may be poor, and the carrier mobility in the semiconductor structure will still be low.

[0072] In some embodiments, the steps of forming the source / drain doped regions 111 and performing annealing may include: doping the oxide semiconductor layers 110 on opposite sides of the gate 130; and after doping, performing annealing to activate ions in the doped layer 120 and to allow some of the doped ions in the doped layer 120 to diffuse into the oxide semiconductor layer 110. The diffusion of activated doped ions from the doped layer 120 into the oxide semiconductor layer 110 can pin more oxygen vacancies, preventing a large number of oxygen vacancies from disappearing during annealing, which would affect the channel performance. These doped ions will then remain in the oxide semiconductor layer 110.

[0073] refer to Figure 18 In some embodiments, after annealing, an insulating layer 160 and source / drain electrodes 150 may be formed. The source / drain electrodes 150 are located on both sides of the gate 130 and on a portion of the oxide semiconductor layer 110 away from the substrate 100. The material of the source / drain electrodes 150 may include one or more of polysilicon or tungsten. The insulating layer 160 may be located between the gate 130 and the source / drain electrodes 150, covering the sides of the gate 130 and the source / drain electrodes 150. The insulating layer 160 isolates the gate 130 and the source / drain electrodes 150.

[0074] Continue to refer to Figure 18 A filling layer 180 can also be formed, which covers the top and side surfaces of the doped layer 120, gate 130, source / drain 150, insulating layer 160, etc., and the top surface of the filling layer 180 covers the top surface of the gate 130 and the top surface of the source / drain 150. The material of the filling layer 180 may include one or more of silicon oxide or silicon nitride.

[0075] The method for manufacturing a semiconductor structure provided in this disclosure includes: providing a substrate; forming an oxide semiconductor layer and a doped layer, wherein the oxide semiconductor layer is located on a portion of the surface of the substrate, and the doped layer is located at least between the oxide semiconductor layer and the substrate, and the doped layer contains doped ions; forming a gate located on a portion of the oxide semiconductor layer away from the substrate; forming source / drain doped regions located within the oxide semiconductor layer on both sides of the gate; and performing an annealing process to diffuse some of the doped ions in the doped layer into the oxide semiconductor layer, thereby pinning oxygen vacancies in the oxide semiconductor layer. This method can improve the carrier mobility in the semiconductor structure and optimize the performance of the semiconductor structure.

[0076] Those skilled in the art will understand that the above embodiments are specific examples of implementing this disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of this disclosure. Any person skilled in the art can make their own modifications and alterations without departing from the spirit and scope of this disclosure; therefore, the scope of protection of this disclosure should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: The substrate includes a substrate and at least one fin located on the substrate; A doped layer is located on a portion of the surface of the substrate, and the doped layer contains doped ions; An oxide semiconductor layer is located on the surface of the doped layer on the side away from the substrate and is in direct contact with the doped layer without a barrier layer between them. The oxide semiconductor layer has dopant ions diffused from the doped layer. The dopant ions are used to pin oxygen vacancies in the oxide semiconductor layer to increase the number of oxygen vacancies in the oxide semiconductor layer as carrier migration tracks. The gate is located on the portion of the oxide semiconductor layer away from the substrate; The source and drain doped regions are located within the oxide semiconductor layer on both sides of the gate. The oxide semiconductor layer and the gate both span the at least one fin.

2. The semiconductor structure according to claim 1, characterized in that, The doped ions include one or more of fluorine ions or hydrogen ions.

3. The semiconductor structure according to claim 1, characterized in that, The material of the doped layer includes silicon nitride.

4. The semiconductor structure according to claim 1, characterized in that, The thickness of the doped layer is 10nm-30nm.

5. The semiconductor structure according to any one of claims 1 to 4, characterized in that, The substrate also has an isolation layer that covers a portion of the side surface of the at least one fin, and the top surface of the at least one fin is higher than the top surface of the isolation layer; the oxide semiconductor layer is located at least on the top surface of the at least one fin and on the side surface above the isolation layer; the doped layer is located at least on a portion of the surface of the isolation layer and on the top and side surface of the at least one fin.

6. The semiconductor structure according to claim 5, characterized in that, The at least one fin includes a plurality of fins spaced apart along a preset direction; the oxide semiconductor layer and the gate both span the at least one fin along the preset direction.

7. The semiconductor structure according to claim 5, characterized in that, The material of the isolation layer includes one or more of silicon nitride, silicon oxide, and silicon oxynitride.

8. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure also includes: The source and drain are located on both sides of the gate and on a portion of the surface of the oxide semiconductor layer.

9. The semiconductor structure according to claim 8, characterized in that, The semiconductor structure further includes an insulating layer located between the gate and the source / drain electrodes, the insulating layer covering the sidewalls of the gate and the sidewalls of the source / drain electrodes. The oxide semiconductor layer located directly below the source / drain electrodes and the insulating layer in a direction perpendicular to the substrate surface is the source / drain doped region.

10. A method for manufacturing a semiconductor structure, characterized in that, include: Provide initial substrate; A portion of the initial substrate is patterned to form at least one fin, the remaining portion of the initial substrate below the at least one fin serving as a substrate, the substrate and the at least one fin forming a base; A doped layer is formed on a portion of the surface of the substrate, the doped layer containing doped ions; An oxide semiconductor layer is formed on the surface of the doped layer away from the substrate, and the oxide semiconductor layer is in direct contact with the doped layer without any barrier layer between them; A gate is formed on the surface of the oxide semiconductor layer away from the substrate, wherein both the oxide semiconductor layer and the gate span the at least one fin. Source and drain doped regions are formed in the oxide semiconductor layers on both sides of the gate; Annealing is performed to allow some of the doped ions in the doped layer to diffuse into the oxide semiconductor layer. The doped ions are used to pin oxygen vacancies in the oxide semiconductor layer to increase the number of oxygen vacancies that serve as carrier migration tracks in the oxide semiconductor layer.

11. The manufacturing method according to claim 10, characterized in that, Before forming the gate, the method further includes: The surface of the oxide semiconductor layer is treated using a plasma processing technique.

12. The manufacturing method according to claim 10, characterized in that, The steps of forming the source / drain doped regions and performing the annealing process include: doping the oxide semiconductor layers on opposite sides of the gate; and after performing the doping process, performing the annealing process to activate the ions in the doped layers and to allow some of the doped ions in the doped layers to diffuse into the oxide semiconductor layers.

13. The manufacturing method according to claim 10, characterized in that, After forming the at least one fin and before forming the doped layer, the method further includes: An isolation layer is formed, the isolation layer covering the top surface of the substrate and a portion of the side surface of the at least one fin, wherein the top surface of the at least one fin is higher than the top surface of the isolation layer; The doped layer is formed at least on a portion of the surface of the isolation layer, on the top surface of the at least one fin, and on the side surface above the isolation layer.

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