Interface composite structure, preparation method and application thereof, and tandem solar cell with two ends

Abstract

The application provides a two-end laminated solar cell of an interface composite structure and a preparation method and application thereof, wherein the interface composite structure comprises a boron-rich silicon layer, the boron-rich silicon layer is formed by boron doping on a silicon wafer or a silicon wafer multilayer structure, the boron doping concentration of the boron-rich silicon layer is 1x10 20 -5x10 21 cm ‑3 -3, and the atomic proportion of boron is 0.2-10at.%. The interface composite structure provided in the application replaces the TCO interface composite layer in the prior art with the boron-rich silicon layer, the boron-rich silicon layer has high hydrophilicity, high conductivity and high defect density which are comparable to the TCO layer, and the close combination of the top cell and the bottom cell and the rapid recombination of carriers are ensured.

Description

Technical Field

[0001] This invention relates to the field of tandem solar cell technology, and more specifically, to a two-terminal tandem solar cell with an interface composite structure, its preparation method, and its application. Background Technology

[0002] Currently, common two-terminal tandem solar cells often employ a sandwich-like structure, consisting of a bottom cell, an interface composite layer, and a top cell from bottom to top. The interface composite layer acts as an intermediate layer connecting the top and bottom cells, ensuring electron-hole recombination within the cell. The interface composite layer typically uses transparent conductive oxide (TCO) materials. Due to the excellent hydrophilicity of TCO, the carrier transport layer precursor for the top cell can be uniformly and rapidly coated onto the surface of the interface composite layer via spin coating or spraying, preparing for the coverage of the perovskite precursor. Furthermore, the numerous defects in TCO allow for rapid recombination of carriers from the top and bottom cells.

[0003] However, the TCO interface composite layer exhibits significant optical parasitic absorption and lateral shunting phenomena, leading to a decrease in the short-circuit current density and open-circuit voltage of the tandem solar cell. Furthermore, TCO is typically prepared using physical deposition methods, which suffer from strong ion bombardment effects, easily reducing the passivation of the bottom cell surface and complicating the cell structure, significantly increasing manufacturing costs. Therefore, removing the TCO interface composite layer is beneficial for improving the performance of tandem solar cells, simplifying the cell structure, and reducing manufacturing costs.

[0004] However, removing the TCO interface composite layer presents challenges in achieving a tight connection between the top and bottom cells. This is because common bottom cells are monocrystalline silicon solar cells, whose front surface carrier selection and passivation layers are typically hydrophobic silicon layers. However, the fabrication of the bottom carrier transport layer of the top cell requires a highly hydrophilic surface, which inhibits the uniform spreading and coverage of the precursor for the bottom carrier transport layer. This phenomenon is more pronounced on textured silicon surfaces. This makes it difficult for the bottom carrier transport layer of the top cell to bond tightly with the top carrier transport layer of the bottom cell, leading to a decrease in cell performance. To improve this poor contact, some preliminary attempts have been made. For example, atomic layer deposition (ALD) has been used to directly deposit titanium dioxide (TiO2) or tin oxide (SnO2) as the electron transport layer of the top cell onto a highly doped silicon surface, resulting in tandem cells with relatively high efficiency. However, the complex equipment and low batch yield of the ALD method significantly increase the manufacturing cost of tandem cells, making mass production impossible in the short term. Summary of the Invention

[0005] To address the shortcomings of existing technologies, this invention provides an interface composite structure that uses a boron-rich silicon layer to replace the TCO interface composite layer in existing technologies. The boron-rich silicon layer has high hydrophilicity, high conductivity, and high defect density comparable to the TCO layer, ensuring a tight bond between the top and bottom cells and rapid recombination of charge carriers.

[0006] To address the aforementioned problems, this invention provides an interface composite structure comprising a boron-rich silicon layer, wherein the boron-rich silicon layer is formed by boron doping on a silicon wafer or a multilayer silicon wafer structure, and the boron doping concentration of the boron-rich silicon layer is 1×10⁻⁶. 20 –5×10 21 cm -3 The atomic percentage of boron is 0.2–10 at.%.

[0007] Optionally, the thickness of the boron-rich silicon layer is 1–200 nm.

[0008] Optionally, the thickness of the boron-rich silicon layer is 1–10 nm.

[0009] Optionally, the bulk resistivity of the boron-rich silicon layer is 0.5–10 mΩ·cm.

[0010] A method for preparing an interface composite structure includes the following steps:

[0011] S1. Pre-processing of silicon wafers or multilayer silicon wafer structures;

[0012] S2. The pretreated silicon wafer or silicon wafer multilayer structure is subjected to boron doping treatment, and a moderately boron-doped silicon layer, a boron-rich silicon layer and a boron source residual layer located on the surface of the boron-rich silicon layer are formed in the boron-doped silicon wafer or silicon wafer multilayer structure.

[0013] S3. Remove the residual boron source layer in an aqueous hydrogen fluoride solution to obtain the interface composite structure.

[0014] Optionally, the preparation method further includes the step: S4, immersing the boron-rich silicon layer alternately in a strong oxidizing solution and an aqueous solution of hydrogen fluoride to remove part of the oxidized boron-rich silicon layer, thereby adjusting the thickness of the interface composite structure.

[0015] Optionally, the surface morphology of the silicon wafer or the multilayer silicon wafer structure after the pretreatment in step S1 is planar, pyramidal textured, or inverted pyramidal textured.

[0016] This invention provides a two-terminal tandem solar cell that uses a boron-rich silicon layer as an interface composite structure. By adjusting the thickness of the boron-rich silicon layer, the magnitude of optical parasitic absorption loss and lateral shunt loss of the interface composite structure can be adjusted, thereby controlling the current density and open-circuit voltage of the tandem solar cell.

[0017] A two-terminal stacked solar cell includes a top cell and a bottom cell, and also includes an interface composite structure located between the top cell and the bottom cell.

[0018] Optionally, the bottom cell is a TOPCon crystalline silicon cell, a PERC crystalline silicon cell, or an SHJ crystalline silicon cell.

[0019] Optionally, the internal structure of the top battery, from top to bottom, includes an anti-reflection layer, a current collection layer, a hole transport layer, a perovskite layer, and an electron transport layer.

[0020] A method for manufacturing a two-terminal stacked solar cell involves first preparing an interface composite structure on a silicon wafer or a multilayer silicon wafer structure, then preparing a bottom cell structure on this basis, and finally preparing a top cell on the surface of the interface composite structure.

[0021] Compared with the prior art, the present invention has the following advantages:

[0022] 1. The boron-rich silicon layer exhibits excellent hydrophilicity, high conductivity, and high defect content, comparable to existing TCO interlayers. Furthermore, reducing the thickness of the boron-rich silicon layer can decrease its optical parasitic absorption, thereby reducing lateral shunt losses. Additionally, the simultaneous appearance of the boron-rich silicon layer and moderately boron-doped silicon layers after boron doping significantly reduces additional processing steps and damage to the bottom cell passivation. These latter two points provide a clear competitive advantage over existing TCO interlayers.

[0023] 2. Based on the highly hydrophilic boron-rich silicon layer, the carrier transport layer beneath the top cell can be rapidly and uniformly fabricated on large-area flat or textured surfaces using low-cost methods such as spin coating or spraying, leveraging existing raw materials and manufacturing processes. This significantly reduces the cost of large-area tandem solar cells. Furthermore, the low optical loss of the boron-rich silicon layer allows the bottom cell to absorb more incident light, resulting in higher photoelectric conversion efficiency for the tandem cell. Attached Figure Description

[0024] Figure 1 This is a schematic diagram of the structure of the two-end stacked solar cell in Embodiment 1 of the present invention;

[0025] Figure 2 This is a schematic diagram of the structure of the two-end stacked solar cell in Embodiment 2 of the present invention;

[0026] Figure 3 This is a schematic diagram of the structure of the two-end stacked solar cell in Embodiment 3 of the present invention;

[0027] Figure 4 This is a schematic diagram of the structure of the two-end stacked solar cell in Embodiment 4 of the present invention.

[0028] Explanation of reference numerals in the attached figures:

[0029] 1. Boron-rich silicon layer; 2. Bottom cell; 3. Top cell;

[0030] 21. Moderately boron-doped silicon layer; 22. Monocrystalline silicon layer; 23. Moderately phosphorus-doped silicon layer; 24. Back electrode; 25. Heavily boron-doped polycrystalline silicon layer; 26. Tunneling silicon oxide layer; 27. Heavily phosphorus-doped polycrystalline silicon layer;

[0031] 31. Antireflection layer; 32. Current collection layer; 33. Hole transport layer; 34. Perovskite layer; 35. Electron transport layer. Detailed Implementation

[0032] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0033] In this invention, the silicon wafer includes a monocrystalline silicon wafer. The multilayer silicon wafer structure includes TOPCon multilayer silicon wafer structure, SHJ multilayer silicon wafer structure, and PERC multilayer silicon wafer structure. The TOPCon multilayer silicon wafer structure includes a monocrystalline silicon / tunneling silicon oxide / amorphous silicon stack structure and a monocrystalline silicon / tunneling silicon oxide / polycrystalline silicon stack structure.

[0034] In this invention, the moderately boron-doped silicon layer 21 specifically refers to a boron active doping concentration of 1×10⁻⁶. 17 –5×10 19 cm -3 The silicon layer. The moderately phosphorus-doped silicon layer 23 specifically refers to a phosphorus active doping concentration of 1×10⁻⁶. 17 –5×10 19 cm -3 The silicon layer.

[0035] In this invention, the heavily boron-doped polycrystalline silicon layer 25 specifically refers to a boron active doping concentration of 5 × 10⁻⁶. 19 –1×10 20 cm -3 The polycrystalline silicon layer.

[0036] In this invention, the heavily phosphorus-doped polycrystalline silicon layer 27 specifically refers to a phosphorus active doping concentration of 5 × 10⁻⁶. 19 –5×10 20 cm -3 The polycrystalline silicon layer.

[0037] In this invention, the pretreatment of silicon wafers or multilayer silicon wafer structures includes surface polishing, texturing, cleaning, oxidation, amorphous silicon deposition, and other processing methods, which are used to prepare for the boron doping treatment of silicon wafers or multilayer silicon wafer structures.

[0038] Example 1

[0039] Fabrication of bottom batteries with interfacial composite structures 2

[0040] The starting material is a p-type monocrystalline silicon (pc-Si) wafer or an n-type monocrystalline silicon (nc-Si) wafer substrate with a thickness of 15-500 micrometers and a bulk resistivity of 1-3 Ω·cm. First, one surface of the monocrystalline silicon wafer is mechanically polished or texturized; this surface serves as the front surface. Next, the wafer undergoes conventional cleaning and conventional double-sided boron diffusion treatment, resulting in regions with high boron doping concentrations on both sides of the wafer. Based on the different boron doping concentrations in the monocrystalline silicon, the boron-doped regions are divided from the surface inwards into boron-rich silicon layers 1 (pc-Si, n ... +++ Si) and a moderately boron-doped silicon layer 21 (p + (c-Si). Furthermore, the boron source remaining on the surface of the boron-rich silicon layer 1 will form a boron source residue layer.

[0041] The boron source residue layer was then removed with hydrogen fluoride, followed by oxidation of the silicon wafer surface. The wafer was then immersed in a low-concentration HF aqueous solution at room temperature to remove the oxidized boron-rich silicon layer 1, yielding the boron-rich silicon layer 1 of the desired thickness. Next, a single-sided texturing process was used to remove the moderately boron-doped silicon layer 21 on the back surface of the wafer, exposing the silicon substrate and simultaneously texturing the back surface. Following this, conventional cleaning and single-sided phosphorus diffusion processes were performed to obtain a moderately phosphorus-doped silicon layer 23 (n... + (c-Si). Then, conventional hydrogenation treatment is performed to improve passivation. Finally, the back electrode 24 is fabricated on the single-crystal silicon layer 22.

[0042] Fabrication of top cell 3 (formal nip perovskite solar cell) structure

[0043] First, the bottom cell 2 with the interface composite structure is cleaned. Then, an electron transfer layer (ETL) precursor is spin-coated or spray-coated onto the surface of the boron-rich silicon layer 1 to obtain a uniform precursor film. Next, a complete electron transfer layer 35 is fabricated. Then, a perovskite layer 34, a hole transport layer 33, a current collection layer 32, and a passivation and antireflection layer 31 are sequentially fabricated on top of this layer using conventional processes. Finally, the top cell 3 / interface composite structure / bottom cell 2, a two-terminal stacked solar cell structure, is encapsulated using conventional encapsulation processes to obtain the finished solar cell, as shown in the image. Figure 1 As shown.

[0044] Furthermore, in this embodiment, the monocrystalline silicon wafer between the moderately phosphorus-doped silicon layer 23 and the moderately boron-doped silicon layer 21 is a monocrystalline silicon layer 22.

[0045] Furthermore, in this embodiment, the boron source residue layer is removed by soaking the silicon wafer in a low-concentration hydrogen fluoride aqueous solution of 1–10 vol.% for 10–300 seconds at room temperature.

[0046] Furthermore, in this embodiment, conventional oxidation methods are used to oxidize the silicon wafer surface, such as hot concentrated nitric acid oxidation or hot oxygen oxidation.

[0047] Furthermore, in this embodiment, the silicon wafer is subjected to double-sided boron diffusion treatment, and the thickness of the medium boron-doped silicon layer 21 is 5–10 micrometers.

[0048] Furthermore, in this embodiment, the bottom battery 2 is a bifacial TOPCon crystalline silicon battery.

[0049] Furthermore, in this embodiment, the boron doping concentration of the boron-rich silicon layer 1 is 1×10⁻⁶. 20 –5×10 21 cm -3 The atomic percentage of boron is 0.2–10 at.%, the thickness is 1–10 nm, and the bulk resistivity is 0.5–10 mΩ·cm.

[0050] Example 2

[0051] Fabrication of bottom batteries with interface composite structures 2

[0052] First, prepare a p-type or n-type monocrystalline silicon wafer substrate as the starting material, with a substrate thickness of 15–500 micrometers and a bulk resistivity of 1–3 Ω·cm. First, mechanically polish or texturize one surface, using this treated surface as the front surface. After routine cleaning of the silicon wafer substrate, prepare a tunneling silicon oxide layer 26 (tunneling SiOx) on the front surface. Then, prepare a boron-containing amorphous silicon layer (or intrinsic amorphous silicon layer) on the front surface of the tunneling silicon oxide layer using a CVD process, followed by high-temperature heat treatment in an inert atmosphere (or conventional double-sided boron diffusion treatment) to prepare a heavily boron-doped polycrystalline silicon layer 25 (p... ++ poly-Si), while obtaining a moderately boron-doped silicon layer 21 (p + c-Si), boron-rich silicon layer 1 (p +++ The silicon oxide (Si) layer and the boron source residue layer are arranged as follows: A moderately boron-doped silicon layer 21 is located on the back surface of the tunneling silicon oxide layer 26, and a boron-rich silicon layer 1 is located on the front surface of the heavily boron-doped polycrystalline silicon layer 25. The boron source residue layer on the front surface of the boron-rich silicon layer 1 is then removed using a hydrogen fluoride solution. The boron-rich silicon layer 1 is then oxidized and immersed in a low-concentration HF aqueous solution at room temperature to remove the oxidized portion, thereby adjusting the thickness of the boron-rich silicon layer 1.

[0053] Then, a portion of the moderately boron-doped silicon layer 21 is removed using a single-sided texturing process, with a thickness of 5–10 micrometers, exposing the silicon substrate and simultaneously texturing the back surface of the silicon substrate. Following routine cleaning of the silicon substrate, a routine single-sided phosphorus diffusion process is performed on the back surface of the silicon substrate to obtain a moderately phosphorus-doped silicon layer 23 (n... + (c-Si). It is then subjected to conventional hydrogenation treatment to improve passivation. Finally, a back electrode 24 is fabricated on the single-crystal silicon layer 22.

[0054] Fabrication of top cell 3 (formal nip perovskite solar cell) structure

[0055] After cleaning the bottom cell 2 with the interface composite structure, an electron transfer layer (ETL) precursor is added to the surface of the boron-rich silicon layer 1 by spin coating or spraying to obtain a uniform precursor film. Then, a complete electron transfer layer 35 is prepared. Subsequently, a perovskite layer 34, a hole transport layer 33, a current collection layer 32, and a passivation and antireflection layer 31 are sequentially prepared on top of this layer using conventional processes. Finally, the top cell 3 / interface composite structure / bottom cell 2 are encapsulated using conventional encapsulation processes to obtain the finished solar cell, as shown in the image. Figure 2 As shown.

[0056] In this embodiment, the CVD process details include, but are not limited to: temperature 150°C, pressure 0.5 Torr, silane flow rate 5 sccm, hydrogen flow rate 20 sccm, diborane flow rate 3 sccm, RF power 5W, and duration 160s. The high-temperature heat treatment process details include, but are not limited to: temperature 920°C, atmospheric pressure, nitrogen flow rate 800 sccm, and duration 30min.

[0057] Furthermore, in this embodiment, the bottom battery 2 is a front-surface TOPCon crystalline silicon battery.

[0058] Furthermore, in this embodiment, the boron doping concentration of the boron-rich silicon layer 1 is 1×10⁻⁶. 20 –5×10 21 cm -3 The atomic percentage of boron is 0.2–10 at.%, the thickness is 1–10 nm, and the bulk resistivity is 0.5–10 mΩ·cm.

[0059] Example 3

[0060] Fabrication of bottom batteries with interfacial composite structures 2

[0061] First, prepare p-type monocrystalline silicon (pc-Si) wafers or n-type monocrystalline silicon (nc-Si) wafers as starting materials, with a thickness of 15–500 micrometers and a bulk resistivity of 1–3 Ω·cm. First, polish or texturize one surface of the silicon wafer, treating the front surface of the substrate. Then, perform routine cleaning and routine double-sided boron diffusion treatment to obtain regions with high boron doping concentrations in the monocrystalline silicon on both sides of the wafer. Based on the different boron doping concentrations in the monocrystalline silicon, the boron-doped regions are divided from the surface inwards into boron-rich silicon layers 1 (pc-Si, n ... +++ Si) and a moderately boron-doped silicon layer 21 (p + The substrate is then immersed in a low-concentration hydrogen fluoride (HF) aqueous solution of 1–10 vol.% for 10–300 seconds to remove the residual boron source layer. The silicon wafer substrate is then surface-oxidized and immersed in the HF aqueous solution to remove the partially oxidized boron-rich silicon layer 1, yielding a boron-rich silicon layer 1 of the desired thickness.

[0062] Then, the moderately boron-doped silicon layer 21 on the back surface of the silicon wafer is removed by conventional single-sided texturing, with a thickness of 5–10 micrometers, exposing the substrate and simultaneously texturing the back surface of the substrate. After conventional cleaning, a tunneling silicon oxide layer 26 (tunneling SiOx) is prepared using an oxidation method. Subsequently, a phosphorus-containing amorphous silicon layer is prepared on one side of the back surface silicon oxide layer by chemical vapor deposition (CVD), followed by high-temperature heat treatment in an inert atmosphere to prepare a heavily phosphorus-doped polycrystalline silicon layer 27 (n++ poly-Si), while a moderately phosphorus-doped silicon layer 23 (n+c-Si) is obtained above the tunneling silicon oxide layer 26. Then, conventional hydrogenation treatment is performed to improve passivation. Finally, the back electrode 24 is prepared on the heavily phosphorus-doped polycrystalline silicon layer 27.

[0063] Fabrication of top cell 3 (formal nip perovskite solar cell) structure

[0064] First, the bottom cell 2 with the interface composite structure is cleaned. Then, an electron transfer layer (ETL) precursor is spin-coated or spray-coated onto the surface of the boron-rich silicon layer 1 to obtain a uniform precursor film. Next, a complete electron transfer layer 35 is fabricated. Then, a perovskite layer 34, a hole transport layer 33, a current collection layer 32, and a passivation and antireflection layer 31 are sequentially fabricated on top of this layer using conventional processes. Finally, the top cell 3 / interface composite structure / bottom cell 2 are encapsulated using conventional encapsulation processes to obtain the finished solar cell, as shown in the image. Figure 3 As shown.

[0065] Furthermore, in this embodiment, the CVD process details include, but are not limited to: temperature 150°C, pressure 0.5 Torr, silane flow rate 10 sccm, hydrogen flow rate 20 sccm, phosphine flow rate 6 sccm, RF power 5W, and duration 150s. The high-temperature heat treatment process details include, but are not limited to: temperature 920°C, atmospheric pressure, nitrogen flow rate 800 sccm, and duration 30min.

[0066] Furthermore, in this embodiment, the bottom battery 2 is a back-surface TOPCon crystalline silicon battery.

[0067] Furthermore, in this embodiment, the boron doping concentration of the boron-rich silicon layer 1 is 1×10⁻⁶. 20 –5×10 21 cm -3 The atomic percentage of boron is 0.2–10 at.%, the thickness is 1–10 nm, and the bulk resistivity is 0.5–10 mΩ·cm.

[0068] Example 4

[0069] Fabrication of bottom batteries with interfacial composite structures 2

[0070] The starting material is a p-type or n-type monocrystalline silicon substrate with a thickness of 15–500 micrometers and a bulk resistivity of 1–3 Ω·cm. First, one surface is polished or texturized, and this treated surface becomes the front surface of the silicon substrate. Then, a single-sided texturing process is used to texturize the back surface of the substrate. After conventional cleaning, tunneling silicon oxide (SiOx) layers 26 are simultaneously prepared on both the front and back surfaces of the silicon substrate using an oxidation method. Next, a boron-containing amorphous silicon layer is prepared on one side of the tunneling SiOx layer 26 on the front surface of the substrate using chemical vapor deposition (CVD), and a phosphorus-containing amorphous silicon layer is prepared on one side of the tunneling SiOx layer 26 on the back surface. This is followed by high-temperature heat treatment in an inert atmosphere to form heavily boron-doped polycrystalline silicon layers 25 (p... ++ poly-Si) and heavily phosphorus-doped polycrystalline silicon layer 27 (n ++ poly-Si), while simultaneously obtaining moderately boron-doped or phosphorus-doped silicon layers (p + c-Si,n + c-Si), boron-rich silicon layer 1 (p +++The silicon layer consists of a moderately boron-doped silicon layer 21 beneath the tunneling silicon oxide layer 26 on the front surface, a heavily boron-doped polycrystalline silicon layer 25 above the tunneling silicon oxide layer 26, and a boron-rich silicon layer 1 above the heavily boron-doped polycrystalline silicon layer 25. The boron source residue layer on the front surface is then removed by immersion in a low-concentration (1–10 vol.%) aqueous solution of hydrogen fluoride (HF) at room temperature for 10–300 seconds. Surface oxidation is then performed using a suitable conventional oxidation method, followed by immersion in the hydrogen fluoride aqueous solution to remove the partially oxidized boron-rich silicon layer 1, resulting in a boron-rich silicon layer 1 of the desired thickness. Conventional hydrogenation is then performed to improve passivation. Finally, a back electrode 24 is fabricated on the heavily phosphorus-doped polycrystalline silicon layer 27.

[0071] Fabrication of top cell 3 (formal nip perovskite solar cell) structure

[0072] First, the bottom cell 2 with the interface composite structure is cleaned. Then, an electron transfer layer (ETL) precursor is spin-coated or spray-coated onto the surface of the boron-rich silicon layer 1 to obtain a uniform precursor film. Next, a complete electron transfer layer 35 is fabricated. Then, a perovskite layer 34, a hole transport layer 33, a current collection layer 32, and a passivation and antireflection layer 31 are sequentially fabricated on top of this layer using conventional processes. Finally, the top cell 3 / interface composite structure / bottom cell 2 are encapsulated using conventional encapsulation processes to obtain the finished solar cell, as shown in the image. Figure 4 As shown.

[0073] Furthermore, in this embodiment, the CVD process details include, but are not limited to: temperature 150℃, pressure 0.5 Torr; boron-containing amorphous silicon: silane flow rate 5 sccm, hydrogen flow rate 20 sccm, diborane flow rate 3 sccm, RF power 5W, duration 160s; phosphorus-containing amorphous silicon: silane flow rate 10 sccm, hydrogen flow rate 20 sccm, phosphine flow rate 6 sccm, RF power 5W, duration 150s. The high-temperature heat treatment process details include, but are not limited to: temperature 920℃, atmospheric pressure, nitrogen flow rate 800 sccm, duration 30min.

[0074] Furthermore, in this embodiment, the bottom battery 2 is a bifacial TOPCon crystalline silicon battery.

[0075] Furthermore, in this embodiment, the boron doping concentration of the boron-rich silicon layer 1 is 1×10⁻⁶. 20 –5×10 21 cm -3 The atomic percentage of boron is 0.2–10 at.%, the thickness is 1–10 nm, and the bulk resistivity is 0.5–10 mΩ·cm.

[0076] While the disclosure is as stated above, its scope of protection is not limited thereto. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of this disclosure, and all such changes and modifications will fall within the protection scope of this invention.

Claims

1. A two-terminal stacked solar cell, comprising a top cell (3) and a bottom cell (2), characterized in that: It also includes an interface composite structure located between the top cell (3) and the bottom cell (2), wherein the top cell (3) is a perovskite cell, and the interface composite structure includes a boron-rich silicon layer (1), which is formed by boron doping on a silicon wafer or a multilayer silicon wafer structure, and the boron doping concentration of the boron-rich silicon layer (1) is 1×10⁻⁶. 20 –5×10 21 cm -3 The boron atomic ratio is 0.2–10 at%, the bulk resistivity of the boron-rich silicon layer (1) is 0.5–10 mΩ·cm, the thickness of the boron-rich silicon layer (1) is 1–10 nm, and the preparation method of the interface composite structure includes the following steps: S1. Pre-processing of silicon wafers or multilayer silicon wafer structures; S2. The pretreated silicon wafer or silicon wafer multilayer structure is subjected to boron doping treatment, and a moderately boron-doped silicon layer (21), a boron-rich silicon layer (1) and a boron source residual layer located on the surface of the boron-rich silicon layer (1) are formed in the boron-doped silicon wafer or silicon wafer multilayer structure. S3. Remove the residual boron source layer in an aqueous hydrogen fluoride solution to obtain the interface composite structure; The method for preparing the top battery includes at least: preparing an electron transport layer (35) on the surface of the boron-rich silicon layer (1).

2. The two-terminal stacked solar cell according to claim 1, characterized in that, The preparation method of the interface composite structure further includes the following steps: S4, immersing the boron-rich silicon layer (1) alternately in a strong oxidizing solution and an aqueous solution of hydrogen fluoride to remove part of the oxidized boron-rich silicon layer (1) in order to adjust the thickness of the interface composite structure.

3. The two-terminal stacked solar cell according to claim 1, characterized in that: After the pretreatment in step S1, the surface morphology of the silicon wafer or multilayer silicon wafer structure of the bottom cell is planar, pyramidal textured, or inverted pyramidal textured.

4. The two-terminal stacked solar cell according to claim 1, characterized in that, The bottom cell (2) is a TOPCon crystalline silicon cell, a PERC crystalline silicon cell, or a SHJ crystalline silicon cell.

5. A method for manufacturing a two-terminal stacked solar cell as described in any one of claims 1-4, characterized in that, Includes the following steps: First, an interface composite structure is prepared on a silicon wafer or a silicon wafer multilayer structure. Then, a bottom cell (2) structure is prepared on this basis. Finally, a top cell (3) is prepared on the surface of the interface composite structure.

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