Batteries, battery manufacturing methods, and photovoltaic modules

Abstract

This invention discloses a battery, a method for fabricating the battery, and a photovoltaic module. The battery includes: a silicon substrate with a textured surface on its front side and a textured area and a smooth area on its back side, the textured area being recessed relative to the smooth area; a first amorphous silicon layer and a second amorphous silicon layer; a first transparent conductive film layer and a second transparent conductive film layer, the first transparent conductive film layer being disposed on the front side of the first amorphous silicon layer and the second transparent conductive film layer being disposed on the back side of the second amorphous silicon layer; and a second metal electrode disposed on the back side of the second transparent conductive film layer, the second metal electrode including: a main grid line disposed in the textured area. The textured area can enhance the adhesion of the silicon substrate, improve the connection strength between the main grid line and the silicon substrate, and prevent the solder ribbon from pulling off the second metal electrode after applying tension, thereby improving the overall reliability of the battery.

Description

Technical Field

[0001] This invention relates to the field of battery technology, and in particular to a battery, a method for preparing the battery, and a photovoltaic module. Background Technology

[0002] Currently, traditional heterojunction solar cells have a double-textured structure. Their fabrication process includes five steps: texturing, PECVD (plasma-enhanced chemical vapor deposition) deposition of an amorphous silicon layer, PVD (physical vapor deposition) deposition of a transparent conductive film, screen printing, and testing and sorting. This process is simple, yields high results, and is gradually becoming the mainstay of future commercial battery development. Benefiting from excellent surface passivation and a highly conductive transparent film, heterojunction solar cells exhibit high on-state voltage and high fill power. However, limited by the high absorption of the transparent conductive film and amorphous silicon layer, and the low reflection within the textured back surface, low current is increasingly impacting the efficiency of heterojunction solar cells.

[0003] In related technologies, the back of a heterojunction solar cell is made into a smooth surface to increase the internal reflectivity of light and enhance the absorption of long wavelengths by the silicon substrate, thereby increasing the battery current. However, the polished silicon substrate surface is too flat, resulting in a small contact area and weak adhesion between the screen-printed metal electrode and the silicon substrate surface. This leads to a high contact resistivity between the metal electrode and the transparent conductive film layer. Furthermore, the adhesion between the metal electrode and the transparent conductive film layer weakens due to the reduced surface roughness. When tension is applied to the solder ribbon, the ribbon will pull the metal electrode off the battery surface, resulting in low ribbon tension and affecting battery performance and the reliability of the packaged battery. Summary of the Invention

[0004] This invention aims to at least solve one of the technical problems existing in the prior art. To this end, this invention proposes a battery that can improve the connection strength between the main grid line and the silicon substrate, making it less likely for the solder ribbon to pull the second metal electrode off the silicon substrate, thereby improving the overall reliability of the battery.

[0005] The present invention further proposes a method for preparing a battery.

[0006] The present invention further proposes a photovoltaic module.

[0007] The battery according to the present invention includes: a silicon substrate having a front side and a back side, the front side having a textured surface, and the back side having a textured region and a smooth region, the textured region being recessed relative to the smooth region; a first amorphous silicon layer and a second amorphous silicon layer, the first amorphous silicon layer including: a first intrinsic amorphous silicon layer and a first doped amorphous silicon layer, the first intrinsic amorphous silicon layer being disposed on the front side of the silicon substrate, the first doped amorphous silicon layer being disposed on the front side of the first intrinsic amorphous silicon layer, and the second amorphous silicon layer including: a second intrinsic amorphous silicon layer and a second doped amorphous silicon layer, the second intrinsic amorphous silicon layer being... The second doped amorphous silicon layer is disposed on the back side of the silicon substrate, and the second transparent conductive film layer is disposed on the back side of the second intrinsic amorphous silicon layer; a first transparent conductive film layer and a second transparent conductive film layer are disposed on the front side of the first amorphous silicon layer and the second transparent conductive film layer are disposed on the back side of the second amorphous silicon layer; and a first metal electrode and a second metal electrode are disposed on the front side of the first transparent conductive film layer and the second metal electrode is disposed on the back side of the second transparent conductive film layer, the second metal electrode including: a main gate line disposed on the textured region.

[0008] According to the battery of the present invention, the main grid line is disposed in the textured area, which can enhance the adhesion of the silicon substrate, thereby improving the connection strength between the main grid line and the silicon substrate. Furthermore, there is a connection between the main grid line and the solder ribbon. When a pulling force is applied to the solder ribbon, the solder ribbon is less likely to pull the second metal electrode off the silicon substrate, thereby improving the overall reliability of the battery.

[0009] In some examples of the present invention, the first transparent conductive film layer is an ITO layer, and the second transparent conductive film layer is an ITO layer.

[0010] In some examples of the present invention, the width of the textured area corresponding to the main grid line is d1, and the width of the main grid line is d2. d1 and d2 satisfy the following relationship: 100um≤d1≤2000um, 50um≤d2≤1000um.

[0011] In some examples of this invention, d2 satisfies the relationship: 50um≤d2≤300um.

[0012] In some examples of the present invention, the difference between the width of the textured area corresponding to the main grid line and the width of the main grid line is △d1, and △d1 satisfies the relationship: △d1>40um.

[0013] In some examples of the present invention, the second metal electrode further includes a sub-gate line connected to the main gate line, the sub-gate line being disposed in the textured area.

[0014] In some examples of the present invention, the velvet area includes: a plurality of first sub-velvet areas and a plurality of second sub-velvet areas, the plurality of first sub-velvet areas being spaced apart in a first direction and the plurality of second sub-velvet areas being spaced apart in a second direction perpendicular to the first direction, a smooth area being disposed between adjacent first sub-velvet areas and second sub-velvet areas, and a plurality of main grid lines and a plurality of sub-grid lines being disposed in the first sub-velvet areas and the plurality of sub-grid lines being disposed in the second sub-velvet areas.

[0015] In some examples of the present invention, the width of the second sub-textured area is greater than the width of the sub-gate line.

[0016] In some examples of the present invention, the width of the second sub-textured area is d3, and the width of the sub-gate line is d4. d3 and d4 satisfy the following relationship: 80um≤d3≤300um, 20um≤d4≤60um.

[0017] In some examples of the present invention, the width difference between the second sub-textured area and the sub-gate line is △d2, and △d2 satisfies the relationship: △d2>40um.

[0018] In some examples of the present invention, the difference between the height of the plane where the smooth area is located and the top of the velvety area is h1, and h1 satisfies the relationship: 1um≤h1≤5um.

[0019] The method for fabricating a battery according to the present invention includes the following steps: selecting a silicon substrate and polishing the front and back sides of the silicon substrate to form a smooth surface; oxidizing the front and back sides of the silicon substrate to form an oxide layer; removing the oxide layer on the front side of the silicon substrate; performing laser windowing on the back side of the silicon substrate; texturing the areas of the laser-windowed areas on the front and back sides of the silicon substrate to form a textured area; removing the remaining oxide layer on the front and back sides of the silicon substrate, forming the textured area and the smooth area on the back side of the silicon substrate; depositing an amorphous silicon layer and a transparent conductive film layer on the front and back sides of the silicon substrate, respectively; printing metal electrodes on the transparent conductive film layers on the front and back sides of the silicon substrate, and printing the main grid lines corresponding to the metal electrodes on the back side of the silicon substrate on the textured area.

[0020] In some examples of the present invention, the step of oxidizing the front and back sides of the silicon substrate to form an oxide layer includes: placing the silicon substrate in a container and introducing O2 or O2+H2O, while maintaining the temperature at 750°C-900°C.

[0021] In some examples of the present invention, the step of printing the metal electrode further includes: printing the sub-gate lines of the metal electrode corresponding to the back side of the silicon substrate on the textured area.

[0022] In some examples of the present invention, in the step of laser windowing on the back side of the silicon substrate, the wavelength of the laser is between 500nm and 550nm, and the power is between 10W and 30W.

[0023] In some examples of the present invention, the step of removing the oxide layer on the front side of the silicon substrate includes: placing the silicon substrate on an HF acid aqueous solution, etching to remove the oxide layer on the front side of the silicon substrate, wherein the HF acid aqueous solution has a mass concentration of 1%-5%, a temperature of 20-25°C, and a time of 120-240s.

[0024] In some examples of the present invention, the step of forming the textured area is to place the silicon substrate in an alkaline solution to form a texture, wherein the mass concentration of the alkaline solution is 1%-5%, the temperature is 60℃-85℃, and the time is 30s-100s.

[0025] The photovoltaic module according to the present invention includes: the battery described above.

[0026] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0027] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which:

[0028] Figure 1 This is a schematic diagram of a battery according to an embodiment of the present invention;

[0029] Figure 2 This is a schematic diagram of the back of a battery according to an embodiment of the present invention;

[0030] Figure 3 This is a flowchart of a battery preparation method according to an embodiment of the present invention.

[0031] Figure label:

[0032] 1. Battery;

[0033] 10. Silicon substrate; 11. Front side; 12. Back side; 13. Textured area; 14. Smooth area; 15. First sub-textured area; 16. Second sub-textured area; 20. First amorphous silicon layer; 30. Second amorphous silicon layer; 40. First transparent conductive film layer; 50. Second transparent conductive film layer; 60. First metal electrode; 70. Second metal electrode; 71. Main gate line; 72. Sub-gate line. Detailed Implementation

[0034] The embodiments of the present invention are described in detail below. The embodiments described with reference to the accompanying drawings are exemplary. The embodiments of the present invention are described in detail below.

[0035] The following is for reference. Figures 1-3 A battery 1 and a method for preparing the battery 1 are described according to an embodiment of the present invention.

[0036] like Figure 1 As shown, the battery 1 according to an embodiment of the present invention includes: a silicon substrate 10, a first amorphous silicon layer 20, a second amorphous silicon layer 30, a first transparent conductive film layer 40, a second transparent conductive film layer 50, a first metal electrode 60, and a second metal electrode 70. The silicon substrate 10 is the material used to manufacture the battery 1 and can be P-type or N-type amorphous silicon. The silicon substrate 10 has a front side 11 and a back side 12. Understandably, the silicon substrate 10 or the solar cell 1 has two surfaces. The surface that mainly receives sunlight is the front side 11, which is the main light-receiving surface. The other surface opposite to the front side 11 is the non-main sunlight-receiving surface of the solar cell 1 or the silicon substrate 10, which is the back side 12.

[0037] like Figure 2 As shown, the front side 11 of the silicon substrate 10 is textured, and the texture can be formed into a pyramid texture, which can play a good role in light trapping and can replace the texturing and related cleaning processes in traditional processes. The back side 12 is provided with a textured area 13 and a smooth area 14. The textured area 13 can enhance the adhesion of the silicon substrate 10, while the smooth area 14 can improve the internal reflectivity of light and enhance the absorption of long wavelengths by the silicon substrate 10, thereby increasing the current of the cell 1.

[0038] Furthermore, the textured area 13 is recessed relative to the smooth area 14, which allows for better differentiation between the two areas, facilitating subsequent fabrication of the battery 1. Since the textured area 13 is lower than the smooth area 14, during the PVD deposition of the ITO (indium tin oxide) thin film, the film deposited on the recessed portion, i.e., the textured area 13, will be relatively thick. Since metal electrodes will be printed on the textured area 13, the thick transparent conductive film layer can more effectively prevent corrosion of the metal electrodes, resulting in better under-metal passivation. Conversely, in an implementation where the textured area 13 is higher than the smooth area 14, the transparent conductive film layer deposited on the raised surface of the textured area 13 will be thinner, making it less resistant to metal corrosion and less abrasion-resistant.

[0039] like Figure 1As shown, the first amorphous silicon layer 20 includes a first intrinsic amorphous silicon layer and a first doped amorphous silicon layer. The first intrinsic amorphous silicon layer is disposed on the front side 11 of the silicon substrate 10, and the first doped amorphous silicon layer is disposed on the front side 11 of the first intrinsic amorphous silicon layer. The second amorphous silicon layer 30 includes a second intrinsic amorphous silicon layer and a second doped amorphous silicon layer. The second intrinsic amorphous silicon layer is disposed on the back side 12 of the silicon substrate 10, and the second doped amorphous silicon layer is disposed on the back side 12 of the second intrinsic amorphous silicon layer. In this design, both the first doped amorphous silicon layer and the second doped amorphous silicon layer can be n-type or p-type. It is important to note that when the first doped amorphous silicon layer is n-type, the second doped amorphous silicon layer is p-type, and vice versa. In the first amorphous silicon layer 20, there is at least one layer of both the first intrinsic amorphous silicon layer and the first doped amorphous silicon layer. Similarly, in the second amorphous silicon layer 30, there is also at least one layer of both the second intrinsic amorphous silicon layer and the second doped amorphous silicon layer. This arrangement is reasonable, allowing both the front side 11 and the back side 12 of the silicon substrate 10 to form crystalline silicon substrates 10.

[0040] like Figure 1 As shown, a first transparent conductive film layer 40 is disposed on the front side 11 of the first amorphous silicon layer 20, and a second transparent conductive film layer 50 is disposed on the back side 12 of the second amorphous silicon layer 30. The first transparent conductive film layer 40 is an ITO layer, and the second transparent conductive film layer 50 is also an ITO layer. A first metal electrode 60 is disposed on the front side 11 of the first transparent conductive film layer 40, and a second metal electrode 70 is disposed on the back side 12 of the second transparent conductive film layer 50. The first transparent conductive film layer 40 can cooperate with the first metal electrode 60 to conduct electricity on the front side 11 of the battery 1, while the second transparent conductive film layer 50 can cooperate with the second metal electrode 70 to conduct electricity on the back side 12 of the battery 1.

[0041] like Figure 2 As shown, the second metal electrode 70 includes a main grid line 71 disposed in the textured region 13. The main grid line 71 mainly serves to collect current and conducts current after being soldered to the solder ribbon. The textured region 13 enhances the adhesion of the main grid line 71 to the silicon substrate 10, thereby improving the connection strength between the main grid line 71 and the silicon substrate 10. Furthermore, since there is a connection between the main grid line 71 and the solder ribbon, the solder ribbon is less likely to pull the second metal electrode 70 off the silicon substrate 10 after a pulling force is applied, thus improving the overall reliability of the battery 1.

[0042] The width of the textured region 13 corresponding to the main gate line 71 is d1, and the width of the main gate line is d2. d1 and d2 satisfy the following relationship: 100um≤d1≤2000um, 50um≤d2≤1000um. Setting the width of the main gate line 71 within a certain range ensures that the main gate line 71 meets the requirements of the battery 1 and satisfies the conductivity function. The width of the textured region 13 corresponding to the main gate line 71 is also set within a certain range, and the width of the textured region 13 corresponding to the main gate line 71 is generally wider than the width of the main gate line 71. This ensures the stability and reliability of the connection between the main gate line 71 and the silicon substrate 10.

[0043] Furthermore, d2 satisfies the relationship: 50um ≤ d2 ≤ 300um. Since batteries 1 with a main grid line width of 1000um are rare or have been phased out of the market, it is preferable to set the maximum width of the main grid line 71 to 300um, which is more reasonable and better meets market demand.

[0044] Furthermore, the difference between the width of the textured region 13 corresponding to the main gate line 71 and the width of the main gate line 71 is Δd1, and Δd1 satisfies the relationship: Δd1 > 40µm. That is, when the textured region 13 corresponding to the main gate line 71 is disposed on the silicon substrate 10, the width of the textured region 13 corresponding to the main gate line 71 needs to exceed the width of the main gate line 71 by 40µm. This better ensures the alignment accuracy between the textured region 13 corresponding to the main gate line 71 and the metal electrode gate line during printing, allowing the main gate line 71 to be disposed within the width range of the textured region 13 corresponding to the main gate line 71, thus ensuring the reliability of the main gate line 71's placement.

[0045] In addition, such as Figure 2 As shown, the second metal electrode 70 further includes a sub-gate line 72, which is connected to the main gate line 71 and is disposed in the textured region 13. The sub-gate line 72 is connected to the main gate line 71, and the main gate line 71 can collect the current from the sub-gate line 72. The sub-gate line 72 is mainly responsible for collecting the current generated by the battery 1. By disposing of the sub-gate line 72 in the textured region 13, the contact surface between the sub-gate line 72 and the silicon substrate 10 is textured, resulting in a large specific surface area and low contact resistance. If the sub-gate line 72 is disposed outside the second sub-textured region 16 and printed into the smooth region 14, the smooth region has a small specific surface area and high contact resistance. This ensures that the contact between the sub-gate line 72 and the silicon substrate 10 does not increase, thereby improving the efficiency of the battery 1.

[0046] Specifically, such as Figure 2As shown, the velvet area 13 includes: a plurality of first sub-velvet areas 15 and a plurality of second sub-velvet areas 16. The plurality of first sub-velvet areas 15 are spaced apart in a first direction, and the plurality of second sub-velvet areas 16 are spaced apart in a second direction perpendicular to the first direction. A smooth area 14 is provided between adjacent first sub-velvet areas 15 and second sub-velvet areas 16. There are a plurality of main grid lines 71 and sub-grid lines 72. The plurality of main grid lines 71 are provided in the first sub-velvet areas 15, and the plurality of sub-grid lines 72 are provided in the second sub-velvet areas 16.

[0047] This arrangement better suits the distribution of the main grid lines 71 and sub-grid lines 72 on the back side 12 of the battery 1, and is easier to arrange. The multiple main grid lines 71 are arranged in the first sub-textured area 15, and the multiple sub-grid lines 72 are arranged in the second sub-textured area 16. This makes it less likely for the solder ribbon to pull the second metal electrode 70 off the silicon substrate 10, improving the overall reliability of the battery 1. The sub-grid lines 72 are printed within the second sub-textured area 16, which ensures that the contact between the sub-grid lines 72 and the silicon substrate 10 does not increase, thus improving the efficiency of the battery 1. In addition, a smooth area 14 is provided between the adjacent first sub-textured area 15 and second sub-textured area 16. This allows the smooth area 14 to be as large as possible, thereby improving the internal reflectivity of light, enhancing the absorption of long wavelengths by the silicon substrate 10, and increasing the current of the battery 1.

[0048] Furthermore, the width of the second sub-textured region 16 is greater than the width of the sub-gate line 72. This arrangement allows the sub-gate line 72 to be completely disposed within the second sub-textured region 16. In this case, the contact surface between the sub-gate line 72 and the silicon substrate 10 is textured, with a large specific surface area and low contact resistance. If the sub-gate line 72 extends beyond the range of the second sub-textured region 16 and is printed into the smooth region 14, the smooth surface has a small specific surface area and high contact resistance. Thus, by ensuring that the sub-gate line 72 is printed within the range of the second sub-textured region 16, the contact between the sub-gate line 72 and the silicon substrate 10 is not increased.

[0049] The width of the second sub-textured region 16 is d3, and the width of the sub-gate line 72 is d4. d3 and d4 satisfy the following relationship: 80um ≤ d3 ≤ 300um, 20um ≤ d4 ≤ 60um. Setting the width of the sub-gate line 72 within a certain range allows it to meet the requirements of the battery 1 and fulfill its conductivity function. The width of the second sub-textured region 16 is also set within a certain range, and it is generally wider than the width of the sub-gate line 72. This allows the sub-gate line 72 to be printed within the second sub-textured region 16, ensuring that the contact between the sub-gate line 72 and the silicon substrate 10 does not increase.

[0050] Furthermore, the width difference between the second sub-textured region 15 and the sub-gate line 72 is Δd2, which satisfies the relationship: Δd2 > 40µm. That is, when the second sub-textured region 16 is disposed on the silicon substrate 10, the width of the second sub-textured region 16 needs to be 40µm, the width of the sub-gate line 72. This better ensures the alignment accuracy of the second sub-textured region 16 and the metal electrode gate line during printing, allowing the sub-gate line 72 to be disposed within the width range of the second sub-textured region 16, ensuring the reliability of the main gate line 71 and the sub-gate line 72. Moreover, the sub-gate line 72 can be printed within the range of the second sub-textured region 16, ensuring that the contact between the sub-gate line 72 and the silicon substrate 10 does not increase.

[0051] It should be noted that the difference between the height of the smooth area 14 and the top of the velvet area 13 is h1, and h1 satisfies the relationship: 1um ≤ h1 ≤ 5um. Setting the difference between the height of the smooth area 14 and the top of the velvet area 13 within this range can better distinguish between the velvet area 13 and the smooth area 14.

[0052] Of course, the thickness of the silicon substrate 10 is h2, the thickness of the first amorphous silicon layer 20 and the second amorphous silicon layer 30 is h3, and the thickness of the first transparent conductive film layer 40 and the second transparent conductive film layer 50 is h4. h2, h3, and h4 satisfy the following relationships: 90um ≤ h2 ≤ 200um, 5nm ≤ h3 ≤ 15nm, 50nm ≤ h4 ≤ 120nm. The thickness of the silicon substrate 10 needs to be kept within a certain range to ensure the overall structure of the battery 1 is relatively stable. Similarly, the thickness of the first amorphous silicon layer 20 and the second amorphous silicon layer 30 also needs to be kept within a certain range for ease of installation and to better position the first amorphous silicon layer 20 and the second amorphous silicon layer 30 on the silicon substrate 10. Likewise, the thickness of the first transparent conductive film layer 40 and the second transparent conductive film layer 50 needs to be kept within a certain range for ease of installation and to better position the first transparent conductive film layer 40 and the second transparent conductive film layer 50 on the first amorphous silicon layer 20 and the second amorphous silicon layer 30, respectively.

[0053] In addition, a laser-grooved area 12 is provided on the back side 12 of the silicon substrate 10, and a textured area 13 is disposed within the laser-grooved area. The laser-grooved area is recessed relative to other areas of the back side 12 of the silicon substrate 10. The textured area 13 is disposed within the laser-grooved area, thus the area of ​​the laser-grooved area is the textured area 13, while the other areas of the back side 12 of the silicon substrate 10 are the smooth area 14. This recessed arrangement of the textured area 13 relative to the smooth area 14 allows for better differentiation between the textured area 13 and the smooth area 14, facilitating subsequent fabrication of the battery 1. The textured area 13 is lower than the smooth area 14. During the manufacturing process, the oxide mask is opened using a laser, resulting in a simple process with high control precision, fewer steps, low cost, and no chemical pollution, making it more feasible for mass production. Conversely, if the textured area 13 is higher than the smooth area 14, the subsequent process will introduce a post-etching cleaning solution, which will require additional chemicals. This not only increases the cost of chemicals and pollution emissions, but also makes it difficult to control the wet process, which can easily introduce contamination and reduce yield. As a result, the possibility of large-scale mass production is relatively low.

[0054] like Figure 3 As shown, according to an embodiment of the present invention, the battery 1 is the battery 1 described in the above embodiments, and the method for preparing the battery 1 includes the following steps:

[0055] S1. Select a silicon substrate 10 and polish the front side 11 and back side 12 of the silicon substrate 10 to form a smooth surface. That is, first select the silicon substrate 10, then remove dirt and traces on the silicon substrate 10, and form an initial smooth surface on the front side 11 and back side 12 of the silicon substrate 10. The solution selected for polishing is an alkaline solution with a mass concentration of 5%-15%, the temperature is controlled at 75-85℃, and the time is controlled at 30s-600s. The alkaline solution includes, but is limited to, one or more of NaOH, KOH, and TMAH (tetramethylammonium hydroxide).

[0056] S2. Oxidize the front side 11 and back side 12 of the silicon substrate 10 to form an oxide layer. That is, an oxide layer is formed on both the front side 11 and back side 12 of the silicon substrate 10. The oxide layer can be a SiO2 oxide layer, which can mainly be used as a mask. The thickness of the SiO2 layer ranges from 2nm to 50nm.

[0057] S3. Remove the oxide layer on the front side 11 of the silicon substrate 10. Removing the oxide layer on the front side 11 of the silicon substrate 10 first facilitates subsequent texturing on the front side 11 of the silicon substrate 10. This also allows for a more reasonable process setup and makes the operation simpler and more convenient.

[0058] S4. Perform laser windowing on the back side 12 of the silicon substrate 10. Windowing means creating a groove on the back side 12 of the silicon substrate 10 to expose the area that needs to be welded or cooled. Using laser windowing is simple to operate and has high precision. During laser windowing, the laser melts away the oxide layer of the windowed area.

[0059] S5. Texturing is performed on the laser-windowed areas of the silicon substrate 10 front side 11 and back side 12 to form a textured area 13. Since the oxide layer on the silicon substrate 10 front side 11 has been removed in the previous operation, textured area 13 can be formed on the silicon substrate 10 front side 11. The oxide layer in the laser-windowed area of ​​the silicon substrate 10 back side 12 has also been melted away by the laser, so textured area 13 can also be formed in the laser-windowed area of ​​the silicon substrate 10 back side 12.

[0060] S6. Remove the remaining oxide layer on the front side 11 and back side 12 of the silicon substrate 10, and form a textured area 13 and a smooth area 14 on the back side 12 of the silicon substrate 10. The remaining oxide layer on the front side 11 and back side 12 of the silicon substrate 10 can be removed using an HF acid solution. In this way, the area on the back side 12 of the silicon substrate 10 with laser windowing can be formed as textured area 13, while the other areas on the back side 12 of the silicon substrate 10 will be formed as smooth area 14. Since the height of textured area 13 is lower than that of unwindowed area, the height of textured area 13 can be lower than that of smooth area 14, making it easier to distinguish between textured area 13 and smooth area 14.

[0061] S7. An amorphous silicon layer and a transparent conductive film layer are deposited on the front side 11 and back side 12 of the silicon substrate 10, respectively. The amorphous silicon layer is deposited first, followed by the transparent conductive film layer, so that the battery 1 is formed.

[0062] S8. Metal electrodes are printed on the transparent conductive film layers on the front side 11 and back side 12 of the silicon substrate 10. The main grid line 71 corresponding to the metal electrode on the back side 12 of the silicon substrate 10 is printed on the textured area 13. The transparent conductive film layer can cooperate with the metal electrodes to achieve conductivity on both the front side 11 and back side 12 of the battery 1. The main grid line 71 corresponding to the metal electrode on the back side 12 of the silicon substrate 10 is printed on the textured area 13. The textured area 13 can enhance the adhesion of the silicon substrate 10, thereby improving the connection strength between the main grid line 71 and the silicon substrate 10. Since there is a connection between the main grid line 71 and the solder ribbon, the solder ribbon is less likely to pull the second metal electrode 70 off the silicon substrate 10 after a pulling force is applied, thus improving the overall reliability of the battery 1.

[0063] It should be noted that throughout the entire manufacturing process of battery 1, the process equipment is based on conventional battery 1 mass production line equipment, which can avoid increasing costs. In addition, after step S8, battery 1 needs to be tested and sorted as a whole to separate qualified and unqualified products, thereby improving the product yield.

[0064] Step S2 includes placing the silicon substrate 10 in a container, typically introducing O2 or O2+H2O into an oxidation furnace, and maintaining the temperature at 750℃-900℃. Placing the silicon substrate 10 in an oxidation furnace and introducing O2 or O2+H2O can form oxide layers on both the front side 11 and back side 12 of the silicon substrate 10. Maintaining the temperature at 750℃-900℃ improves the effectiveness and stability of the formed oxide layer. Alternatively, an oxide layer can be formed by introducing ozone. However, if the oxide layer is to be used as a mask, ozone cannot be used because the oxide film formed by ozone is very thin, approximately 1nm-2nm, and cannot serve as a mask to block etching by strong alkalis.

[0065] Of course, step S8 also includes: printing the sub-gate line 72 corresponding to the metal electrode on the back side 12 of the silicon substrate 10 on the textured area 13. By printing the sub-gate line 72 corresponding to the metal electrode on the back side 12 of the silicon substrate 10 on the textured area 13, it is ensured that the sub-gate line 72 is printed within the textured area 13, thus ensuring that the contact between the sub-gate line 72 and the silicon substrate 10 does not increase, thereby improving the efficiency of the cell 1.

[0066] According to an optional embodiment of the present invention, in step S4, the wavelength of the laser is between 500nm and 550nm, and the power is between 10W and 30W. Controlling the laser wavelength between 500nm and 550nm and the power between 10W and 30W can improve the effect and accuracy of laser windowing.

[0067] Optionally, step S3 includes: placing the silicon substrate 10 on an HF acid aqueous solution, etching away the oxide layer on the front side 11 of the silicon substrate 10, wherein the mass concentration of the HF acid aqueous solution is 1%-5%, the temperature is 20-25°C, and the time is 120-240s. Placing the silicon substrate 10 on the acid aqueous solution, while using a protective water film to cover the back side 12, and using a chain etching machine to etch away the oxide layer on the front side 11 of the silicon substrate 10, allows for better and more precise removal of the oxide layer on the front side 11 of the silicon substrate 10 without affecting the back side 12. The HF acid aqueous solution, with a mass concentration of 1%-5%, a temperature of 20-25°C, and a time of 120-240s, allows for better and more comprehensive etching away of the oxide layer in the non-ink areas of the back side 12 of the silicon substrate 10.

[0068] In addition, step S5 involves texturing the silicon substrate 10 in an alkaline solution with a mass concentration of 1%-5%, a temperature of 60℃-85℃, and a time of 30s-100s. In the alkaline solution, texturing can be more conveniently performed on the laser-windowed areas of the front side 11 and back side 12 of the silicon substrate 10, forming a textured area 13. Controlling the mass concentration of the alkaline solution between 1%-5%, the temperature between 60℃-85℃, and the time between 30s-100s improves the texturing effect and allows for differentiation between the textured area 13 and the smooth area 14. Furthermore, the alkaline solution includes, but is not limited to, one or more of NaOH, KOH, and TMAH.

[0069] A photovoltaic module according to an embodiment of the present invention includes: the battery 1 described in the above embodiments.

[0070] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0071] In the description of this invention, "first feature" and "second feature" may include one or more of the features. In the description of this invention, "a plurality of" means two or more. In the description of this invention, "above" or "below" the second feature may include direct contact between the first and second features, or it may include contact between the first and second features not being in direct contact but through another feature between them. In the description of this invention, "above," "over," and "on top" of the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicating that the first feature is at a higher horizontal level than the second feature.

[0072] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example.

[0073] Although embodiments of the invention have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the claims and their equivalents.

Claims

1. A battery, characterized in that, include: A silicon substrate having a front side and a back side, the front side having a textured surface, and the back side having a textured area and a smooth area, the textured area being recessed relative to the smooth area; A first amorphous silicon layer and a second amorphous silicon layer, wherein the first amorphous silicon layer includes: a first intrinsic amorphous silicon layer and a first doped amorphous silicon layer, the first intrinsic amorphous silicon layer is disposed on the front side of the silicon substrate, the first doped amorphous silicon layer is disposed on the front side of the first intrinsic amorphous silicon layer, and the second amorphous silicon layer includes: a second intrinsic amorphous silicon layer and a second doped amorphous silicon layer, the second intrinsic amorphous silicon layer is disposed on the back side of the silicon substrate, and the second doped amorphous silicon layer is disposed on the back side of the second intrinsic amorphous silicon layer; A first transparent conductive film layer and a second transparent conductive film layer, wherein the first transparent conductive film layer is disposed on the front side of the first amorphous silicon layer, and the second transparent conductive film layer is disposed on the back side of the second amorphous silicon layer, and the thickness of the second transparent conductive film layer located in the textured area is greater than the thickness of the second transparent conductive film layer located in the smooth area; and A first metal electrode and a second metal electrode, wherein the first metal electrode is disposed on the front side of the first transparent conductive film layer, and the second metal electrode is disposed on the back side of the second transparent conductive film layer, the second metal electrode comprising: a main grid line disposed on the textured area.

2. The battery according to claim 1, characterized in that, The first transparent conductive film layer is an ITO layer, and the second transparent conductive film layer is an ITO layer.

3. The battery according to claim 1, characterized in that, The width of the velvet area corresponding to the main grid line is d1, and the width of the main grid line is d2. d1 and d2 satisfy the following relationship: 100um≤d1≤2000um, 50um≤d2≤1000um.

4. The battery according to claim 3, characterized in that, d2 satisfies the relation: 50um≤d2≤300um.

5. The battery according to claim 1, characterized in that, The difference between the width of the textured area corresponding to the main grid line and the width of the main grid line is △d1, and △d1 satisfies the relationship: △d1>40um.

6. The battery according to claim 1, characterized in that, The second metal electrode further includes a sub-gate line, which is connected to the main gate line and is disposed in the textured area.

7. The battery according to claim 6, characterized in that, The velvet area includes: a plurality of first sub-velvet areas and a plurality of second sub-velvet areas. The plurality of first sub-velvet areas are spaced apart in a first direction and the plurality of second sub-velvet areas are spaced apart in a second direction perpendicular to the first direction. A smooth area is provided between adjacent first sub-velvet areas and second sub-velvet areas. There are a plurality of main grid lines and a plurality of sub-grid lines. The plurality of main grid lines are provided in the first sub-velvet areas and the plurality of sub-grid lines are provided in the second sub-velvet areas.

8. The battery according to claim 7, characterized in that, The width of the second sub-textured area is greater than the width of the sub-gate line.

9. The battery according to claim 8, characterized in that, The width of the second sub-textured area is d3, and the width of the sub-grid line is d4. d3 and d4 satisfy the following relationship: 80um≤d3≤300um, 20um≤d4≤60um.

10. The battery according to claim 7, characterized in that, The width difference between the second sub-textured area and the sub-gate line is Δd2, and Δd2 satisfies the relationship: Δd2>40um.

11. The battery according to claim 1, characterized in that, The height difference between the plane containing the smooth area and the top of the velvety area is h1, and h1 satisfies the relationship: 1um≤h1≤5um.

12. A method for preparing a battery according to any one of claims 1-11, characterized in that, Includes the following steps: A silicon substrate is selected, and the front and back sides of the silicon substrate are polished to form a smooth surface; The front and back sides of the silicon substrate are oxidized to form an oxide layer; Remove the oxide layer on the front side of the silicon substrate; Laser windowing is performed on the back side of the silicon substrate; Texturing is performed in the laser-windowed areas on the front and back sides of the silicon substrate to form a textured area. The remaining oxide layer on the front and back sides of the silicon substrate is removed, and a textured area and a smooth area are formed on the back side of the silicon substrate; An amorphous silicon layer and a transparent conductive film layer are deposited on the front and back sides of the silicon substrate, respectively; Metal electrodes are printed on the transparent conductive film layers on the front and back sides of the silicon substrate, and the main gate lines of the metal electrodes corresponding to the back side of the silicon substrate are printed on the textured area.

13. The method for preparing a battery according to claim 12, characterized in that, The step of oxidizing the front and back sides of the silicon substrate to form an oxide layer includes: The silicon substrate is placed in a container and O2 or O2+H2O is introduced, while the temperature is maintained at 750℃-900℃.

14. The method for preparing a battery according to claim 12, characterized in that, The step of printing the metal electrode further includes: The sub-gate lines corresponding to the metal electrodes on the back side of the silicon substrate are printed in the textured area.

15. The method for preparing a battery according to claim 12, characterized in that, In the step of performing laser windowing on the back side of the silicon substrate, The wavelength of the laser is between 500nm and 550nm, and the power is between 10W and 30W.

16. The method for preparing a battery according to claim 12, characterized in that, The step of removing the oxide layer on the front side of the silicon substrate includes: The silicon substrate is placed on an HF acid aqueous solution, and the oxide layer on the front side of the silicon substrate is etched away. The HF acid aqueous solution has a mass concentration of 1%-5%, a temperature of 20-25°C, and a time of 120-240s.

17. The method for preparing a battery according to claim 12, characterized in that, The step of forming the velvety area is as follows: The silicon substrate is texturized by placing it in an alkaline solution with a mass concentration of 1%-5%, a temperature of 60℃-85℃, and a time of 30s-100s.

18. A photovoltaic module, characterized in that, include: The battery according to any one of claims 1-11.

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