A power fail safe reset circuit, method and fault arc circuit breaker

Abstract

The present application relates to the technical field of electrical equipment safety, in particular to a power-off misreset prevention circuit, method and fault arc circuit breaker. The circuit comprises a resistor R1, a delay module, a resistor R2, a reset switch K1, a reset terminal and a detection terminal. The circuit uses the charging delay of a capacitor, adds a detection function for the reset switch, so that the microprocessor can distinguish whether the reset of the fault arc circuit breaker is caused by the reset button being pressed or by the power-off reset caused by the tripping of the front-end protection device to cut off the power supply of the fault arc circuit breaker, thereby judging whether the operating mechanism of the fault arc circuit breaker should be reset and closed, and avoiding the occurrence of mis-closing. The method adds a judgment of the high and low levels of the I / O port connected to the detection terminal in the startup item of the microprocessor, thereby avoiding the occurrence of mis-closing.

Description

Technical Field

[0001] This invention relates to the field of electrical equipment safety technology, specifically to a circuit, method, and fault arc circuit breaker for preventing accidental reset during power outages. Background Technology

[0002] Residential wiring is prone to aging and damage due to prolonged use or external forces and environmental influences. This leads to a decrease in the insulation strength between the live and neutral wires and between them, resulting in series and parallel arcing faults. These arcing paths can take months or even years to develop, making them difficult to detect. When an arcing fault occurs, the temperature can reach thousands of degrees Celsius, generating a large amount of heat that further burns the insulation layer, creating carbonization paths. Over time, this can damage the circuit and cause poor contact. In severe cases, it can lead to breakdown damage in electronic products containing integrated circuits. Furthermore, arcing faults can easily ignite surrounding flammable materials. In areas where open flames are strictly prohibited, such as gas plants, an arcing fault can easily cause an explosion. In residential buildings, if flammable materials are near the arcing point, it can cause a residential fire, resulting in property damage and personal injury.

[0003] Arc fault protection technology is a relatively new circuit protection technology, primarily designed to prevent and avoid electrical safety accidents caused by arc faults, minimizing personal injury and property damage. Arc fault circuit breakers (AFCs) can detect the occurrence of arc faults in real time and automatically interrupt them. They mainly employ circuits with embedded chips as microprocessors, capable of real-time detection of circuit current and arc fault judgment based on sudden changes in current. However, as a protection device that samples and calculates the main line current waveform in real time, an AFC inevitably faces a problem: the microprocessor may crash due to current surges in the main line. Therefore, a reset button is designed in the AFC to reset and restart the microprocessor. But this introduces a practical application problem: if a fault occurs in the downstream line protected by the AFC, not only will the AFC trip, but the upstream protection devices will also trip. In this case, the AFC loses power due to the upstream protection activation, forcing the microprocessor to reset. If the staff resets the front-end protection device of the faulty arc circuit breaker at this time, the faulty arc circuit breaker will be powered, the microprocessor will start working again, and the program will run again, which will drive the action mechanism to reset and close. If the fault has not been eliminated at this time, the reset and closing of the action mechanism of the faulty arc circuit breaker will be a mistaken closing, which may lead to the burning of the load or even a fire in severe cases. Summary of the Invention

[0004] To address the aforementioned problems, this invention provides a circuit, method, and fault arc circuit breaker to prevent accidental reset during power outages. The specific technical solution is as follows:

[0005] A circuit for preventing accidental reset due to power failure includes a resistor R1, a delay module, a resistor R2, a reset switch K1, a reset terminal, and a detection terminal;

[0006] One end of the delay module is connected to one end of resistor R1 and the reset end, respectively;

[0007] The other end of the delay module is connected to one end of resistor R2, the detection end, and one end of reset switch K1, respectively.

[0008] The other end of resistor R1 and the other end of resistor R2 are respectively connected to a high level.

[0009] The reset terminal is connected to the reset pin of the microprocessor; the detection terminal is connected to the I / O port of the microprocessor.

[0010] The other end of the reset switch K1 is grounded.

[0011] Preferably, the delay module includes a capacitor C.

[0012] Preferably, the resistance value of resistor R1 is equal to the resistance value of resistor R2.

[0013] A method for preventing accidental reset due to power failure, applied to the aforementioned circuit, includes the following steps:

[0014] Step S1: Connect the reset terminal to the reset pin of the microprocessor;

[0015] Step S2: Connect the detection terminal to the microprocessor's I / O port;

[0016] Step S3: The microprocessor determines the voltage level of the I / O port connected to the detection terminal;

[0017] Step S4: If the I / O port connected to the detection terminal is at a low level, the judgment result is that the reset switch K1 is closed, and then the operating mechanism of the fault arc circuit breaker is driven to reset and close.

[0018] In step S5, if the I / O port connected to the detection terminal is at a high level, the judgment result is that the microprocessor has been powered off and reset. In this case, the operating mechanism of the fault arc circuit breaker will not be driven to reset and close, and the original state will be maintained.

[0019] A fault arc circuit breaker includes a microprocessor and a power-off false reset circuit. The reset terminal of the power-off false reset circuit is connected to the reset pin of the microprocessor, and the detection terminal of the power-off false reset circuit is connected to the I / O port of the microprocessor. The microprocessor is used to determine whether to drive the operating mechanism of the fault arc circuit breaker to reset and close based on the voltage level at the I / O port connected to the detection terminal.

[0020] Preferably, when the I / O port connected to the detection terminal is at a low level and the microprocessor determines that the reset switch K1 is closed, the operating mechanism of the fault arc circuit breaker is driven to reset and close; when the I / O port connected to the detection terminal is at a high level and the microprocessor determines that the power-off reset is achieved, the operating mechanism of the fault arc circuit breaker is not driven to reset and close, and the original state is maintained.

[0021] The beneficial effects of this invention are as follows: This invention provides a circuit and method for preventing accidental reset of a fault arc circuit breaker due to power failure. This circuit utilizes the charging delay of a capacitor and adds a detection function to check whether the reset switch has been pressed. This allows the microprocessor to distinguish, after a reset, whether the fault arc circuit breaker was reset due to the reset button being pressed or due to a power failure reset caused by the tripping of a front-end protection device cutting off the power supply to the fault arc circuit breaker. This allows the microprocessor to determine whether the operating mechanism of the fault arc circuit breaker should be reset and closed, thus preventing accidental closing. The circuit design is simple and easy to implement, and its function is stable and reliable. While ensuring the normal function of the reset button, it avoids the possibility of accidental closing due to power failure reset, greatly improving the reliability of the fault arc circuit breaker.

[0022] The method of the present invention adds the judgment of the high and low level of the I / O port of the connection detection terminal to the startup item of the microprocessor, which avoids the occurrence of accidental closing and improves the reliability and safety of the fault arc circuit breaker.

[0023] The fault arc circuit breaker of the present invention adds the judgment of the high and low level of the I / O port of the connection detection terminal to the startup item of the microprocessor, thereby improving reliability and safety. Attached Figure Description

[0024] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the accompanying drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. In all the drawings, similar elements or parts are generally identified by similar reference numerals. In the drawings, the elements or parts are not necessarily drawn to scale.

[0025] Figure 1 This is the circuit schematic diagram of the present invention. Detailed Implementation

[0026] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0027] It should be understood that, when used in this specification and the appended claims, the terms "comprising" and "including" indicate the presence of the described features, integrals, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or collections thereof.

[0028] It should also be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise.

[0029] It should also be further understood that the term "and / or" as used in this specification and the appended claims refers to any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0030] Example 1:

[0031] like Figure 1 As shown, a specific embodiment of the present invention provides a circuit to prevent accidental reset due to power failure, including resistor R1, a delay module, resistor R2, reset switch K1, a reset terminal, and a detection terminal;

[0032] One end of the delay module is connected to one end of resistor R1 and the reset end, respectively;

[0033] The other end of the delay module is connected to one end of resistor R2, the detection end, and one end of reset switch K1, respectively.

[0034] The other end of resistor R1 and the other end of resistor R2 are respectively connected to a high level.

[0035] The reset pin is connected to the microprocessor's reset pin and is high by default. If this pin is set to low, the microprocessor is reset. When it returns to high, the microprocessor starts up. The detection pin is connected to the microprocessor's I / O port.

[0036] The other end of the reset switch K1 is grounded. Specifically, the delay module includes a capacitor C, which has good charging delay characteristics. The resistance of resistor R1 is equal to that of resistor R2. The high level of the microprocessor is 3.3V, the low level is 0V (ground), and GND is the ground terminal of the circuit board.

[0037] To ensure that the reset switch K1 can properly reset the faulty arc circuit breaker, one end of it is connected to the ground terminal GND of the circuit board, and the other end is connected to the reset pin REST line of the microprocessor through capacitor C. In this way, as long as the reset button K1 is pressed, since the voltage across capacitor C cannot change abruptly, capacitor C will couple a low level to the REST line, which will set the microprocessor reset pin to a low level, reset the program, and allow it to run again. This can solve the problem of the microprocessor program running away.

[0038] To prevent false resets, a circuit to prevent power failure resets was added to the fault arc circuit breaker. The R_KEY line was connected to the microprocessor's I / O port. At the same time, a judgment on the high or low level of this I / O port was added to the microprocessor's startup program. If the level is low, it is determined that the reset switch K1 has been pressed, and the operating mechanism is driven to reset and close. If the level is high, it is determined that the power failure reset has occurred, and the operating mechanism is not reset and remains in its original state.

[0039] In this way, when reset switch K1 is pressed, it conducts. Since the voltage across capacitor C cannot change abruptly, when the right end of capacitor C is pulled low by reset switch K1, the left end also becomes low, causing REST to go low. The microprocessor is reset. Then, the left end of capacitor C is charged to a high level by the +3.3V power supply through resistor R, and the microprocessor's reset pin REST goes high, starting the microprocessor. The microprocessor then immediately checks the level of the I / O port connected to the detection terminal. If reset switch K1 is still pressed, the detection terminal line is low. If reset switch K1 is released, because the voltage across capacitor C cannot change abruptly and has a charging delay function, the right end of capacitor C is still being charged by the +3.3V power supply through resistor R2, remaining low for a period of time. Therefore, regardless of whether reset switch K1 is still pressed, the I / O port connected to the detection terminal line is low, and the microprocessor determines that reset switch K1 is pressed, thus initiating the reset mechanism.

[0040] In the case of a power-off reset, after the front-end protection of the fault arc breaker trips, the entire circuit of the fault arc breaker is de-energized and at a low level, and the microprocessor shuts down. When the front-end protection of the fault arc breaker is reset and closed, the fault arc breaker receives power. At this time, both ends of capacitor C are charged with a 3.3V high level. Due to the symmetry of the circuit, the voltage levels of the reset and detection terminals will remain consistent. That is, when the reset terminal returns to a high level and the microprocessor is started, the voltage level of the detection terminal is also high when the microprocessor program restarts. Therefore, the microprocessor will determine that it is a power-off reset and will not perform a reset operation on the actuating mechanism. In summary, the fault arc breaker's anti-power-off false reset circuit cleverly distinguishes between button reset and power-off reset through the charging delay of capacitor C, thus avoiding the situation of false reset due to power failure.

[0041] Example 2:

[0042] This embodiment provides a method for preventing accidental reset during power failure, applied to the aforementioned circuit, including the following steps:

[0043] Step S1: Connect the reset terminal to the reset pin of the microprocessor;

[0044] Step S2: Connect the detection terminal to the microprocessor's I / O port;

[0045] Step S3: The microprocessor determines the voltage level of the I / O port connected to the detection terminal;

[0046] Step S4: If the I / O port connected to the detection terminal is at a low level, the judgment result is that the reset switch K1 is closed, and the operating mechanism of the fault arc circuit breaker is driven to reset and close.

[0047] In step S5, if the I / O port connected to the detection terminal is at a high level, the judgment result is that the microprocessor has been powered off and reset. In this case, the operating mechanism of the fault arc circuit breaker will not be driven to reset and close, and the original state will be maintained.

[0048] Example 3:

[0049] This embodiment provides a fault arc circuit breaker, including a microprocessor and a power-off false reset protection circuit. The reset terminal of the power-off false reset protection circuit is connected to the reset pin of the microprocessor, and the detection terminal of the power-off false reset protection circuit is connected to the I / O port of the microprocessor. The microprocessor is used to determine whether to drive the operating mechanism of the fault arc circuit breaker to reset and close based on the level of the I / O port connected to the detection terminal. When the I / O port connected to the detection terminal is at a low level, the microprocessor determines that the reset switch K1 is closed, and then drives the operating mechanism of the fault arc circuit breaker to reset and close. When the I / O port connected to the detection terminal is at a high level, the microprocessor determines that the power-off reset is activated, and then does not drive the operating mechanism of the fault arc circuit breaker to reset and close, maintaining its original state.

[0050] The circuit of this invention utilizes the excellent charging delay characteristics of capacitors and designs a symmetrical circuit structure, enabling the fault arc circuit breaker to effectively distinguish between a reset caused by pressing the reset button and a power failure reset caused by the tripping of the front-end protection device and the disconnection of the power supply to the fault arc circuit breaker. This allows the breaker to determine whether the operating mechanism of the fault arc circuit breaker should be reset and closed, thus avoiding accidental closing.

[0051] Those skilled in the art will recognize that the units of the various examples described in connection with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of the invention.

[0052] In the embodiments provided in this application, it should be understood that the division of units is only a logical functional division. In actual implementation, there may be other division methods, such as multiple units can be combined into one unit, one unit can be split into multiple units, or some features can be ignored.

[0053] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention, and they should all be covered within the scope of the claims and specification of the present invention.

Claims

1. A circuit for preventing accidental reset due to power failure, characterized in that, Includes resistor R1, delay module, resistor R2, reset switch K1, reset terminal, and detection terminal; One end of the delay module is connected to one end of resistor R1 and the reset end, respectively; The other end of the delay module is connected to one end of resistor R2, the detection end, and one end of reset switch K1, respectively. The other end of resistor R1 and the other end of resistor R2 are respectively connected to a high level. The reset terminal is connected to the reset pin of the microprocessor; the detection terminal is connected to the I / O port of the microprocessor. The other end of the reset switch K1 is grounded.

2. The anti-power-loss reset circuit according to claim 1, characterized in that, The delay module includes a capacitor C.

3. The circuit for preventing accidental reset due to power failure according to claim 1, characterized in that, The resistance value of resistor R1 is equal to the resistance value of resistor R2.

4. A method for preventing accidental reset due to power failure, characterized in that, Applied to the circuit according to any one of claims 1-3, the method includes the following steps: Step S1: Connect the reset terminal to the reset pin of the microprocessor; Step S2: Connect the detection terminal to the microprocessor's I / O port; Step S3: The microprocessor determines the voltage level of the I / O port connected to the detection terminal; Step S4: If the I / O port connected to the detection terminal is at a low level, the judgment result is that the reset switch K1 is closed, and then the operating mechanism of the fault arc circuit breaker is driven to reset and close. In step S5, if the I / O port connected to the detection terminal is at a high level, the judgment result is that the microprocessor has been powered off and reset. In this case, the operating mechanism of the fault arc circuit breaker will not be driven to reset and close, and the original state will be maintained.

5. A fault arc circuit breaker, characterized in that, The circuit includes a microprocessor and the anti-power-loss reset circuit as described in any one of claims 1-3, wherein the reset terminal of the anti-power-loss reset circuit is connected to the reset pin of the microprocessor, and the detection terminal of the anti-power-loss reset circuit is connected to the I / O port of the microprocessor; the microprocessor is used to determine whether to drive the operating mechanism of the fault arc circuit breaker to reset and close based on the level at the I / O port connected to the detection terminal.

6. A fault arc circuit breaker according to claim 5, characterized in that, When the I / O port connected to the detection terminal is at a low level, the microprocessor determines that the reset switch K1 is closed, and then drives the operating mechanism of the fault arc circuit breaker to reset and close; when the I / O port connected to the detection terminal is at a high level, the microprocessor determines that the power-off reset is true, and then does not drive the operating mechanism of the fault arc circuit breaker to reset and close, maintaining its original state.

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