Control device and control method for asymmetrical half-bridge flyback circuit

Abstract

The application provides a control device and a control method of an asymmetric half-bridge flyback circuit. The control method comprises: in a discontinuous operation mode, controlling the asymmetric half-bridge flyback circuit to perform the following operation cycle: controlling the asymmetric half-bridge flyback circuit to enter a switching stage, the switching stage comprising N switching periods, N≥1, wherein in the switching period, a first switch and a second switch in a switching module of the asymmetric half-bridge flyback circuit are alternately turned on and turned off; when the excitation current of a transformer module of the asymmetric half-bridge flyback circuit is demagnetized to 0 in the Nth switching period of the N switching periods, controlling the asymmetric half-bridge flyback circuit to enter a rest stage, wherein in the rest stage, the first switch and the second switch are both turned off; and when the rest stage lasts for a predetermined time, entering a next switching stage, wherein the second switch is first turned on until the excitation current is equal to a negative current required for realizing zero-voltage turn-on of the first switch in a critical conduction mode.

Description

Technical Field

[0001] This application relates to the field of circuit technology, and more specifically to a control device and control method for an asymmetric half-bridge flyback circuit. Background Technology

[0002] With the development of consumer electronics applications, the demand for portable charging devices and adapters is increasing, leading to higher requirements for high-power, miniaturized power supplies (i.e., increased power density). Traditional power supplies are mostly flyback type. While flyback power supplies have a simple structure, they are bulky and have low efficiency, and these drawbacks become more pronounced as power increases. Half-bridge resonant circuits (LLC) offer better efficiency and higher power density at high power levels, but their cost is relatively high, and they perform poorly in applications with a wide output voltage range. In medium-to-high power applications, asymmetric half-bridge flyback circuits, compared to traditional flyback power supplies, can significantly improve efficiency, reduce size, and increase power density, while also offering a cost advantage over half-bridge resonant circuits (LLC). Therefore, they are becoming increasingly popular in medium-to-high power applications. Summary of the Invention

[0003] One aspect of this application provides a control method for an asymmetric half-bridge flyback circuit, comprising: in an intermittent operating mode, controlling the asymmetric half-bridge flyback circuit to cycle through the following operations: controlling the asymmetric half-bridge flyback circuit to enter a switching phase, the switching phase comprising N switching cycles, N≥1, wherein in the switching cycle, the first switch and the second switch in the switching module of the asymmetric half-bridge flyback circuit alternately turn on and off; when the excitation current of the transformer module of the asymmetric half-bridge flyback circuit demagnetizes to 0 in the Nth switching cycle of the N switching cycles, controlling the asymmetric half-bridge flyback circuit to enter a resting phase, wherein in the resting phase, both the first switch and the second switch are turned off; and after the resting phase lasts for a predetermined time, entering the next switching phase, wherein the second switch is controlled to turn on first until the excitation current is equal to the negative current required to achieve zero-voltage turn-on of the first switch in the critical turn-on mode.

[0004] Another aspect of this application provides a control device for an asymmetric half-bridge flyback circuit, comprising: a control chip configured to: in an intermittent operating mode, control the asymmetric half-bridge flyback circuit to cycle through the following operations: control the asymmetric half-bridge flyback circuit to enter a switching phase, the switching phase comprising N switching cycles, N≥1, wherein in the switching cycle, a first switch and a second switch in the switching module of the asymmetric half-bridge flyback circuit are alternately turned on and off; when the excitation current of the transformer module of the asymmetric half-bridge flyback circuit demagnetizes to 0 in the Nth switching cycle of the N switching cycles, control the asymmetric half-bridge flyback circuit to enter a resting phase, wherein in the resting phase, both the first switch and the second switch are turned off; and after the resting phase lasts for a predetermined time, enter the next switching phase, wherein control the second switch to turn on first until the excitation current is equal to the negative current required to achieve zero-voltage turn-on of the first switch in the critical turn-on mode.

[0005] According to the control device and control method of the asymmetric half-bridge flyback circuit of this application, through optimized intermittent operation mode control, it can operate at a high efficiency state under different power levels. Attached Figure Description

[0006] The various aspects of this application can be best understood by reading the following detailed description in conjunction with the accompanying drawings. Note that, according to industry standard practice, the various features are not necessarily drawn to scale. In the figures, similar numerical labels describe similar components. Similar numbers with different letter suffixes may indicate different instances of similar components. In the accompanying drawings:

[0007] Figure 1 A schematic block diagram of a control system for an asymmetric half-bridge flyback circuit according to an embodiment of this application is shown.

[0008] Figure 2 A schematic diagram of the circuit structure of a control system for an asymmetric half-bridge flyback circuit according to an embodiment of this application is shown.

[0009] Figure 3 A schematic diagram of the operating waveform of an asymmetric half-bridge flyback circuit according to an embodiment of this application in critical conduction mode (CrM) is shown.

[0010] Figure 4 A schematic diagram of the operating waveform of the asymmetric half-bridge flyback circuit according to an embodiment of this application in conventional discontinuous operation mode (DCM) is shown.

[0011] Figure 5 A schematic diagram of the operating waveform of the asymmetric half-bridge flyback circuit according to an embodiment of this application in optimized DCM mode is shown.

[0012] Figure 6A schematic diagram showing the operating frequency and current curves of an asymmetric half-bridge flyback circuit according to an embodiment of this application is provided.

[0013] Figure 7 A schematic diagram of the operating waveform of an asymmetric half-bridge flyback circuit according to an embodiment of this application as the output load varies is shown.

[0014] Figure 8 A schematic diagram of a control device for an asymmetric half-bridge flyback circuit according to an embodiment of this application is shown;

[0015] Figure 9 A schematic diagram illustrating an example of a control device for an asymmetric half-bridge flyback circuit according to an embodiment of this application is shown;

[0016] Figure 10a A schematic diagram illustrating the determination of the number of switching cycles according to an embodiment of this application is shown;

[0017] Figure 10b A schematic diagram illustrating the determination of the number of switching cycles according to an embodiment of this application is shown;

[0018] Figure 11 A schematic diagram of the operating waveform of the asymmetric half-bridge flyback circuit according to an embodiment of this application in optimized DCM mode is shown.

[0019] Figure 12 A schematic flowchart of a control method for an asymmetric half-bridge flyback circuit according to an embodiment of this application is shown;

[0020] Figure 13 A schematic flowchart illustrating a method for determining the number of switching cycles according to an embodiment of this application is shown; and

[0021] Figure 14 A schematic flowchart of a method for determining the number of switching cycles according to an embodiment of this application is shown. Detailed Implementation

[0022] The features and exemplary embodiments of various aspects of this application will now be described in detail. Numerous specific details are set forth in the following detailed description to provide a comprehensive understanding of this application. However, it will be apparent to those skilled in the art that this application can be implemented without requiring some of these specific details. The following description of embodiments is merely intended to provide a better understanding of this application by illustrating examples. This application is by no means limited to any specific configurations and algorithms presented below, but covers any modifications, substitutions, and improvements to elements, components, and algorithms without departing from the spirit of this application. Well-known structures and techniques are not shown in the accompanying drawings and the following description in order to avoid unnecessary obfuscation of this application.

[0023] Figure 1 A schematic block diagram of a control system for an asymmetric half-bridge flyback circuit according to an embodiment of this application is shown. Figure 1 As shown, the control system 100 of the asymmetric half-bridge flyback circuit according to an embodiment of this application includes a control module 101, a switching module 102, a resonant module 103, a transformer module 104, a rectifier module 105, an output module 106, and a feedback module 107.

[0024] Switch module 102 is connected to input voltage Vin and control module 101. Switch module 102 receives control signals from control module 101 to turn on or off according to the control signals.

[0025] The resonant module 103 is connected to the switching module 102 and processes the input voltage provided by the switching module 102.

[0026] The transformer module 104 is connected to the resonant module 103 to transform the input voltage provided by the resonant module 103. The transformer module 104 is also connected to the control module 101 to feed back the operating status of the transformer module 104 to the control module 101.

[0027] The rectifier module 105 is connected to the transformer module 104, receives the voltage and current signals provided by the transformer module 104, rectifies them, and provides the rectified voltage and current signals to the output module 106.

[0028] The output module 106 is connected to the rectifier module 105 and provides the output signal based on the rectified voltage and current signals provided by the rectifier module 105.

[0029] Feedback module 107 is connected to output module 106 and receives the output signal provided by output module 106. Feedback module 107 is also coupled to control module 101 and provides feedback signal based on the output signal to control module 101.

[0030] The control module 101 provides control signals to the switch module 102 based on the feedback signals from the feedback module 107.

[0031] Figure 2 A schematic diagram of the circuit structure of a control system for an asymmetric half-bridge flyback circuit according to an embodiment of this application is shown. The control system 100 for the asymmetric half-bridge flyback circuit according to an embodiment of this application includes a control module 201, a switching module 202, a resonant module 203, a transformer module 204, a rectifier module 205, an output module 206, and a feedback module 207.

[0032] like Figure 2As shown, the switch module 202 is connected to the input voltage Vin and the control module 201. The switch module 202 receives a control signal from the control module 201 to turn the device on or off according to the control signal. The switch module 202 includes a first switch S1 and a second switch S2, which are connected in series between the input voltage Vin and ground. The first terminal of the first switch S1 is connected to the input voltage Vin, the second terminal of the first switch S1 is connected to the first terminal of the second switch S2, and the third terminal of the first switch S1 is connected to the first pin (shown as GH) of the control module 201; the second terminal of the second switch S2 is connected to the ground, and the third terminal of the second switch S2 is connected to the second pin (shown as GL) of the control module 201. In some embodiments, the first switch S1 and the second switch S2 may be switching devices such as MOSFETs, transistors, or gallium nitride (GaN).

[0033] The resonant module 203 is connected to the switch module 202 and processes the input voltage provided by the switch module 202. The resonant module 203 includes an inductor Lr and a capacitor Cr. One end of the inductor Lr is connected to the connection point between the second terminal of the first switch S1 and the first terminal of the second switch S2, and the other end of the inductor Lr is connected to the transformer module 204. One end of the capacitor Cr is connected to the second terminal of the second switch S2, i.e., the ground terminal, and the other end of the capacitor Cr is connected to the transformer module 204.

[0034] Transformer module 204 is connected to resonant module 203 to transform the input voltage provided via resonant module 203. Transformer module 204 includes a primary winding connected to the other end of the inductor Lr and the other end of the capacitor Cr of resonant module 203. Transformer module 204 also includes a secondary winding connected to rectifier module 205. Through the primary and secondary windings, transformer module 204 transforms the input voltage provided via resonant module 203 and provides the transformed voltage and current signals to rectifier module 205. It should be understood that although resonant module 203 and transformer module 204 are described separately here, inductor Lr can also be considered as the leakage inductance of transformer module 204. Furthermore, transformer module 204 includes an auxiliary winding connected to the third pin (shown as AUX) of control module 201. The auxiliary winding feeds back the operating state of transformer module 204 to control module 201.

[0035] The rectifier module 205 receives the voltage and current signals provided by the transformer module 204 and rectifies them. For example... Figure 2 As shown, in some embodiments, the rectifier module 205 includes a third switch S3 and a controller 209 (e.g., an SR controller), wherein the third switch S3 is turned on or off according to the control of the controller 209 to achieve rectification.

[0036] Output module 206 is connected to rectifier module 205, and further coupled to transformer module 204, providing an output signal based on the rectified voltage and current signals provided by rectifier module 205. In some embodiments, output module 206 may include an output capacitor C. out Output capacitor C out Used to filter out the switching frequency ripple in the voltage signal from transformer module 204.

[0037] Feedback module 207 is connected to output module 206 and receives the output signal provided by output module 206. Feedback module 207 is also coupled to control module 201, for example, to a fourth pin (shown as FB) of control module 201, providing a feedback signal based on the output signal to control module 201. In some embodiments, feedback module 207 includes a voltage regulator (e.g., TL431) and an optocoupler. It should be understood that the circuitry shown for feedback module 207 is merely an example and is not limited to that circuitry.

[0038] Control module 201 provides control signals to switch module 202 based on feedback signals from feedback module 207. Control module 201 also includes a ground pin (shown as GND).

[0039] It should be understood that Figure 1 and Figure 2 This is merely an example implementation of a control system for an asymmetric half-bridge flyback circuit and is not limited to the example described above. For example, the resonant module 203 can also be coupled to both ends of the first switch S1. It should also be understood that... Figure 1 and Figure 2 A control system that is solely based on an asymmetric half-bridge flyback circuit can be understood as including both the asymmetric half-bridge flyback circuit and the control module.

[0040] Asymmetric half-bridge flyback circuits can operate in different modes, such as critical conduction mode (CrM) and discontinuous conduction mode (DCM). When operating under heavy loads, asymmetric half-bridge flyback circuits typically operate in CrM mode. In CrM mode, only a switching phase is included, during which the first and second switches in the switching module of the asymmetric half-bridge flyback circuit alternately turn on and off.

[0041] Figure 3 A schematic diagram of the operating waveforms of the asymmetric half-bridge flyback circuit according to an embodiment of this application in CrM mode is shown below. (See reference below.) Figure 2 and Figure 3 This will illustrate the specific operation of the asymmetric half-bridge flyback circuit in CrM mode.

[0042] exist Figure 3 middle, I outRepresents the output current. GH and GL represent the control waveforms of the first switch S1 and the second switch S2, respectively. A high level indicates that the corresponding switch is in the on state, and a low level indicates that the corresponding switch is in the off state. V HB This represents the voltage at the midpoint of the half-bridge arm, i.e., the voltage at the connection point between the first switch S1 and the second switch S2. Lr This represents the current flowing through inductor Lr. Lm The excitation current representing transformer module 204, when the first switch S1 is turned on, i Lm with i Lr The same applies; when the second switch S2 is turned on, its current is shown by the dashed line, where I P For the excitation current i Lm The maximum value, i.e., the positive peak current, I N For the excitation current i Lm The minimum value of I, i.e., the negative peak current. sec This represents the current on the line of rectifier module 205.

[0043] In CrM mode, when the first switch S1 is on and the second switch S2 is off, the input voltage V in Energy is stored in transformer module 204 and capacitor Cr. When the first switch S1 is turned off and the second switch S2 is turned on, capacitor Cr resonates with inductor Lr and transfers energy to the secondary side (i.e., the secondary winding) of transformer module 204. In CrM mode, the excitation current i can be adjusted. Lm The negative current value is used to achieve zero-voltage switching (ZVS) of the first switch S1. In this mode, the output current I... out It is represented as:

[0044]

[0045] Where, N ps This refers to the turns ratio of the primary winding to the secondary winding of the transformer. Therefore, by adjusting the excitation current i of the transformer module 204... Lm Peak current I P The output current I can be adjusted. out .

[0046] The resonant frequency of the resonant module 203 can be expressed as:

[0047]

[0048] That is, the resonant frequency is controlled by the inductor Lr and the capacitor Cr.

[0049] When the demagnetization time of transformer module 204 (i.e., i Lm From I p The time taken to change it to 0 is denoted as t.dem The resonant period of the resonant module 203 (which is the reciprocal of the resonant frequency, denoted as t) is the resonant period of the resonant module 203. r When a certain relationship is satisfied (e.g., t) dem ≈0.6t r The primary and secondary sides of transformer module 204 can achieve or approach zero current turn-off, at which point the efficiency is optimal.

[0050] As the load decreases, the excitation current i Lm Peak current I P As the switching frequency increases and the resonant current on the primary side and the hard-turn-off current on the secondary side of transformer module 204 increase, continued operation in CrM mode will significantly reduce efficiency. In this case, switching to DCM mode can be used to prevent peak current I... P The frequency of operation continues to increase, while the operating frequency continues to decrease.

[0051] Figure 4 A schematic diagram of the operating waveform of the asymmetric half-bridge flyback circuit according to an embodiment of this application in conventional DCM mode is shown. Figure 4 The symbols used in the text are similar to those in the text. Figure 3 The same applies, so I won't elaborate further.

[0052] like Figure 4 As shown, in the traditional DCM mode, firstly, the asymmetric half-bridge flyback circuit is controlled to enter the switching phase. During this phase, the first switch S1 in the switching module is turned on, then the first switch S1 is turned off and the second switch S2 is turned on. Next, a rest phase begins, during which both the first switch S1 and the second switch S2 are turned off. This process is then repeated. In this traditional DCM mode, as shown in the figure, the excitation current i can be... Lm Peak current I P Operating at its most efficient state, i.e., demagnetization time (t) dem ) and resonance period (t) r ) satisfy a certain relationship (e.g., t) dem ≈0.6t r When the transformer module 204 is in operation, both the primary and secondary sides can achieve or approach zero current turn-off. In this conventional mode, the output current is adjusted by increasing the duration of the pause phase. At this time, the output current I... out It is represented as:

[0053]

[0054] Where, N ps It is the turns ratio of the primary winding to the secondary winding of the transformer, t1 is the duration of the switching phase, and t2 is the duration of the rest phase.

[0055] However, in traditional DCM mode, a hard turn-on occurs before each switching phase, and the operating frequency remains high under medium load, leading to efficiency loss. Furthermore, in traditional DCM mode, a switching window is typically added at the transition point between CrM and DCM modes to avoid repeated switching between the two modes. To improve efficiency, the resonant peak point is usually chosen as the switching turn-on point, resulting in a pause duration t2 of at least 1.5 valley resonant cycles, thus limiting the maximum output current in traditional DCM mode. Therefore, the output current point for transitioning from CrM mode to DCM mode is usually set lower; otherwise, the system is prone to repeated switching between the two modes. In this case, the higher switching frequency and hard current turn-off in CrM mode before entering DCM mode also lead to efficiency loss.

[0056] In view of the above problems, an optimized control method for DCM mode is proposed according to embodiments of this application. In the optimized DCM mode, the asymmetric half-bridge flyback circuit operates cyclically as follows: First, it enters a switching phase, which includes N switching cycles, where N≥1. During the switching cycle, the first switch S1 and the second switch S2 in the switching module S202 of the asymmetric half-bridge flyback circuit alternately turn on and off. Hereinafter, the switching cycle can also be referred to as the CrM cycle, and N switching cycles can also be considered as N cycles operating in CrM mode, since the first and second switches alternately turn on and off in CrM mode. When the excitation current of the transformer module of the asymmetric half-bridge flyback circuit demagnetizes to 0 in the Nth switching cycle of the N switching cycles, it enters a rest phase, during which both the first switch S1 and the second switch S2 are turned off. After the rest phase lasts for a predetermined time, it enters the next switching phase, wherein the second switch S2 is first turned on until the excitation current equals the negative current required to achieve zero-voltage turn-on of the first switch S1 in CrM mode.

[0057] Figure 5 A schematic diagram of the operating waveform of the asymmetric half-bridge flyback circuit according to an embodiment of this application in optimized DCM mode is shown. Figure 5 An example of N=3 is shown; however, it should be understood that N can be any integer greater than or equal to 1. Figure 5 The symbols used in the text are similar to those in the text. Figure 3 and Figure 4 The same applies, so I won't repeat it further. In addition, DCM_on represents whether the signal is in the switching phase or the pause phase. When DCM_on is high, it is in the switching phase, and the duration of the corresponding switching phase is t1. When DCM_on is low, it is in the pause phase, and the duration of the corresponding pause phase is t2.

[0058] like Figure 5 As shown, the duration of the switching phase is t1. During the switching phase, the conduction time of the second switch S2 in the continuous conduction phase is t3, and the conduction time of the second switch S2 in the last CrM cycle is equal to the excitation current i. Lm Demagnetization time t dem The pause phase lasts for t2. After the pause phase ends, the conduction time of the second switch S2 is t4, where t3 = t dem +t4. Therefore, in the optimized DCM mode, the switching phase can still be considered as N complete CrM cycles. Thus, the output current I out It can still be represented as:

[0059]

[0060] Compared to the traditional DCM mode, the optimized DCM mode increases the maximum output current due to the longer switching phase duration t1. Therefore, the switching point output current between CrM and DCM modes can be set higher, allowing for earlier entry into DCM mode when the load decreases, thus improving system efficiency. Furthermore, in the optimized DCM mode, the switching phase can still be considered as N complete CrM cycles, thus still achieving zero-voltage turn-on and zero-current turn-off, further improving efficiency. Additionally, the single hard-switching loss at the end of the pause phase is reduced, and its frequency is lowered by a factor of N, resulting in further loss reduction. Moreover, during stable operation, adjusting the number of switching cycles in DCM mode, i.e., adjusting the switching phase duration, alters the DCM mode period, achieving frequency jitter and optimizing electromagnetic interference (EMI).

[0061] Figure 6 A schematic diagram illustrating the operating frequency and current curves of an asymmetric half-bridge flyback circuit according to an embodiment of this application is shown. Figure 6 In the middle, the topmost value is the excitation current i. Lm Peak current I P With output current I out Relationship diagram; the middle represents the switching frequency f. SW With output current I out A relationship diagram, where f SW_AVG f represents the average switching frequency in DCM mode. DCM f represents the envelope frequency in DCM mode. REF This is the reference frequency (e.g., above 20kHz); below is the number of switching cycles N in DCM mode as a function of the output current I. out A relationship diagram, where N MAX This represents the maximum adjustable value for the number of switching cycles. As shown in the graph, with the output current I... out Decrease, excitation current iLm Peak current I P Reduce the switching frequency f SW Increase. To prevent the excitation current i Lm Peak current I P Further reduction, transitioning from CrM mode to DCM mode. In DCM mode, the excitation current i Lm Peak current I P An improvement over the CrM mode, and with the increase in output current I out Decrease to a stable average switching frequency f SW_AVG It also gradually decreases by changing the number of switching cycles N and the envelope frequency f. DCM Always slightly above the reference frequency f REF This improves efficiency. As the average switching frequency f increases... SW_AVG Reduce to f REF The switching frequency no longer decreases, and at this time the excitation current i Lm Peak current I P Reduce the output current I further. out In the output current I out When the current is less than a preset threshold, the asymmetric half-bridge flyback circuit is in burst mode, at which time the excitation current i Lm Peak current I P This is a preset constant value. In this application, in DCM mode, the number N of switching cycles is defined as follows: (The duration of a switching phase plus the duration of the corresponding pause phase is called an envelope cycle, t...) period =t1+t2, the entire DCM mode can be regarded as a cycle of the envelope period, which is dynamically changeable.

[0062] Figure 7 A schematic diagram of the operating waveforms of an asymmetric half-bridge flyback circuit according to an embodiment of this application as the output load varies is shown. Figure 7 middle, I out GH represents the output current, and GH represents the turn-on signal of the first switch S1, the amplitude of which represents the current cycle peak current I. P Size, f SW f represents the switching frequency in DCM mode. SW_AVG f represents the average switching frequency in DCM mode. DCM The envelope frequency represents the DCM mode, and N represents the number of switching cycles within the envelope period.

[0063] When the output current I out When the current is large, the asymmetric half-bridge flyback circuit operates in CrM mode, and the output current I... out Reduce, peak current I P Reduce the switching frequency fsw The frequency increases. Subsequently, the asymmetric half-bridge flyback circuit enters DCM mode, and after N consecutive CrM cycles (N≥1), it enters a rest phase. As the load decreases, N gradually decreases to 1, causing the envelope frequency f to rise. DCM Always maintain a frequency greater than the reference frequency f REF (>20kHz) to avoid audio noise. When N=1 and the switching frequency f sw Reduce to f REF At that time, the peak current I will continue to decrease. P Maintain operating frequency f SW Unchanged. As the load continues to decrease, causing the output current to decrease by I... out When the value falls below the preset threshold, the system will enter Burst mode.

[0064] Figure 8 A schematic diagram of a control device for an asymmetric half-bridge flyback circuit according to an embodiment of this application is shown. This control device can be embodied as a control chip 800. It should be understood that... Figure 8 The control chip 800 shown is merely an example and should not be construed as limiting the functionality and scope of the embodiments of this disclosure.

[0065] like Figure 8 As shown, the control chip 800 includes: a power supply module 801, which receives the chip's operating voltage VCC and provides power to other modules of the control chip 800, and includes a VCC pin; a first sampling module 802, which samples the operating state and output voltage of the transformer module, and includes an AUX pin; a second sampling module 803, which samples the voltage fed back by the feedback module, and includes an FB pin; a drive module 804, which drives the switches in the switch module to turn on or off, and includes GH and GL pins; and a logic control component 805, which is connected to each module of the control chip 800 and is used to perform overall control based on the information provided by each module. The logic control component 805 can be implemented as an analog circuit, a digital application-specific circuit, or an MCU, for example. Additionally, the control chip 800 also includes a ground pin GND. In some implementations, the control chip 800 also includes a CS pin and a CFG pin (external configuration pin), where the CS pin can sample the current of the resonant module, and the CFG pin can be used to adjust some operating parameters of the control chip 800 according to an analog or digital configuration scheme.

[0066] The control chip 800 is configured to: in the DCM, control the asymmetric half-bridge flyback circuit to cycle through the following operations: control the asymmetric half-bridge flyback circuit to enter a switching phase, which includes N switching cycles, N≥1, wherein in this switching cycle, the first switch S1 and the second switch S2 in the switching module of the asymmetric half-bridge flyback circuit are alternately turned on and off; when the excitation current of the transformer module of the asymmetric half-bridge flyback circuit demagnetizes to 0 in the Nth switching cycle of the N switching cycles, control the asymmetric half-bridge flyback circuit to enter a resting phase, wherein in this resting phase, both the first switch S1 and the second switch S2 are turned off; and after the resting phase lasts for a predetermined time, enter the next switching phase, wherein the second switch S2 is first turned on until the excitation current is equal to the negative current required to achieve zero-voltage turn-on of the first switch S1 in CrM mode.

[0067] As described above, in the optimized DCM mode, the number N of switching cycles per envelope cycle is dynamically adjustable. In some embodiments, the control chip 800 is further configured to: determine the previous envelope cycle in the DCM mode, wherein the previous envelope cycle includes the duration of the previous switching phase and the duration of the previous pause phase; determine the number of switching cycles in the previous envelope cycle; determine the average switching frequency in the previous envelope cycle based on the previous envelope cycle and the number of switching cycles in the previous envelope cycle; compare the average switching frequency with a predetermined reference frequency; and determine the number of switching cycles in the current envelope cycle based on the result of the comparison. In some embodiments, the average switching frequency is determined by dividing the number of switching cycles in the previous envelope cycle by the previous envelope cycle. In some embodiments, the comparison determines a ratio of the average switching frequency to the predetermined reference frequency, and the number of switching cycles in the current envelope cycle is determined according to this ratio.

[0068] In some embodiments, the control chip 800 is further configured to: determine a previous envelope cycle in DCM mode, wherein the previous envelope cycle includes the duration of a previous switching phase and the duration of a previous pause phase, and determine the envelope frequency of the previous envelope cycle based on the previous envelope cycle; compare the envelope frequency of the previous envelope cycle with a predetermined reference frequency; and adjust the number of switching cycles in the current envelope cycle based on the comparison result. In some embodiments, if the envelope frequency of the previous envelope cycle is lower than the predetermined reference frequency, the number of switching cycles in the previous envelope cycle is reduced to determine the number of switching cycles in the current envelope cycle; if the envelope frequency of the previous envelope cycle is higher than the predetermined reference frequency and exceeds a predetermined threshold, the number of switching cycles in the previous envelope cycle is increased to determine the number of switching cycles in the current envelope cycle; and if the envelope frequency of the previous envelope cycle is higher than the predetermined reference frequency but does not exceed the predetermined threshold, the number of switching cycles in the previous envelope cycle is kept unchanged to determine the number of switching cycles in the current envelope cycle.

[0069] In some embodiments, the control chip 800 is further configured to: determine the time of N switching cycles; determine the output current to be controlled by the asymmetric half-bridge flyback circuit based on the voltage fed back by the feedback module of the asymmetric half-bridge flyback circuit; determine the positive peak current of the excitation current based on the output current; determine the negative peak current of the excitation current based on the magnitude of the negative current required to achieve zero-voltage turn-on of the first switch; and determine the current envelope period required to achieve the output current based on the positive peak current, the negative peak current, and the time of N switching cycles.

[0070] In some embodiments, the control chip 800 is further configured to determine the duration of the pause phase based on the current envelope period and the duration of the switching phase. Specifically, the duration of the pause phase is determined by the difference between the time of the current envelope period and the duration of the switching phase.

[0071] It should be understood that although the above description uses the control chip 800 to control the DCM mode of the asymmetric half-bridge flyback circuit, the CrM mode of the asymmetric half-bridge flyback circuit can also be controlled by the control chip 800.

[0072] Figure 9 A schematic diagram illustrating an example of a control device for an asymmetric half-bridge flyback circuit according to an embodiment of this application is shown. It should be understood that... Figure 9 The modules shown can be used as Figure 8 A portion of the control chip 800 shown may be incorporated, for example, into the logic control component 805.

[0073] like Figure 9As shown, counter 901 counts the number of switching cycles (the time it takes for the first switch S1 or the second switch S2 to complete one turn-on and one turn-off is considered one switching cycle). When the DCM_on signal is set to high, it indicates the start of the switching phase, and counter 901 counts the number of times the first switch S1 or the second switch S2 is switched. When comparator 902 determines that the number of switching cycles counted by counter 901 has reached N and the current switching cycle has been completed, the DCM_on signal is set to low, indicating the start of the pause phase.

[0074] Timer 903 performs time statistics. Specifically, timer 903 detects the previous envelope cycle when the rising edge of the DCM_on signal arrives and resets the timer to zero. When the falling edge of DCM_on arrives, it detects the on-time of DCM_on (i.e., the high-level period, which is also the duration t1 of the switching phase).

[0075] For chips employing current-mode control, the control chip can determine the required output current I based on the voltage fed back from the feedback module of the asymmetric half-bridge flyback circuit. out The positive peak current I of the excitation current is determined based on the output current. P The negative peak current I of the excitation current is determined based on the magnitude of the negative current required to achieve zero-voltage switching of the first switch. N Based on the duration t1 of the switching phase and the positive peak current I of the excitation current. P and negative peak current I N The envelope period required to achieve this output current can be calculated, i.e.:

[0076]

[0077] After the comparator 904 determines that the time counted by the timer 903 has reached the calculated envelope period and the operating voltage of the transformer module based on the asymmetric half-bridge flyback circuit detects the valley signal, DCM_on is set to high level, and the next envelope period (i.e., the next cycle) begins.

[0078] It should also be understood that Figure 9 This is merely an example implementation; the specific arrangement of the control device for the asymmetric half-bridge flyback circuit according to embodiments of this application is not limited thereto.

[0079] In some implementations, the number of switching cycles in the current envelope cycle can be calculated based on the average switching frequency of the previous envelope cycle, and the updated number of switching cycles can be used in the current envelope cycle. Specifically, Figure 10a As shown, the previous envelope period t in DCM mode is determined. period_pre and the number N of switching cycles within the previous envelope cycle. preThe number N of switching cycles within the previous envelope cycle. pre Except for the previous envelope period t period_pre Determine the average switching frequency f within the previous envelope period SW_AVG Based on the average switching frequency f in the previous envelope period SW_AVG With reference frequency f REF The ratio between them determines the number N of switching cycles in the current envelope cycle.

[0080] As an example, Figure 11 A schematic diagram of the operating waveform of the asymmetric half-bridge flyback circuit according to an embodiment of this application in optimized DCM mode is shown. Figure 11 The symbols used are consistent with those in the previous diagrams and will not be repeated here. Furthermore, `timer` represents the timing status of timer 903, and `counter` represents the counting status of counter 901. For example... Figure 11 As shown, at time t0, the envelope frequency f of the previous envelope period is determined. DCM_pre and average switching frequency f SW_AVG If the average switching frequency f SW_AVG With reference frequency f REF If the ratio between the two is between 2 and 3, then the number of switching cycles in the current envelope cycle is determined to be 2. At time t1, the average switching frequency f of the previous envelope cycle is determined. SW_AVG With reference frequency f REF If the ratio between them is between 3 and 4, then the number of switching cycles in the current envelope period is determined to be 3. Envelope frequency f DCM It remains at a low level, but above the audio level.

[0081] In some implementations, the number of switching cycles in the current envelope cycle can be calculated based on the envelope frequency of the previous envelope cycle, and the updated number of switching cycles can be used in the current envelope cycle. Specifically, Figure 10b As shown, the previous envelope period t in DCM mode is determined. period_pre And then determine the envelope frequency f of the previous envelope period. DCM_pre According to the envelope frequency f DCM_pre With reference frequency f REF The magnitude of the signal is used to adjust the number of switching cycles within the current envelope period. In some embodiments, the envelope frequency f in the previous envelope period... DCM_pre Below the predetermined reference frequency f REF In this case, the number of switching cycles in the previous envelope period is reduced (e.g., by 1) to determine the number of switching cycles in the current envelope period, thereby increasing the envelope frequency of the current envelope period; at the envelope frequency f of the previous envelope period DCM_pre Higher than the predetermined reference frequency f REFIf the number of switching cycles exceeds a predetermined threshold, the number of switching cycles in the previous envelope period is increased (e.g., incremented by 1) to determine the number of switching cycles in the current envelope period, thereby reducing the envelope frequency of the current envelope period; and the envelope frequency f in the previous envelope period... DCM_pre Higher than the predetermined reference frequency f REF However, if the predetermined threshold is not exceeded, the number of switching cycles in the previous envelope period is kept unchanged to determine the number of switching cycles in the current envelope period.

[0082] Figure 12 A schematic flowchart illustrating a control method for an asymmetric half-bridge flyback circuit according to an embodiment of this application is shown. Figure 12 As shown, the control method 1200 for an asymmetric half-bridge flyback circuit according to an embodiment of this application includes: in an intermittent operating mode, controlling the asymmetric half-bridge flyback circuit to cycle through the following operations S1202-S1206. At S1202, the asymmetric half-bridge flyback circuit is controlled to enter a switching phase, which includes N switching cycles, N≥1, wherein during the switching cycle, the first switch and the second switch in the switching module of the asymmetric half-bridge flyback circuit alternately turn on and off. At S1204, when the excitation current of the transformer module of the asymmetric half-bridge flyback circuit demagnetizes to 0 in the Nth switching cycle of the N switching cycles, the asymmetric half-bridge flyback circuit is controlled to enter a resting phase, wherein during the resting phase, both the first switch and the second switch are turned off. At S1206, after the resting phase lasts for a predetermined time, the next switching phase is entered, wherein the second switch is controlled to first turn on until the excitation current equals the negative current required to achieve zero-voltage turn-on of the first switch in the critical turn-on mode.

[0083] In some embodiments, the number of switching cycles in the current envelope cycle can be calculated based on the average switching frequency of the previous envelope cycle, and the updated number of switching cycles can be used in the current envelope cycle. Figure 13 A schematic flowchart illustrating a method for determining the number of switching cycles according to an embodiment of this application is shown. Figure 13As shown, the method 1300 for determining the number of switching cycles according to an embodiment of this application includes S1302-S1310. At S1302, a previous envelope cycle in an intermittent operating mode is determined, wherein the previous envelope cycle includes the duration of a previous switching phase and the duration of a previous pause phase. At S1304, the number of switching cycles within the previous envelope cycle is determined. At S1306, the average switching frequency within the previous envelope cycle is determined based on the previous envelope cycle and the number of switching cycles within the previous envelope cycle. At S1308, the average switching frequency is compared with a predetermined reference frequency. At S1310, the number of switching cycles within the current envelope cycle is determined based on the result of the comparison. In some embodiments, the average switching frequency is determined by dividing the number of switching cycles within the previous envelope cycle by the previous envelope cycle. In some embodiments, the comparison determines a ratio of the average switching frequency to the predetermined reference frequency, and the number of switching cycles within the current envelope cycle is determined according to the ratio.

[0084] In some embodiments, the number of switching cycles in the current envelope period can be calculated based on the envelope frequency of the previous envelope period, and the updated number of switching cycles can be used in the current envelope period. Figure 14 A schematic flowchart illustrating a method for determining the number of switching cycles according to an embodiment of this application is shown. Figure 14 As shown, the method 1400 for determining the number of switching cycles according to an embodiment of this application includes steps S1402-S1406. At S1402, a previous envelope cycle in the intermittent operating mode is determined, wherein the previous envelope cycle includes the duration of a previous switching phase and the duration of a previous pause phase, and the envelope frequency of the previous envelope cycle is determined based on the previous envelope cycle. At S1404, the envelope frequency is compared with a predetermined reference frequency. At S1406, the number of switching cycles within the current envelope cycle is adjusted based on the comparison result. In some embodiments, if the envelope frequency of the previous envelope cycle is lower than a predetermined reference frequency, the number of switching cycles in the previous envelope cycle is reduced to determine the number of switching cycles in the current envelope cycle; if the envelope frequency of the previous envelope cycle is higher than the predetermined reference frequency and exceeds a predetermined threshold, the number of switching cycles in the previous envelope cycle is increased to determine the number of switching cycles in the current envelope cycle; and if the envelope frequency of the previous envelope cycle is higher than the predetermined reference frequency but does not exceed the predetermined threshold, the number of switching cycles in the previous envelope cycle remains unchanged to determine the number of switching cycles in the current envelope cycle.

[0085] In some embodiments, the method 1300 for determining the number of switching cycles according to the present application further includes: determining the time of the N switching cycles; determining the output current to be controlled by the asymmetric half-bridge flyback circuit based on the voltage fed back by the feedback module of the asymmetric half-bridge flyback circuit; determining the positive peak current of the excitation current based on the output current, and determining the negative peak current of the excitation current based on the magnitude of the negative current required to achieve zero-voltage turn-on of the first switch; and determining the current envelope period required to achieve the output current based on the positive peak current, the negative peak current, and the time of the N switching cycles.

[0086] In some embodiments, the control method for the asymmetric half-bridge flyback circuit further includes determining the duration of the pause phase based on the time of the current envelope cycle and the duration of the switching phase. Specifically, the duration of the pause phase is determined by the difference between the time of the current envelope cycle and the duration of the switching phase.

[0087] According to the control device and control method of the asymmetric half-bridge flyback circuit in the embodiments of this application, by optimizing the control mode of DCM mode, the efficiency of DCM mode can be greatly improved, and the output current at the switching point between CrM mode and DCM mode can be increased, so that the asymmetric half-bridge flyback circuit can work in the working mode with the best efficiency, thereby improving the efficiency of the asymmetric half-bridge circuit under different loads.

[0088] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and control devices according to various embodiments of the present disclosure. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based integrated circuit that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0089] This invention can be implemented in other specific forms without departing from its spirit and essential characteristics. For example, the algorithm described in a particular embodiment can be modified without departing from the basic spirit of the invention. Therefore, the present embodiments are to be regarded as exemplary rather than limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description, and all changes falling within the meaning and scope of the claims and their equivalents are thus included within the scope of the invention.

Claims

1. A control method for an asymmetric half-bridge flyback circuit, comprising: In intermittent operation mode, the control of the asymmetric half-bridge flyback circuit cycles through the following operations: The asymmetric half-bridge flyback circuit is controlled to enter the switching stage, which includes N switching cycles, N≥1, wherein in the switching cycle, the first switch and the second switch in the switching module of the asymmetric half-bridge flyback circuit are alternately turned on and off. When the excitation current of the transformer module of the asymmetric half-bridge flyback circuit demagnetizes to 0 in the Nth switching cycle of the N switching cycles, the asymmetric half-bridge flyback circuit is controlled to enter the rest phase, wherein the first switch and the second switch are both turned off in the rest phase. as well as After the pause phase lasts for a predetermined time, the next switching phase begins, wherein the second switch is controlled to turn on first until the excitation current is equal to the negative current required to achieve zero-voltage turn-on of the first switch in the critical conduction mode.

2. The control method according to claim 1 further includes: Determine the previous envelope period in the intermittent working mode, wherein the previous envelope period includes the duration of the previous switching phase and the duration of the previous pause phase; Determine the number of switching cycles within the previous envelope cycle; The average switching frequency in the previous envelope period is determined based on the previous envelope period and the number of switching periods in the previous envelope period. The average switching frequency is compared with a predetermined reference frequency; as well as The number of switching cycles within the current envelope period is determined based on the results of the comparison.

3. The control method according to claim 1 further includes: Determine the previous envelope period in the intermittent working mode, wherein the previous envelope period includes the duration of the previous switching phase and the duration of the previous pause phase, and determine the envelope frequency of the previous envelope period based on the previous envelope period. The envelope frequency of the previous envelope cycle is compared with a predetermined reference frequency; as well as The number of switching cycles within the current envelope period is adjusted based on the results of the comparison.

4. The control method according to claim 2, wherein, The average switching frequency is determined by dividing the number of switching cycles in the previous envelope period by the previous envelope period.

5. The control method according to claim 2, wherein, The comparison determines the ratio of the average switching frequency to the predetermined reference frequency, and the number of switching cycles within the current envelope period is determined based on the ratio.

6. The control method according to claim 3, wherein, If the envelope frequency of the previous envelope cycle is lower than the predetermined reference frequency, the number of switching cycles in the previous envelope cycle is reduced to determine the number of switching cycles in the current envelope cycle. If the envelope frequency of the previous envelope cycle is higher than the predetermined reference frequency and exceeds the predetermined threshold, the number of switching cycles in the previous envelope cycle is increased to determine the number of switching cycles in the current envelope cycle. as well as If the envelope frequency of the previous envelope cycle is higher than the predetermined reference frequency but does not exceed the predetermined threshold, the number of switching cycles in the previous envelope cycle is kept unchanged to determine the number of switching cycles in the current envelope cycle.

7. The control method according to claim 2 or 3 further includes: Determine the time of the N switching cycles; The output current to be controlled by the asymmetric half-bridge flyback circuit is determined based on the voltage fed back by the feedback module of the asymmetric half-bridge flyback circuit. The positive peak current of the excitation current is determined based on the output current; The negative peak current of the excitation current is determined based on the magnitude of the negative current required to achieve zero-voltage switching of the first switch; as well as The current envelope period required to achieve the output current is determined based on the positive peak current, the negative peak current, and the time of the N switching cycles.

8. The control method according to claim 7, further comprising: The duration of the pause phase is determined based on the time of the current envelope cycle and the duration of the switching phase.

9. A control device for an asymmetric half-bridge flyback circuit, comprising: A control chip is configured to control the asymmetric half-bridge flyback circuit to cycle through the following operations in intermittent operating mode: The asymmetric half-bridge flyback circuit is controlled to enter the switching stage, which includes N switching cycles, N≥1, wherein in the switching cycle, the first switch and the second switch in the switching module of the asymmetric half-bridge flyback circuit are alternately turned on and off. When the excitation current of the transformer module of the asymmetric half-bridge flyback circuit demagnetizes to 0 in the Nth switching cycle of the N switching cycles, the asymmetric half-bridge flyback circuit is controlled to enter the rest phase, wherein the first switch and the second switch are both turned off in the rest phase. as well as After the pause phase lasts for a predetermined time, the next switching phase begins, wherein the second switch is controlled to turn on first until the excitation current is equal to the negative current required to achieve zero-voltage turn-on of the first switch in the critical conduction mode.

10. The control device according to claim 9, wherein, The control chip is also configured to: Determine the previous envelope period in the intermittent working mode, wherein the previous envelope period includes the duration of the previous switching phase and the duration of the previous pause phase; Determine the number of switching cycles within the previous envelope cycle; The average switching frequency in the previous envelope period is determined based on the previous envelope period and the number of switching periods in the previous envelope period. The average switching frequency is compared with a predetermined reference frequency; as well as The number of switching cycles within the current envelope period is determined based on the results of the comparison.

11. The control device according to claim 9, wherein, The control chip is also configured to: Determine the previous envelope period in the intermittent working mode, wherein the previous envelope period includes the duration of the previous switching phase and the duration of the previous pause phase, and determine the envelope frequency of the previous envelope period based on the previous envelope period. The envelope frequency is compared with a predetermined reference frequency; as well as The number of switching cycles within the current envelope period is adjusted based on the results of the comparison.

12. The control device according to claim 10, wherein, The average switching frequency is determined by dividing the number of switching cycles in the previous envelope period by the previous envelope period.

13. The control device according to claim 10, wherein, The comparison determines the ratio of the average switching frequency to the predetermined reference frequency, and the number of switching cycles within the current envelope period is determined based on the ratio.

14. The control device according to claim 11, wherein, If the envelope frequency of the previous envelope cycle is lower than the predetermined reference frequency, the number of switching cycles in the previous envelope cycle is reduced to determine the number of switching cycles in the current envelope cycle. If the envelope frequency of the previous envelope cycle is higher than the predetermined reference frequency and exceeds the predetermined threshold, the number of switching cycles in the previous envelope cycle is increased to determine the number of switching cycles in the current envelope cycle. as well as If the envelope frequency of the previous envelope cycle is higher than the predetermined reference frequency but does not exceed the predetermined threshold, the number of switching cycles in the previous envelope cycle is kept unchanged to determine the number of switching cycles in the current envelope cycle.

15. The control device according to claim 10 or 11, wherein, The control chip is also configured to: Determine the time of the N switching cycles; The output current to be controlled by the asymmetric half-bridge flyback circuit is determined based on the voltage fed back by the feedback module of the asymmetric half-bridge flyback circuit. The positive peak current of the excitation current is determined based on the output current; The negative peak current of the excitation current is determined based on the magnitude of the negative current required to achieve zero-voltage switching of the first switch; as well as The current envelope period required to achieve the output current is determined based on the positive peak current, the negative peak current, and the time of the N switching cycles.

16. The control device according to claim 15, wherein, The control chip is also configured to determine the duration of the pause phase based on the time of the current envelope cycle and the duration of the switching phase.

17. The control device according to claim 9, wherein, The asymmetric half-bridge flyback circuit includes: The switching module, connected to the input voltage and the control device, is configured to receive a control signal from the control device to turn on or off according to the control signal. A resonant module, connected to the switching module, is configured to process the input voltage provided via the switching module; The transformer module is connected to the resonant module and the control device, performs voltage transformation on the input voltage provided by the resonant module, and feeds back the operating status of the transformer module to the control device. A rectifier module, connected to the transformer module, rectifies the voltage and current signals provided by the transformer module; An output module, connected to the rectifier module, provides an output signal based on the rectified voltage and current signals provided by the rectifier module; and The feedback module is connected to the output module and the control device, receives the output signal provided by the output module, and provides a feedback signal based on the output signal to the control device.

Images