Signal generating device capable of suppressing noise

Abstract

The present application relates to a signal generating device capable of suppressing noise. A signal generating device includes: a glitch suppression circuit including n m-stage inverters coupled in series and configured to receive an input signal and perform an inversion operation on the input signal based on a plurality of voltage signals to generate an output signal, and when a glitch occurs in the input signal, adjust a switching threshold voltage of the m-stage inverters based on the plurality of voltage signals to generate a glitch-removed output signal; a level detection circuit configured to detect a logic level of the output signal provided from the glitch suppression circuit to generate a level detection signal and a complementary level detection signal; and a voltage signal generating circuit configured to receive the input signal, a complementary input signal, the level detection signal, and the complementary level detection signal to generate the plurality of voltage signals and provide the plurality of voltage signals to the glitch suppression circuit.

Description

Technical Field

[0001] Various implementations may typically involve integrated circuit technology, and more specifically, signal generating devices capable of suppressing glitch or noise. Background Technology

[0002] Electronic devices can include many electronic components, and computer systems among these electronic components can include many semiconductor devices configured with semiconductor elements. The semiconductor devices constituting a computer system can communicate with each other by sending and receiving clock signals and data. Semiconductor devices can include buffer circuits that amplify and / or buffer input signals to generate output signals. A general-purpose buffer circuit can be a differential amplifier, which differentially amplifies positive and negative input signals to generate an output signal. Glitches can be unwanted impulse noise in digital signals and can cause erroneous outputs or spontaneous errors in digital systems, thus requiring methods for glitch filtering. Summary of the Invention

[0003] In embodiments of this disclosure, a signal generating device may include: a glitch suppression circuit comprising n series-connected m-stage inverters (where n is a natural number and m is an even number greater than or equal to 2), configured to receive an input signal and perform an inversion operation on the input signal based on a plurality of voltage signals to generate an output signal, and when a glitch occurs in the input signal, adjust the switching threshold voltage of the m-stage inverters based on the plurality of voltage signals to generate a glitch-removed output signal; a level detection circuit configured to detect the logic level of the output signal provided from the glitch suppression circuit to generate a level detection signal and a complementary level detection signal; and a voltage signal generating circuit configured to receive an input signal, a complementary input signal, a level detection signal, and a complementary level detection signal to generate a plurality of voltage signals and provide the plurality of voltage signals to the glitch suppression circuit.

[0004] In embodiments of this disclosure, a signal generating device may include: a first inverting circuit configured to invert an input signal based on a first gating voltage signal and a second gating voltage signal to generate a complementary input signal, wherein a switching threshold voltage of the first inverting circuit is adjusted based on a first control voltage signal when a glitch occurs in the input signal; a second inverting circuit configured to invert the complementary input signal received from the first inverting circuit based on a third gating voltage signal and a fourth gating voltage signal to generate an output signal, wherein a switching threshold voltage of the second inverting circuit is adjusted based on a second control voltage signal when a glitch occurs in the complementary input signal; and a level detection circuit, wherein... The circuit is configured to generate clock pulses at the rising and falling edges of the output signal received from the second inverting circuit, detect the logic level of the output signal based on the clock pulses to generate a level detection signal and a complementary level detection signal; and a voltage signal generation circuit configured to generate a first control voltage signal and a second control voltage signal, a first gating voltage signal and a second gating voltage signal, a third gating voltage signal and a fourth gating voltage signal having a first power supply voltage level or a second power supply voltage level based on the level detection signal and the complementary level detection signal received from the level detection circuit, and to provide the generated voltage signals to the first inverting circuit and the second inverting circuit. Attached Figure Description

[0005] The above and other aspects, features and advantages of the subject matter of this disclosure will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0006] Figure 1 This is a diagram illustrating the configuration of a signal generating device according to an embodiment of the present disclosure;

[0007] Figure 2 This is a diagram illustrating the configuration of a glitch suppression circuit according to an embodiment of the present disclosure;

[0008] Figure 3 This is a diagram illustrating the configuration of a level detection circuit according to an embodiment of the present disclosure;

[0009] Figure 4 This is a diagram illustrating the configuration of a clock signal generating circuit according to an embodiment of the present disclosure;

[0010] Figure 5 This is a diagram illustrating the configuration of a voltage signal generating circuit according to an embodiment of the present disclosure;

[0011] Figure 6 The diagram illustrates the operation of reducing glitches / noise in a signal generating apparatus according to an embodiment of the present disclosure; and

[0012] Figure 7This is a timing diagram illustrating the operation of a signal generating device according to an embodiment of the present disclosure. Detailed Implementation

[0013] Various embodiments of this teaching are described in detail with reference to the accompanying drawings. The drawings are exemplary diagrams of various embodiments (and intermediate structures). Therefore, variations in the illustrated configurations and shapes will be expected due to, for example, manufacturing techniques and / or tolerances. Consequently, the described embodiments should not be construed as limited to the specific configurations and shapes shown herein, but may include deviations in configuration and shape without departing from the spirit and scope of this teaching as defined by the appended claims.

[0014] This document describes the teachings with reference to cross-sectional and / or planar diagrams of idealized embodiments thereof. However, the embodiments of the teachings should not be construed as limiting the teachings.

[0015] While some embodiments of this teaching have been shown and described, those skilled in the art will understand that changes may be made to these embodiments without departing from the scope and spirit of this teaching.

[0016] In the following text, embodiments of this technology will be described in detail with reference to the accompanying drawings.

[0017] In the description of this disclosure, the terms "first" and "second" may be used to describe various components, but these components are not limited by these terms. These terms may be used to distinguish one component from another. For example, without departing from the scope of this disclosure, a first component may be referred to as a second component and a second component may be referred to as a first component.

[0018] Figure 1 This is a diagram illustrating the configuration of a signal generating device 100 according to an embodiment of the present disclosure.

[0019] Reference Figure 1 The signal generating device 100 can receive the input signal IN and generate the output signal OUT.

[0020] When a glitch (noise) occurs in the input signal IN, the signal generating device 100 can adjust the pulse width of the glitch (noise) by increasing the switching threshold voltage of the transistors constituting the signal generating device 100 based on the voltage signal generated therein.

[0021] The signal generating device 100 can detect the logic level of the output signal OUT (e.g., logic level conversion) and generate a level detection signal BUF_EN and a complementary signal BUF_ENb (hereinafter referred to as "complementary level detection signal BUF_ENb").

[0022] The signal generating device 100 can generate multiple voltage signals based on the input signal IN, the complementary signal INb of the input signal IN (hereinafter referred to as "complementary input signal INb"), the level detection signal BUF_EN, and the complementary level detection signal BUF_ENb. The multiple voltage signals may include multiple control voltage signals and multiple gating voltage signals.

[0023] For example, the multiple control voltage signals may include an odd control voltage signal VST_OD as a first control voltage signal and an even control voltage signal VST_EV as a second control voltage signal. The multiple gating voltage signals may include multiple odd gating voltage signals VP_OD and VN_OD, and multiple even gating voltage signals VP_EV and VN_EV. The multiple odd gating voltage signals VP_OD and VN_OD may include a first odd gating voltage signal VP_OD and a second odd gating voltage signal VN_OD, while the multiple even gating voltage signals VP_EV and VN_EV may include a first even gating voltage signal VP_EV and a second even gating voltage signal VN_EV.

[0024] The signal generating device 100 can receive an input signal IN and, based on multiple gating voltage signals (e.g., a first odd gating voltage signal VP_OD, a second odd gating voltage signal VN_OD, a first even gating voltage signal VP_EV, and a second even gating voltage signal VN_EV), invert the input signal IN to generate an output signal OUT. At this time, when glitches appear in the input signal IN, the signal generating device 100 can remove the glitches from the input signal IN based on multiple control voltage signals (e.g., an odd control voltage signal VST_OD and an even control voltage signal VST_EV) and generate a glitch-free output signal OUT.

[0025] The signal generating device 100 may include a glitch suppression circuit 110, a level detection circuit 120, and a voltage signal generating circuit 130.

[0026] The glitch suppression circuit 110 can receive the input signal IN, remove glitches from the input signal IN, and generate an output signal OUT. The level detection circuit 120 can receive the output signal OUT, detect the level transition of the output signal OUT, and generate a level detection signal BUF_EN and a complementary level detection signal BUF_ENb. The voltage signal generation circuit 130 can receive the input signal IN provided from outside the signal generation device 100, the complementary input signal INb provided from the glitch suppression circuit 110, and the level detection signal BUF_EN and the complementary level detection signal BUF_ENb provided from the level detection circuit 120, to generate multiple voltage signals VST_OD and VST_EV, VP_OD and VN_OD, and VP_EV and VN_EV, and provide the multiple voltage signals VST_OD and VST_EV, VP_OD and VN_OD, and VP_EV and VN_EV to the glitch suppression circuit 110.

[0027] The glitch suppression circuit 110 can receive the input signal IN and generate the output signal OUT based on the odd control voltage signal VST_OD and the even control voltage signal VST_EV, the first odd gating voltage signal VP_OD and the second odd gating voltage signal VN_OD, the first even gating voltage signal VP_EV and the second even gating voltage signal VN_EV provided by the voltage signal generation circuit 130.

[0028] The glitch suppression circuit 110 can be configured with m-stage inverters (m being an even number greater than or equal to 2). For example, the glitch suppression circuit 110 can be configured with two-stage inverters including a first inverter circuit 111 and a second inverter circuit 112, which will be described later. The two-stage inverters can include two inverters connected in series, corresponding to the first inverter circuit 111 and the second inverter circuit 112, respectively, for example, two Schmitt trigger inverters. Although this embodiment has illustrated the glitch suppression circuit 110 as a single two-stage inverter including two Schmitt trigger inverters connected in series, it is not limited thereto. In another embodiment, the glitch suppression circuit 110 can be configured with n m-stage Schmitt trigger inverters connected in series (where n is a natural number). For example, the glitch suppression circuit 110 can be configured with three two-stage Schmitt trigger inverters connected in series, such as... Figure 6 As shown. In another example, the glitch suppression circuit 110 can be configured by a single m-stage Schmitt trigger inverter (e.g., a 4-stage Schmitt trigger inverter).

[0029] The switching threshold voltages of the two Schmitt trigger inverters constituting the glitch suppression circuit 110 can be controlled based on control voltage signals VST_OD and VST_EV. For example, in the two-stage inverter, the switching threshold voltage of the first-stage Schmitt trigger inverter can be increased based on the odd control voltage signal VST_OD, and the switching threshold voltage of the second-stage Schmitt trigger inverter can be increased based on the even control voltage signal VST_EV.

[0030] According to the embodiment, the signal generating device 100 can respond to glitches occurring in the logic low-level input signal IN, for example, low-high-low short pulse glitch (see...). Figure 6 In case 2), the switching threshold voltages of the two Schmitt trigger inverters in the two-stage inverter of the glitch suppression circuit 110 are controlled based on the odd control voltage signal VST_OD (level of the first power supply voltage VDD applied to the first stage Schmitt trigger inverter of the two-stage inverter) and the even control voltage signal VST_EV (level of the second power supply voltage VSS applied to the second stage Schmitt trigger inverter of the two-stage inverter). In the following, the operation of inverting the input signal, which is a logic low (0) level (first logic level), to generate an output signal based on the gating voltage signals VP_OD, VP_EV, VN_OD, and VN_EV, and suppressing the glitch that occurs in the logic low level input signal from a logic low level to a logic high (1) level (second logic level) based on the odd control voltage signal VST_OD and the even control voltage signal VST_EV, can be referred to as the first operating mode in this embodiment.

[0031] Furthermore, the signal generating device 100 according to the embodiment can respond to glitches occurring in the logic high-level input signal IN, for example, high-low-high short pulse glitch (see [link]). Figure 6 In case 1), the switching threshold voltages of the two Schmitt trigger inverters in the two-stage inverter are controlled based on the odd control voltage signal VST_OD (level of the second power supply voltage VSS applied to the first Schmitt trigger inverter of the two-stage inverter) and the even control voltage signal VST_EV (level of the first power supply voltage VDD applied to the second Schmitt trigger inverter of the two-stage inverter). In the following, the operation of inverting the logic high (1) level input signal to generate the output signal OUT based on the gating voltage signals VP_OD, VP_EV, VN_OD, and VN_EV, and suppressing the glitches from logic high to logic low level in the logic high level input signal IN based on the odd control voltage signal VST_OD and the even control voltage signal VST_EV, can be referred to as the second operating mode in this embodiment.

[0032] In the first operating mode, the upper trigger point (UTP) of the first stage Schmitt trigger inverter of the two-stage inverter can be controlled based on the odd control voltage signal VST_OD at the first power supply voltage VDD level, and the lower trigger point (LTP) of the second stage Schmitt trigger inverter of the two-stage inverter can be controlled based on the even control voltage signal VST_EV at the second power supply voltage VSS level.

[0033] In the second operating mode, the lower trigger point (LTP) of the first stage Schmitt trigger inverter of the two-stage inverter can be controlled based on the odd control voltage signal VST_OD at the second power supply voltage VSS level, and the upper trigger point (UTP) of the second stage Schmitt trigger inverter of the two-stage inverter can be controlled based on the even control voltage signal VST_EV at the first power supply voltage VDD level.

[0034] Therefore, in both the first and second operating modes, based on the odd control voltage signal VST_OD and the even control voltage signal VST_EV generated from the level detection signal BUF_EN and the complementary level detection signal BUF_ENb, the signal generating device 100 can control the switching threshold voltages of the first-stage Schmitt trigger inverter and the second-stage Schmitt trigger inverter to increase, thereby adjusting the pulse width of the glitch. For example, the signal generating device 100 can control the pulse width of the glitch to gradually decrease, thereby generating a glitch removal output signal OUT, such as... Figure 6 As shown.

[0035] The level detection circuit 120 can receive the output signal OUT from the glitch suppression circuit 110 and generate the level detection signal BUF_EN and the complementary level detection signal BUF_ENb.

[0036] The level detection circuit 120 can receive the output signal OUT from the glitch suppression circuit 110 and detect the level of the output signal OUT. For example, the level detection circuit 120 can detect the level transition of the output signal OUT based on the glitch of the input signal IN. The level detection circuit 120 can generate a level detection signal BUF_EN and a complementary level detection signal BUF_ENb based on the level transition detection result, and provide the generated level detection signal BUF_EN and the complementary level detection signal BUF_ENb to the voltage signal generation circuit 130.

[0037] The voltage signal generation circuit 130 can receive the input signal IN and the complementary input signal INb, as well as the level detection signal BUF_EN and the complementary level detection signal BUF_ENb generated in the level detection circuit 120 based on the level conversion detection result of the output signal. The voltage signal generation circuit 130 can generate multiple voltage signals, such as the odd control voltage signal VST_OD and the even control voltage signal VST_EV, the first odd gating voltage signal VP_OD and the second odd gating voltage signal VN_OD, and the first even gating voltage signal VP_EV and the second even gating voltage signal VN_EV, and provide the multiple voltage signals to the glitch suppression circuit 110.

[0038] In the first operating mode, the voltage signal generation circuit 130 can provide an odd control voltage signal VST_OD at the level of the first power supply voltage VDD and an even control voltage signal VST_EV at the level of the second power supply voltage VSS, based on the level detection signal BUF_EN and the complementary level detection signal BUF_ENb provided from the level detection circuit 120. For example, the voltage signal generation circuit 130 can provide the odd control voltage signal VST_OD to the first stage inverter (e.g., an odd-numbered inverter of each of n m-stage inverters) in the glitch suppression circuit 110, and provide the even control voltage signal VST_EV to the second stage inverter (e.g., an even-numbered inverter of each of n m-stage inverters) in the glitch suppression circuit 110. Therefore, based on the logic low level level detection signal BUF_EN, the voltage signal generation circuit 130 can provide a first power supply voltage VDD level signal as an odd control voltage signal VST_OD to the odd-numbered inverters in the first operating mode, and provide a second power supply voltage VSS level signal as an even control voltage signal VST_EV to the even-numbered inverters.

[0039] In the second operating mode, the voltage signal generation circuit 130 can provide an odd control voltage signal VST_OD at the level of the second power supply voltage VSS and an even control voltage signal VST_EV at the level of the first power supply voltage VDD, based on the level detection signal BUF_EN and the complementary level detection signal BUF_ENb provided from the level detection circuit 120. For example, the voltage signal generation circuit 130 can provide the odd control voltage signal VST_OD to the first stage inverter (e.g., an odd-numbered inverter of each of n m-stage inverters) in the glitch suppression circuit 110, and provide the even control voltage signal VST_EV to the second stage inverter (e.g., an even-numbered inverter of each of n m-stage inverters) in the glitch suppression circuit 110. Therefore, based on the logic high-level level detection signal BUF_EN, the voltage signal generation circuit 130 can provide a second power supply voltage VSS level signal as an odd control voltage signal VST_OD to the odd-numbered inverters in the second operating mode, and provide a first power supply voltage VDD level signal as an even control voltage signal VST_EV to the even-numbered inverters.

[0040] Figure 2 This is a diagram illustrating the configuration of a glitch suppression circuit 110 according to an embodiment of the present disclosure.

[0041] Reference Figure 2 The glitch suppression circuit 110 can receive the input signal IN, the odd control voltage signal VST_OD and the even control voltage signal VST_EV, the first odd gating voltage signal VP_OD and the first even gating voltage signal VP_EV, the second odd gating voltage signal VN_OD and the second even gating voltage signal VN_EV, and generate the output signal OUT based on the multiple voltage signals.

[0042] The odd control voltage signal VST_OD and the even control voltage signal VST_EV, the first odd gating voltage signal VP_OD and the first even gating voltage signal VP_EV, and the second odd gating voltage signal VN_OD and the second even gating voltage signal VN_EV can be operation control signals for internal circuit operations such as output signal generation operation and glitch suppression operation in the glitch suppression circuit 110.

[0043] The glitch suppression circuit 110 may include a first inverting circuit 111 and a second inverting circuit 112. The first inverting circuit 111 may be a first-stage inverter configured with Schmitt trigger inverters, for example, an odd-numbered inverter; while the second inverting circuit 112 may be a second-stage inverter configured with Schmitt trigger inverters, for example, an even-numbered inverter. In some embodiments, the first inverting circuit 111 may be an odd-numbered inverting circuit, and the second inverting circuit 112 may be an even-numbered inverting circuit.

[0044] For example, the glitch suppression circuit 110 may include: a first inverting circuit 111 configured to receive an input signal IN and invert the input signal IN to generate a complementary input signal INb; and a second inverting circuit 112 configured to receive the complementary input signal INb from the first inverting circuit 111 and invert the complementary input signal INb to generate an output signal OUT.

[0045] When a glitch occurs in the input signal IN, the first inverter circuit 111 and the second inverter circuit 112 can increase the switching threshold voltage of the transistors included therein based on the odd control voltage signal VST_OD and the even control voltage signal VST_EV to control and reduce the pulse width of the glitch.

[0046] The first inverting circuit 111 can receive an odd control voltage signal VST_OD, a first odd gating voltage signal VP_OD, and a second odd gating voltage signal VN_OD from the voltage signal generating circuit 130, which have a first power supply voltage VDD level or a second power supply voltage VSS level. The first inverting circuit 111 can invert the input signal IN based on the first odd gating voltage signal VP_OD and the second odd gating voltage signal VN_OD to generate a complementary input signal INb, and control the switching threshold voltage of the transistor contained therein based on the odd control voltage signal VST_OD.

[0047] For example, in the first operating mode where a glitch occurs in the input signal IN that transitions from a logic low level to a logic high level, the switching threshold voltages of the NMOS transistors N1 and N2 of the first inverter circuit 111 can be increased by applying an odd control voltage signal VST_OD at the level of the first power supply voltage VDD of the first inverter circuit 111. This can increase the level transition time of the glitch in the input signal IN, and thus reduce the pulse width of the glitch in the input signal IN.

[0048] Furthermore, in the second operating mode where a glitch occurs in the input signal IN at a logic high level, transitioning from logic high to logic low, the switching threshold voltages of the PMOS transistors P1 and P2 of the first inverter circuit 111 can be increased by applying an odd control voltage signal VST_OD at the second power supply voltage VSS level of the first inverter circuit 111. This can increase the level transition time of the glitch in the input signal IN, thereby reducing the pulse width of the glitch in the input signal IN.

[0049] The first inverting circuit 111 may include a first inverter 111-1 and a first adjuster 111-2. In an embodiment, the first inverter 111-1 may be an odd-numbered inverter, and the first adjuster 111-2 may be an odd-numbered adjuster.

[0050] For example, the first inverter circuit 111 may include: a first inverter 111-1 configured to receive an input signal IN, invert the input signal IN based on a first odd gating voltage signal VP_OD and a second odd gating voltage signal VN_OD, and generate a complementary input signal INb; and a first regulator 111-2 configured to adjust the switching threshold voltage of the first inverter 111-1 based on an odd control voltage signal VST_OD.

[0051] The first inverter 111-1 may include a first PMOS transistor P1 and a second PMOS transistor P2 connected in series between the first power supply voltage VDD terminal and the complementary input signal INb terminal, and a first NMOS transistor N1 and a second NMOS transistor N2 connected in series between the complementary input signal INb terminal and the second power supply voltage VSS terminal. The first regulator 111-2 may include a third PMOS transistor P3 and a third NMOS transistor N3.

[0052] For example, the first inverter 111-1 may include a first PMOS transistor P1 and a second PMOS transistor P2, configured in a first operating mode to invert a logic-low input signal IN based on a first odd-gated voltage signal VP_OD, thereby generating a logic-high complementary input signal INb. The first inverter 111-1 may also include a first NMOS transistor N1 and a second NMOS transistor N2, configured in a second operating mode to invert a logic-high input signal IN based on a second odd-gated voltage signal VN_OD, thereby generating a logic-low complementary input signal INb.

[0053] Furthermore, the first regulator 111-2 may include a third PMOS transistor P3, configured to adjust the switching threshold voltages of the first PMOS transistor P1 and the second PMOS transistor P2 based on the odd control voltage signal VST_OD provided from the voltage signal generation circuit 130 via the first node node1 in a second operating mode where a glitch (e.g., a high-low-high short pulse glitch) transitions from a logic high level to a logic low level in the input signal IN. The first regulator 111-2 may also include a third NMOS transistor N3, configured to adjust the switching threshold voltages of the first NMOS transistor N1 and the second NMOS transistor N2 based on the odd control voltage signal VST_OD provided from the voltage signal generation circuit 130 via the first node node1 in a first operating mode where a glitch (e.g., a low-high-low short pulse glitch) transitions from a logic low level to a logic high level in the input signal IN.

[0054] When a short high-low-high pulse glitch appears in the logic high-level input signal IN, an odd control voltage signal VST_OD at the second power supply voltage VSS level can be applied to the third PMOS transistor P3 of the first regulator 111-2 through the first node1. This increases the switching threshold voltages of the first PMOS transistor P1 and the second PMOS transistor P2 of the first inverter 111-1, and also increases the level transition time of the glitch. Furthermore, when a short low-high-low pulse glitch appears in the logic low-level input signal IN, an odd control voltage signal VST_OD at the first power supply voltage VDD level can be applied to the third NMOS transistor N3 of the first regulator 111-2 through the first node1. This increases the switching threshold voltages of the first NMOS transistor N1 and the second NMOS transistor N2 of the first inverter 111-1, and also increases the level transition time of the glitch.

[0055] In the first inverter 111-1, a first power supply voltage VDD can be applied to the source of the first PMOS transistor P1, and a first odd-gated voltage signal VP_OD can be applied to the gate of the first PMOS transistor P1. An input signal IN can be applied to the gate of the second PMOS transistor P2, and the source of the second PMOS transistor P2 can be connected to the drain of the first PMOS transistor P1.

[0056] Furthermore, the second power supply voltage VSS can be applied to the source of the first NMOS transistor N1, and the second odd-gated voltage signal VN_OD can be applied to the gate of the first NMOS transistor N1. The input signal IN can be applied to the gate of the second NMOS transistor N2, the source of the second NMOS transistor N2 can be connected to the drain of the first NMOS transistor N1, and the drain of the second NMOS transistor N2 can be connected to the drain of the second PMOS transistor P2.

[0057] In the first regulator 111-2, the third PMOS transistor P3 can be connected between the connection node of the first PMOS transistor P1 and the second PMOS transistor P2 and the first node node1, and the gate of the third PMOS transistor P3 can be connected to the connection node of the second PMOS transistor P2 and the second NMOS transistor N2, which serves as the complementary input signal INb terminal.

[0058] Furthermore, the third NMOS transistor N3 can be connected between the connection node of the first NMOS transistor N1 and the second NMOS transistor N2 and the first node node1, and the gate of the third NMOS transistor N3 can be connected to the connection node of the second PMOS transistor P2 and the second NMOS transistor N2, which serve as the complementary input signal INb terminal.

[0059] In the first operating mode, the first inverter circuit 111 can receive a logic low-level input signal IN. The first PMOS transistor P1 and the second PMOS transistor P2, connected in series and with their gates applied at the second power supply voltage VSS level, can be enabled. The first NMOS transistor N1 and the second NMOS transistor N2, connected in series and with their gates applied at the second power supply voltage VSS level, can be disabled. Therefore, the first inverter circuit 111 can generate a logic high-level complementary input signal INb. At this time, the third NMOS transistor N3, with its gate applied at the first power supply voltage VDD level, can be enabled, while the third PMOS transistor P3, with its gate applied at the first power supply voltage VDD level, can be disabled.

[0060] When a glitch (e.g., a short low-high-low pulse glitch) occurs in the input signal IN, transitioning from a logic low to a logic high level, the first NMOS transistor N1 and the second NMOS transistor N2 can be enabled. Therefore, the switching threshold voltages of the first NMOS transistor N1 and the second NMOS transistor N2 can be increased based on the odd control voltage signal VST_OD, which is supplied to the third NMOS transistor N3 via the first node1, and the pulse width of the glitch in the input signal IN can be reduced by increasing the transition time of the glitch from a logic low to a logic high level in the input signal IN.

[0061] Furthermore, in the second operating mode, the first inverter circuit 111 can receive a logic high-level input signal IN. The first NMOS transistor N1 and the second NMOS transistor N2, connected in series and with their gates applied at the first power supply voltage VDD level, and the second odd-gated voltage signal VN_OD, and the input signal IN, can be enabled. The first PMOS transistor P1 and the second PMOS transistor P2, connected in series and with their gates applied at the first power supply voltage VDD level, and the input signal IN, can be disabled. Therefore, the first inverter circuit 111 can generate a logic low-level complementary input signal INb. At this time, the third NMOS transistor N3, with the odd control voltage signal VST_OD applied at the second power supply voltage VSS level through the first node 1, can be disabled, while the third PMOS transistor P3, with the odd control voltage signal VST_OD applied at the second power supply voltage VSS level through the first node 1, can be enabled.

[0062] When a glitch (e.g., a short high-low-high pulse glitch) occurs in the input signal IN, transitioning from a logic high to a logic low level, the first PMOS transistor P1 and the second PMOS transistor P2 can be enabled. Therefore, by increasing the switching threshold voltages of the first PMOS transistor P1 and the second PMOS transistor P2 based on the odd control voltage signal VST_OD, which is supplied to the third PMOS transistor P3 via the second power supply voltage VSS level through the first node 1, the transition time of the glitch in the input signal IN from a logic high to a logic low level can be increased earlier, thereby reducing the pulse width of the glitch in the input signal IN.

[0063] The second inverter circuit 112 can receive an even control voltage signal VST_EV, a first even gating voltage signal VP_EV, and a second even gating voltage signal VN_EV from the voltage signal generation circuit 130, which have a first power supply voltage VDD level or a second power supply voltage VSS level. The second inverter circuit 112 can invert the complementary input signal INb into an input signal based on the first even gating voltage signal VP_EV and the second even gating voltage signal VN_EV to generate an output signal OUT, and control the switching threshold voltage of the transistors included therein based on the even control voltage signal VST_EV.

[0064] For example, when a glitch occurs in the complementary input signal INb, which is a logic high level received from the first inverter circuit 111, transitioning from a logic high level to a logic low level, the switching threshold voltages of the PMOS transistors P4 and P5 of the second inverter circuit 112 can be increased by applying an even control voltage signal VST_EV at the second power supply voltage VSS level to the second inverter circuit 112. This can increase the level transition time of the glitch in the complementary input signal INb and thus reduce the pulse width of the glitch in the complementary input signal INb.

[0065] Furthermore, when a glitch occurs in the complementary input signal INb, which is at a logic low level and transitions from logic low to logic high, received from the first inverter circuit 111, the switching threshold voltages of the NMOS transistors N4 and NMOS transistor N5 in the second inverter circuit 112 can be additionally increased by the even control voltage signal VST_EV applied to the first power supply voltage VDD level of the second inverter circuit 112. This can increase the level transition time of the glitch in the complementary input signal INb and thus reduce the pulse width of the glitch in the complementary input signal INb.

[0066] The second inverter circuit 112 may include a second inverter 112-1 and a second adjuster 112-2. In an embodiment, the second inverter 112-1 may be an even-numbered inverter and the second adjuster 112-2 may be an even-numbered adjuster.

[0067] For example, the second inverter circuit 112 may include: a second inverter 112-1 configured to receive a complementary input signal INb from the first inverter circuit 111, invert the complementary input signal INb based on a first even gate voltage signal VP_EV and a second even gate voltage signal VN_EV, and generate an output signal OUT; and a second regulator 112-2 configured to adjust the switching threshold voltage of the second inverter 112-1 based on an even control voltage signal VST_EV.

[0068] The second inverter 112-1 may include a fourth PMOS transistor P4 and a fifth PMOS transistor P5 connected in series between the first power supply voltage VDD terminal and the output signal OUT terminal, and a fourth NMOS transistor N4 and a fifth NMOS transistor N5 connected in series between the output signal OUT terminal and the second power supply voltage VSS terminal. The second regulator 112-2 may include a sixth PMOS transistor P6 and a sixth NMOS transistor N6.

[0069] For example, the second inverter 112-1 may include a fourth PMOS transistor P4 and a fifth PMOS transistor P5, configured to invert the complementary input signal INb based on a first even-select voltage signal VP_EV when the complementary input signal INb is at a logic low level, thereby generating a logic high output signal OUT. The second inverter 112-1 may also include a fourth NMOS transistor N4 and a fifth NMOS transistor N5, configured to invert the complementary input signal INb based on a second even-select voltage signal VN_EV when the complementary input signal INb is at a logic high level, thereby generating a logic low output signal OUT.

[0070] Furthermore, the second regulator 112-2 may include a sixth PMOS transistor P6, configured to adjust the switching threshold voltages of the fourth PMOS transistor P4 and the fifth PMOS transistor P5 based on the even control voltage signal VST_EV provided from the voltage signal generation circuit 130 via the second node node2 when a glitch transitioning from a logic high level to a logic low level occurs in the complementary input signal INb at a logic high level, for example, when a high-low-high short pulse glitch occurs in the complementary input signal INb at a logic high level. The second regulator 112-2 may also include a sixth NMOS transistor N6, configured to adjust the switching threshold voltages of the fourth NMOS transistor N4 and the fifth NMOS transistor N5 based on the even control voltage signal VST_EV provided from the voltage signal generation circuit 130 via the second node node2 when a glitch transitioning from a logic low level to a logic high level occurs in the complementary input signal INb at a logic low level, for example, when a low-high-low short pulse glitch occurs in the complementary input signal INb at a logic low level.

[0071] When a high-low-high short pulse glitch appears in the complementary input signal INb at a logic high level, the switching threshold voltages of the fourth PMOS transistor P4 and the fifth PMOS transistor P5 of the second inverter 112-1 can be increased based on the even control voltage signal VST_EV, which is the second power supply voltage VSS level applied to the sixth PMOS transistor P6 of the second regulator 112-2 through the second node2, and thus the level transition time of the glitch can be increased. Furthermore, when a low-high-low short pulse glitch appears in the complementary input signal INb at a logic low level, the switching threshold voltages of the fourth NMOS transistor N4 and the fifth NMOS transistor N5 of the second inverter 112-1 can be increased based on the even control voltage signal VST_EV, which is the first power supply voltage VDD level applied to the sixth NMOS transistor N6 of the second regulator 112-2 through the second node2, and the level transition time of the glitch can also be increased.

[0072] In the second inverter 112-1, the first power supply voltage VDD can be applied to the source of the fourth PMOS transistor P4, and the first even-select voltage signal VP_EV can be applied to the gate of the fourth PMOS transistor P4. The complementary input signal INb can be applied to the gate of the fifth PMOS transistor P5, and the source of the fifth PMOS transistor P5 can be connected to the drain of the fourth PMOS transistor P4.

[0073] Furthermore, the second power supply voltage VSS can be applied to the source of the fourth NMOS transistor N4, and the second even-select voltage signal VN_EV can be applied to the gate of the fourth NMOS transistor N4. The complementary input signal INb can be applied to the gate of the fifth NMOS transistor N5, the source of the fifth NMOS transistor N5 can be connected to the drain of the fourth NMOS transistor N4, and the drain of the fifth NMOS transistor N5 can be connected to the drain of the fifth PMOS transistor P5.

[0074] In the second regulator 112-2, the sixth PMOS transistor P6 can be connected between the connection node of the fourth PMOS transistor P4 and the fifth PMOS transistor P5 and the second node node2, and the gate of the sixth PMOS transistor P6 can be connected to the connection node of the fifth PMOS transistor P5 and the fifth NMOS transistor N5, which serves as the output signal OUT terminal.

[0075] Furthermore, the sixth NMOS transistor N6 can be connected between the connection node of the fourth NMOS transistor N4 and the fifth NMOS transistor N5 and the second node node2, and the gate of the sixth NMOS transistor N6 can be connected to the connection node of the fifth PMOS transistor P5 and the fifth NMOS transistor N5, which serve as the output signal OUT terminal.

[0076] In the first operating mode, the second inverter circuit 112 can receive a logic high-level complementary input signal INb. The fourth NMOS transistor N4 and the fifth NMOS transistor N5, connected in series and with their gates applied to a first power supply voltage VDD level, and the complementary input signal INb, can be enabled. The fourth PMOS transistor P4 and the fifth PMOS transistor P5, connected in series and with their gates applied to a first power supply voltage VDD level, and the complementary input signal INb, can be disabled. Therefore, the second inverter circuit 112 can generate a logic low-level output signal OUT. At this time, the sixth PMOS transistor P6, with a second power supply voltage VSS level even control voltage signal VST_EV applied through the second node 2, can be enabled, while the sixth NMOS transistor N6, with a second power supply voltage VSS level even control voltage signal VST_EV applied through the second node 2, can be disabled.

[0077] When a glitch occurs in the complementary input signal INb, transitioning from logic high to logic low, the fourth PMOS transistor P4 and the fifth PMOS transistor P5 can be enabled. Therefore, by increasing the switching threshold voltages of the fourth PMOS transistor P4 and the fifth PMOS transistor P5 based on the even control voltage signal VST_EV (the second power supply voltage VSS level provided to the sixth PMOS transistor P6 via the second node 2), the transition time of the glitch in the complementary input signal INb from logic high to logic low can be increased earlier, and this can reduce the pulse width of the glitch in the complementary input signal INb.

[0078] Furthermore, in the second operating mode, the second inverter circuit 112 can receive a logic low complementary input signal INb. The fourth PMOS transistor P4 and the fifth PMOS transistor P5, connected in series and with their gates applied to a first even-gated voltage signal VP_EV at the second power supply voltage VSS level and the complementary input signal INb, can be enabled. The fourth NMOS transistor N4 and the fifth NMOS transistor N5, connected in series and with their gates applied to a second even-gated voltage signal VN_EV at the second power supply voltage VSS level and the complementary input signal INb, can be disabled. Therefore, the second inverter circuit 112 can generate a logic high output signal OUT. At this time, the sixth NMOS transistor N6, with an even control voltage signal VST_EV applied to a first power supply voltage VDD level through the second node 2, can be enabled, while the sixth PMOS transistor P6, with an even control voltage signal VST_EV applied to a first power supply voltage VDD level through the second node 2, can be disabled.

[0079] When a glitch occurs in the complementary input signal INb, transitioning from logic low to logic high, the fourth NMOS transistor N4 and the fifth NMOS transistor N5 can be enabled. Therefore, the switching threshold voltages of the fourth NMOS transistor N4 and the fifth NMOS transistor N5 can be increased based on the even control voltage signal VST_EV, which is supplied to the sixth NMOS transistor N6 via the first power supply voltage VDD level through the second node 2. Furthermore, the pulse width of the glitch in the complementary input signal INb can be reduced by increasing the transition time from logic low to logic high in the complementary input signal INb.

[0080] Figure 3 This is a diagram illustrating the configuration of a level detection circuit 120 according to an embodiment of the present disclosure.

[0081] Reference Figure 3The level detection circuit 120 can receive the output signal OUT, detect the level transition of the output signal OUT, and generate the level detection signal BUF_EN and the complementary level detection signal BUF_ENb.

[0082] The level detection circuit 120 may include a delay buffer 120-1, a clock signal generator 120-2, and a level detection signal generator 120-3.

[0083] Delay buffer 120-1 can receive the output signal OUT, delay the output signal OUT, and generate the delayed output signal OUT_D. Delay buffer 120-1 can be configured to prevent or mitigate setup violations of level detection signal generator 120-3 when level detection circuit 120 receives output signal OUT to generate clock signal CLK.

[0084] Clock signal generator 120-2 can generate a clock signal CLK based on the delayed output signal OUT_D. Clock signal generator 120-2 can receive the delayed output signal OUT_D to generate the clock signal CLK and provide the generated clock signal CLK to level detection signal generator 120-3. See below for further details. Figure 4 A detailed description of the clock signal generator 120-2 is provided.

[0085] The level detection signal generator 120-3 can generate the level detection signal BUF_EN and the complementary level detection signal BUF_ENb based on the clock signal CLK.

[0086] The level detection signal generator 120-3 may include a flip-flop, such as a D flip-flop. The D flip-flop can receive the output signal OUT from the glitch suppression circuit 110 through the input terminal D, receive the clock signal CLK from the clock signal generator 120-2 through the clock terminal, and output the level detection signal BUF_EN and the complementary level detection signal BUF_ENb through the output terminals Q and / Q.

[0087] Based on the clock signal CLK, the level detection signal generator 120-3 can generate a logic low level level detection signal BUF_EN and a logic high level complementary level detection signal BUF_ENb when the output signal OUT is logic low, and generate a logic high level level detection signal BUF_EN and a logic low level complementary level detection signal BUF_ENb when the output signal OUT is logic high.

[0088] When the chip enable signal CE is input to the reset terminal RST of the D flip-flop, the D flip-flop can be reset.

[0089] Figure 4This is a diagram illustrating the configuration of a clock signal generator 120-2 according to an embodiment of the present disclosure.

[0090] Reference Figure 4 The clock signal generator 120-2 can receive the delayed output signal OUT_D from the delay buffer 120-1 and generate the clock signal CLK.

[0091] The clock signal generator 120-2 can generate pulses as clock signal CLK at the rising and falling edges of the output signal OUT (e.g., the delayed output signal OUT_D).

[0092] Clock signal generator 120-2 may include a first inverter 121, a second inverter 122, and an XOR gate 123. The first inverter 121 and the second inverter 122 can delay the first delayed output signal OUT_D from the delay buffer 120-1 to generate a second delayed output signal. XOR gate 123 can receive the first delayed output signal OUT_D from the delay buffer 120-1 and the second delayed output signal from the second inverter 122, perform an XOR operation on the first delayed output signal OUT_D and the second delayed output signal, and generate the XORed output as the clock signal CLK. Therefore, clock signal generator 120-2 can generate pulses at the rising and falling edges of the first delayed output signal OUT_D, respectively, as the clock signal. The clock signal CLK can be provided to the clock terminal of the D flip-flop in the level detection signal generator 120-3.

[0093] Figure 5 This is a diagram illustrating the configuration of a voltage signal generating circuit 130 according to an embodiment of the present disclosure.

[0094] Reference Figure 5 The voltage signal generation circuit 130 can receive the input signal IN, the complementary input signal INb, and the level detection signal BUF_EN and the complementary level detection signal BUF_ENb provided from the level detection circuit 120, generate multiple voltage signals, and provide the multiple voltage signals to the glitch suppression circuit 110. The multiple voltage signals may include an odd control voltage signal VST_OD, an even control voltage signal VST_EV, a first odd gating voltage signal VP_OD, a second odd gating voltage signal VN_OD, a first even gating voltage signal VP_EV, and a second even gating voltage signal VN_EV.

[0095] The voltage signal generation circuit 130 can generate an odd control voltage signal VST_OD and an even control voltage signal VST_EV based on the logic levels of the level detection signal BUF_EN and the complementary level detection signal BUF_ENb. Furthermore, the voltage signal generation circuit 130 can generate a first odd-gated voltage signal VP_OD and a second odd-gated voltage signal VN_OD based on the logic levels of the input signal IN, the level detection signal BUF_EN, and the complementary level detection signal BUF_ENb. The voltage signal generation circuit 130 can also generate a first even-gated voltage signal VP_EV and a second even-gated voltage signal VN_EV based on the logic levels of the complementary input signal INb, the level detection signal BUF_EN, and the complementary level detection signal BUF_ENb.

[0096] In the implementation, when the glitch suppression circuit 110 is composed of, for example Figure 2 In the single two-stage inverter configuration shown, the voltage signal generation circuit 130 can provide an odd control voltage signal VST_OD, a first odd gating voltage signal VP_OD, and a second odd gating voltage signal VN_OD, having one of the levels of a first power supply voltage VDD and a second power supply voltage VSS, to the first inverter circuit 111, which is the first stage inverter of the two-stage inverter. Furthermore, the voltage signal generation circuit 130 can provide an even control voltage signal VST_EV, a first even gating voltage signal VP_EV, and a second even gating voltage signal VN_EV, having one of the levels of a first power supply voltage VDD and a second power supply voltage VSS, to the second inverter circuit 112, which is the second stage inverter of the two-stage inverter.

[0097] In another embodiment, when the glitch suppression circuit 110 consists of multiple two-stage inverters (e.g., Figure 6 When the three two-stage inverters (unit1, unit2, and unit3) shown are configured, the voltage signal generation circuit 130 can provide an odd control voltage signal VST_OD, a first odd gating voltage signal VP_OD, and a second odd gating voltage signal VN_OD, each having a level of either the first power supply voltage VDD or the second power supply voltage VSS, to the first-stage inverter 110-1 in each of the three two-stage inverters (unit1, unit2, and unit3). The voltage signal generation circuit 130 can also provide an even control voltage signal VST_EV, a first even gating voltage signal VP_EV, and a second even gating voltage signal VN_EV, each having a level of either the first power supply voltage VDD or the second power supply voltage VSS, to the second-stage inverter 110-2 in each of the three two-stage inverters (unit1, unit2, and unit3).

[0098] In another embodiment, when the glitch suppression circuit 110 is configured with n m-stage inverters, the voltage signal generation circuit 130 can provide an odd-numbered inverter of each m-stage inverter with an odd control voltage signal VST_OD, a first odd gating voltage signal VP_OD, and a second odd gating voltage signal VN_OD, each having a level of either a first power supply voltage VDD or a second power supply voltage VSS. The voltage signal generation circuit 130 can also provide an even-numbered inverter of each m-stage inverter with an even control voltage signal VST_EV, a first even gating voltage signal VP_EV, and a second even gating voltage signal VN_EV, each having a level of either a first power supply voltage VDD or a second power supply voltage VSS.

[0099] The voltage signal generating circuit 130 can generate multiple voltage signals as shown in Table 1 below.

[0100] [Table 1]

[0101] VST_OD VSS VDD VST_EV VDD VSS VP_OD VDD VSS VP_EV VSS VDD VN_OD VDD VSS VN_EV VSS VDD

[0102] The voltage signal generation circuit 130 may include multiple voltage signal generators configured to receive an input signal IN and a complementary input signal INb, as well as a level detection signal BUF_EN and a complementary level detection signal BUF_ENb, to generate multiple voltage signals. For example, the voltage signal generation circuit 130 may include: a first voltage signal generator configured to generate a signal of a second power supply voltage VSS level or a first power supply voltage VDD level based on the level detection signal BUF_EN and the complementary level detection signal BUF_ENb, as an odd control voltage signal VST_OD; and a second voltage signal generator configured to generate a signal of a first power supply voltage VDD level or a second power supply voltage VSS level based on the level detection signal BUF_EN and the complementary level detection signal BUF_ENb, as an even control voltage signal VST_EV.

[0103] Furthermore, the voltage signal generation circuit 130 may include: a third voltage signal generator configured to generate a signal at the input signal IN level or the second power supply voltage VSS level based on the level detection signal BUF_EN and the complementary level detection signal BUF_ENb, as a first odd-gated voltage signal VP_OD; and a fourth voltage signal generator configured to generate a signal at the second power supply voltage VSS level or the complementary input signal INb level based on the level detection signal BUF_EN and the complementary level detection signal BUF_ENb, as a first even-gated voltage signal VP_EV. Additionally, the voltage signal generation circuit 130 may include: a fifth voltage signal generator configured to generate a signal at the first power supply voltage VDD level or the input signal IN level based on the level detection signal BUF_EN and the complementary level detection signal BUF_ENb, as a second odd-gated voltage signal VN_OD; and a sixth voltage signal generator configured to generate a signal at the complementary input signal INb level or the first power supply voltage VDD level based on the level detection signal BUF_EN and the complementary level detection signal BUF_ENb, as a second even-gated voltage signal VN_EV.

[0104] The voltage signal generation circuit 130 may include a first multiplexer 131 to a sixth multiplexer 136 as a first voltage signal generator to a sixth voltage signal generator. Referring below... Figure 5 The first multiplexer 131 to the sixth multiplexer 136, which constitute the first voltage signal generator to the sixth voltage signal generator, are described in detail in Table 1.

[0105] The first voltage signal generator may include a first multiplexer 131 configured to generate an odd control voltage signal VST_OD of either a second power supply voltage VSS level or a first power supply voltage VDD level based on the logic levels of a level detection signal BUF_EN (which serves as a selection signal) and a complementary level detection signal BUF_ENb. For example, the first multiplexer 131 may be configured to select and output the odd control voltage signal VST_OD of the second power supply voltage VSS level when the level detection signal BUF_EN has a logic high (1) level (which serves as a second logic level), and to select and output the odd control voltage signal VST_OD of the first power supply voltage VDD level when the level detection signal BUF_EN has a logic low (0) level (which serves as a first logic level).

[0106] The second voltage signal generator may include a second multiplexer 132 configured to generate an even control voltage signal VST_EV at either a first power supply voltage VDD level or a second power supply voltage VSS level based on the logic levels of the level detection signal BUF_EN and the complementary level detection signal BUF_ENb, which serve as selection signals. For example, the second multiplexer 132 may be configured to select and output the even control voltage signal VST_EV at the first power supply voltage VDD level when the level detection signal BUF_EN has a logic high (1) level, and to select and output the even control voltage signal VST_EV at the second power supply voltage VSS level when the level detection signal BUF_EN has a logic low (0) level.

[0107] The third voltage signal generator may include a third multiplexer 133 configured to generate a first odd-selection voltage signal VP_OD based on the logic levels of the input signal IN level or the second power supply voltage VSS level, which are used as selection signals, a level detection signal BUF_EN and a complementary level detection signal BUF_ENb. For example, the third multiplexer 133 may be configured to select and output the first odd-selection voltage signal VP_OD of the input signal IN level (e.g., the first power supply voltage VDD level) when the level detection signal BUF_EN has a logic high (1) level, and to select and output the first odd-selection voltage signal VP_OD of the second power supply voltage VSS level when the level detection signal BUF_EN has a logic low (0) level.

[0108] The fourth voltage signal generator may include a fourth multiplexer 134 configured to generate a first even-select voltage signal VP_EV at the level of a second power supply voltage VSS or the level of a complementary input signal INb, based on the logic levels of a level detection signal BUF_EN and a complementary level detection signal BUF_ENb, which serve as selection signals. For example, the fourth multiplexer 134 may be configured to select and output the first even-select voltage signal VP_EV at the level of the second power supply voltage VSS when the level detection signal BUF_EN has a logic high (1) level, and to select and output the first even-select voltage signal VP_EV at the level of the complementary input signal INb (e.g., the level of the first power supply voltage VDD) when the level detection signal BUF_EN has a logic low (0) level.

[0109] The fifth voltage signal generator may include a fifth multiplexer 135 configured to generate a second odd-gated voltage signal VN_OD at either the level of a first power supply voltage VDD or the level of an input signal IN, based on the logic levels of a level detection signal BUF_EN and a complementary level detection signal BUF_ENb, which serve as selection signals. For example, the fifth multiplexer 135 may be configured to select and output the second odd-gated voltage signal VN_OD at the level of the first power supply voltage VDD when the level detection signal BUF_EN has a logic high (1) level, and to select and output the second odd-gated voltage signal VN_OD at the level of the input signal IN (e.g., the level of the second power supply voltage VSS) when the level detection signal BUF_EN has a logic low (0) level.

[0110] The sixth voltage signal generator may include a sixth multiplexer 136 configured to generate a second even-select voltage signal VP_EV at the level of a complementary input signal INb or the level of a first power supply voltage VDD, based on the logic levels of a level detection signal BUF_EN and a complementary level detection signal BUF_ENb, which serve as selection signals. For example, the sixth multiplexer 136 may be configured to select and output the second even-select voltage signal VN_EV at the level of the complementary input signal INb (e.g., the level of the second power supply voltage VSS) when the level detection signal BUF_EN has a logic high (1) level, and to select and output the second even-select voltage signal VN_EV at the level of the first power supply voltage VDD when the level detection signal BUF_EN has a logic low (0) level.

[0111] Each of the first multiplexer 131 to the sixth multiplexer 136 in the voltage signal generation circuit 130 may include multiple logic gates. For example, the first multiplexer 131 includes a first NAND gate 131-1, a second NAND gate 131-2, and a third NAND gate 131-3; the second multiplexer 132 includes a first NAND gate 132-1, a second NAND gate 132-2, and a third NAND gate 132-3; ...; and the sixth multiplexer 136 includes a first NAND gate 136-1, a second NAND gate 136-2, and a third NAND gate 136-3.

[0112] In the first multiplexer 131, the first NAND gate 131-1 can receive the second power supply voltage VSS level signal and the level detection signal BUF_EN. The second NAND gate 131-2 can receive the first power supply voltage VDD level signal and the complementary level detection signal BUF_ENb. The third NAND gate 131-3 can receive the output signals of the first NAND gate 131-1 and the second NAND gate 131-2 and generate an odd control voltage signal VST_OD. For example, the first multiplexer 131 can output the second power supply voltage VSS level signal as the odd control voltage signal VST_OD when the level detection signal BUF_EN is at a logic high level, and output the first power supply voltage VDD level signal as the odd control voltage signal VST_OD when the level detection signal BUF_EN is at a logic low level.

[0113] In the second multiplexer 132, the first NAND gate 132-1 can receive the first power supply voltage VDD level signal and the level detection signal BUF_EN. The second NAND gate 132-2 can receive the second power supply voltage VSS level signal and the complementary level detection signal BUF_ENb. The third NAND gate 132-3 can receive the output signals of the first NAND gate 132-1 and the second NAND gate 132-2 and generate the even control voltage signal VST_EV. For example, the second multiplexer 132 can output the first power supply voltage VDD level signal as the even control voltage signal VST_EV when the level detection signal BUF_EN is at a logic high level, and output the second power supply voltage VSS level signal as the even control voltage signal VST_EV when the level detection signal BUF_EN is at a logic low level.

[0114] In the third multiplexer 133, the first NAND gate 133-1 can receive the input signal IN and the level detection signal BUF_EN. The second NAND gate 133-2 can receive the second power supply voltage VSS level signal and the complementary level detection signal BUF_ENb. The third NAND gate 133-3 can receive the output signals of the first NAND gate 133-1 and the second NAND gate 133-2 and generate a first odd-selection voltage signal VP_OD. For example, the third multiplexer 133 can output a signal at the level of the input signal IN (e.g., the first power supply voltage VDD level signal) as the first odd-selection voltage signal VP_OD when the level detection signal BUF_EN is at a logic high level, and output a signal at the level of the second power supply voltage VSS level as the first odd-selection voltage signal VP_OD when the level detection signal BUF_EN is at a logic low level.

[0115] In the fourth multiplexer 134, the first NAND gate 134-1 can receive the second power supply voltage VSS level signal and the level detection signal BUF_EN. The second NAND gate 134-2 can receive the complementary input signal INb and the complementary level detection signal BUF_ENb. The third NAND gate 134-3 can receive the output signals of the first NAND gate 134-1 and the second NAND gate 134-2 and generate the first even-select voltage signal VP_EV. For example, the fourth multiplexer 134 can output the second power supply voltage VSS level signal as the first even-select voltage signal VP_EV when the level detection signal BUF_EN is at a logic high level, and output a signal at the complementary input signal INb level (e.g., the first power supply voltage VDD level signal) as the first even-select voltage signal VP_EV when the level detection signal BUF_EN is at a logic low level.

[0116] In the fifth multiplexer 135, the first NAND gate 135-1 can receive the first power supply voltage VDD level signal and the level detection signal BUF_EN. The second NAND gate 135-2 can receive the input signal IN and the complementary level detection signal BUF_ENb. The third NAND gate 135-3 can receive the output signals of the first NAND gate 135-1 and the second NAND gate 135-2, and generate the second odd-selection voltage signal VN_OD. For example, the fifth multiplexer 135 can output the first power supply voltage VDD level signal as the second odd-selection voltage signal VN_OD when the level detection signal BUF_EN is at a logic high level, and output the input signal IN level signal (e.g., the second power supply voltage VSS level signal) as the second odd-selection voltage signal VN_OD when the level detection signal BUF_EN is at a logic low level.

[0117] In the sixth multiplexer 136, the first NAND gate 136-1 can receive the complementary input signal INb and the level detection signal BUF_EN. The second NAND gate 136-2 can receive the first power supply voltage VDD level signal and the complementary level detection signal BUF_ENb. The third NAND gate 136-3 can receive the output signals of the first NAND gate 136-1 and the second NAND gate 136-2 and generate the second even-select voltage signal VN_EV. For example, the sixth multiplexer 136 can output a signal at the level of the complementary input signal INb (e.g., the second power supply voltage VSS level signal) as the second even-select voltage signal VN_EV when the level detection signal BUF_EN is at a logic high level, and output a signal at the level of the first power supply voltage VDD level as the second even-select voltage signal VN_EV when the level detection signal BUF_EN is at a logic low level.

[0118] Figure 6This is a diagram illustrating the process of reducing glitches and / or noise using a signal generating device 100 according to an embodiment of this disclosure. Figure 6 The illustration shows a glitch suppression circuit 110 configured with three inverter chains connected in series (e.g., three two-stage inverters unit1, unit2, and unit3), but is not limited to this configuration. In the glitch suppression circuit 110, the maximum value of glitch and / or noise that each unit (e.g., each two-stage inverter) can suppress can be determined. Therefore, when the glitch suppression circuit 110 is configured with n inverter chains (n ​​units) connected in series, glitch and / or noise can be removed at n times the maximum value per unit.

[0119] Reference Figure 6 The operation of the signal generating device 100 according to an embodiment of the present disclosure is described.

[0120] The glitch suppression circuit 110 of the signal generating device 100 can be configured by a plurality of two-stage inverters connected in series (e.g., n two-stage Schmitt trigger inverters (where n is a natural number)).

[0121] Figure 6 Examples are given of glitches and / or noise in an input signal IN that must be held at a logic high or logic low level. Case 1 is the process of suppressing high-low-high glitches and / or noise in a logic high input signal IN, while Case 2 is the process of suppressing low-high-low glitches and / or noise in a logic low input signal IN.

[0122] For example, when a logic low glitch occurs in the logic high input signal IN, it can be directed to... Figure 6 Each of the two-stage inverters, unit1, unit2, and unit3, is connected to... Figure 2 The first inverter circuit 111 applies an odd control voltage signal VST_OD of the second power supply voltage VSS level to the odd-numbered inverter 110-1, thereby increasing the switching threshold voltage of the PMOS transistor constituting the odd-numbered inverter 110-1. Figure 6 In and Figure 2 The even-numbered inverter 110-2 corresponding to the second inverter circuit 112 is given an even control voltage signal VST_EV at the level of the first power supply voltage VDD to increase the switching threshold voltage of the NMOS transistor constituting the even-numbered inverter 110-2. Through this repeated operation, the switching threshold voltage can be increased via... Figure 6 The inverter chains unit1, unit2, and unit3 illustrated in the diagram progressively reduce high-low-high glitches and / or noise (Case 1).

[0123] Furthermore, when a logic high-level glitch occurs in the logic low-level input signal IN, it can be directed to... Figure 6 In and Figure 2 An odd control voltage signal VST_OD at the level of the first power supply voltage VDD is applied to the odd-numbered inverter 110-1 corresponding to the first inverter circuit 111 to increase the switching threshold voltage of the NMOS transistor constituting the odd-numbered inverter 110-1. This can be achieved by... Figure 6 In and Figure 2 The even-numbered inverter 110-2 corresponding to the second inverter circuit 112 is given an even control voltage signal VST_EV at the level of the second power supply voltage VSS to increase the switching threshold voltage of the PMOS transistor constituting the even-numbered inverter 110-2. Through repeated operation, this can be achieved via... Figure 6 The inverter chains unit1, unit2, and unit3 illustrated in the example progressively reduce low-high-low glitches and / or noise (case 2).

[0124] Figure 7 This is a timing diagram illustrating the operation of the signal generating device 100 according to an embodiment of the present disclosure.

[0125] Reference Figure 7 When glitches and / or noise occur in the input signal IN, the signal generating device 100 can detect the level transition of the output signal OUT. When a high-low-high glitch as indicated by "A" occurs in the input signal IN, the switching threshold voltage of the PMOS transistor's conduction path can be increased earlier during the level transition from high-low logic level to low-high logic level of the glitch in the input signal IN, thereby increasing the high-low logic level transition time of the glitch in the input signal IN. Then, during the level transition from low-high logic level to high-low logic level of the glitch in the input signal IN, the switching threshold voltage of the NMOS transistor's conduction path can be increased, thereby further increasing the high-low logic level transition time of the glitch in the input signal.

[0126] Therefore, the pulse width of the glitch in the input signal IN during the logic high-low-high level transition can be reduced by simply increasing the level transition time of the high-low level portion of the high-low-high logic level glitch (A) as indicated by "c".

[0127] When a low-high-low glitch as indicated by "B" appears in the input signal IN, the switching threshold voltage of the NMOS transistor's conduction path can be increased earlier during the level transition from low-high logic level to high-low logic level in the glitch of the input signal IN, thereby increasing the low-high logic level transition time of the glitch of the input signal IN. Then, the switching threshold voltage of the PMOS transistor's conduction path can be increased during the level transition from high-low logic level to logic low-high level in the glitch of the input signal IN, thereby further increasing the low-high logic level transition time of the glitch of the input signal IN. Therefore, the level transition time in the low-high logic level portion indicated by "e" in the low-high-low logic level glitch (B) can be increased only, thereby reducing the pulse duration width of the glitch of the input signal IN during the logic low-high-low level transition.

[0128] The clock signal CLK can be generated at the rising and falling edges of the output signal OUT, and the level detection signal BUF_EN and the complementary level detection signal BUF_ENb can be generated based on the clock signal CLK.

[0129] The level detection signal BUF_EN can be a signal used in the voltage signal generation circuit 130 to determine whether a high-low-high glitch or a low-high-low glitch occurs in the input signal IN.

[0130] The embodiments described above are intended to be illustrative and not limiting. Various alternatives and equivalents are also possible. The embodiments are not limited to those described herein. The embodiments are also not limited to any particular type of semiconductor device. Other additions, reductions, or modifications to this disclosure are readily apparent and are intended to fall within the scope of the appended claims.

[0131] Cross-references to related applications

[0132] This application claims priority to Korean Patent Application No. 10-2021-0188509, filed with the Korean Intellectual Property Office on December 27, 2021, the entire contents of which are incorporated herein by reference.

Claims

1. A signal generating device, the signal generating device comprising: A glitch suppression circuit includes n m-stage inverters connected in series, receives an input signal and performs an inversion operation on the input signal to generate an output signal, and adjusts the switching threshold voltage of the n m-stage inverters when a glitch occurs in the input signal to generate a glitch-removed output signal. A level detection circuit detects the logic level of the output signal provided by the glitch suppression circuit to generate a level detection signal and a complementary level detection signal; as well as A voltage signal generating circuit receives the level detection signal and the complementary level detection signal to generate a control voltage signal and provides the control voltage signal to the glitch suppression circuit. Where n is a natural number, and m is an even number greater than or equal to 2, and Each of the n m-stage inverters adjusts its switching threshold voltage in response to a corresponding control voltage signal in the control voltage signal, wherein the corresponding control voltage signal switches between a first power supply voltage level and a second power supply voltage level based on the level detection signal and the complementary level detection signal.

2. The signal generating device according to claim 1, wherein, The control voltage signals include odd control voltage signals provided to each odd-numbered inverter circuit of each of the n m-stage inverters, and even control voltage signals provided to each even-numbered inverter circuit of each of the n m-stage inverters. The voltage signal generating circuit further generates, based on the input signal, the complementary input signal, the level detection signal, and the complementary level detection signal, a first odd-selection voltage signal and a second odd-selection voltage signal for each odd-numbered inverter circuit in each m-stage inverter, and a first even-selection voltage signal and a second even-selection voltage signal for each even-numbered inverter circuit in each m-stage inverter.

3. The signal generating device according to claim 2, wherein, Each m-stage inverter in the glitch suppression circuit includes: An odd-numbered inverter circuit that inverts the input signal based on a first odd-selection voltage signal and a second odd-selection voltage signal to generate the complementary input signal, and adjusts the switching threshold voltage of the odd-numbered inverter circuit based on the odd control voltage signal; and An even-numbered inverting circuit performs an inversion operation on the complementary input signal based on the first even-selection voltage signal and the second even-selection voltage signal to generate the output signal, and adjusts the switching threshold voltage of the even-numbered inverting circuit based on the even control voltage signal.

4. The signal generating device according to claim 3, wherein, The odd-numbered inverting circuit includes: An odd-numbered inverter that inverts the input signal based on the first odd-selection voltage signal and the second odd-selection voltage signal to generate the complementary input signal; and An odd-numbered regulator adjusts the switching threshold voltage of the odd-numbered inverter based on the odd control voltage signal, and The even-numbered inverting circuit includes: An even-numbered inverter that inverts the complementary input signals based on the first even-selection voltage signal and the second even-selection voltage signal to generate the output signal; and An even-numbered regulator adjusts the switching threshold voltage of the even-numbered inverter based on the even-numbered control voltage signal.

5. The signal generating device according to claim 4, wherein, The odd-numbered inverter includes: A first inverter, in a first operating mode, inverts the input signal based on the first odd-selection voltage signal to generate the complementary input signal; and A second inverter, in a second operating mode, inverts the input signal based on the second odd-selection voltage signal to generate the complementary input signal, and The odd number adjuster includes: A first regulator, in the first operating mode, adjusts the switching threshold voltage of the first inverter based on the odd control voltage signal when a glitch occurs in the input signal, transitioning from a first logic level to a second logic level; and A second regulator, in the second operating mode, adjusts the switching threshold voltage of the second inverter based on the odd control voltage signal when a glitch occurs in the input signal, causing the signal to transition from the second logic level to the first logic level.

6. The signal generating device according to claim 5, wherein, The first inverter of the odd-numbered inverter includes a first PMOS transistor and a second PMOS transistor, which are connected in series between a first power supply voltage terminal and a complementary input signal terminal. The first odd-selection voltage signal and the input signal are respectively applied to the gates of the first PMOS transistor and the second PMOS transistor. The first regulator of the odd-numbered regulator includes a third PMOS transistor connected between the connection node of the first PMOS transistor and the second PMOS transistor and a first node for applying the odd control voltage signal, and the gate of the third PMOS transistor is connected to the complementary input signal terminal.

7. The signal generating device according to claim 6, wherein, The second inverter of the odd-numbered inverter includes a first NMOS transistor and a second NMOS transistor, which are connected in series between a second power supply voltage terminal and the complementary input signal terminal. The second odd-selection voltage signal and the input signal are respectively applied to the gates of the first NMOS transistor and the second NMOS transistor. The second regulator of the odd-numbered regulator includes a third NMOS transistor connected between the connection node of the first NMOS transistor and the second NMOS transistor and the first node for applying the odd control voltage signal, and the gate of the third NMOS transistor is connected to the complementary input signal terminal.

8. The signal generating device according to claim 4, wherein, The even-numbered inverter includes: A first inverter, in a second operating mode, inverts the complementary input signal based on the first even-select voltage signal to generate the output signal; and A second inverter, in the first operating mode, inverts the complementary input signal based on the second even-select voltage signal to generate the output signal, and The even-numbered adjustment mechanism includes: A first regulator, in the second operating mode, adjusts the switching threshold voltage of the first inverter based on the even control voltage signal when a glitch occurs in the complementary input signal, transitioning from a first logic level to a second logic level; and A second regulator, in the first operating mode, adjusts the switching threshold voltage of the second inverter based on the even control voltage signal when a glitch occurs in the complementary input signal transitioning from the second logic level to the first logic level.

9. The signal generating device according to claim 8, wherein, The first inverter of the even-numbered inverter includes a first PMOS transistor and a second PMOS transistor, which are connected in series between a first power supply voltage terminal and an output signal terminal. The first even-select voltage signal and the complementary input signal are respectively applied to the gates of the first PMOS transistor and the second PMOS transistor. The first regulator of the even-numbered regulator includes a third PMOS transistor connected between the connection node of the first PMOS transistor and the second PMOS transistor and a second node for applying the even control voltage signal, and the gate of the third PMOS transistor is connected to the output signal terminal.

10. The signal generating device according to claim 9, wherein, The second inverter of the even-numbered inverter includes a first NMOS transistor and a second NMOS transistor, which are connected in series between the second power supply voltage terminal and the output signal terminal. The second even-select voltage signal and the complementary input signal are respectively applied to the gates of the first NMOS transistor and the second NMOS transistor. The second regulator of the even-numbered regulator includes a third NMOS transistor connected between the connection node of the first NMOS transistor and the second NMOS transistor and the second node for applying the even control voltage signal, and the gate of the third NMOS transistor is connected to the output signal terminal.

11. The signal generating device according to claim 1, wherein, The level detection circuit performs an XOR operation on the first delayed signal and the second delayed signal of the output signal to generate clock pulses at the rising and falling edges of the output signal. Based on the clock pulses, it detects the logic level of the output signal to generate the level detection signal and the complementary level detection signal, and provides the level detection signal and the complementary level detection signal to the voltage signal generation circuit.

12. The signal generating device according to claim 2, wherein, The voltage signal generating circuit includes: A control voltage signal generator generates an odd control voltage signal and an even control voltage signal at the first power supply voltage level or the second power supply voltage level based on the level detection signal and the complementary level detection signal, and provides the odd control voltage signal and the even control voltage signal to the glitch suppression circuit. A first gate voltage signal generator, based on the level detection signal and the complementary level detection signal, generates a first odd gate voltage signal and a first even gate voltage signal of one of the input signal level and the complementary input signal level or the second power supply voltage level, and provides the first odd gate voltage signal and the first even gate voltage signal to the glitch suppression circuit; and A second gating voltage signal generator generates a second odd gating voltage signal and a second even gating voltage signal based on the level detection signal and the complementary level detection signal, which are either the input signal level or the complementary input signal level or the first power supply voltage level, and provides the second odd gating voltage signal and the second even gating voltage signal to the glitch suppression circuit.

13. The signal generating device according to claim 12, wherein, The control voltage signal generator includes: A first multiplexer, based on the level detection signal and the complementary level detection signal, selects and outputs a signal of either the second power supply voltage level or the first power supply voltage level as the odd control voltage signal; and The second multiplexer selects and outputs a signal of either the first power supply voltage level or the second power supply voltage level based on the level detection signal and the complementary level detection signal, as the even control voltage signal.

14. The signal generating device according to claim 13, wherein, In a first operating mode where a glitch occurs in the input signal at the first logic level, transitioning from the first logic level to the second logic level, the first multiplexer and the second multiplexer select the odd control voltage signal at the first power supply voltage level and the even control voltage signal at the second power supply voltage level based on the complementary level detection signal, and output the selected odd control voltage signal and even control voltage signal to the odd-numbered inverting circuit and the even-numbered inverting circuit of each m-stage inverter. In a second operating mode where a glitch occurs in the input signal of the second logic level, transitioning from the second logic level to the first logic level, the first multiplexer and the second multiplexer select the odd control voltage signal of the second power supply voltage level and the even control voltage signal of the first power supply voltage level based on the level detection signal, and output the selected odd control voltage signal and even control voltage signal to the odd-numbered inverter circuit and the even-numbered inverter circuit of each m-stage inverter.

15. The signal generating device according to claim 14, wherein, The first gating voltage signal generator includes: A third multiplexer, based on the level detection signal and the complementary level detection signal, selects and outputs a signal of either the input signal level or the second power supply voltage level as the first odd-select voltage signal; and A fourth multiplexer selects and outputs a signal based on the level detection signal and the complementary level detection signal, either the second power supply voltage level or the complementary input signal level, as the first even-select voltage signal.

16. The signal generating device according to claim 15, wherein, In the first operating mode where a glitch occurs in the input signal at the first logic level, transitioning from the first logic level to the second logic level, the third and fourth multiplexers, based on the complementary level detection signal, select a first odd-selection gate voltage signal at the second power supply voltage level and a first even-selection gate voltage signal at the complementary input signal level of the first power supply voltage level. They then output the selected first odd-selection gate voltage signal and the first even-selection gate voltage signal to the odd-numbered inverter circuit and the even-numbered inverter circuit of each m-stage inverter. In the second operating mode where a glitch occurs in the input signal of the second logic level, transitioning from the second logic level to the first logic level, the third multiplexer and the fourth multiplexer, based on the level detection signal, select the first odd-selection voltage signal and the first even-selection voltage signal of the second power supply voltage level as the input signal level of the first power supply voltage level, and output the selected first odd-selection voltage signal and the first even-selection voltage signal to the odd-numbered inverter circuit and the even-numbered inverter circuit of each m-stage inverter.

17. The signal generating device according to claim 16, wherein, The second gating voltage signal generator includes: A fifth multiplexer, based on the level detection signal and the complementary level detection signal, selects and outputs a signal of either the first power supply voltage level or the input signal level as the second odd-selection voltage signal; and The sixth multiplexer selects and outputs a signal based on the level detection signal and the complementary level detection signal, either the complementary input signal level or the first power supply voltage level, as the second even-select voltage signal.

18. The signal generating device according to claim 17, wherein, In the first operating mode where a glitch occurs in the input signal at the first logic level, transitioning from the first logic level to the second logic level, the fifth and sixth multiplexers, based on the complementary level detection signal, select the second odd-selection voltage signal and the second even-selection voltage signal at the first power supply voltage level as the input signal level of the second power supply voltage level, and output the selected second odd-selection voltage signal and the second even-selection voltage signal to the odd-numbered inverter circuit and the even-numbered inverter circuit of each m-stage inverter. In the second operating mode where a glitch occurs in the input signal of the second logic level, transitioning from the second logic level to the first logic level, the fifth multiplexer and the sixth multiplexer select the second odd-selection voltage signal of the first power supply voltage level and the second even-selection voltage signal of the complementary input signal level of the second power supply voltage level based on the level detection signal, and output the selected second odd-selection voltage signal and the second even-selection voltage signal to the odd-numbered inverter circuit and the even-numbered inverter circuit of each m-stage inverter.

19. A signal generating device, the signal generating device comprising: A first inverting circuit inverts an input signal based on a first gating voltage signal and a second gating voltage signal to generate a complementary input signal. When a glitch occurs in the input signal, the switching threshold voltage of the first inverting circuit is adjusted based on a first control voltage signal, which switches between a first power supply voltage level and a second power supply voltage level. A second inverting circuit inverts the complementary input signal received from the first inverting circuit based on a third gating voltage signal and a fourth gating voltage signal to generate an output signal. When a glitch occurs in the complementary input signal, the switching threshold voltage of the second inverting circuit is adjusted based on a second control voltage signal, which switches between a first power supply voltage level and a second power supply voltage level. A level detection circuit generates clock pulses at the rising and falling edges of the output signal received from the second inverting circuit, and detects the logic level of the output signal based on the clock pulses to generate a level detection signal and a complementary level detection signal; and A voltage signal generating circuit generates a first control voltage signal and a second control voltage signal, a first gating voltage signal and a second gating voltage signal, and a third gating voltage signal and a fourth gating voltage signal having a first power supply voltage level or a second power supply voltage level, based on the level detection signal and the complementary level detection signal received from the level detection circuit, and provides the generated voltage signal to the first inverting circuit and the second inverting circuit.

20. The signal generating device according to claim 19, wherein, In a first operating mode where a glitch occurs in the input signal at the first logic level, transitioning from the first logic level to the second logic level, the voltage signal generation circuit, based on the complementary level detection signal, selects the first control voltage signal at the first power supply voltage level and the first and second gating voltage signals at the second power supply voltage level, and provides the selected voltage signals to the first inverting circuit. Furthermore, based on the complementary level detection signal, the circuit selects the second control voltage signal at the second power supply voltage level and the third and fourth gating voltage signals at the first power supply voltage level, and provides the selected voltage signals to the second inverting circuit. In a second operating mode where a glitch occurs in the input signal at the second logic level, transitioning from the second logic level to the first logic level, the voltage signal generation circuit selects the first control voltage signal and the first gating voltage signal and the second gating voltage signal at the second power supply voltage level based on the level detection signal, and provides the selected voltage signal to the first inverting circuit. Furthermore, based on the level detection signal, the circuit selects the second control voltage signal and the third gating voltage signal and the fourth gating voltage signal at the first power supply voltage level, and provides the selected voltage signal to the second inverting circuit.

21. The signal generating device according to claim 20, wherein, The first inverting circuit includes: A first inverter, based on the first gating voltage signal and the second gating voltage signal, inverts the input signal to generate the complementary input signal through a first output terminal; and A first regulator adjusts the switching threshold voltage of the first inverter based on the first control voltage signal, and The second inverting circuit includes: A second inverter, based on the third and fourth gate voltage signals, inverts the complementary input signal received from the first output terminal of the first inverter to generate the output signal via the second output terminal; and A second regulator adjusts the switching threshold voltage of the second inverter based on the second control voltage signal.

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