Phase adaptive adjustment circuit and time-frequency device

Abstract

The application discloses a phase self-adaptive adjusting circuit and a time-frequency device, and belongs to the technical field of time unification.The phase self-adaptive adjusting circuit comprises a coupling back check module, a time-frequency processing module and a plurality of varactor phase modulation modules, each varactor phase modulation module is used for being connected with a driving link and an external frequency receiving device, each varactor phase modulation module is further connected with the coupling back check module and the time-frequency processing module respectively, and the coupling back check module is connected with the time-frequency processing module.Based on not using a phase-locked loop, the application realizes the improvement of the phase consistency among each target frequency signal reaching the frequency receiving device, and has low phase noise.In addition, the phase compensation process is adaptive, so that the time-frequency device combined with the phase self-adaptive adjusting circuit has batch producibility.

Description

Technical Field

[0001] This invention belongs to the field of time unification technology, particularly the field of frequency source technology, and specifically relates to a phase adaptive adjustment circuit and a time-frequency device. Background Technology

[0002] Time unification domain equipment (time-frequency equipment) often serves as a frequency reference source, outputting standard frequencies such as 10MHz and 100MHz to subsequent equipment (frequency receiving equipment). Currently, the frequency output circuits of traditional time unification domain equipment mainly include low-phase-noise temperature-controlled crystal oscillators, low-noise amplifiers, power dividers, and LC filters. To ensure the synchronization of each output frequency, the core of frequency output circuit development focuses on ensuring low phase noise characteristics for each frequency signal. However, parasitic parameters between the components of the frequency output circuit itself can cause phase deviations between the output frequencies, and current frequency output circuit solutions lack improvement measures for phase consistency. Inconsistent phases in the frequency signals output by time unification domain equipment will weaken the performance of subsequent equipment. For example, in radar equipment, inconsistent phases will cause significant errors in the radar's coherent applications, leading to weakened radar performance. This is especially true for electronically scanned phased array radars, which have multiple receiving and transmitting channels; phase consistency between these channels is fundamental to ensuring radar detection accuracy and power.

[0003] like Figure 1 This paper illustrates a 100MHz driver amplifier link with six outputs. Each hardware link introduces phase deviation to the 100MHz signal output through power dividers, low-noise amplifiers, and LC filters. Analysis of the hardware links reveals that the worst-case phase deviation scenario is the sum of the phase deviations from the three-stage power divider, the first-stage low-noise amplifier, and the LC filter. Taking the ZPD9-2C5-1000-742 power divider as an example, this model introduces a phase deviation of 0.2° at 100MHz, resulting in a total phase deviation of 0.6° across the three stages. Taking the ZDH6018DC-1500MHz low-noise amplifier as another example, this model introduces a phase deviation of 5°. Using a commonly used Chebyshev ninth-order low-pass LC filter as an example, simulation analysis shows that the LC filter introduces a phase deviation of 2.33°. The above analysis shows that the worst-case phase deviation of the hardware link is 7.93°. Moreover, this analysis result is only the typical value calculated for the device at room temperature. Under high or low operating temperatures, the phase deviation generated by the device may be further deteriorated. Therefore, the phase deviation that may be generated by each hardware link is 0°~7.93°.

[0004] One approach is to add a phase-locked loop (PLL) circuit to the current frequency output circuit to ensure phase consistency. However, while ensuring phase consistency, this introduces significant noise, which degrades the phase noise of the frequency signal. Therefore, this approach is not advisable.

[0005] Therefore, how to ensure low phase noise while maintaining phase consistency between various frequency signals is a technical challenge that equipment in the field of time unification urgently needs to overcome. Summary of the Invention

[0006] The purpose of this invention is to overcome one or more shortcomings of the prior art and provide a phase adaptive adjustment circuit and time-frequency device.

[0007] The objective of this invention is achieved through the following technical solution:

[0008] First aspect

[0009] The first aspect of the present invention provides a phase adaptive adjustment circuit for connection to an external driver amplifier link. The driver amplifier link is used to input a reference frequency signal from a crystal oscillator, and outputs multiple delayed frequency signals after amplifying and filtering the input reference frequency signal. The adaptive adjustment circuit includes a coupling feedback module, a time-frequency processing module, and multiple varactor diode phase modulation modules. Each varactor diode phase modulation module is used to connect to the driver amplifier link and an external frequency receiving device. Each varactor diode phase modulation module is also connected to the coupling feedback module and the time-frequency processing module, respectively. The coupling feedback module is connected to the time-frequency processing module.

[0010] The time-frequency processing module is used to measure the first phase difference between the reference frequency signal output by the crystal oscillator and the reference frequency signal, and to perform frequency correction on the crystal oscillator according to the first phase difference. The frequency-corrected crystal oscillator outputs a reference frequency signal synchronized with the reference frequency signal to the driver amplifier link.

[0011] The varactor diode phase modulation module is used to transmit the delayed frequency signal output from the driver amplifier link to the frequency receiving device;

[0012] The coupling feedback module is used to couple the delayed frequency signals output from each varactor diode phase modulation module to the frequency receiving device to the time-frequency processing module.

[0013] The time-frequency processing module is also used to measure the second phase difference between each delayed frequency signal coupled to the reference frequency signal and the input through the coupling feedback module, and generate each first voltage control signal according to each second phase difference.

[0014] The varactor diode phase modulation module is also used to compensate the phase of the delayed frequency signal accessed from the driver amplifier link according to the corresponding first voltage control signal, and generate a target frequency signal after phase compensation. The target frequency signal is used to output to the frequency receiving device.

[0015] By setting a varactor diode phase modulation module after the driver amplifier link, after the varactor diode phase modulation module is connected to the external frequency receiving equipment, the delayed frequency signal forwarded from the driver amplifier link to the frequency receiving equipment via the varactor diode phase modulation module is first coupled back through the coupling back check module. The coupled delayed frequency signal is then transmitted to the time and frequency processing module. The time and frequency processing module calculates the phase deviation value (second phase difference) and generates a first voltage control signal to change the capacitance value of the varactor diode, thereby changing the capacitance value of the varactor diode and compensating for the phase deviation value caused by the driver amplifier link.

[0016] Preferably, the varactor diode phase modulation module includes a varactor diode, a hollow wire-wound inductor unit, a high-pass filter unit, a first π-attenuation unit, and a second π-attenuation unit. The negative terminal of the varactor diode is used to connect to the first voltage-controlled signal corresponding to the varactor diode phase modulation module itself, and the positive terminal of the varactor diode is grounded. The first end of the hollow wire-wound inductor unit is connected to the negative terminal of the varactor diode, and the second end of the hollow wire-wound inductor unit is connected to the first end of the first π-attenuation unit. The second end of the first π-attenuation unit is used to connect to the driver amplifier link. The negative terminal of the varactor diode is also connected to the first end of the high-pass filter unit. The second end of the high-pass filter unit is connected to the first end of the second π-attenuation unit. The second end of the second π-attenuation unit is used to connect to the frequency receiving device and the second end of the second π-attenuation unit is also connected to the coupling feedback module.

[0017] Preferably, a first DC blocking capacitor is connected in series between the second end of the hollow wire-wound inductor unit and the first end of the first π-attenuation unit; a second DC blocking capacitor is connected in series between the first end of the hollow wire-wound inductor unit and the first end of the high-pass filter unit.

[0018] Preferably, the hollow wire-wound inductor unit includes a first hollow wire-wound inductor, a second hollow wire-wound inductor, and a third capacitor. The first hollow wire-wound inductor, the second hollow wire-wound inductor, and the third capacitor are connected in parallel. The first end of the first hollow wire-wound inductor is connected to the negative terminal of the varactor diode, and the second end of the first hollow wire-wound inductor is connected to the first end of the first π decay unit.

[0019] Preferably, the time-frequency processing module includes a DAC conversion unit, a TDC time difference measurement unit, and a main control MCU unit. The adaptive adjustment circuit further includes an FPGA module. The FPGA module is connected to the coupling feedback module, the TDC time difference measurement unit, the DAC conversion unit, and the main control MCU unit, respectively. The TDC time difference measurement unit is connected to a crystal oscillator and is also connected to the main control MCU unit. The DAC conversion unit is connected to the crystal oscillator and is also connected to a varactor diode phase modulation module.

[0020] The FPGA module is used to transmit the various delay frequency signals coupled into the coupling back detection module to the TDC time difference measurement unit;

[0021] The TDC time difference measurement unit is used to measure the first phase difference between the reference frequency signal output by the crystal oscillator and the reference frequency signal, and to measure the second phase difference between each delay frequency signal and the reference frequency signal, and to send the first phase difference and each second phase difference to the main control MCU unit.

[0022] The main control MCU unit is used to generate a first DAC control signal according to the first phase difference and generate each second DAC control signal according to each second phase difference, and transmit the first DAC control signal and each second DAC control signal to the DAC conversion unit via the FPGA module.

[0023] The DAC conversion unit is used to generate first voltage-controlled signals according to each second DAC control signal, and to generate second voltage-controlled signals according to the first DAC control signals, and output the second voltage-controlled signals to the crystal oscillator.

[0024] Preferably, the transmission lines of each delay frequency signal inside the FPGA module are subject to equal length constraints, as are the transmission lines of each second DAC control signal inside the FPGA module.

[0025] Preferably, the coupling feedback module includes multiple coupling capacitors and multiple analog-to-digital converters;

[0026] Each coupling capacitor is used to couple the delayed frequency signals output from each varactor diode phase modulation module to each analog-to-digital converter in a one-to-one correspondence.

[0027] Each analog-to-digital converter is used to perform analog-to-digital conversion on each delayed frequency signal and transmit the converted delayed frequency signals to the time-frequency processing module.

[0028] Preferably, the adaptive adjustment circuit further includes a power supply module for supplying power to the coupling feedback module and the time-frequency processing module.

[0029] Preferably, the power supply module includes a high-precision, low-noise, and low-temperature-drift reference voltage source and a low-noise LDO regulated voltage source. The reference voltage source is used to output a first reference voltage to the DAC conversion unit, and the LDO regulated voltage source is used to output a first operating voltage to the DAC conversion unit.

[0030] The beneficial effects of the first aspect of the present invention are as follows:

[0031] (1) Without using a phase-locked loop, the phase consistency between the target frequency signals is improved and the phase noise is low. In addition, the phase compensation process is adaptive, which makes the time and frequency equipment that incorporates the phase adaptive adjustment circuit implemented in the first aspect of the present invention mass-producible.

[0032] (2) By setting up the hollow wire-wound inductor unit, the high-pass filter unit, the first π decay unit, the second π decay unit, the first DC blocking capacitor and the second DC blocking capacitor, the suppression of DC component and DC noise is realized, and the overall low phase noise performance of the phase adaptive adjustment circuit is further improved.

[0033] (3) By constraining the length of the transmission lines within the FPGA module, phase deviations introduced by the FPGA module are avoided;

[0034] (4) By using a high-precision, low-noise and low-temperature drift reference voltage source and a low-noise LDO voltage regulator, the accuracy and low-noise characteristics of the voltage-controlled signal output by the DAC conversion unit are guaranteed, thereby further improving the overall phase adjustment accuracy and low phase noise performance of the phase adaptive adjustment circuit.

[0035] Second aspect

[0036] A second aspect of the present invention provides a time-frequency device comprising a phase adaptive adjustment circuit, a driver amplifier link, and a crystal oscillator as described in the first aspect of the present invention. The phase adaptive adjustment circuit is connected to the driver amplifier link and is also used to connect to an external frequency receiving device. The crystal oscillator is connected to both the phase adaptive adjustment circuit and the driver amplifier link.

[0037] The second aspect of the present invention provides the same beneficial effects as the first aspect. At the same time, the time and frequency device implemented by the second aspect of the present invention improves the phase consistency among the multiple frequency signals output by the time and frequency device without using a phase-locked loop structure, thus meeting the high requirements for coherent consistency in fields such as radar. Attached Figure Description

[0038] Figure 1 This is a circuit schematic diagram of a 100M driver amplifier link proposed in the background art;

[0039] Figure 2This is a block diagram of a phase adaptive adjustment circuit;

[0040] Figure 3 This is the first part of the circuit schematic diagram for the varactor diode phase modulation module;

[0041] Figure 4 Part 2 of the circuit schematic for the varactor diode phase modulation module

[0042] Figure 5 This is a circuit schematic diagram of a coupling return detection module;

[0043] Figure 6 This is the first part of the circuit schematic diagram for the TDC time difference measurement unit;

[0044] Figure 7 This is the second part of the circuit schematic diagram for the TDC time difference measurement unit;

[0045] Figure 8 A circuit schematic diagram of a DAC conversion unit;

[0046] Figure 9 A circuit schematic for a reference voltage source and a low-noise LDO regulated power source;

[0047] Figure 10 A circuit schematic diagram for generating voltage-controlled signals for calibration. Detailed Implementation

[0048] The technical solution of the present invention will be clearly and completely described below with reference to the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0049] Example 1

[0050] This embodiment provides a phase adaptive adjustment circuit applied within a time-frequency device. The phase adaptive adjustment circuit is used to connect to the driver amplifier link within the time-frequency device and to an external frequency receiving device. The driver amplifier link receives a reference frequency signal from an OCXO crystal oscillator, amplifies and filters the received reference frequency signal, and outputs multiple delayed frequency signals. The external frequency receiving device receives the target frequency signal output by the phase adaptive adjustment circuit after phase adjustment.

[0051] For details, please refer to Figures 2 to 10A phase adaptive adjustment circuit includes a coupling feedback module, a time-frequency processing module, and multiple varactor diode phase modulation modules. Each varactor diode phase modulation module is used to connect to the driver amplifier link and an external frequency receiving device. Each varactor diode phase modulation module is also connected to the coupling feedback module and the time-frequency processing module, respectively. The coupling feedback module is connected to the time-frequency processing module.

[0052] The time-frequency processing module measures the first phase difference between the reference frequency signal output by the OCXO crystal oscillator and the reference frequency signal obtained by the time-frequency device from a local or upstream frequency source. Based on this first phase difference, it performs frequency correction on the OCXO crystal oscillator. The frequency-corrected crystal oscillator outputs a reference frequency signal synchronized with the reference frequency signal to the driver amplifier link. The time-frequency processing module outputs a reference frequency signal synchronized with the reference frequency signal after frequency correction of the OCXO crystal oscillator; this frequency correction process uses the frequency correction process described in the conventional embodiment. A phase shift occurs when the reference frequency signal flows through the driver amplifier link; the reference frequency signal with the phase shift is defined as the delayed frequency signal.

[0053] The varactor diode phase modulation module is used to transmit the delayed frequency signal output from the driver amplifier link to the frequency receiving device.

[0054] The coupling feedback module is used to couple the delayed frequency signals output from each varactor diode phase modulation module to the frequency receiving device and connect them to the time and frequency processing module.

[0055] The time-frequency processing module is also used to measure the second phase difference between each delayed frequency signal coupled to the reference frequency signal and the input through the coupling feedback module, and to generate each first voltage control signal according to each second phase difference.

[0056] The varactor diode phase modulation module is also used to compensate the phase of the delayed frequency signal accessed from the driver amplifier link according to the corresponding first voltage control signal, and generate the target frequency signal after phase compensation.

[0057] The working principle of the phase adaptive adjustment circuit implemented in this embodiment is as follows:

[0058] First, the phase adaptive adjustment circuit is connected to the driver amplifier link and the frequency receiving device respectively. The delayed frequency signal output by the driver amplifier link is transmitted to the frequency receiving device through the varactor diode phase modulation module. At this time, the delayed frequency signals output by each varactor diode phase modulation module to the frequency receiving device are coupled into the time-frequency processing module through the coupling feedback module. The time-frequency processing module performs phase offset measurement of the delayed frequency signal and generates a voltage control signal. The varactor diodes in the varactor diode phase modulation module generate different phase delays under different voltage control signals, thereby realizing phase offset compensation of the delayed frequency signal. This ensures that the frequency signals output after phase compensation by each varactor diode remain synchronized. Finally, when each target frequency signal arrives at the frequency receiving device, they maintain a low phase offset that is acceptable to the frequency receiving device.

[0059] After adjustment by the phase adaptive adjustment circuit, the phase difference between each target frequency signal was actually measured, and the average phase difference was about 2.2°.

[0060] As a preferred embodiment, the varactor diode phase modulation module includes a varactor diode, a hollow wire-wound inductor unit, a high-pass filter unit, a first π-attenuation unit, and a second π-attenuation unit. The negative terminal of the varactor diode is used to connect to the first voltage-controlled signal corresponding to the varactor diode phase modulation module itself, and the positive terminal of the varactor diode is grounded. The first end of the hollow wire-wound inductor unit is connected to the negative terminal of the varactor diode. The second end of the hollow wire-wound inductor unit is connected to the first end of the first π-attenuation unit via a first DC blocking capacitor. The second end of the first π-attenuation unit is used to connect to the driver amplifier link via a first RF connector. The negative terminal of the varactor diode is also connected to the first end of the high-pass filter unit via a second DC blocking capacitor. The second end of the high-pass filter unit is connected to the first end of the second π-attenuation unit. The second end of the second π-attenuation unit is used to connect to the frequency receiving device via a second RF connector. The second end of the second π-attenuation unit is also connected to the coupling feedback module.

[0061] In this embodiment, there are a total of six varactor diode phase modulation modules, which are used to adjust the phase of the six delayed frequency signals output from the driver amplifier link in a one-to-one correspondence. See [link to specific implementation circuit of the varactor diode phase modulation module]. Figure 3 and Figure 4 .exist Figure 3 and Figure 4In this configuration, the varactor diode VD1 is an SC305. The air-wound inductor unit includes a first air-wound inductor L10, a second air-wound inductor L9, and a third capacitor C94. The first air-wound inductor L10 and the second air-wound inductor L9 are either fixed inductors or manually adjustable inductors. The first π-attenuation unit includes a first resistor R659, a second resistor R655, and a third resistor R660. The high-pass filter unit includes a third inductor L11, a fourth inductor L12, a fourth capacitor C98, a fifth capacitor C95, and a seventh capacitor C102. The second π-attenuation unit includes a fourth resistor R661, a fifth resistor R662, and a sixth resistor R656. The negative terminal of varactor diode VD1 is connected to the first terminal of the first hollow wire-wound inductor L10, the first terminal of the second DC blocking capacitor C97, the first terminal of the seventh resistor R657, and the first terminal of the eighth resistor R658, respectively. The positive terminal of varactor diode VD1 is grounded. A sixth capacitor C101 is connected in parallel between the negative and positive terminals of varactor diode VD1. The first hollow wire-wound inductor L10, the second hollow wire-wound inductor L9, and the third capacitor C94 are connected in parallel. The second terminal of the first hollow wire-wound inductor L10 is connected to the first terminal of the first DC blocking capacitor C96. The second terminal of the first DC blocking capacitor C96 is connected to the first terminal of the second resistor R655 and the first terminal of the third resistor R660, respectively. The second terminal of the third resistor R660 is grounded. The second terminal of the second resistor R655 is connected to the first terminal of the first resistor R659. The second terminal of the first resistor R659 is grounded. The first terminal of the first resistor R659 is connected to an output port of the driver amplifier link via a first RF connector. A ninth resistor R538 and a tenth resistor R537 are connected in series between the negative terminal of the varactor diode VD1 and the first terminal of the first DC blocking capacitor C96. The second terminal of the second DC blocking capacitor C97 is connected to the first terminal of the third inductor L11, the first terminal of the fourth capacitor C98, and the first terminal of the fifth capacitor C95, respectively. The second terminal of the third inductor L11 is grounded. The second terminal of the fourth capacitor C98 is connected to the second terminal of the fifth capacitor C95, the first terminal of the fourth inductor L12, and the first terminal of the seventh capacitor C102, respectively. The second terminal of the fourth inductor L12 is grounded. The second terminal of the seventh capacitor C102 is grounded. The second terminal of the fourth capacitor C98 is also connected to the first terminal of the fourth resistor R661 and the first terminal of the sixth resistor R656, respectively. The second terminal of the fourth resistor R661 is grounded. The second terminal of the sixth resistor R656 is connected to the first terminal of the fifth resistor R662 and the first terminal of the eighth capacitor C99, respectively. The second terminal of the eighth capacitor C99 is connected to a port of the frequency receiving device via a second RF connector.

[0062] As a preferred embodiment, the coupling feedback module includes multiple coupling capacitors and multiple analog-to-digital converters (ADCs). Each coupling capacitor couples the delayed frequency signals output from each varactor diode phase modulation module to the corresponding ADC. Each ADC performs analog-to-digital conversion on the delayed frequency signals and transmits the converted signals to the time-frequency processing module.

[0063] In this embodiment, there are six coupling capacitors and six analog-to-digital converters. A coupling feedback unit, consisting of one coupling capacitor and one analog-to-digital converter, couples one delay frequency signal. Therefore, the coupling feedback module contains a total of six coupling feedback units. A specific implementation circuit of the coupling feedback unit can be found [see...]. Figure 5 .exist Figure 4 and Figure 5 In this example, the analog-to-digital converter D5 uses the model SGM7SZ04YN5G. The first terminal of coupling capacitor C100 is connected to the second terminal of the eighth capacitor C99. The second terminal of coupling capacitor C100 is connected to terminal A of analog-to-digital converter D5 via the ninth capacitor C116. Terminal A of analog-to-digital converter D5 is also connected to the first terminals of the eleventh resistor R665, the twelfth resistor R669, and the thirteenth resistor R670. The second terminal of the eleventh resistor R665 is connected to the 3.3V power supply terminal VCC3V3-100MCHECK, the first terminal of the tenth capacitor C114, and the first terminal of the eleventh capacitor C115. The second terminals of the tenth capacitor C114 and the eleventh capacitor C115 are both grounded. The second terminal of the twelfth resistor R669 is grounded. The second terminal of the thirteenth resistor R670 is connected to the Y terminal of analog-to-digital converter D5. The second terminal of the eleventh resistor R665 is also connected to the VCC terminal of analog-to-digital converter D5. The Y terminal of analog-to-digital converter D5 is connected to the time and frequency processing module via the fourteenth resistor R667.

[0064] As a preferred embodiment, the phase adaptive adjustment circuit also includes an FPGA module, and the coupling feedback module is connected to the time-frequency processing module via the FPGA module. The time-frequency processing module includes a DAC conversion unit, a TDC time difference measurement unit, and a main control MCU unit. The FPGA module is connected to the coupling feedback module, the TDC time difference measurement unit, the DAC conversion unit, and the main control MCU unit, respectively. The TDC time difference measurement unit is used to connect to the OCXO crystal oscillator and is also connected to the main control MCU unit. The DAC conversion unit is used to connect to the crystal oscillator and is also connected to the varactor diode phase modulation module.

[0065] The FPGA module is used to transmit the various delay frequency signals coupled into the coupling feedback module to the TDC time difference measurement unit. When transmitting the various delay frequency signals, the FPGA module imposes equal-length constraints on the transmission lines of each delay frequency signal within the FPGA module, ensuring that the transmission lines traversed by each delay frequency signal within the FPGA module are of equal length.

[0066] The TDC time difference measurement unit is used to measure the first phase difference between the reference frequency signal output by the OCXO crystal oscillator and the reference frequency signal, and to measure the second phase difference between each delay frequency signal and the reference frequency signal, and sends the first phase difference and each second phase difference to the main control MCU unit.

[0067] The main control MCU unit generates a first DAC control signal based on the first phase difference and generates corresponding second DAC control signals based on each of the second phase differences. It then transmits the first DAC control signal and each of the second DAC control signals to the DAC conversion unit via the FPGA module. Specifically, when transmitting the second DAC control signals, the FPGA module imposes equal-length constraints on the transmission lines of each second DAC control signal within the FPGA module, ensuring that the transmission lines traversed by each second DAC control signal within the FPGA module are of equal length.

[0068] The DAC conversion unit is used to generate each first voltage-controlled signal according to each second DAC control signal, and to generate a second voltage-controlled signal according to the first DAC control signal, and output the second voltage-controlled signal to the OCXO crystal oscillator.

[0069] In this embodiment, the main control MCU unit includes a single-chip microcomputer of model GD32F450VIT6 (not shown in the figure). The FPGA module uses an FPGA chip of model GW1N-UV9LQ144C6 / I5 (not shown in the figure). The Y terminal of the analog-to-digital converter D5 is connected to the first terminal of the fourteenth resistor R667. The second terminal of the fourteenth resistor R667 is connected to a general-purpose I / O port of the FPGA chip via the fifteenth resistor R672. Through this general-purpose I / O port, the FPGA chip receives a delay frequency signal coupled into the coupling feedback module. The FPGA chip does not perform any processing on the input delay frequency signal, but only forwards the delay frequency signal to the TDC time difference measurement unit. The TDC time difference measurement unit includes a first TDC time difference measurement subunit for the first time difference measurement and three second TDC time difference measurement subunits for the second phase difference measurement. Each second TDC time difference measurement subunit completes the phase deviation (second phase difference) measurement of the two delay frequency signals.

[0070] A specific implementation circuit of the second TDC time difference measurement subunit is shown below. Figure 6 and Figure 7The second TDC time difference measurement subunit includes a time difference measurement chip D29, model MS1022. The STOP2 pin of the time difference measurement chip D29 is connected to a general-purpose I / O port of the FPGA chip via the sixteenth resistor R816, used to receive one delayed frequency signal after the transmission line length is constrained by the FPGA chip. The STOP1 pin of the time difference measurement chip D29 is connected to a general-purpose I / O port of the FPGA chip via the seventeenth resistor R819, used to receive another delayed frequency signal after the transmission line length is constrained by the FPGA chip. The START terminal of D29 is connected to a general-purpose I / O port of the FPGA chip via the eighteenth resistor R822. The EN_START, EN_STOP1, and EN_STOP2 terminals of the time difference measurement chip D29 are connected to the 3.3V power supply terminal VCC3V3_TDC1 via the nineteenth resistor R824. The VCC and VIO terminals of the time difference measurement chip D29 are connected to the 3.3V power supply terminal VCC3V3_TDC1. The INT, SSN, SCK, SI, SO, and RSTN terminals of the time difference measurement chip D29 are each connected to a general-purpose I / O port of the microcontroller. The 3.3V power supply terminal VCC3V3_TDC1 is obtained by filtering the 3.3V DC voltage output from the 3.3V power supply terminal VCC3V3_TDC. The 3.3V power supply terminal VCC3V3_TDC is connected to the first terminal of the first ferrite bead L45. The second terminal of the first ferrite bead L45 is connected to the 3.3V power supply terminal VCC3V3_TDC1, the first terminal of the twelfth capacitor C418, the first terminal of the thirteenth capacitor C419, the first terminal of the fourteenth capacitor C420, and the first terminal of the fifteenth capacitor C421. The second terminals of the twelfth capacitor C418, the thirteenth capacitor C419, the fourteenth capacitor C420, and the fifteenth capacitor C421 are all grounded. The XIN pin of the time difference measurement chip D29 is used to input the 5MHz clock obtained by dividing the reference frequency signal within the time and frequency equipment. The XIN pin of the time difference measurement chip D29 is connected to the first end of the twentieth resistor R836, and the second end of the twentieth resistor R836 is connected to the D terminal of the D-type flip-flop D32 and... The D-type flip-flop D32 uses the model 74LVC1G80GW. The VCC terminal of the D-type flip-flop D32 is connected to the first terminal of the sixteenth capacitor C430 and the 3.3V power supply terminal VCC3V3, respectively. The second terminal of the sixteenth capacitor C430 is grounded. The CLK terminal of the D-type flip-flop D32 is connected to the 5M clock obtained by dividing the reference frequency signal in the time and frequency equipment. The reference frequency signal can be 1PPS, etc.

[0071] The DAC conversion unit includes one first DAC conversion subunit and six second DAC conversion subunits. The first DAC conversion subunit generates a second voltage-controlled signal based on the first DAC control signal and outputs the second voltage-controlled signal to the OCXO crystal oscillator. Each second DAC conversion subunit generates a corresponding first voltage-controlled signal based on each second DAC control signal. A specific implementation circuit of the second DAC conversion subunit is shown below. Figure 8 As shown. In Figure 8 The second DAC conversion subunit includes a DAC conversion chip D17, model TPC116S1-VR. The SYNCn, CLK, and DIN terminals of the DAC chip D17 are each connected to a general-purpose I / O port of the FPGA chip via a voltage divider resistor. This is used to receive the second DAC control signal generated by the main control MCU unit. The voltage divider resistor between the SYNCn terminal of the DAC chip D17 and the FPGA chip is R775; the voltage divider resistor between the CLK terminal of the DAC chip D17 and the FPGA chip is R776; and the voltage divider resistor between the DIN terminal of the DAC chip D17 and the FPGA chip is R777. The SYNCn terminal of the DAC chip D17 is also connected to the 3.3V power supply terminal VCC_3V3 via the twenty-first resistor R773. The SYNCn terminal of the DAC chip D17 is also grounded via the seventeenth capacitor C270, and the CLK terminal of the DAC chip D17 is also grounded via the eighteenth capacitor C271. The DIN terminal is also grounded via the nineteenth capacitor C272. The twenty-second resistor R774 is connected in series between the VOUT and VFB terminals of the DAC converter chip D17. The VREF terminal of the DAC converter chip D17 is connected to the first reference voltage output terminal VCC5V_REF1 via the twenty-third resistor R778. The VOUT terminal of the DAC converter chip D17 is used to connect to the second terminal of the seventh resistor R657. The VOUT terminal of the DAC converter chip D17 is used to output the first voltage-controlled signal. The VDD terminal of the DAC converter chip D17 is used to connect to the first operating voltage, which is output from the 5V power supply terminal VCC_5V0_DAC1. The 5V power supply terminal VCC_5V0_DAC1 is also connected to the first terminal of the twentieth capacitor C268 and the first terminal of the twenty-first capacitor C269, respectively. The second terminals of the twentieth capacitor C268 and the second terminals of the twenty-first capacitor C269 are both grounded.

[0072] All the aforementioned 3.3V and 5V power supply terminals are output from the power module within the phase adaptive adjustment circuit. To improve the low phase noise performance and phase adjustment accuracy of the phase adaptive adjustment circuit, a high-precision, low-noise, and low-temperature-drift reference voltage source and a low-noise LDO regulator are selected within the power module. The reference voltage source outputs a first reference voltage of 5V, and this first reference voltage output terminal is VCC5V_REF1. The LDO regulator outputs a first operating voltage, and this 5V power supply terminal is VCC_5V0_DAC1.

[0073] A specific implementation circuit of a reference voltage source and an LDO regulated power supply is as follows: Figure 9 As shown. In Figure 9In this system, the reference voltage source D18 is model CLREF0650AT, and the LDO regulated source N10 is model TPL803250-S5TR-S. The IN terminal of the reference voltage source D18 is connected to the first terminal of the 22nd capacitor C289, the 23rd capacitor C288, the 2nd ferrite bead L33, and the 3rd ferrite bead L34, respectively. The second terminal of the 2nd ferrite bead L33 is connected to the 5.4V power supply terminal VCC5V4 in the power module, and the second terminal of the 3rd ferrite bead L34 is connected to the 5.2V power supply terminal VCC_5V2 in the power module. The second terminals of the 22nd capacitor C289 and the 23rd capacitor C288 are both grounded. The EN terminal of the reference voltage source D18 is connected to the IN terminal of the reference voltage source D18. The FILTER terminal of the reference voltage source D18 is grounded through the 24th capacitor C292. The OUTF and OUTS terminals of the reference voltage source D18 are used to output the first reference voltage. The OUTF and OUTS terminals of the reference voltage source D18 are connected to the first terminal of the 25th capacitor C290 and the 26th capacitor C291, respectively. The second terminals of the 25th capacitor C290 and the 26th capacitor C291 are both grounded. The IN terminal of the LDO voltage regulator N10 is connected to the 5.4V power supply terminal VCC5V4 in the power module, the first terminals of capacitors C273 (27th), C274 (28th), C275 (29th), C276 (30th), and C277 (31st). The second terminals of capacitors C273, C274, C275, C276, and C277 are all grounded. The IN terminal of the LDO voltage regulator N10 is also connected to the EN terminal of the LDO voltage regulator N10 via resistor R779 (24th). The EN terminal of the LDO voltage regulator N10 is also grounded via capacitor C279 (32nd). A 33rd capacitor C278 is connected in series between the OUT terminal of N10 and the NC terminal of the LDO regulator N10. The NC terminal of the LDO regulator N10 is grounded through the 34th capacitor C287. The OUT terminal of the LDO regulator N10 is used to output the first working voltage. The OUT terminal of the LDO regulator N10 is also grounded through the 35th capacitor C280, the 36th capacitor C281, the 37th capacitor C282, the 38th capacitor C283, the 39th capacitor C284, the 40th capacitor C285, and the 41st capacitor C286. The 35th capacitor C280, the 36th capacitor C281, the 37th capacitor C282, the 38th capacitor C283, the 39th capacitor C284, the 40th capacitor C285, and the 41st capacitor C286 are connected in parallel.

[0074] To enhance the multi-scenario compatibility of the phase adaptive adjustment circuit, the ninth resistor R538 and the tenth resistor R537 can be either not mounted or both set to 0 ohms. The eighth resistor R658 can be not mounted or set to 0 ohms. When the eighth resistor R658 is set to 0 ohms, its second terminal is connected to a voltage-controlled signal used to adjust the varactor diode VD1. Specifically, as shown... Figure 10 As shown, the phase adaptive adjustment circuit also includes a sub-circuit for generating a calibration voltage control signal. Figure 10 In this circuit, the sub-circuit that generates the calibration voltage control signal includes a voltage regulator N4, which is an LDO voltage regulator. The VIN terminal of voltage regulator N4 is connected to the 5.2V power supply VCC_5V2 in the power module. The VIN terminal of voltage regulator N4 is also connected to the first terminals of capacitors C103 (42nd), C106 (43rd), and C104 (44th), and the first terminal of resistor R663 (25th). The second terminal of resistor R663 is connected to the EN terminal of voltage regulator N4. The second terminals of capacitors C103 (42nd), C106 (43rd), and C104 (44th) are all grounded. The EN terminal of voltage regulator N4 is also grounded via capacitor C105 (45th). A capacitor C107 (46th) is connected in series between the VOUT and BYP terminals of voltage regulator N4. The PG terminal of voltage regulator N4 is connected to the 5.2V power supply in the power module via resistor R666 (26th). The source terminal VCC_5V2, the FB terminal of the voltage regulator N4 is connected to the first terminal of the 27th resistor R664 and the first terminal of the 28th resistor R668 respectively. The second terminal of the 28th resistor R668 is grounded through the 29th resistor R671. The second terminal of the 27th resistor R664 is connected to the VOUT terminal of the voltage regulator N4, the first terminal of the 47th capacitor C108, the first terminal of the 48th capacitor C109, the first terminal of the 49th capacitor C110, the first terminal of the 50th capacitor C111, the first terminal of the 51st capacitor C112, and the first terminal of the 52nd capacitor C113 respectively. The second terminals of the 47th capacitor C108, the 48th capacitor C109, the 49th capacitor C110, the 50th capacitor C111, the 51st capacitor C112, and the 52nd capacitor C113 are all grounded. The VOUT terminal of the voltage regulator N4 is used to output the calibration voltage control signal.

[0075] Example 2

[0076] This embodiment provides a time and frequency device, including a phase adaptive adjustment circuit, a driver amplifier link, and a crystal oscillator implemented in Embodiment 1. The phase adaptive adjustment circuit is connected to the driver amplifier link and is also used to connect to an external frequency receiving device. The crystal oscillator is connected to both the phase adaptive adjustment circuit and the driver amplifier link.

[0077] The above description is merely a preferred embodiment of the present invention. It should be understood that the present invention is not limited to the forms disclosed herein and should not be construed as excluding other embodiments. It can be used in various other combinations, modifications, and environments, and can be altered within the scope of the concept described herein through the above teachings or related technologies or knowledge. Modifications and variations made by those skilled in the art that do not depart from the spirit and scope of the present invention should be within the protection scope of the appended claims.

Claims

1. A phase adaptive adjustment circuit, characterized in that, The circuit is used to connect to an external driver amplifier link, which is used to input a reference frequency signal from a crystal oscillator, amplify and filter the input reference frequency signal, and output multiple delayed frequency signals. The adaptive adjustment circuit includes a coupling feedback module, a time-frequency processing module, and multiple varactor diode phase modulation modules. Each varactor diode phase modulation module is used to connect to the driver amplifier link and an external frequency receiving device. Each varactor diode phase modulation module is also connected to the coupling feedback module and the time-frequency processing module, respectively. The coupling feedback module is connected to the time-frequency processing module. The time-frequency processing module is used to measure the first phase difference between the reference frequency signal output by the crystal oscillator and the reference frequency signal, and to perform frequency correction on the crystal oscillator according to the first phase difference. The frequency-corrected crystal oscillator outputs a reference frequency signal synchronized with the reference frequency signal to the driver amplifier link. The varactor diode phase modulation module is used to transmit the delayed frequency signal output from the driver amplifier link to the frequency receiving device; The coupling feedback module is used to couple the delayed frequency signals output from each varactor diode phase modulation module to the frequency receiving device to the time-frequency processing module. The time-frequency processing module is also used to measure the second phase difference between each delayed frequency signal coupled to the reference frequency signal and the input through the coupling feedback module, and generate each first voltage control signal according to each second phase difference. The varactor diode phase modulation module is also used to compensate the phase of the delayed frequency signal accessed from the driver amplifier link according to the corresponding first voltage control signal, and generate a target frequency signal after phase compensation. The target frequency signal is used to output to the frequency receiving device. The varactor diode phase modulation module includes a varactor diode, a hollow wire-wound inductor unit, a high-pass filter unit, a first π-attenuation unit, and a second π-attenuation unit. The negative terminal of the varactor diode is used to connect to the first voltage-controlled signal corresponding to the varactor diode phase modulation module itself, and the positive terminal of the varactor diode is grounded. The first end of the hollow wire-wound inductor unit is connected to the negative terminal of the varactor diode, and the second end of the hollow wire-wound inductor unit is connected to the first end of the first π-attenuation unit. The second end of the first π-attenuation unit is used to connect to the driver amplifier link. The negative terminal of the varactor diode is also connected to the first end of the high-pass filter unit. The second end of the high-pass filter unit is connected to the first end of the second π-attenuation unit. The second end of the second π-attenuation unit is used to connect to the frequency receiving device and the second end of the second π-attenuation unit is also connected to the coupling feedback module. A first DC blocking capacitor is connected in series between the second end of the hollow wire-wound inductor unit and the first end of the first π decay unit. A second DC blocking capacitor is connected in series between the first end of the hollow wire-wound inductor unit and the first end of the high-pass filter unit. The hollow wire-wound inductor unit includes a first hollow wire-wound inductor, a second hollow wire-wound inductor, and a third capacitor. The first hollow wire-wound inductor, the second hollow wire-wound inductor, and the third capacitor are connected in parallel. The first end of the first hollow wire-wound inductor is connected to the negative terminal of the varactor diode, and the second end of the first hollow wire-wound inductor is connected to the first end of the first π decay unit.

2. The phase adaptive adjustment circuit according to claim 1, characterized in that, The time-frequency processing module includes a DAC conversion unit, a TDC time difference measurement unit, and a main control MCU unit. The adaptive adjustment circuit also includes an FPGA module. The FPGA module is connected to the coupling feedback module, the TDC time difference measurement unit, the DAC conversion unit, and the main control MCU unit, respectively. The TDC time difference measurement unit is connected to a crystal oscillator and is also connected to the main control MCU unit. The DAC conversion unit is connected to the crystal oscillator and is also connected to a varactor diode phase modulation module. The FPGA module is used to transmit the various delay frequency signals coupled into the coupling back detection module to the TDC time difference measurement unit; The TDC time difference measurement unit is used to measure the first phase difference between the reference frequency signal output by the crystal oscillator and the reference frequency signal, and to measure the second phase difference between each delay frequency signal and the reference frequency signal, and to send the first phase difference and each second phase difference to the main control MCU unit. The main control MCU unit is used to generate a first DAC control signal according to the first phase difference and generate each second DAC control signal according to each second phase difference, and transmit the first DAC control signal and each second DAC control signal to the DAC conversion unit via the FPGA module. The DAC conversion unit is used to generate first voltage-controlled signals according to each second DAC control signal, and to generate second voltage-controlled signals according to the first DAC control signals, and output the second voltage-controlled signals to the crystal oscillator.

3. The phase adaptive adjustment circuit according to claim 2, characterized in that, The transmission lines of each delay frequency signal inside the FPGA module are subject to equal length constraints, as are the transmission lines of each second DAC control signal inside the FPGA module.

4. The phase adaptive adjustment circuit according to claim 1, characterized in that, The coupling feedback module includes multiple coupling capacitors and multiple analog-to-digital converters; Each coupling capacitor is used to couple the delayed frequency signals output from each varactor diode phase modulation module to each analog-to-digital converter in a one-to-one correspondence. Each analog-to-digital converter is used to perform analog-to-digital conversion on each delayed frequency signal and transmit the converted delayed frequency signals to the time-frequency processing module.

5. The phase adaptive adjustment circuit according to claim 2, characterized in that, The adaptive adjustment circuit also includes a power supply module, which supplies power to the coupling feedback module and the time-frequency processing module.

6. The phase adaptive adjustment circuit according to claim 5, characterized in that, The power supply module includes a high-precision, low-noise, and low-temperature-drift reference voltage source and a low-noise LDO regulated voltage source. The reference voltage source is used to output a first reference voltage to the DAC conversion unit, and the LDO regulated voltage source is used to output a first operating voltage to the DAC conversion unit.

7. A time-frequency device, characterized in that, The device includes a phase adaptive adjustment circuit, a driver amplifier link, and a crystal oscillator as described in any one of claims 1-6, wherein the phase adaptive adjustment circuit is connected to the driver amplifier link, and the phase adaptive adjustment circuit is also used to connect to an external frequency receiving device, and the crystal oscillator is connected to both the phase adaptive adjustment circuit and the driver amplifier link.

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