A sample-and-hold based charge pump phase-locked loop lock detection circuit

Abstract

A kind of charge pump phase-locked loop lock detection circuit based on sample and hold, characterized by comprising: voltage voltage conversion circuit A, voltage voltage conversion circuit B, sample and hold circuit SH1, sample and hold circuit SH2 and comparator.Control voltage of the loop filter output in charge pump phase-locked loop is as the input of lock detection circuit, it is connected to the input of voltage voltage conversion circuit A and voltage voltage conversion circuit B respectively, wherein the input of voltage voltage conversion circuit B output end is connected voltage-controlled oscillator;Voltage voltage conversion circuit A output end connects the input of sample and hold circuit SH1 and sample and hold circuit SH2 to carry out signal sampling, adjacent time window under sample and hold circuit SH1 and SH2 will sampling result be saved at output end respectively, the output of SH1 is connected to the positive input of comparator, the output of SH2 is connected to the negative input of comparator, and lock result is determined by the output voltage of comparator.

Description

Technical Field

[0001] This invention relates to a sample-and-hold charge pump phase-locked loop (PLL) detection circuit, belonging to the field of integrated circuit technology. Background Technology

[0002] One of the most common applications of phase-locked loop (PLL) circuits is as the local oscillator (LO) signal in radio frequency (RF) front-end (RF) circuits. The RF front-end refers to the circuitry from the antenna to the point where the first frequency conversion is completed. During down-conversion, the signal is mixed with a locally generated oscillation signal to convert the RF carrier to an intermediate frequency (IF) or baseband signal. When transmitting the signal, the IF or baseband signal needs to be up-converted back to the RF carrier, amplified by a power amplifier, and then transmitted through the antenna. In this process, a PLL circuit is typically used as the LO signal. Simultaneously, the transceiver's channel selection is also achieved by setting the LO frequency. With the rapid development of semiconductor technology over the past two decades, PLLs, with their advantages of high integration, low power consumption, and high performance, have become the mainstream choice for LO signals in fully integrated CMOS wireless transceivers.

[0003] The next-generation mobile communication standard is committed to significantly improving data transmission rates. Massive MIMO is one of the key technologies in 5G communication and has broad research prospects. In massive MIMO application scenarios, hundreds of antenna arrays are used to enable a large number of terminal users to share frequency resources simultaneously. The system has multiple transmit and receive channels, requiring multiple local oscillator signals, which places increasingly higher demands on reducing lock-in time. The lock-in time of the phase-locked loop depends on the automatic frequency correction algorithm during coarse tuning, the loop parameters during fine tuning, and the working time of lock-in detection.

[0004] Currently, the most common lock-in detection method involves counting the reference frequency signal and the divided frequency signal from the oscillator, performing hundreds or thousands of counts, using the period of the reference signal as the unit. When the counts of the two signals match, the phase-locked loop is considered to be locked. This process significantly extends the overall lock-in time. Summary of the Invention

[0005] The purpose of this invention is to provide a sample-and-hold charge pump phase-locked loop (PLL) lock detection circuit that can reduce the lock detection process time while ensuring loop performance.

[0006] The objective of this invention is achieved through the following technical solution:

[0007] A charge pump phase-locked loop (PLL) detection circuit based on sample-and-hold includes: a voltage-to-voltage conversion circuit A, a voltage-to-voltage conversion circuit B, a sample-and-hold circuit SH1, a sample-and-hold circuit SH2, and a comparator, with the following connections:

[0008] The control voltage output from the loop filter in the charge pump phase-locked loop serves as the input to the lock-in detection circuit, which is connected to the inputs of voltage-to-voltage conversion circuit A and voltage-to-voltage conversion circuit B, respectively. The output of voltage-to-voltage conversion circuit B is connected to the input of the voltage-controlled oscillator. The output of voltage-to-voltage conversion circuit A is simultaneously connected to the inputs of sample-and-hold circuits SH1 and SH2 for signal sampling. In adjacent time windows, sample-and-hold circuits SH1 and SH2 store the sampling results at their respective outputs. The output of sample-and-hold circuit SH1 is connected to the positive input of the comparator, and the output of sample-and-hold circuit SH2 is connected to the negative input of the comparator. The lock-in result is determined by the output voltage of the comparator.

[0009] Furthermore, the common-mode voltage of the comparator needs to be in the range of 0.2VCC to 0.8VCC.

[0010] Furthermore, the relationship between the locking result and the comparator's output voltage is as follows:

[0011] When the comparator output voltage is 0 to 0.3VCC, the locked state is unlocked;

[0012] When the comparator output voltage is between 0.3VCC and 0.7VCC, the lockout state is locked.

[0013] When the comparator output voltage is between 0.7VCC and VCC, the lockout state is unlocked.

[0014] Furthermore, voltage conversion circuit B is connected in series between the loop filter and the voltage-controlled oscillator to ensure that the control voltage signal is transmitted to the voltage-controlled oscillator and reduce leakage current.

[0015] Furthermore, both voltage-to-voltage conversion circuits A and B are unity-gain amplifiers.

[0016] Furthermore, the voltage conversion circuits A and B have the same circuit structure, both including transistors PM1, PM2, NM1, and NM2.

[0017] Transistors PM1 and PM2 are PMOS transistors, while NM1 and NM2 are NMOS transistors. Transistors PM1 and PM2 form a current mirror structure as the output load, and transistors NM1 and NM2 form a differential input pair, with the differential inputs connected to their gate terminals respectively. Connecting the drain terminal of transistor NM2 to its gate terminal achieves a unity-gain configuration for the amplifier.

[0018] Furthermore, both sample-and-hold circuits SH1 and SH2 are low-mismatch sample-and-hold circuits.

[0019] Furthermore, the sample-and-hold circuits SH1 and SH2 have the same circuit structure, both including: three inverters INV1, INV2 and INV3 for time delay, switches S1, S2 and S3, capacitor C1 for holding voltage, and operational amplifier OP1.

[0020] The clock control input signal is connected to switch S2 as the enable signal for switch S2. At the same time, the clock control input signal is also connected to the delay inverter INV1. The output of INV1 is connected to the input of INV2. The output of INV2 is used as the enable signal for switch S1. The output of INV2 is also used as the input of INV3. The output of INV3 is used as the enable signal for switch S3.

[0021] Switch S1 is connected between the sampling input and the upper plate of capacitor C1, switch S2 is connected between the lower plate of capacitor C1 and the sampling output, and switch S3 is connected between the upper plate of capacitor C1 and the sampling output. The lower plate of capacitor C1 is connected to the positive terminal of op-amp OP1, the negative terminal of op-amp OP1 is shorted to ground, and the op-amp output is the sampling output.

[0022] Furthermore, in sampling mode, S1 and S2 are on while S3 is off, and the capacitor tracks the input voltage. In hold mode, S1 and S2 are off while S3 is on, and the input voltage is held. Introducing an inverter can adjust the signal delay and reduce charge injection effects. The reference clock signal is multiplexed, and its positive and negative signals are used as the clock signals for the sample-and-hold circuit to achieve signal sampling and holding within adjacent time windows.

[0023] The beneficial effects of this invention compared to the prior art are as follows:

[0024] This invention introduces a sample-and-hold circuit, a voltage-to-voltage conversion circuit, and a comparator circuit into the charge pump phase-locked loop. This allows for real-time detection of the charge pump phase-locked loop's state while ensuring loop performance. This significantly shortens the locking detection process, accelerates the locking process of the charge pump phase-locked loop, and lays the foundation for meeting the requirements of rapid channel switching. Attached Figure Description

[0025] Figure 1 This is a block diagram of a charge pump phase-locked loop locking detection circuit based on sample-and-hold according to the present invention;

[0026] Figure 2 This is a schematic diagram of one specific implementation of a voltage-to-voltage conversion circuit;

[0027] Figure 3 This is a schematic diagram of one specific implementation of a sample-and-hold circuit;

[0028] Figure 4 This is a schematic diagram of the comparator's common-mode voltage requirement. Detailed Implementation

[0029] The specific embodiments of the present invention will now be described with reference to the accompanying drawings to enable those skilled in the art to better understand the invention. It should be particularly noted that in the following description, detailed descriptions of known functions and designs that might obscure the main content of the invention will be omitted here.

[0030] The sample-and-hold charge pump phase-locked loop (PLL) lock-in detection circuit operates in real-time alongside the PLL. Voltage conversion circuits A and B protect and extract the sensitive signal—the input control voltage of the voltage-controlled oscillator (VCO). Voltage conversion circuit B ensures the control voltage signal is delivered to the VCO and reduces leakage current. Voltage conversion circuit A delivers the control voltage to sample-and-hold circuits SH1 and SH2, sampling and holding the voltage within two adjacent time windows. The held voltage is used as the positive and negative inputs of a comparator for comparison, and the comparison result determines the loop's lock-in state according to a corresponding table.

[0031] like Figure 1 As shown, the present invention proposes a charge pump phase-locked loop (PLL) lock-in detection circuit based on sample-and-hold, comprising: a voltage-to-voltage conversion circuit A, a voltage-to-voltage conversion circuit B, a sample-and-hold circuit SH1, a sample-and-hold circuit SH2, and a comparator, the connection relationships of which are as follows:

[0032] The control voltage output from the loop filter in the charge pump phase-locked loop serves as the input to the lock-in detection circuit, which is connected to the inputs of voltage-to-voltage conversion circuit A and voltage-to-voltage conversion circuit B, respectively. The output of voltage-to-voltage conversion circuit B is connected to the input of the voltage-controlled oscillator. The output of voltage-to-voltage conversion circuit A is simultaneously connected to the inputs of sample-and-hold circuits SH1 and SH2 for signal sampling. In adjacent time windows, sample-and-hold circuits SH1 and SH2 store the sampling results at their respective outputs. The output of sample-and-hold circuit SH1 is connected to the positive input of the comparator, and the output of sample-and-hold circuit SH2 is connected to the negative input of the comparator. The lock-in result is determined by the output voltage of the comparator.

[0033] Voltage conversion circuits A and B are both unity-gain amplifiers.

[0034] Both sample-and-hold circuits SH1 and SH2 are low-mismatch sample-and-hold circuits.

[0035] The table showing the correspondence between the comparator's comparison results and the locking results is as follows:

[0036] 0~0.3VCC Unlocked 0.3VCC~0.7VCC locking 0.7VCC~VCC Unlocked

[0037] Example

[0038] Figure 1A sample-and-hold charge pump phase-locked loop locking detection circuit is provided as an embodiment of the present invention, such as... Figure 1 As shown, it mainly includes: voltage-to-voltage conversion circuit A, voltage-to-voltage conversion circuit B, sample-and-hold circuit SH1, sample-and-hold circuit SH2, and a comparator. Their connections are as follows: The control voltage output from the loop filter in the charge pump phase-locked loop serves as the input to the lock-in detection circuit, which is connected to the inputs of voltage-to-voltage conversion circuit A and voltage-to-voltage conversion circuit B, respectively. The output of voltage-to-voltage conversion circuit B is connected to the input of the voltage-controlled oscillator (VCO). The output of voltage-to-voltage conversion circuit A is connected to the inputs of sample-and-hold circuits SH1 and SH2 for signal sampling. In adjacent time windows, sample-and-hold circuits SH1 and SH2 store the sampling results at their respective outputs. The output of SH1 is connected to the positive input of the comparator, and the output of SH2 is connected to the negative input of the comparator. The lock-in result is determined by the output voltage of the comparator.

[0039] like Figure 2 As shown, the voltage-to-voltage conversion circuit is a simple unity-gain amplifier. If all transistors are matched, the output voltage is equal to the input voltage. The implementation of the MOS transistor circuit is also given.

[0040] The voltage conversion circuit can reduce the impact of the lock detection circuit on the phase-locked loop, and at the same time transmit the sensitive signal control voltage to facilitate the subsequent circuit to make state judgments.

[0041] Voltage conversion circuits A and B have the same circuit structure, both including transistors PM1, PM2, NM1, and NM2; transistors PM1 and PM2 are PMOS transistors, and NM1 and NM2 are NMOS transistors; transistors PM1 and PM2 form a current mirror structure as the output load, and transistors NM1 and NM2 form a differential input pair, with the differential inputs connected to their gate terminals respectively; connecting the drain terminal and gate terminal of transistor NM2 achieves a unity-gain amplifier configuration.

[0042] like Figure 3 As shown, a low-mismatch implementation of the sample-and-hold circuit is presented. In sampling mode, S1 and S2 are on, and S3 is off, with the capacitor tracking the input voltage. In hold mode, S1 and S2 are off, and S3 is on, holding the input voltage. Introducing an inverter can adjust the signal delay and reduce charge injection effects. A reference clock signal is multiplexed, with its positive and negative signals used as the clock signals for the sample-and-hold circuit to achieve signal sampling and holding within adjacent time windows.

[0043] The sample-and-hold circuits SH1 and SH2 have the same circuit structure, both including: three inverters INV1, INV2 and INV3 for time delay, switches S1, S2 and S3, capacitor C1 for holding voltage, and operational amplifier OP1;

[0044] The clock control input signal is connected to switch S2 as the enable signal for switch S2. At the same time, the clock control input signal is also connected to the delay inverter INV1. The output of INV1 is connected to the input of INV2. The output of INV2 is used as the enable signal for switch S1. The output of INV2 is also used as the input of INV3. The output of INV3 is used as the enable signal for switch S3.

[0045] Switch S1 is connected between the sampling input and the upper plate of capacitor C1, switch S2 is connected between the lower plate of capacitor C1 and the sampling output, and switch S3 is connected between the upper plate of capacitor C1 and the sampling output. The lower plate of capacitor C1 is connected to the positive terminal of op-amp OP1, the negative terminal of op-amp OP1 is shorted to ground, and the op-amp output is the sampling output.

[0046] like Figure 4 As shown, in addition to requiring high gain, the comparator's input common-mode voltage needs to be within the range of 0.2VCC to 0.8VCC. When the phase-locked loop loses lock, the charge pump continuously charges or discharges. At this time, the sampling and holding results are relatively close in adjacent time windows, which may cause the detection result to be judged as locked, resulting in a false judgment. Therefore, requirements are placed on the comparator's common-mode voltage.

[0047] By introducing a sample-and-hold circuit, a voltage-to-voltage conversion circuit, and a comparator circuit into the loop, the state of the phase-locked loop can be detected in real time while ensuring the performance of the charge pump phase-locked loop. This greatly shortens the time of the lock detection process, accelerates the lock process of the phase-locked loop, and lays the foundation for meeting the requirements of fast channel switching.

[0048] Although the illustrative specific embodiments of the present invention have been described above to enable those skilled in the art to understand the invention, it should be understood that the invention is not limited to the scope of the specific embodiments. For those skilled in the art, various changes are obvious as long as they are within the spirit and scope of the invention as defined and determined by the appended claims, and all inventions utilizing the concept of the present invention are protected.

Claims

1. A sample-and-hold charge pump phase-locked loop (PLL) locking detection circuit, characterized in that... include: The voltage-to-voltage conversion circuit A, voltage-to-voltage conversion circuit B, sample-and-hold circuit SH1, sample-and-hold circuit SH2, and comparator are connected as follows: The control voltage output from the loop filter in the charge pump phase-locked loop serves as the input to the lock-in detection circuit, which is connected to the inputs of voltage-to-voltage conversion circuit A and voltage-to-voltage conversion circuit B, respectively. The output of voltage-to-voltage conversion circuit B is connected to the input of the voltage-controlled oscillator. The output of voltage-to-voltage conversion circuit A is simultaneously connected to the inputs of sample-and-hold circuits SH1 and SH2 for signal sampling. In adjacent time windows, sample-and-hold circuits SH1 and SH2 store the sampling results at their respective outputs. The output of sample-and-hold circuit SH1 is connected to the positive input of the comparator, and the output of sample-and-hold circuit SH2 is connected to the negative input of the comparator. The lock-in result is determined by the output voltage of the comparator. The sample-and-hold circuits SH1 and SH2 have the same circuit structure, both including: three inverters INV1, INV2 and INV3 for time delay, switches S1, S2 and S3, capacitor C1 for holding voltage, and operational amplifier OP1. The clock control input signal is connected to switch S2 as the enable signal for switch S2. At the same time, the clock control input signal is also connected to the delay inverter INV1. The output of INV1 is connected to the input of INV2. The output of INV2 is used as the enable signal for switch S1. The output of INV2 is also used as the input of INV3. The output of INV3 is used as the enable signal for switch S3. Switch S1 is connected between the sampling input and the upper plate of capacitor C1, switch S2 is connected between the lower plate of capacitor C1 and the sampling output, and switch S3 is connected between the upper plate of capacitor C1 and the sampling output; the lower plate of capacitor C1 is connected to the positive terminal of op-amp OP1, the negative terminal of op-amp OP1 is shorted to ground, and the op-amp output is the sampling output. In sampling mode, S1 and S2 are on and S3 is off, and the capacitor tracks the input voltage. In hold mode, S1 and S2 are off and S3 is on, and the input voltage is held. Introducing an inverter can adjust the signal delay and reduce the charge injection effect. The reference clock signal is reused, and its positive and negative signals are used as the clock signals for the sample-and-hold circuit to achieve sampling and holding of the signal in adjacent time windows.

2. The charge pump phase-locked loop locking detection circuit based on sample-and-hold as described in claim 1, characterized in that: The common-mode voltage of the comparator needs to be in the range of 0.2VCC to 0.8VCC.

3. The charge pump phase-locked loop locking detection circuit based on sample-and-hold as described in claim 1, characterized in that: The relationship between the locking result and the comparator's output voltage is as follows: When the comparator output voltage is 0~0.3VCC, the locked state is unlocked; When the comparator output voltage is between 0.3VCC and 0.7VCC, the lockout state is locked. When the comparator output voltage is between 0.7VCC and VCC, the lockout state is unlocked.

4. The charge pump phase-locked loop locking detection circuit based on sample-and-hold as described in claim 1, characterized in that: The voltage conversion circuit B is connected in series between the loop filter and the voltage-controlled oscillator to ensure that the control voltage signal is transmitted to the voltage-controlled oscillator and to reduce leakage current.

5. The charge pump phase-locked loop locking detection circuit based on sample-and-hold as described in claim 1, characterized in that: Voltage conversion circuits A and B are both unity-gain amplifiers.

6. The charge pump phase-locked loop locking detection circuit based on sample-and-hold as described in claim 1 or 5, characterized in that: The voltage conversion circuits A and B have the same circuit structure, both including transistors PM1, PM2, NM1, and NM2. Transistors PM1 and PM2 are PMOS transistors, while NM1 and NM2 are NMOS transistors. Transistors PM1 and PM2 form a current mirror structure as the output load, and transistors NM1 and NM2 form a differential input pair, with the differential inputs connected to their gate terminals respectively. Connecting the drain terminal of transistor NM2 to its gate terminal achieves a unity-gain configuration for the amplifier.

7. The charge pump phase-locked loop locking detection circuit based on sample-and-hold as described in claim 1, characterized in that: Both sample-and-hold circuits SH1 and SH2 are low-mismatch sample-and-hold circuits.

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