Frequency synthesizer

Abstract

A frequency synthesizer that can output a signal with high frequency accuracy while suppressing an increase in the size of a circuit is provided. The frequency synthesizer includes a time-to-digital converter that outputs a time-to-digital value corresponding to a time event of a trigger signal with respect to a reference signal; a comparison section that compares a value based on the time-to-digital value and a target value; an oscillation section that generates a synthesis signal; and a frequency adjustment section that adjusts the frequency of the synthesis signal based on a comparison result of the comparison section, the time-to-digital converter including a state transition section that outputs state information showing an internal state based on a time event of the trigger signal, a transition state acquisition section that acquires and holds the state information in synchronization with the reference signal, and a calculation section that calculates the time-to-digital value corresponding to the number of transitions of the internal state based on the state information acquired by the transition state acquisition section.

Description

Technical Field

[0001] This invention relates to frequency synthesizers. Background Technology

[0002] Patent Document 1 describes a frequency synthesizer comprising: a frequency ΔΣ modulation unit that measures the frequency ratio of a clock signal output from a voltage-controlled oscillator to a reference signal; a frequency comparator that compares a target frequency value with the frequency of a signal whose output signal of the frequency ΔΣ modulation unit is set to k times; an integrator that integrates the signal whose output signal of the frequency comparator is set to k0 times; a digital-to-analog converter that converts the digital signal output from the integrator into an analog signal; and a voltage-controlled oscillator that generates a clock signal with a frequency corresponding to the voltage of the output signal of the digital-to-analog converter. According to this frequency synthesizer, the time required for locking the frequency or phase of the clock signal can be reduced, and idle tones can be suppressed even when the clock signal fluctuates during locking.

[0003] Patent Document 1: Japanese Patent Application Publication No. 2017-92833

[0004] However, in the frequency synthesizer described in Patent Document 1, in order to accurately measure the frequency ratio of the clock signal to the reference signal to generate a high-precision clock signal, multiple frequency ΔΣ modulation units need to be connected in parallel, which greatly increases the circuit size. Summary of the Invention

[0005] One solution of the frequency synthesizer involved in this invention includes:

[0006] A time-to-digital converter is input to a reference period signal and a composite signal. When the shorter period signal is used as the reference signal and the longer period signal is used as the trigger signal, the converter outputs a digital time value corresponding to the time event of the trigger signal relative to the reference signal.

[0007] The comparison unit compares the value of the digital time value output from the time-to-digital converter with the target value;

[0008] The oscillator generates the synthesized signal; and

[0009] The frequency adjustment unit adjusts the frequency of the synthesized signal based on the comparison result from the comparison unit.

[0010] The time-to-digital converter has the following features:

[0011] The state transition unit initiates the internal state transition based on the time event of the trigger signal and outputs state information showing the internal state.

[0012] A transition state acquisition unit acquires and maintains the state information synchronously with the reference signal from the state transition unit; and

[0013] The calculation unit calculates the time value corresponding to the number of transitions of the internal state based on the state information obtained by the transition state acquisition unit. Attached Figure Description

[0014] Figure 1 This is a block diagram illustrating a configuration example of the frequency synthesizer according to the first embodiment.

[0015] Figure 2 This is a block diagram illustrating other configuration examples of the frequency synthesizer of the first embodiment.

[0016] Figure 3 This is a diagram showing an example of the configuration of the frequency adjustment unit.

[0017] Figure 4 This is a diagram showing an example of filter configuration.

[0018] Figure 5 This is a graph showing the gain characteristics of a low-pass filter.

[0019] Figure 6 This is a diagram showing the phase characteristics of a low-pass filter.

[0020] Figure 7 This is a diagram illustrating an example of the configuration of the time-to-digital converter in the first embodiment.

[0021] Figure 8 This is a timing diagram illustrating an example of the operation timing of the time-to-digital converter in the first embodiment.

[0022] Figure 9 This is a timing diagram illustrating an example of the operation timing of the time-to-digital converter in the first embodiment.

[0023] Figure 10 This is a graph showing the relationship between the phase difference PD, the count value DCNT, and the digital time value TD.

[0024] Figure 11 This is a diagram illustrating an example of the configuration of the time-to-digital converter in the second embodiment.

[0025] Figure 12 This is a timing diagram illustrating an example of the operation timing of the time-to-digital converter in the second embodiment.

[0026] Figure 13 This is a diagram showing an example of the configuration of the arithmetic unit in the third embodiment.

[0027] Figure 14This is a graph showing an example of the relationship between signal S[63:0] and each count value, each accumulated value, each weighting coefficient value, and each time digital value.

[0028] Figure 15 This is a diagram showing an example of the configuration of the state transition unit.

[0029] Figure 16 This is a diagram showing an example of the configuration of the state transition unit.

[0030] Figure 17 This is a diagram showing an example of the configuration of the state transition unit.

[0031] Figure 18 This is a block diagram illustrating a configuration example of the frequency synthesizer according to the fifth embodiment.

[0032] Figure 19 This is a block diagram illustrating other configuration examples of the frequency synthesizer according to the fifth embodiment.

[0033] Explanation of reference numerals in the attached figures

[0034] 1… Frequency synthesizer, 10… Time-to-digital converter, 11… State transition unit, 12… Transition state acquisition unit, 13… Arithmetic unit, 20… Comparison unit, 21… Latch circuit, 22… Latch circuit, 23… Adder / subtractor, 24… Latch circuit, 25… Accumulator, 26… Subtractor, 30… Frequency adjustment unit, 31… Filter, 32… Gain adjustment circuit, 40… Oscillator, 111… AND logic circuit, 112… Logic inversion circuit, 113… Counter, 114-1~114-q… Delay element, 121… Latch circuit, 122-0~122-q… D flip-flop, 130… Accumulator, 131… Accumulator, 132… Multiplier, 133… Subtractor, 1 34…Encoder, 135…Converter, 136…Accumulator, 137…Accumulator, 138…Multiplier, 139…Subtractor, 201…Bit Separator, 202…Logic Inversion Circuit, 203…Logic Inversion Circuit, 204…Selector, 205…Selector, 206…Selector, 207…Selector, 208…Selection Signal Generation Unit, 209…Selection Signal Generation Unit, 210…ΣCalculator, 211…ΣCalculator, 212…ΣIntegrator, 213…Accumulator, 214…Multiplier, 215…Accumulator, 216…Subtractor, 217…Latch Circuit, 218…Accumulator, 219…Subtractor, 220…Latch Circuit, 221…TD Selection Unit. Detailed Implementation

[0035] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. Furthermore, the embodiments described below are not intended to unduly limit the scope of the invention as defined in the claims. Additionally, all configurations described below are not necessarily essential components of the present invention.

[0036] 1. First Implementation Method

[0037] 1-1. Structure and Operation of Frequency Synthesizers

[0038] Figure 1 This is a block diagram illustrating an example of the configuration of the frequency synthesizer according to the first embodiment. Additionally, Figure 2 This is a block diagram illustrating other configuration examples of the frequency synthesizer of the first embodiment. For example... Figure 1 and Figure 2 As shown, the frequency synthesizer 1 of the first embodiment includes a time-to-digital converter 10, a comparison unit 20, a frequency adjustment unit 30, and an oscillation unit 40.

[0039] The time-to-digital converter 10 is input with a reference period signal S ref and the synthesized signal S VCO When using the reference period signal S ref and the synthesized signal S output from the oscillator 40 VCO When the shorter-period signal is used as the reference signal RCLK and the longer-period signal is used as the trigger signal TRG, the output is the digital time value TD corresponding to the time event of the trigger signal TRG relative to the reference signal RCLK. The reference period signal S... ref For example, it can be a signal input from outside the frequency synthesizer 1, or a signal generated by an oscillation circuit (not shown) of the frequency synthesizer 1.

[0040] exist Figure 1 In the example, the reference periodic signal S ref and the synthesized signal S VCO The signal with the shorter period in the signal is the synthesized signal S. VCO The signal with a longer period is the reference periodic signal S. ref Therefore, the time-to-digital converter 10 outputs a synthesized signal S. VCO The reference signal is RCLK, and the reference period signal is S. ref The digital value TD represents the time when the trigger signal TRG is activated. Conversely, in... Figure 2 In the example, the reference periodic signal S ref and the synthesized signal S VCO The shorter-period signal in the reference period signal S is the shorter-period signal. ref The signal with a longer period is the synthesized signal S. VCO Therefore, the time-to-digital converter 10 outputs a reference periodic signal S. ref The reference signal RCLK and the synthesized signal S VCO The digital value TD represents the time when the trigger signal TRG is activated.

[0041] In this embodiment, the time-to-digital converter 10 functions as a phase detection unit that outputs a digital time value TD corresponding to the phase difference between the time events of the reference signal RCLK and the time events of the trigger signal TRG. The time event of the trigger signal TRG refers to the timing of the change in the trigger signal TRG; for example, it could be either the rising or falling edge of the trigger signal TRG, or both the rising and falling edges of the trigger signal TRG. Similarly, the time event of the reference signal RCLK refers to the timing of the change in the reference signal RCLK; for example, it could be either the rising or falling edge of the reference signal RCLK, or both the rising and falling edges of the reference signal RCLK.

[0042] Furthermore, a detailed configuration example of the time-to-digital converter 10 will be described later.

[0043] The digital time value TD output from the time-to-digital converter 10 is used as the phase signal P. VCO The input is given to the comparison unit 20. The comparison unit 20 compares the signals based on the phase signal P. VCO The comparison unit 20 compares the change in the digital time value TD with the target value FCW, and outputs an error signal ε as a comparison result. In this embodiment, the comparison unit 20 compares the change in the digital time value TD with the set value FCW, and outputs the difference between the change in the digital time value TD and the set value FCW as an error signal ε. That is, in this embodiment, the value of the digital time value TD, which is the object of comparison for the comparison unit 20, is the change in the digital time value TD, and the target value, which is the object of comparison, is the set value FCW. The set value FCW is, for example, a value determined based on a preset multiplication ratio or division ratio, and can be the value of a signal input from outside the frequency synthesizer 1, or the value after reading data pre-stored in a storage unit (not shown) of the frequency synthesizer 1.

[0044] like Figure 1 and Figure 2 As shown, for example, the comparison unit 20 includes a latch circuit 21 formed by multiple D flip-flops, a latch circuit 22 formed by multiple other D flip-flops, and an adder / subtractor 23. The latch circuits 21 and 22 cause the reference period signal S to... ref and the synthesized signal S VCO The longer period signal is used as the sampling signal S s Action. The sampling signal S input to latch circuits 21 and 22. s exist Figure 1 In the example, the reference periodic signal S ref ,exist Figure 2 In the example, the signal is a synthesized signal S. VCO The latch circuit 21 and the sampling signal S s The rising edge is synchronously captured and held as the phase signal P. VCOThe digital value of the time TD. Latch circuit 22 and sampling signal S s The rising edge of the signal is synchronously captured and held by latch circuit 21. Furthermore, latch circuits 21 and 22 can also be synchronized with the sampling signal S. s The operation is synchronized with the falling edge. The difference between the signal held by latch circuit 21 and the signal held by latch circuit 22 at the output of adder / subtractor 23 is equivalent to the sampled signal S. s The error signal ε is the difference between the change in the digital time value TD and the set value FCW within one cycle. When the change in the digital time value TD is the same as the set value FCW, the error signal ε is zero; when the change in the digital time value TD is greater than the set value FCW, the error signal ε is positive; and when the change in the digital time value TD is less than the set value FCW, the error signal ε is negative.

[0045] The frequency adjustment unit 30 adjusts the synthesized signal S based on the error signal ε, which is the comparison result of the comparison unit 20. VCO frequency f VCO In this embodiment, the frequency adjustment unit 30 outputs an adjustment signal S based on the error signal ε. VCO frequency f VCO The control signal VC.

[0046] In this embodiment, the frequency adjustment unit 30 adjusts the synthesized signal S based on the error signal ε. VCO frequency f VCO This ensures that the difference between the change in the digital time value TD and the set value FCW, which is the target value of that change, remains constant. The frequency adjustment unit 30 can also adjust the frequency f. VCO This allows the difference between the change in the digital time value TD and the set value FCW to become zero, and also allows adjustment of the frequency f. VCO This makes the difference between the change in the digital time value TD and the set value FCW a constant value, either positive or negative.

[0047] Figure 3 This is a diagram showing an example of the configuration of the frequency adjustment unit 30. Figure 3 In this example, the frequency adjustment unit 30 includes a filter 31 and a gain adjustment circuit 32. The filter 31 receives the error signal ε, which is the difference between the change in the input digital time value TD and the set value FCW, which is the target value, and the sampled signal S. s The synchronously operating digital filter functions as a loop filter for the output noise-reduced signal FLTO. Filter 31 may also include a low-pass filter, a lead filter, a lag filter, or a lag-lead filter. For example, filter 31 is implemented as... Figure 4The transfer function H(z) of the first-order IIR filter shown is expressed by equation (1). The first-order IIR filter functions as a low-pass filter, a lead filter, a lag filter, or a lag-lead filter by adjusting the coefficients a0, a1, and b1 of the transfer function H(z).

[0048] [Mathematical Expression 1]

[0049]

[0050] For example, in the reference periodic signal S ref frequency f ref For 260MHz, the synthesized signal S VCO frequency f VCO At a frequency of 12MHz, the sampling signal S s frequency f s It is 12MHz. By setting a0 = a1 ≈ 0.01292 and b1 ≈ 0.97416, the cutoff frequency f can be achieved. c =100kHz low-pass filter. Additionally, in the reference periodic signal S ref frequency f ref For 260MHz, the synthesized signal S VCO frequency f VCO At a frequency of 26.4MHz, the sampled signal S s frequency f s It is 26.4MHz. By setting a0 = a1≈0.0591 and b1≈0.98817, the cutoff frequency f can be achieved. c =100kHz low-pass filter. In Figure 5 and Figure 6 The cutoff frequencies f are shown in the figure. c Gain and phase characteristics of a 100kHz low-pass filter.

[0051] The output of gain adjustment circuit 32 is used to adjust the synthesized signal S. VCO frequency f VCO The control signal VC makes the output signal FLTO of filter 31 constant.

[0052] Back Figure 1 and Figure 2 The oscillation unit 40 generates a synthesized signal S based on the control signal VC output from the frequency adjustment unit 30. VCO For example, the oscillation unit 40 may include a voltage-controlled oscillator (not shown) that outputs a signal with a frequency corresponding to the voltage value of the control signal VC. The oscillation unit 40 may use the output signal of this voltage-controlled oscillator as a synthesized signal S. VCOThe output may also include a frequency divider (not shown) that divides the output signal of the voltage-controlled oscillator, with the output signal of the frequency divider serving as the synthesized signal S. VCO Output.

[0053] In such Figure 1 or Figure 2 In the frequency synthesizer 1 of the first embodiment configured as described above, the frequency adjustment unit 30 adjusts the synthesized signal S. VCO frequency f VCO The difference between the change in the digital time value TD and the set value FCW is kept constant, thereby forming the synthesized signal S. VCO A stable FLL at the desired frequency. FLL is an abbreviation for Frequency Locked Loop.

[0054] 1-2. Composition and Operation of Time-to-Digital Converters

[0055] Figure 7 This is a diagram illustrating an example configuration of the time-to-digital converter 10 in the first embodiment. (See diagram for details.) Figure 7 As shown, the time-to-digital converter 10 includes a state transition unit 11, a transition state acquisition unit 12, and an arithmetic unit 13.

[0056] The state transition unit 11 initiates the internal state transition based on the time event of the trigger signal TRG and outputs state information indicating the internal state. For example... Figure 7 As shown, in this embodiment, the state transition unit 11 includes an AND circuit 111, a logic inversion circuit 112, and a counter 113.

[0057] The logic AND circuit 111 outputs a trigger signal TRG, which is then ANDed with the output signal of the logic inversion circuit 112. The logic AND signal output from the logic AND circuit 111 becomes low when the trigger signal TRG is low, and becomes the same logic level as the output signal of the logic inversion circuit 112 when the trigger signal TRG is high.

[0058] The logic inversion circuit 112 outputs a signal whose logic level is inverted from the logic AND signal output from the logic AND circuit 111. Therefore, when the trigger signal TRG is high, the logic level of the logic AND signal alternately repeats between low and high levels. That is, the logic AND circuit 111 and the logic inversion circuit 112 constitute a ring oscillation circuit, and the state transition unit 11 outputs the logic AND signal output from the logic AND circuit 111 as an oscillation signal GRO. It can be considered that the change in the logic level of the oscillation signal GRO is equivalent to the change in the internal state of the state transition unit 11. That is, the state transition unit 11 starts the state transition based on the rising edge of the trigger signal TRG and stops the state transition based on the falling edge of the trigger signal TRG.

[0059] Counter 113 counts at least one of the rising and falling edges of the oscillation signal GRO output from state transition unit 11 and outputs a count value CNT. The count value CNT is state information indicating the internal state of state transition unit 11, and in this embodiment, it corresponds to the number of internal state transitions since the start of state transition in state transition unit 11. Alternatively, counter 113 may stop counting when the count value CNT reaches a predetermined upper limit value, and output that upper limit value as the count value CNT. Furthermore, the count value CNT is initialized to zero before the next time event of trigger signal TRG.

[0060] The transition state acquisition unit 12 synchronously acquires and holds the count value CNT as state information from the state transition unit 11 along with the reference signal RCLK. For example... Figure 7 As shown, in this embodiment, the transition state acquisition unit 12 includes a latch circuit 121 formed by multiple D flip-flops. The latch circuit 121 acquires a count value CNT, which serves as state information, synchronously with the rising edge of the reference signal RCLK, and holds it as a count value DCNT, which serves as state information. The count value DCNT corresponds to the number of transitions of the internal state of the state transition unit 11 during the period from the start of the state transition unit 11 to each rising edge that generates the reference signal RCLK.

[0061] The calculation unit 13 calculates a time value TD corresponding to the number of transitions of the internal state of the state transition unit 11 based on the count value DCNT, which is the state information acquired and maintained by the transition state acquisition unit 12. Alternatively, the calculation unit 13 may calculate an accumulated value based on the count value DCNT, summing the number of transitions of the internal state of the state transition unit 11, and then calculate the time value TD based on this accumulated value. For example, the calculation unit 13 may perform a prescribed operation on the weighted value accumulated over time and the accumulated value summing the number of transitions of the internal state of the state transition unit 11 to calculate the time value TD. The prescribed operation could be, for example, subtraction.

[0062] like Figure 7As shown, in this embodiment, the arithmetic unit 13 includes an accumulator 130, an accumulator 131, a multiplier 132, and a subtractor 133.

[0063] The accumulator 130 accumulates the count value DCNT, which is state information, synchronously with the rising edge of the reference signal RCLK, and outputs the accumulated value ACNT. The accumulated value ACNT is the accumulated value after adding up the number of transitions of the internal state of the state transition unit 11 from the state transition unit 11 to each rising edge that generates the reference signal RCLK.

[0064] Accumulator 131 increments by 1 synchronously with the rising edge of the reference signal RCLK. The accumulated value output from accumulator 131 indicates the total number of rising edges of the reference signal RCLK.

[0065] Multiplier 132 multiplies the accumulated value output from accumulator 131 by an integer N. The integer N is, for example, set to the upper limit of the count value CNT. The multiplied value of multiplier 132 is N times the total number of rising edges of the reference signal RCLK, and is a weighted value accumulated over time. That is, multiplier 132 outputs a weighting coefficient value WC.

[0066] Subtractor 133 outputs the digital time value TD as the result of subtracting the accumulated value ACNT from the weighting coefficient value WC. This digital time value TD corresponds to the phase difference between the time events of the reference signal RCLK and the trigger signal TRG.

[0067] In addition, the latch circuit 121 and the accumulator 131 can both operate synchronously with the falling edge of the reference signal RCLK, or they can operate synchronously with both the rising and falling edges of the reference signal RCLK.

[0068] Figure 8 and Figure 9 This is a timing diagram illustrating an example of the operation timing of the time-to-digital converter 10. Figure 8 and Figure 9 middle, Figure 7 The integer N is 64, and the time event of the reference signal RCLK is a rising edge. Furthermore, relative to one cycle T of the reference signal RCLK, the phase difference PD between the time event of the reference signal RCLK and the time event of the trigger signal TRG is... Figure 8 In the example, it is T×0.5, in Figure 9 In the example, it is T×0.7.

[0069] exist Figure 8 and Figure 9In the example, when the trigger signal TRG is generated, the state transition unit 11 starts the state transition, the logic level of the oscillation signal GRO alternately repeats low level and high level, and the count value CNT increases one by one from 0 in sync with the rising edge of the oscillation signal GRO.

[0070] Furthermore, in Figure 8 In the example, whenever a time event occurs with the reference signal RCLK, the count value DCNT increases as follows: 0, 4, 12, 20, 29, 37. Simultaneously, the accumulated value ACNT increases as follows: 0, 4, 16, 36, 65. Additionally, whenever a time event occurs with the reference signal RCLK, the weighting coefficient value WC increases as follows: 0, 64, 128, 192, 256, 320. As a result, the digital time value TD increases as follows: 0, 64, 124, 176, 220, 255.

[0071] On the other hand, Figure 9 In the example, whenever a time event occurs with the reference signal RCLK, the count value DCNT increases as follows: 0, 2, 10, 19, 27, 35. Simultaneously, the accumulated value ACNT increases as follows: 0, 2, 12, 31, 58. Additionally, whenever a time event occurs with the reference signal RCLK, the weighting coefficient value WC increases as follows: 0, 64, 128, 192, 256, 320. As a result, the digital time value TD increases as follows: 0, 64, 126, 180, 225, 262.

[0072] When on Figure 8 and Figure 9 When comparing, the phase difference PD is larger. Figure 9 In the example, the digital time value TD becomes smaller than the phase difference PD. Figure 8 In the example, the time digital value TD is a large value. That is, the time digital converter 10 outputs a time digital value TD that is larger as the phase difference PD increases. However, the time digital converter 10 can also output a time digital value TD that is smaller as the phase difference PD increases.

[0073] Figure 10 This is a graph showing the relationship between the phase difference PD and the count value DCNT and the digital time value TD. Figure 10 In this context, the upper limit of the count value CNT is 64. For example... Figure 10As shown, whenever a time event occurs with the reference signal RCLK, the count value DCNT is incremented, and the digital time value TD increases. When the time event of the reference signal RCLK is set to the 0th rising edge, with phase differences PD of T×0.5 and T×0.7, the count value DCNT reaches 64, the upper limit of the count value CNT, at the 9th rising edge of the reference signal RCLK. Furthermore, with phase differences PD of T×1.5 and T×1.7, the count value DCNT reaches 64, the upper limit of the count value CNT, at the 10th rising edge of the reference signal RCLK. Moreover, after the 10th rising edge of the reference signal RCLK, the difference between the digital time value TD with a phase difference PD of T×1.5 and the digital time value TD with a phase difference PD of T×0.5 remains 64, and the difference between the digital time value TD with a phase difference PD of T×1.7 and the digital time value TD with a phase difference PD of T×0.7 remains 64. That is, the relationship becomes as follows: when the phase difference PD increases by one cycle of the reference signal RCLK time T, the digital time value TD increases by 64.

[0074] Thus, the digital time value TD becomes a value corresponding to the phase difference between the time events of the reference signal RCLK and the trigger signal TRG. Therefore, the time-to-digital converter 10 functions as a phase detection unit that detects the phase difference between the reference signal RCLK and the trigger signal TRG. Furthermore, as mentioned earlier, the reference signal RCLK and the trigger signal TRG are respectively reference period signals S... ref and the synthesized signal S VCO Any one of them. Therefore, the frequency adjustment unit 30 adjusts the synthesized signal S. VCO frequency f VCO This ensures that the difference between the change in the digital time value TD and the set value FCW remains constant, thereby forming a reference period signal S. ref With the synthesized signal S VCO The phase difference changes according to the set value FCW while synthesizing the signal S VCO The FLL is stable at the desired frequency. Furthermore, in the case where the accumulator 131 is reset before the state transition unit 11 begins a state transition, a reference period signal S is generated. ref With the synthesized signal S VCO The phase difference is constant, and the synthesized signal S VCO A PLL that is stable at the desired frequency. PLL is an abbreviation for Phase Locked Loop.

[0075] 1-3. Effects

[0076] As explained above, in the frequency synthesizer 1 of the first embodiment, the time-to-digital converter 10 outputs a digital time value TD corresponding to the time event of the trigger signal TRG relative to the reference signal RCLK, where the reference signal RCLK is a reference period signal S. ref and the synthesized signal S VCO The signal with a shorter period in the signal is the trigger signal TRG, which is a signal with a longer period. Furthermore, the comparison unit 20 compares the change in the digital time value TD with the target value FCW, which is the setpoint, and the frequency adjustment unit 30 adjusts the synthesized signal S. VCO The frequency ensures that the difference between the change in the digital time value TD and the target value remains constant. Therefore, the time-to-digital converter 10 serves as the detection reference period signal S. ref With the synthesized signal S VCO The phase detection unit functions to detect the phase difference, and the FLL is formed by the time-to-digital converter 10, the comparator 20, the frequency adjustment unit 30, and the oscillator 40, thus enabling the output of a synthesized signal S at the desired frequency. VCO Furthermore, the time-to-digital converter 10 has a relatively simple configuration including a state transition unit 11, a transition state acquisition unit 12, and an arithmetic unit 13. By increasing the number of bits in the digital time value TD, the phase detection resolution is improved, thus enhancing the synthesis signal S. VCO The frequency accuracy is high. Therefore, according to the frequency synthesizer 1 of the first embodiment, compared with the frequency synthesizer that uses a circuit with multiple frequency ΔΣ modulation units arranged in parallel to replace the time-to-digital converter 10, it is possible to output a synthesized signal S with high frequency accuracy while suppressing the increase in circuit size. VCO .

[0077] Furthermore, according to the frequency synthesizer 1 of the first embodiment, the noise component is reduced by the filter 31 of the frequency adjustment unit 30, therefore, the synthesized signal S VCO The SNR is improved. SNR is an abbreviation for Signal to Noise Ratio.

[0078] Furthermore, according to the frequency synthesizer 1 of the first embodiment, the arithmetic unit 13 of the time-to-digital converter 10 calculates the digital time value TD based on the accumulated value ACNT obtained by the transition state acquisition unit 12 after accumulating the count value DCNT. Therefore, by increasing the number of accumulations, the resolution of phase detection is improved, and the synthesized signal S can be improved. VCO Frequency accuracy.

[0079] 2. Second Implementation Method

[0080] Hereinafter, regarding the frequency synthesizer 1 of the second embodiment, the same reference numerals are used for the same constituent elements as in the first embodiment, and descriptions that are repeated in the first embodiment are omitted or simplified. The description will mainly focus on the contents that are different from the first embodiment.

[0081] The configuration of the frequency synthesizer 1 in the second embodiment and Figure 1 The configurations are the same, therefore their illustrations and descriptions are omitted. In the frequency synthesizer 1 of the second embodiment, the configuration of the time-to-digital converter 10 differs from that of the first embodiment.

[0082] Figure 11 This is a diagram illustrating an example configuration of the time-to-digital converter 10 in the second embodiment. (See diagram for details.) Figure 11 As shown, the time-to-digital converter 10 includes a state transition unit 11, a transition state acquisition unit 12, and an arithmetic unit 13.

[0083] The state transition unit 11 initiates the internal state transition based on the time event of the trigger signal TRG and outputs state information indicating the internal state. For example... Figure 11 As shown, in this embodiment, the state transition unit 11 includes a logic AND circuit 111, a logic inversion circuit 112, and a counter 113. The state transition unit 11 includes a multi-stage delay circuit with multiple delay elements 114-1 to 114-q. q is an integer greater than or equal to 2.

[0084] Delay elements 114-1 to 114-q are connected in a chain to form a multi-stage delay circuit with one input and q outputs. Delay elements 114-1 to 114-q are either buffer elements or logic inverting elements. It is desirable that the delay times of delay elements 114-1 to 114-q be approximately equal; therefore, the same type of element is used for delay elements 114-1 to 114-q. Hereinafter, we will assume that all delay elements 114-1 to 114-q are buffer elements.

[0085] The input terminal of delay element 114-1 becomes the input terminal of the multi-stage delay circuit. Furthermore, the output terminals of each of delay elements 114-1 to 114-q become the q output terminals of the multi-stage delay circuit. Signals D1 to Dq are sequentially output from the q output terminals of the multi-stage delay circuit and from the input terminal side of the multi-stage delay circuit.

[0086] The input terminal of delay element 114-1 is fed with a trigger signal TRG. The trigger signal TRG changes from low to high, and the high-level signal propagates within delay element 114-1, causing signal D1 to change from low to high. Furthermore, for each integer i greater than 2 and less than q, the high-level signal Di-1 propagates within delay element 114-i, causing signal Di to change from low to high. That is, when the trigger signal TRG changes from low to high, the high-level signal propagates sequentially within delay elements 114-1 to 114-q, causing signals D1 to Dq to change sequentially from low to high.

[0087] Similarly, when the trigger signal TRG changes from high to low, the low-level signal propagates within delay element 114-1, causing signal D1 to change from high to low. Furthermore, for each integer i greater than 2 and less than q, the low-level signal Di-1 propagates within delay element 114-i, causing signal Di to change from high to low. That is, when the trigger signal TRG changes from high to low, the low-level signal propagates sequentially within delay elements 114-1 to 114-q, causing signals D1 to Dq to change sequentially from high to low.

[0088] Thus, the combination of the trigger signal TRG and the logic levels of the q signals D1 to Dq indicates the state of the multi-stage delay circuit, and the multi-stage delay circuit begins state transition based on the time event of the trigger signal TRG. The state of the multi-stage delay circuit corresponds to the internal state of the state transition unit 11, and the trigger signal TRG and the q signals D1 to Dq correspond to the state information indicating the internal state of the state transition unit 11.

[0089] The transition state acquisition unit 12 synchronously acquires and maintains the trigger signal TRG and q signals D1 to Dq as state information from the state transition unit 11 along with the reference signal RCLK. For example... Figure 11 As shown, in this embodiment, the transition state acquisition unit 12 includes a plurality of D flip-flops 122-0 to 122-q. The D flip-flops 122-0 acquire the trigger signal TRG synchronously with the rising edge of the reference signal RCLK and hold it as signal S0. Furthermore, for each integer i of 1 to q, the D flip-flops 122-i acquire the signal Di synchronously with the rising edge of the reference signal RCLK and hold it as signal Si.

[0090] The arithmetic unit 13 calculates a digital time value TD corresponding to the number of transitions of the internal state of the state transition unit 11 based on the state information, i.e., the count value DCNT, acquired and maintained by the transition state acquisition unit 12. Alternatively, the arithmetic unit 13 may calculate the digital time value TD synchronously with the reference signal RCLK, based on the accumulated value obtained by summing the number of transitions of the internal state of the state transition unit 11. The operation may be, for example, subtraction.

[0091] like Figure 11 As shown, in this embodiment, the arithmetic unit 13 includes an encoder 134, a conversion unit 135, an accumulator 136, an accumulator 137, a multiplier 138, and a subtractor 139.

[0092] The encoder 134 counts the number of high-level signals among the q signals S0 to Sq held by the transition state acquisition unit 12, and outputs a count value CNTX. That is, if there are j high-level signals among the signals S0 to Sq, the count value CNTX is j.

[0093] The conversion unit 135 converts the count value CNTX output from the encoder 134 into a count value CNT and outputs it. The count value CNT corresponds to the number of state transitions since the state transition unit 11 started transitioning based on the time event of the trigger signal TRG. When the time event of the trigger signal TRG is a rising edge, the count value CNTX corresponds to the number of state transitions of the state transition unit 11. Therefore, when the trigger signal TRG is high, the conversion unit 135 outputs the same count value CNT as CNTX. On the other hand, when the time event of the trigger signal TRG is a falling edge, the value obtained by subtracting the count value CNTX from q+1 corresponds to the number of state transitions of the state transition unit 11. Therefore, when the trigger signal TRG is low, the conversion unit 135 outputs the count value CNT obtained by subtracting the count value CNTX from q+1.

[0094] The accumulator 136 accumulates the count value CNT output from the converter 135 synchronously with the rising edge of the reference signal RCLK, and outputs the accumulated value ACNT.

[0095] Accumulator 137 increments by 1 synchronously with the rising edge of the reference signal RCLK. The accumulated value output from accumulator 137 indicates the total number of rising edges of the reference signal RCLK.

[0096] Multiplier 138 multiplies the accumulated value output from accumulator 137 by an integer N. The integer N is, for example, set to the upper limit of the count value CNT. The multiplied value of multiplier 138 is N times the total number of rising edges of the reference signal RCLK, and is a weighted value accumulated over time. That is, multiplier 138 outputs a weighting coefficient value WC.

[0097] The subtractor 139 outputs the value obtained by subtracting the accumulated value ACNT from the weighting coefficient value WC, which is used as the digital time value TD. This digital time value TD corresponds to the phase difference between the time events of the reference signal RCLK and the trigger signal TRG.

[0098] Figure 12 This is a timing diagram illustrating an example of the operation timing of the time-to-digital converter 10 in the second embodiment. Figure 12middle, Figure 11 The upper limit of the count value CNT and the integer N are both 64, and the integer q is 63. Additionally, the timing event of the reference signal RCLK is the rising edge, and the timing events of the trigger signal TRG are both the rising and falling edges.

[0099] exist Figure 12 In the example, a rising edge of the trigger signal TRG is generated between the first and second rising edges of the reference signal RCLK, and the state transition unit 11 begins a state transition. Then, when the count value CNTX increases synchronously with the rising edges of the reference signal RCLK, as in the order of 4, 12, 20, 29, 37, 45, 53, 62, and reaches the upper limit value of 64, the state transition unit 11 stops the state transition. The count value CNT also increases as in the order of 4, 12, 20, 29, 37, 45, 53, 62 and reaches the upper limit value of 64. Accompanying this, the accumulated value ACNT increases as in the order of 0, 4, 16, 36, 65, 102, 147, 200, 262, 326, 390. Furthermore, the weighting coefficient value WC increases synchronously with the rising edge of the reference signal RCLK, as shown in the figures 64, 128, 192, 256, 320, 384, 448, 512, 576, 640, and 704. As a result, the digital time value TD increases as shown in the figures 64, 124, 176, 220, 255, 282, 301, 312, and 314, and remains at 314.

[0100] In addition, Figure 12 In the example, a falling edge of the trigger signal TRG is generated between the 12th and 13th rising edges of the reference signal RCLK, and the state transition unit 11 initiates the state transition. Then, the count value CNTX decreases synchronously with the rising edges of the reference signal RCLK as follows: 62, 54, 45, 37, 29, 21, 14, 4. When it reaches the lower limit of 0, the state transition unit 11 stops the state transition. The count value CNT increases as follows: 2, 10, 19, 27, 35, 43, 51, 60, reaching the upper limit of 64. Simultaneously, the accumulated value ACNT increases as follows: 0, 2, 12, 31, 58, 93, 136, 187, 247, 311, 375. Furthermore, the weighting coefficient value WC increases synchronously with the rising edge of the reference signal RCLK, as shown in the figures 768, 832, 896, 960, 1024, 1088, 1152, 1216, 1280, 1344, and 1408. As a result, the digital time value TD increases as shown in the figures 768, 830, 884, 929, 966, 995, 1016, 1029, and 1033, and remains at 1033.

[0101] In addition, Figure 12In the example, a rising edge of the trigger signal TRG is generated between the 23rd and 24th rising edges of the reference signal RCLK, and the state transition unit 11 initiates a state transition. Then, the count value CNTX increases synchronously with the rising edges of the reference signal RCLK, as in the order of 1, 9, 17, 26, and 34. The count value CNT also increases synchronously with the rising edges of the reference signal RCLK, as in the order of 1, 9, 17, 26, and 34, and simultaneously, the accumulated value ACNT increases synchronously with the rising edges of the reference signal RCLK, as in the order of 0, 1, 10, 27, and 53. Furthermore, the weighting coefficient value WC increases synchronously with the rising edges of the reference signal RCLK, as in the order of 1472, 1536, 1600, 1664, and 1728. As a result, the time digital value TD increases synchronously with the rising edges of the reference signal RCLK, as in the order of 1472, 1535, 1590, 1637, and 1675.

[0102] The frequency synthesizer 1 of the second embodiment described above can achieve the same effect as the first embodiment.

[0103] Furthermore, in the frequency synthesizer 1 of the second embodiment, the state transition unit 11 includes a multi-stage delay circuit with multiple delay elements 114-1 to 114-q having a propagation trigger signal TRG. Therefore, according to the frequency synthesizer 1 of the second embodiment, the number of internal states of the state transition unit 11 can be increased according to the number of delay elements 114-1 to 114-q, thereby improving the phase detection resolution of the time-to-digital converter 10 and improving the synthesized signal S. VCO Frequency accuracy.

[0104] Alternatively, a loop can be formed in the multi-stage delay circuit of the state transition unit 11 so that the signal Dq output from the delay element 114-q is input to the delay element 114-1 during the period when the logic level of the trigger signal TRG is constant. In this case, the arithmetic unit 13 can count the number of times the trigger signal TRG propagates in the multi-stage delay circuit, and calculate the digital time value TD based on the count value and the signals S0 to Sq. In this way, the number of delay elements 114-1 to 114-q or D flip-flops 122-0 to 122-q can be reduced.

[0105] 3. Third Implementation Method

[0106] Hereinafter, regarding the frequency synthesizer 1 of the third embodiment, the same reference numerals are used for the same constituent elements as in the first or second embodiment, and descriptions that are repeated in the first or second embodiment are omitted or simplified. The description will mainly focus on the differences from the first and second embodiments.

[0107] In the frequency synthesizer 1 of the third embodiment, similar to the frequency synthesizer 1 of the second embodiment, the time-to-digital converter 10 includes a state transition unit 11 including a multi-stage delay circuit, a transition state acquisition unit 12 for acquiring the input signal and multiple output signals of the multi-stage delay circuit, and an arithmetic unit 13.

[0108] In the second embodiment, the time-to-digital converter 10 operates normally when the time interval between two consecutive time events of the trigger signal TRG is longer than the time for the state transition unit 11 to transition from the start state to the stop state. That is, in the second embodiment, when the time interval between two consecutive time events of the trigger signal TRG is longer than the propagation time of the trigger signal TRG within the multi-stage delay circuit included in the transition state acquisition unit 12, the multi-stage delay circuit performs a state transition based on one time event of the trigger signal TRG, thereby calculating the correct digital time value TD. In contrast, in the third embodiment, the time-to-digital converter 10 operates normally when the time interval between two consecutive time events of the trigger signal TRG is longer than half the time for the state transition unit 11 to transition from the start state to the stop state. That is, in the third embodiment, when the time interval between two consecutive time events of the trigger signal TRG is longer than half the propagation time of the trigger signal TRG within the multi-stage delay circuit included in the transition state acquisition unit 12, and the multi-stage delay circuit performs a state transition based on two or fewer time events of the trigger signal TRG, the correct digital time value TD can be calculated.

[0109] In the time-to-digital converter 10 of the third embodiment, the state transition unit 11 and the transition state acquisition unit 12 are configured the same as in the second embodiment, but the configuration of the arithmetic unit 13 is different from that in the second embodiment. Figure 13 This is a diagram showing an example of the configuration of the arithmetic unit 13 in the third embodiment. Furthermore, Figure 13 This paper shows an example of the configuration of the arithmetic unit 13 when 64 signals S0 to S63 are output from the transition state acquisition unit 12, i.e., when q = 63. However, q can also be a number other than 63. Furthermore, in Figure 13 In this signal, the 64-bit signal S[63:0] is equivalent to 64 signals S63 to S0. Furthermore, the upper 32 bits of signal S[63:32] are equivalent to 32 signals S63 to S32, and the lower 32 bits of signal S[63:0] are equivalent to 32 signals S31 to S0. Additionally, the most significant bit of signal S

[63] is equivalent to signal S63, and the least significant bit of signal S[63:0] is equivalent to signal S0.

[0110] like Figure 13As shown, the arithmetic unit 13 in the third embodiment includes a bit separation unit 201, logic inversion circuits 202 and 203, selectors 204, 205, 206 and 207, selection signal generation units 208 and 209, Σ calculation units 210 and 211, Σ integration unit 212, accumulator 213, multiplier 214, accumulator 215, subtractor 216, latch circuit 217, accumulator 218, subtractor 219, latch circuit 220, and TD selection unit 221.

[0111] The bit separation unit 201 separates the signal S[63:0] into a lower 32-bit signal S[31:0] and a higher 32-bit signal S[63:32] and outputs them. In addition, the bit separation unit 201 outputs the least significant bit signal S[0] and the most significant bit signal S

[63] of the signal S[63:0].

[0112] The logic inversion circuit 202 outputs a 32-bit logic inverted signal after inverting the logic levels of the 32-bit signals S[63:32] output from the bit separation section 201.

[0113] The logic inversion circuit 203 outputs a 32-bit logic inverted signal after inverting the logic levels of the 32-bit signals S[31:0] output from the bit separation section 201.

[0114] Selector 204 selects the upper-level selection signal Sel output from selection signal generation unit 208. 10up Choose either the 32-bit signal S[63:32] or the 32-bit inverted logic signal output from the logic inversion circuit 202 as the 64-bit signal S. 10 The upper 32 bits of the signal S of [63:0] 10 [63:32] Output.

[0115] Selector 205 selects the lower-order selection signal Sel output from selection signal generation unit 208. 10low Choose any one of the following: a 32-bit high-level signal with each bit having a logic value of 1, a 32-bit signal S[31:0], and a 32-bit logic inverted signal output from the logic inversion circuit 203, and use it as the 64-bit signal S. 10 The lower 32 bits of the signal S of [63:0] 10 [31:0] Output.

[0116] Selector 206 selects the upper-level selection signal Sel output from selection signal generation unit 209. 01upChoose any one of the following: the 32-bit inverted logic signal output from the logic inversion circuit 202, the 32-bit signal S[63:32], and the 32-bit high-level signal with each bit having a logic value of 1, as the 64-bit signal S. 01 The upper 32 bits of the signal S of [63:0] 01 [63:32] Output.

[0117] Selector 207 selects the lower-order selection signal Sel output from selection signal generation unit 209. 01low Choose either the 32-bit inverted logic signal output from logic inversion circuit 203 or the 32-bit signal S[31:0] as the 64-bit signal S. 01 The lower 32 bits of the signal S of [63:0] 01 [31:0] Output.

[0118] The selection signal generation unit 208 generates and outputs the upper bit selection signal Sel based on the signals S[0] and S

[63] output from the bit separation unit 201. 10up and lower-level selection signal Sel 10low Specifically, when the logic value of signal S[0] is different from the logic value of signal S

[63] , the selection signal generation unit 208 outputs a higher-order selection signal Sel that causes selector 204 to select the 32-bit signal S[63:32] and selector 205 to select the 32-bit signal S[31:0]. 10up and lower-level selection signal Sel 10low Additionally, when the logic values ​​of signal S[0] and signal S

[63] are both 0, the selection signal generation unit 208 outputs a higher-order selection signal Sel that causes selector 204 to select the 32-bit signal S[63:32] and selector 205 to select the 32-bit high-level signal. 10up and lower-level selection signal Sel 10low Additionally, when the logic values ​​of signal S[0] and signal S

[63] are both 1, the selection signal generation unit 208 outputs a logic inverted signal that causes selector 204 to select the 32-bit signal S[63:32], and a higher-order selection signal Sel that causes selector 205 to select the 32-bit high-level signal. 10up and lower-level selection signal Sel 10low .

[0119] The selection signal generation unit 209 generates and outputs the upper bit selection signal Sel based on the signals S[0] and S

[63] output from the bit separation unit 201. 01up and lower-level selection signal Sel 01lowSpecifically, when the logic values ​​of signal S[0] and signal S

[63] are different, the selection signal generation unit 209 outputs a higher-order selection signal Sel that causes selector 206 to select the 32-bit signal S[63:32] and selector 207 to select the 32-bit signal S[31:0]. 01up and lower-level selection signal Sel 01low Additionally, when the logic values ​​of signal S[0] and signal S

[63] are both 0, the selection signal generation unit 209 outputs a higher-level selection signal Sel that causes selector 206 to select a 32-bit high-level signal and selector 207 to select a 32-bit signal S[31:0]. 01up and lower-level selection signal Sel 01low Additionally, when the logic values ​​of signal S[0] and signal S

[63] are both 1, the selection signal generation unit 209 outputs a higher-order selection signal Sel that causes selector 206 to select the 32-bit high-level signal and selector 207 to select the 32-bit inverted signal S[31:0]. 01up and lower-level selection signal Sel 01low .

[0120] The Σ calculation unit 210 is input with a 32-bit signal S output from the selector 204. 10 [63:32] and the 32-bit signal S output from selector 205 10 The 64-bit signal S formed by [31:0] 10 [63:0], for signal S 10 The count value Σ10′ is calculated by counting the number of bits with a logic value of 1 in [63:0]. Then, the Σ calculation unit 210 calculates the signal S of the least significant bit. 10 When the logic value of [0] is 1, the count value Σ will be... 10 ′ as the count value Σ 10 Output, the signal S in the least significant bit 10 When the logical value of [0] is 0, the count value Σ will be subtracted from 64. 10 The obtained value is used as the count value Σ. 10 Output.

[0121] The Σ calculation unit 211 is input with a 32-bit signal S output from the selector 206. 01 [63:32] and the 32-bit signal S output from selector 207 01 The 64-bit signal S formed by [31:0] 01 [63:0], for signal S 01 The count value Σ is calculated by counting the number of bits with a logic value of 1 in [63:0]. 01Then, the Σ calculation part 211 calculates the signal S in the least significant bit. 01 When the logic value of [0] is 1, the count value Σ will be... 01 ′ as the count value Σ 01 Output, the signal S in the least significant bit 01 When the logical value of [0] is 0, the count value Σ will be subtracted from 64. 01 The obtained value is used as the count value Σ. 01 Output.

[0122] When the logic values ​​of both signal S[0] and signal S

[63] are 0, the Σ integration unit 212 will count the value Σ. 10 As the count value Σ i The output will be the count value Σ when the logic value of signal S[0] is 1. 01 As the count value Σ i The output will use 64 as the count value Σ when the logic value of signal S[0] is 0 and the logic value of signal S

[63] is 1. i Output. Additionally, the Σ integration unit 212 will output the count value Σ when both the logic values ​​of signal S[0] and signal S

[63] are 1. 10 As the count value Σ j The output will be the count value Σ when the logic value of signal S[0] is 0. 01 As the count value Σ j The output will use 64 as the count value Σ when the logic value of signal S[0] is 1 and the logic value of signal S

[63] is 0. j Output: Count value Σ i This is the number of times the internal state of the state transition unit 11 transitions from the state transition unit 11 at the rising edge of the trigger signal TRG to each rising edge of the reference signal RCLK during the period. Additionally, the count value Σ... j The number of times the internal state of the state transition unit 11 transitions from the falling edge of the trigger signal TRG to each rising edge of the reference signal RCLK during the period.

[0123] Accumulator 213 increments by 1 synchronously with the rising edge of the reference signal RCLK. The accumulated value output from accumulator 213 indicates the total number of rising edges of the reference signal RCLK.

[0124] Multiplier 214 multiplies the accumulated value output from accumulator 213 by 64. 64 is the count value Σ. i The upper limit of the multiplication factor is N times the total number of rising edges of the reference signal RCLK, which is a weighted value accumulated over time. That is, the multiplier 214 outputs the weighting coefficient value WC.

[0125] Accumulator 215 synchronously increments the count value Σ with the rising edge of the reference signal RCLK. i Accumulate and output the accumulated value ΣA i Accumulated value ΣA i The accumulator 215 accumulates the number of state transitions of the internal state of the state transition unit 11 during the period from the rising edge of the trigger signal TRG to each rising edge of the reference signal RCLK. i Accumulate a specified number of times. Whenever the logic value of signal S[0] changes from 0 to 1, the accumulated value ΣA is incremented. i Initialize to 0.

[0126] The output of subtractor 216 is the sum of the weighted coefficients WC and ΣA. i The value obtained.

[0127] The latch circuit 217 is composed of multiple D flip-flops, and is connected to the timing signal TM output from the Σ integration unit 212. i The rising edge synchronously acquires the value output from subtractor 216 as the digital time value TD. i Maintain. For example, when the logic value of signal S[0] changes from 0 to 1, the Σ integration unit 212 will maintain the timing signal TM. i Set to high level, when the logic value of signal S[0] changes from 1 to 0, the timing signal TM will be activated. i Set to low level. Digital time value TD i It becomes a value corresponding to the phase difference between the rising edge of the reference signal RCLK and the rising edge of the trigger signal TRG.

[0128] Accumulator 218 accumulates the count value Σ synchronously with the rising edge of the reference signal RCLK. j Output the accumulated value ΣA j Accumulated value ΣA j The accumulator 218 accumulates the number of times the internal state of the state transition unit 11 transitions from the state transition unit 11 at the falling edge of the trigger signal TRG to each rising edge of the reference signal RCLK. j Accumulate a specified number of times. Whenever the logic value of signal S[0] changes from 1 to 0, the accumulated value ΣA is incremented. j Initialize to 0.

[0129] Subtractor 219 outputs the sum of its weights WC and ΣA. j The value obtained.

[0130] The latch circuit 220 is composed of multiple D flip-flops, and is connected to the timing signal TM output from the Σ integration unit 212. jThe rising edge synchronously acquires the value output from subtractor 219 and uses it as the digital time value TD. j Maintain. For example, when the logic value of signal S[0] changes from 1 to 0, the Σ integration unit 212 will maintain the timing signal TM. j Set to high level, when the logic value of signal S[0] changes from 0 to 1, the timing signal TM will be activated. j Set to low level. Digital time value TD j It becomes a value corresponding to the phase difference between the rising edge of the reference signal RCLK and the falling edge of the trigger signal TRG.

[0131] The TD selection unit 221 selects the digital time value TD based on the trigger signal TRG. i and time digital value TD j The TD selection unit 221 selects the digital time value TD when the trigger signal TRG is low. j When the trigger signal TRG is high, the digital time value TD is selected. i .

[0132] exist Figure 14 The diagram shows the signal S[63:0] and the count value Σ that change due to the state transition of the state transition unit 11. 10 ′、Σ 01 ′、Σ 10 Σ 01 , Σ i , Σ j Accumulated value ΣA i ΣA j Weighting coefficient value WC and time digital value TD i TD j An example of the relationship between TD.

[0133] Furthermore, the signal generation units 208 and 209, the Σ calculation units 210 and 211, the Σ integration unit 212, and the accumulators 213, 215, and 218 can all operate synchronously with the falling edge of the reference signal RCLK, or they can operate synchronously with both the rising and falling edges of the reference signal RCLK.

[0134] The frequency synthesizer 1 according to the third embodiment described above can achieve the same effect as the first or second embodiment.

[0135] Furthermore, in the frequency synthesizer 1 of the third embodiment, the multi-stage delay circuit included in the state transition unit 11 performs state transitions based on two or fewer time events of the trigger signal TRG. That is, the time required for the trigger signal TRG to propagate from the input terminal of the multi-stage delay circuit to the final output terminal, i.e., the delay time of the multi-stage delay circuit, is shorter than one cycle of the trigger signal TRG. Therefore, according to the frequency synthesizer 1 of the third embodiment, the number of transitions of the internal state of the state transition unit 11 based on the respective time events of the trigger signal TRG can be easily separated into a count value Σ. i and count value Σ j Therefore, the synthesized signal S can be improved without complex calculations in the calculation of the digital time value TD. VCO Frequency accuracy.

[0136] also, Figure 13 When the delay time of the multi-stage delay circuit is longer than half a period of the trigger signal TRG but shorter than one period of the trigger signal TRG, the arithmetic unit 13, configured in this way, separates the number of internal state transitions of the state transition unit 11 into two count values ​​Σ. i , Σ j This can also be extended. For any integer n greater than or equal to 1, the arithmetic unit 13 can be configured such that, when the delay time of the multi-stage delay circuit is longer than n / 2 periods of the trigger signal TRG but shorter than (n+1) / 2 periods of the trigger signal TRG, the number of transitions of the internal state of the state transition unit 11 is separated into n+1 count values ​​Σ. i , Σ j .

[0137] 4. Fourth Implementation Method

[0138] Hereinafter, regarding the frequency synthesizer 1 of the fourth embodiment, the same reference numerals are used for the same constituent elements as in any of the first to third embodiments, and descriptions that are repeated in any of the first to third embodiments are omitted or simplified. The descriptions will mainly focus on the contents that are different from the first to third embodiments.

[0139] In the frequency synthesizer 1 of the fourth embodiment, similar to the frequency synthesizer 1 of the second or third embodiment, the time-to-digital converter 10 includes a state transition unit 11 including a multi-stage delay circuit, a transition state acquisition unit 12 for acquiring the input signal and multiple output signals of the multi-stage delay circuit, and an arithmetic unit 13.

[0140] In the time-to-digital converter 10 of the second or third embodiment, in the multi-stage delay circuit included in the state transition unit 11, the trigger signal TRG propagates sequentially within multiple delay elements 114-1 to 114-q, and the transition state acquisition unit 12 acquires the trigger signal TRG as state information and the output signals of the delay elements 114-1 to 114-q. In contrast, in the time-to-digital converter 10 of the fourth embodiment, in the multi-stage delay circuit, the trigger signal TRG branches and propagates within multiple delay elements 114-1 to 114-r, and the transition state acquisition unit 12 acquires the trigger signal TRG as state information and the output signals of the delay elements 114-1 to 114-r. r is an integer greater than or equal to 2 and is an integer greater than q.

[0141] In the time-to-digital converter 10 of the fourth embodiment, the configuration of the transition state acquisition unit 12 and the calculation unit 13 is the same as that of the second or third embodiment, but the configuration of the state transition unit 11 is different from that of the second and third embodiments.

[0142] Figure 15 , Figure 16 as well as Figure 17 These are diagrams showing examples of the configuration of the state transition unit 11 in the third embodiment. Figure 15 , Figure 16 as well as Figure 17 In the example, the multi-stage delay circuit of the state transition unit 11 includes r delay elements 114-1 to 114-r. The delay times of the delay elements 114-1 to 114-r are set to be approximately equal.

[0143] exist Figure 15 , Figure 16 as well as Figure 17 In the example, the trigger signal TRG branches and is input to four delay elements 114-1 to 114-4. The wiring lengths from the branch point to the input terminals of the four delay elements 114-1 to 114-4 are different from each other. Due to the difference in delay of these wirings, the timing event of the trigger signal TRG first arrives at the input terminal of delay element 114-1, then at the input terminal of delay element 114-2, then at the input terminal of delay element 114-3, and finally at the input terminal of delay element 114-4.

[0144] exist Figure 15In the example, the multi-stage delay circuit has: a signal path in which the trigger signal TRG propagates in the order of delay element 114-1, delay element 114-5, delay element 114-9, ..., delay element 114-(r-3); a signal path in which the trigger signal TRG propagates in the order of delay element 114-2, delay element 114-6, delay element 114-10, ..., delay element 114-(r-2); a signal path in which the trigger signal TRG propagates in the order of delay element 114-3, delay element 114-7, delay element 114-11, ..., delay element 114-(r-1); and a signal path in which the trigger signal TRG propagates in the order of delay element 114-4, delay element 114-8, delay element 114-12, ..., delay element 114-r.

[0145] exist Figure 16 In the example, the multi-stage delay circuit has: a signal path in which the trigger signal TRG propagates in the order of delay element 114-1, delay element 114-5, delay element 114-9, ..., delay element 114-(r-3); a signal path in which the trigger signal TRG propagates in the order of delay element 114-2, delay element 114-6, delay element 114-10, ..., delay element 114-(r-2); and a signal path in which the trigger signal TRG propagates in the order of delay element 114-2, delay element 114-7, delay element 114-1 1. The signal path of the delay element 114-(r-1) in sequence; the signal path of the trigger signal TRG in the order of delay element 114-2, delay element 114-7, delay element 114-12, ..., delay element 114-r; the signal path of the trigger signal TRG in the order of delay element 114-2, delay element 114-8; the signal path of the trigger signal TRG in delay element 114-3; and the signal path of the trigger signal TRG in delay element 114-4.

[0146] exist Figure 17In the example, the multi-stage delay circuit has the following signal paths: the trigger signal TRG propagates in the order of delay elements 114-1, 114-5, 114-9, 114-13, ..., 114-(r-3); the trigger signal TRG propagates in the order of delay elements 114-1, 114-6, 114-10, 114-14, ..., 114-(r-2); the trigger signal TRG propagates in the order of delay elements 114-1, 114-6, 114-11, 114-15, ..., 114-(r-1); the trigger signal TRG propagates in the order of delay elements 114-1, ..., 114-(r-1). The signal paths of delay elements 114-6, 114-11, 114-16, ..., 114-r in sequence; the signal paths of trigger signal TRG in the order of delay elements 114-1, 114-6, 114-15; the signal paths of trigger signal TRG in the order of delay elements 114-1, 114-7; the signal paths of trigger signal TRG in the order of delay elements 114-1, 114-8; the signal paths of trigger signal TRG within delay element 114-2; the signal paths of trigger signal TRG within delay element 114-3; and the signal paths of trigger signal TRG within delay element 114-4.

[0147] exist Figure 15 , Figure 16 as well as Figure 17 In the example, when the signals at the input terminals of delay elements 114-1 to 114-4 are set to D0 to D3, and the output signal of delay element 114-j is set to Dj+3 for each integer j greater than 1 and less than r, a timing event triggering signal TRG is generated. Accompanying this, for example, timing events are generated in the order of signals D0, D1, D2, and Dr. That is, signals D0 to Dr are state information indicating the internal state of the state transition unit 11. The transition state acquisition unit 12 acquires signals D0 to Dr as state information and outputs signals S0 to Sr. Then, the calculation unit 13 calculates the digital time value TD based on signals S0 to Sr. Here, in Figure 15 , Figure 16 as well as Figure 17 In the example, when the number r of delay elements included in the state transition unit 11 is set to Figure 11 or Figure 13 When the number of delay elements q included in the state transition unit 11 is four times, the number of internal states also becomes four times.

[0148] Furthermore, the number of delay elements or branch locations included in a multi-stage delay circuit, the number of signal paths for the propagation trigger signal TRG, etc., are not limited to... Figure 15 , Figure 16 as well as Figure 17 Examples can be selected appropriately.

[0149] The frequency synthesizer 1 according to the fourth embodiment described above can achieve the same effect as any of the embodiments in the first to third embodiments.

[0150] Furthermore, in the frequency synthesizer 1 of the fourth embodiment, after the trigger signal TRG branches in the state transition unit 11, it propagates within multiple delay elements 114-1 to 114-r. Therefore, compared to the second or third embodiment, the number of internal states in the state transition unit 11 increases, resulting in improved resolution of the state information acquired by the transition state acquisition unit 12 and improved accuracy of the time digital value TD calculated by the calculation unit 13. Thus, according to the frequency synthesizer 1 of the fourth embodiment, a synthesized signal S with higher frequency accuracy than that of the second or third embodiment can be generated based on the time digital value TD output from the time-to-digital converter 10. VCO .

[0151] 5. Fifth Implementation Method

[0152] Hereinafter, for the frequency synthesizer 1 of the fifth embodiment, the same reference numerals are used for the same constituent elements as in any of the first to fourth embodiments, and descriptions that are repeated in any of the first to fourth embodiments are omitted or simplified. The descriptions will mainly focus on the contents that are different from the first to fourth embodiments.

[0153] Figure 18 This is a block diagram illustrating a configuration example of the frequency synthesizer 1 according to the fifth embodiment. Additionally, Figure 19 This is a block diagram illustrating other configuration examples of the frequency synthesizer 1 according to the fifth embodiment. For example... Figure 18 and Figure 19 As shown, the frequency synthesizer 1 of the fifth embodiment is the same as that of the first to fourth embodiments, including a time-to-digital converter 10, a comparison unit 20, a frequency adjustment unit 30, and an oscillation unit 40.

[0154] The time-to-digital converter 10 is input with a reference period signal S ref and the synthesized signal S VCO When using the reference period signal S ref and the synthesized signal S output from the oscillator 40 VCOWhen the shorter-period signal is used as the reference signal RCLK and the longer-period signal is used as the trigger signal TRG, the output is the digital time value TD corresponding to the time event of the trigger signal TRG relative to the reference signal RCLK. The reference period signal S... ref For example, it can be a signal input from outside the frequency synthesizer 1, or a signal generated by an oscillation circuit (not shown) of the frequency synthesizer 1.

[0155] exist Figure 18 In the example, the reference periodic signal S ref and the synthesized signal S VCO The signal with a shorter period in the middle is the synthesized signal S. VCO The signal with a longer period is the reference periodic signal S. ref Therefore, the time-to-digital converter 10 outputs a synthesized signal S. VCO The reference signal RCLK is used as the reference period signal S. ref The digital value TD represents the time when the trigger signal TRG is activated. Conversely, in... Figure 19 In the example, the reference periodic signal S ref and the synthesized signal S VCO The shorter-period signal in the middle is the reference periodic signal S. ref The signal with a longer period is the synthesized signal S. VCO Therefore, the time-to-digital converter 10 outputs a reference periodic signal S. ref The reference signal RCLK is used as the reference signal and the synthesized signal S is used as the synthesized signal. VCO The digital value TD represents the time when the trigger signal TRG is activated.

[0156] In the fifth embodiment, similar to the first to fourth embodiments, the time-to-digital converter 10 functions as a phase detection unit that outputs a digital time value TD corresponding to the phase difference between the time event of the reference signal RCLK and the time event of the trigger signal TRG. The detailed configuration example of the time-to-digital converter 10 is the same as in any of the first to fourth embodiments, therefore its illustrations and descriptions are omitted.

[0157] The digital time value TD output from the time-to-digital converter 10 is used as the phase signal P. VCO The input is given to the comparison unit 20. The comparison unit 20 compares the signals based on the phase signal P. VCOThe comparison unit 20 compares the held digital time value TD with the target value and outputs an error signal ε as a comparison result. In this embodiment, the comparison unit 20 compares the held digital time value TD with the accumulated value of the set value FCW, and outputs the difference between the held digital time value TD and the accumulated value of the set value FCW as an error signal ε. That is, in this embodiment, the value of the held digital time value TD, which is one of the comparison objects of the comparison unit 20, is the value of the held digital time value TD, and the target value, which is the other comparison object, is the accumulated value of the set value FCW. The set value FCW is a value determined based on a preset multiplication ratio or division ratio, and can be the value of a signal input from outside the frequency synthesizer 1, or the value after reading data pre-stored by a storage unit (not shown) of the frequency synthesizer 1.

[0158] like Figure 18 and Figure 19 As shown, for example, the comparison unit 20 includes a latch circuit 24 formed by multiple D flip-flops, an accumulator 25, and a subtractor 26. The latch circuit 24 and the accumulator 25 are referenced to the periodic signal S. ref and the synthesized signal S VCO The signal with the longer period in the sample is the sampling signal S. s Action. The sampled signal S input to latch circuit 24 and accumulator 25. s exist Figure 18 In the example, the reference periodic signal S ref ,exist Figure 19 The example is the synthesized signal S. VCO The latch circuit 24 and the sampling signal S s The rising edge is synchronously acquired and held as the phase signal P. VCO The digital value of the time TD. Accumulator 25 and sampled signal S s The setpoint FCW is accumulated synchronously with the rising edge of the signal. Furthermore, the latch circuit 24 and the accumulator 25 can also be synchronized with the sampling signal S. s The subtractor 26 operates synchronously with the falling edge of the latch circuit. The subtractor 26 outputs an error signal ε, which is equivalent to the difference between the time digital value TD held by the latch circuit 24 and the accumulated value of the setpoint FCW held by the accumulator 25. When the time digital value TD is the same as the accumulated value of the setpoint FCW, the error signal ε is zero; when the time digital value TD is greater than the accumulated value of the setpoint FCW, the error signal ε is positive; and when the time digital value TD is less than the accumulated value of the setpoint FCW, the error signal ε is negative.

[0159] The frequency adjustment unit 30 adjusts the synthesized signal S based on the error signal ε, which is the comparison result of the comparison unit 20. VCO frequency f VCOIn this embodiment, the frequency adjustment unit 30 outputs an adjustment signal S based on the error signal ε. VCO frequency f VCO The control signal VC.

[0160] In this embodiment, the frequency adjustment unit 30 adjusts the synthesized signal S based on the error signal ε. VCO frequency f VCO This ensures that the difference between the accumulated value of the time digital value TD and the accumulated value of the set value FCW, which serves as the target value for the accumulated value, remains constant. The frequency adjustment unit 30 can also adjust the frequency f. VCO To ensure that the difference between the accumulated value of the time digital value TD and the set value FCW is zero, the frequency f can also be adjusted. VCO This ensures that the difference between the accumulated value of the time digital value TD and the set value FCW becomes a constant value, either positive or negative. The detailed configuration example of the frequency adjustment unit 30 is the same as any of the embodiments in the first to fourth embodiments, therefore its illustrations and descriptions are omitted.

[0161] The oscillation unit 40 generates a synthesized signal S based on the control signal VC output from the frequency adjustment unit 30. VCO For example, the oscillation unit 40 may include a voltage-controlled oscillator (not shown) that outputs a signal with a frequency corresponding to the voltage value of the control signal VC. The oscillation unit 40 may use the output signal of this voltage-controlled oscillator as a synthesized signal S. VCO The output may also include a frequency divider (not shown) that divides the output signal of the voltage-controlled oscillator, with the output signal of the frequency divider serving as the synthesized signal S. VCO Output.

[0162] In such Figure 18 or Figure 19 In the frequency synthesizer 1 of the fifth embodiment configured as described above, the frequency adjustment unit 30 adjusts the synthesized signal S. VCO frequency f VCO This keeps the difference between the accumulated value of the time digital value TD and the set value FCW constant, thereby forming a reference period signal S. ref With the synthesized signal S VCO The phase difference is constant, and the synthesized signal S VCO A stable PLL at the desired frequency.

[0163] As explained above, in the frequency synthesizer 1 of the fifth embodiment, the time-to-digital converter 10 outputs a time digital value TD corresponding to the time event of the trigger signal TRG relative to the reference signal RCLK, where the reference signal RCLK is a reference period signal S. ref and the synthesized signal S VCOThe signal with a shorter period in the signal is the trigger signal TRG, which is a signal with a longer period. Furthermore, the comparison unit 20 compares the value of the held time digital value TD with the target value of the accumulated value of the set value FCW, and the frequency adjustment unit 30 adjusts the synthesized signal S. VCO The frequency of the time-to-digital converter (TD) is such that the difference between the digital time value (TD) and the target value remains constant. Therefore, the time-to-digital converter 10 serves as the detection reference period signal S. ref With the synthesized signal S VCO The phase difference detection unit functions as a PLL, which is formed by a time-to-digital converter 10, a comparator 20, a frequency adjustment unit 30, and an oscillator 40, thus enabling the output of a synthesized signal S at the desired frequency. VCO Furthermore, the time-to-digital converter 10 has a relatively simple configuration, including a state transition unit 11, a transition state acquisition unit 12, and an arithmetic unit 13. By increasing the number of bits in the time digital value TD, the phase detection resolution is improved, thus enhancing the synthesis signal S. VCO The frequency accuracy is high. Therefore, according to the frequency synthesizer 1 of the fifth embodiment, compared with the frequency synthesizer that uses a circuit with multiple frequency ΔΣ modulation units arranged in parallel to replace the time-to-digital converter 10, it is able to output a synthesized signal S with high frequency accuracy while suppressing the increase in circuit size. VCO .

[0164] In addition, the frequency synthesizer 1 according to the fifth embodiment can achieve the same effect as any of the embodiments in the first to fourth embodiments.

[0165] This invention is not limited to this embodiment, and various modifications can be implemented within the scope of the spirit of this invention.

[0166] The above describes the implementation methods and variations, but the present invention is not limited to these implementation methods and can be implemented in various ways without departing from its spirit. For example, the above implementation methods can also be appropriately combined.

[0167] This invention includes configurations that are substantially the same as those described in the embodiments, such as configurations with the same function, method, and result, or configurations with the same purpose and effect. Additionally, this invention includes configurations that replace non-essential parts of the configurations described in the embodiments. Furthermore, this invention includes configurations that can achieve the same effect as those described in the embodiments or that can achieve the same purpose. Additionally, this invention includes configurations that incorporate known technology into the configurations described in the embodiments.

[0168] The following can be derived from the above implementation methods and variations.

[0169] One solution for a frequency synthesizer includes:

[0170] A time-to-digital converter is input to a reference period signal and a composite signal. When the shorter period signal is used as the reference signal and the longer period signal is used as the trigger signal, the converter outputs a digital time value corresponding to the time event of the trigger signal relative to the reference signal.

[0171] The comparison unit compares the value of the digital time value output from the time-to-digital converter with the target value;

[0172] The oscillator generates the synthesized signal; and

[0173] The frequency adjustment unit adjusts the frequency of the synthesized signal based on the comparison result from the comparison unit.

[0174] The time-to-digital converter has the following features:

[0175] The state transition unit initiates the internal state transition based on the time event of the trigger signal and outputs state information showing the internal state.

[0176] A transition state acquisition unit acquires and maintains the state information synchronously with the reference signal from the state transition unit; and

[0177] The calculation unit calculates the time value corresponding to the number of transitions of the internal state based on the state information obtained by the transition state acquisition unit.

[0178] In this frequency synthesizer, the time-to-digital converter (TD-RCD) outputs a digital time value corresponding to the time event of the trigger signal relative to a reference signal. The reference signal is the shorter-period signal between the reference periodic signal and the synthesized signal, while the trigger signal is the longer-period signal. Therefore, the TD-RCD functions as a phase detection unit to detect the phase difference between the reference periodic signal and the synthesized signal, and can output a synthesized signal with the desired frequency through the TD-RCD, comparison unit, frequency adjustment unit, and oscillation unit. Furthermore, the TD-RCD has a relatively simple configuration including a state transition unit, a transition state acquisition unit, and an arithmetic unit, and by increasing the number of bits in the digital time value, the phase detection resolution is improved, thus enhancing the frequency accuracy of the synthesized signal. Therefore, according to this frequency synthesizer, compared to a frequency synthesizer using a circuit with multiple frequency ΔΣ modulation units arranged in parallel to replace the TD-RCD, a signal with high frequency accuracy can be output while suppressing the increase in circuit size.

[0179] In one embodiment of the frequency synthesizer, it could also be that...

[0180] The comparison unit compares the change in the digital time value with a target value determined based on a preset octave ratio or divider ratio, and outputs the difference between the change in the digital time value and the target value as the comparison result.

[0181] The frequency adjustment unit adjusts the frequency of the synthesized signal to keep the difference constant.

[0182] According to this frequency synthesizer, an FLL is formed by a time-to-digital converter, a comparator, a frequency adjustment unit, and an oscillator. Therefore, the synthesized signal is stable when it reaches the desired frequency.

[0183] In one embodiment of the frequency synthesizer, it could also be that...

[0184] The comparison unit compares the value held by the digital time value with the target value determined based on a preset octave ratio or divider ratio, and outputs the difference between the held digital time value and the target value as the comparison result.

[0185] The frequency adjustment unit adjusts the frequency of the synthesized signal to keep the difference constant.

[0186] According to this frequency synthesizer, a PLL is formed by a time-to-digital converter, a comparator, a frequency adjustment unit, and an oscillator. Therefore, the phase difference between the reference periodic signal and the synthesized signal is constant, and the synthesized signal is stable when it reaches the desired frequency.

[0187] In one embodiment of the frequency synthesizer, it could also be that...

[0188] The frequency adjustment unit includes a filter that receives the input difference and adjusts the frequency of the synthesized signal so that the output signal of the filter is constant.

[0189] According to this frequency synthesizer, noise components can be reduced by filters, thus improving the SNR of the synthesized signal.

[0190] In one embodiment of the frequency synthesizer, it could also be that...

[0191] The filters include low-pass filters, lead filters, lag filters, or lag-lead filters.

[0192] In one embodiment of the frequency synthesizer, it could also be that...

[0193] The calculation unit calculates the accumulated value after adding the number of transitions of the internal state based on the state information obtained by the transition state acquisition unit, and calculates the time value based on the accumulated value.

[0194] According to this frequency synthesizer, the resolution of phase detection is improved by increasing the number of times the internal state transitions of the state transition unit are accumulated in the arithmetic section of the time-to-digital converter, thereby improving the frequency accuracy of the synthesized signal.

[0195] In one embodiment of the frequency synthesizer, it could also be that...

[0196] The calculation unit performs a prescribed operation on the weighted value that has been accumulated over time and the accumulated value to calculate the numerical value of time.

[0197] In one embodiment of the frequency synthesizer, it could also be that...

[0198] The state transition unit includes a multi-stage delay circuit, which has multiple delay elements for propagating the trigger signal, and initiates the state transition based on a time event of the trigger signal.

[0199] According to this frequency synthesizer, the number of internal states of the state transition unit can be increased by the number of delay elements. Therefore, the phase detection resolution of the time-to-digital converter can be improved, and the frequency accuracy of the synthesized signal can be improved.

[0200] In one embodiment of the frequency synthesizer, it could also be that...

[0201] The trigger signal then branches and propagates within the plurality of delay elements.

[0202] According to this frequency synthesizer, not only can the maximum delay time of the multi-stage delay circuit be kept short, but the number of internal states of the state transition unit can also be increased. Therefore, the frequency accuracy of the synthesized signal can be improved without complex calculations in the calculation of the digital time value.

[0203] In one embodiment of the frequency synthesizer, it could also be that...

[0204] The multi-stage delay circuit performs the state transition based on no more than two time events of the trigger signal.

[0205] According to this frequency synthesizer, the number of transitions of the internal state of each time event based on the trigger signal can be easily separated, thus improving the frequency accuracy of the synthesized signal without complex calculations in the calculation of the digital time value.

Claims

1. A frequency synthesizer, characterized by, have: A time-to-digital converter is input to a reference period signal and a composite signal. When the shorter period signal is used as the reference signal and the longer period signal is used as the trigger signal, the converter outputs a digital time value corresponding to the time event of the trigger signal relative to the reference signal. The comparison unit compares the value of the digital time value output from the time-to-digital converter with the target value; The oscillation section generates the synthesized signal; as well as The frequency adjustment unit adjusts the frequency of the synthesized signal based on the comparison result from the comparison unit. The time-to-digital converter has the following features: The state transition unit initiates the internal state transition based on the time event of the trigger signal and outputs state information showing the internal state. A transition state acquisition unit acquires and maintains the state information synchronously with the reference signal from the state transition unit; as well as The calculation unit, based on the state information obtained by the transition state acquisition unit, calculates the time value corresponding to the number of transitions in the internal state. The calculation unit calculates the accumulated value after adding the number of transitions of the internal state based on the state information obtained by the transition state acquisition unit, and calculates the time value based on the accumulated value.

2. The frequency synthesizer according to claim 1, characterized in that, The comparison unit compares the change in the digital time value with a target value determined based on a preset octave ratio or divider ratio, and outputs the difference between the change in the digital time value and the target value as the comparison result. The frequency adjustment unit adjusts the frequency of the synthesized signal to keep the difference constant.

3. The frequency synthesizer according to claim 1, characterized in that, The comparison unit compares the value held by the digital time value with the target value determined based on a preset octave ratio or divider ratio, and outputs the difference between the held digital time value and the target value as the comparison result. The frequency adjustment unit adjusts the frequency of the synthesized signal to keep the difference constant.

4. The frequency synthesizer according to claim 2 or 3, characterized in that, The frequency adjustment unit includes a filter that receives the input difference and adjusts the frequency of the synthesized signal so that the output signal of the filter is constant.

5. The frequency synthesizer according to claim 4, characterized in that, The filters include low-pass filters, lead filters, lag filters, or lag-lead filters.

6. The frequency synthesizer according to claim 1, characterized in that, The calculation unit performs a prescribed operation on the weighted value that has been accumulated over time and the accumulated value to calculate the numerical value of time.

7. The frequency synthesizer according to claim 1, wherein, The state transition unit includes a multi-stage delay circuit, which has multiple delay elements for propagating the trigger signal, and initiates the state transition based on a time event of the trigger signal.

8. The frequency synthesizer according to claim 7, characterized in that, The trigger signal then branches and propagates within the plurality of delay elements.

9. The frequency synthesizer of claim 7 or 8, characterized in that, the multi-stage delay circuit performs the state transitions based on time events of the trigger signal of order 2 or less.

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