Pcie bandwidth allocation method, server motherboard and server

Abstract

The application provides a PCIe bandwidth allocation method, a server mainboard and a server, and the method comprises the following steps: in the case that it is determined that a PCIe peripheral to be allocated is successfully connected with a slot on the server mainboard, polling is performed by gradually increasing the bandwidth allocation granularity from the minimum value, and the maximum link width and the negotiated link width of the peripheral that can be read under each bandwidth allocation granularity are recorded; when the bandwidth allocation granularity is increased to the rated bandwidth of the server mainboard to perform the last polling, the hardware connection topology information of the PCIe peripheral to be allocated is determined based on the maximum link width and the negotiated link width of the peripheral polled under each bandwidth allocation granularity. The PCIe bandwidth allocation method, the server mainboard and the server provided by the application can realize automatic bandwidth allocation whether the bandwidth is allocated for the first time or the bandwidth is allocated again after the Riser card and the device on the card are replaced, and the efficiency of bandwidth allocation is improved.

Description

Technical Field

[0001] This invention relates to the field of server technology, and in particular to a PCIe bandwidth allocation method, a server motherboard, and a server. Background Technology

[0002] As servers become increasingly integrated, simplified and intelligent human-computer interaction during server production has become a top priority for both manufacturers and customers. To offer more flexible customization options, servers are often configured with multiple models for a single motherboard. Given the fixed number of slots on a server motherboard, adapter cards (riser cards) are typically installed to accommodate multiple high-speed Peripheral Component Interconnect Express (PCIe) devices. Different types of riser cards are used to connect to different types of PCIe external cards, such as network interface cards (NICs), smart NICs, and Redundant Arrays of Independent Drives (RAID) cards. Subsequently, the Basic Input Output System (BIOS) chip configures the bandwidth of the connected PCIe devices based on bandwidth configuration information.

[0003] Because the bandwidth configuration information for PCIe devices may differ across different models and plans, current technologies require the BIOS or Baseboard Management Controller (BMC) to pre-adapt the Riser card. Specifically, the BMC reads the Riser card's ID, and the BIOS obtains the Riser ID from the BMC via the Intelligent Platform Management Interface (IPMI), then sets and modifies the Riser card's bandwidth allocation according to the corresponding requirements. Furthermore, if the customer needs to replace the Riser card with a different model or the devices on it, the BIOS or BMC needs to be re-adapted, or the customer needs to perform additional operations. Therefore, current technologies are inefficient and lack automation in bandwidth allocation for flexible and changing configuration needs. Summary of the Invention

[0004] This invention provides a PCIe bandwidth allocation method, a server motherboard, and a server to address the shortcomings of inflexible bandwidth allocation in existing PCIe Riser cards.

[0005] This invention provides a PCIe bandwidth allocation method, comprising:

[0006] Once it is confirmed that the PCIe peripheral to be allocated has successfully connected to the slot on the server motherboard, the bandwidth allocation granularity is gradually increased from the minimum value and polled to record the maximum link width and negotiated link width of the peripheral that can be read at each bandwidth allocation granularity.

[0007] When the bandwidth allocation granularity is increased to the rated bandwidth of the server motherboard, the last polling is performed. Based on the maximum link width and negotiated link width of the peripherals polled under each bandwidth allocation granularity, the hardware connection topology information of the PCIe peripherals to be allocated is determined by back-calculation and comparison.

[0008] The PCIe peripherals to be allocated include PCIe Riser cards and / or PCIe devices; the hardware connection topology information includes the optimal bandwidth allocated to the PCIe Riser cards and / or PCIe devices in the correct ports, and the connection structure of the PCIe Riser cards and / or PCIe devices.

[0009] According to a PCIe bandwidth allocation method provided by the present invention, the step of polling by gradually increasing the bandwidth allocation granularity starting from the minimum value after determining that the PCIe peripheral to be allocated has successfully connected to the slot on the server motherboard, and recording the maximum link width and negotiated link width of the peripheral that can be read at each bandwidth allocation granularity, includes:

[0010] Based on the current bandwidth allocation granularity, determine the target root port for this polling;

[0011] If it is determined that device identification information of a downstream peripheral is read from any of the target root ports, the maximum link width of the downstream peripheral is read.

[0012] Based on the maximum link width of the target root port and the maximum link width of the downstream peripheral, the negotiated link width of the downstream peripheral is determined;

[0013] The polling results of this round are integrated with the names of all target root ports, the names of downstream peripherals read from each target root port, and the maximum link width and negotiated link width of each downstream peripheral.

[0014] The number of target root ports is the ratio between the rated bandwidth of the server motherboard and the current bandwidth allocation granularity; the maximum link width of the target root ports is the current bandwidth allocation granularity.

[0015] According to a PCIe bandwidth allocation method provided by the present invention, when the bandwidth allocation granularity is incremented to the rated bandwidth of the server motherboard, a final poll is performed. Based on the maximum link width and negotiated link width of the peripherals polled at each bandwidth allocation granularity, a reverse calculation and comparison are performed to determine the hardware connection topology information of the PCIe peripherals to be allocated, including:

[0016] The target polling result is selected from all polling results based on the principle of reading the maximum number of downstream devices at the maximum bandwidth allocation granularity.

[0017] Based on the maximum link width and negotiated link width of the downstream peripherals carried in the target polling results, the hardware connection topology information of the PCIe peripherals to be allocated is determined.

[0018] According to a PCIe bandwidth allocation method provided by the present invention, the step of determining the hardware connection topology information of the PCIe peripheral to be allocated based on the maximum link width and negotiated link width of the downstream peripheral carried in the target polling result includes:

[0019] If the sum of the maximum link widths of the downstream peripherals carried in the target polling results is greater than the rated bandwidth of the server motherboard, the first Riser card with a bandwidth allocated to the rated bandwidth of the server motherboard will be designated as the first tier.

[0020] If the target polling results contain both downstream peripherals with a maximum link width greater than the negotiated link width and downstream peripherals with a maximum link width equal to the negotiated link width, then determine the second Riser card and the first peripheral to be extended based on the first level.

[0021] Other Riser cards besides the second Riser card are used as third Riser cards, and other downstream peripherals besides the first peripheral are used as second peripherals to extend the second Riser card until no more Riser cards can be extended, thus forming a cascaded second level.

[0022] The bandwidth of at least the first Riser card, the second Riser card, the third Riser card, the first peripheral and the second peripheral, as well as their slot information, are integrated into the hardware connection topology information according to the hierarchical topology structure.

[0023] According to a PCIe bandwidth allocation method provided by the present invention, the step of determining the hardware connection topology information of the PCIe peripheral to be allocated based on the maximum link width and negotiated link width of the downstream peripheral carried in the target polling result includes:

[0024] If the sum of the maximum link widths of the downstream peripherals carried in the target polling results is greater than the rated bandwidth of the server motherboard, the first Riser card with a bandwidth allocated to the rated bandwidth of the server motherboard will be designated as the first tier.

[0025] If the maximum link width of all downstream peripherals is greater than the negotiated link width, determine the second Riser card to be extended based on the first level.

[0026] Based on the names of all target root ports carried in the target polling results, the second level formed by the third peripherals extended on each second Riser card is obtained;

[0027] The bandwidth of the first Riser card, the second Riser card, and the third peripheral, as well as their slot information, are integrated into the hardware connection topology information according to the hierarchical topology structure.

[0028] According to a PCIe bandwidth allocation method provided by the present invention, the step of determining the hardware connection topology information of the PCIe peripheral to be allocated based on the maximum link width and negotiated link width of the downstream peripheral carried in the target polling result includes:

[0029] If the sum of the maximum link widths of the downstream peripherals carried in the target polling result is equal to the rated bandwidth of the server motherboard, and the maximum link widths and negotiated link widths of all downstream peripherals are equal, then all downstream peripherals are connected in parallel in the first layer of the topology, and the bandwidths of each downstream peripheral in the first layer and their slot information are integrated into the hardware connection topology information.

[0030] The present invention also provides a server motherboard, including a slot on the server motherboard, and an input / output system chip for performing the PCIe bandwidth allocation method as described in any of the preceding claims.

[0031] The present invention also provides a server, including a Riser card and a PCIe device connected to the Riser card, and further including the server motherboard as described above.

[0032] According to a server provided by the present invention, the PCIe device is a smart network card or a RAID card.

[0033] The present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the PCIe bandwidth allocation method as described above.

[0034] The PCIe bandwidth allocation method, server motherboard, and server provided by this invention poll and detect the PCIe peripherals connected to the slots based on the minimum bandwidth allocation granularity supported by the platform. As the bandwidth allocation granularity gradually increases, the maximum link width detected by the device and the negotiated link width are compared and judged to determine the hardware connection topology and detailed device connection status of the PCIe peripherals connected to the slots. This achieves automated bandwidth allocation, whether for initial allocation or secondary allocation after replacing the Riser card and the devices on the card, without requiring prior adaptation of the BIOS and BMC or additional customer operations, thus improving bandwidth allocation efficiency and significantly shortening the project development cycle. Attached Figure Description

[0035] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0036] Figure 1 This is one of the flowcharts illustrating the PCIe bandwidth allocation method provided by the present invention;

[0037] Figure 2 This is the second flowchart of the PCIe bandwidth allocation method provided by the present invention;

[0038] Figure 3 This is a schematic diagram of the structure of the server motherboard provided by the present invention;

[0039] Figure 4 This is a schematic diagram of the server structure provided by the present invention. Detailed Implementation

[0040] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0041] The terms "first," "second," etc., used in this application's specification are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and the number of objects is not limited; for example, a first object can be one or more.

[0042] It should be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used in this specification, unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “the” are intended to include the plural forms.

[0043] The terms “comprising” and “including” indicate the presence of the described feature, whole, step, operation, element and / or component, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or collections thereof.

[0044] Figure 1 This is one of the flowcharts illustrating the PCIe bandwidth allocation method provided by this invention. For example... Figure 1 As shown, the method for detecting a flatbed trailer based on an unmanned transport vehicle provided in this embodiment of the invention includes: Step 101: When it is determined that the PCIe peripheral to be allocated is successfully connected to the slot on the server motherboard, the bandwidth allocation granularity is gradually increased from the minimum value to perform polling, and the maximum link width and negotiated link width of the peripheral that can be read under each bandwidth allocation granularity are recorded.

[0045] The PCIe peripherals to be allocated include PCIe Riser cards and / or PCIe devices.

[0046] It should be noted that the execution subject of the PCIe bandwidth allocation method provided in this embodiment of the invention is a PCIe bandwidth allocation device set in the BIOS and located in the server.

[0047] The application scenario of the PCIe bandwidth allocation method provided in this application embodiment is that after the server connects to an unknown configuration peripheral through the PCIe peripheral port, it starts polling the slots on the server motherboard that may be connected to the Riser card throughout the system, and automatically obtains the optimal bandwidth adaptation scheme through reverse calculation.

[0048] It should be noted that the PCIe peripherals to be allocated refer to external devices plugged into slots on the server motherboard. The access methods of the PCIe peripherals to be allocated on the server motherboard include, but are not limited to, multiple PCIe devices inserted in parallel, peripherals expanded by multiple PCIe Riser cards inserted in parallel, and peripherals expanded by cascading PCIe devices and PCIe Riser cards.

[0049] Specifically, in step 101, when the PCIe bandwidth allocation device set in the BIOS detects that there is a PCIe peripheral to be allocated in the slot on the server motherboard based on the signal transmitted from the slot on the server motherboard, it uses the minimum bandwidth allocation granularity supported by the server motherboard to poll the ports that may be connected to the Riser card one by one. In the process of gradually increasing the bandwidth allocation granularity, it records the maximum link width and the negotiated link width of the PCIe peripheral to be allocated in each round.

[0050] Step 102: When the bandwidth allocation granularity is increased to the rated bandwidth of the server motherboard, the last polling is performed. Based on the maximum link width and negotiated link width of the peripherals polled under each bandwidth allocation granularity, the hardware connection topology information of the PCIe peripherals to be allocated is determined by back-calculation and comparison.

[0051] The hardware connection topology information includes the optimal bandwidth allocated to the PCIe Riser card and / or PCIe device in the correct port, as well as the connection structure of the PCIe Riser card and / or PCIe device.

[0052] Specifically, in step 102, the PCIe bandwidth allocation device set in the BIOS performs a final poll when increasing the bandwidth allocation granularity to the rated bandwidth of the server motherboard. After recording the maximum link width and negotiated link width of the peripheral device recorded in the last poll, it performs reverse deduction and comparison with the image relationship information recorded in all previous polls to determine the hardware connection topology between the PCIe Riser card and / or PCIe device inside the PCIe peripheral to be allocated, as well as the optimal bandwidth allocated to the PCIe Riser card and / or PCIe device under the correct port under this topology, and integrates it into hardware connection topology information and records it in the system.

[0053] This invention, based on the platform's minimum supported bandwidth allocation granularity, polls and detects PCIe peripherals connected to the slot. As the bandwidth allocation granularity gradually increases, it compares the maximum detected link width with the negotiated link width to determine the hardware connection topology and detailed device connection status of the PCIe peripherals connected to the slot. This achieves automated bandwidth allocation, whether for initial allocation or secondary allocation after replacing the Riser card and its devices, without requiring prior BIOS and BMC adaptation or additional customer operations. This improves bandwidth allocation efficiency and significantly shortens project development cycles.

[0054] Based on any of the above embodiments, if it is determined that the PCIe peripheral to be allocated is successfully connected to the slot on the server motherboard, the bandwidth allocation granularity is gradually increased from the minimum value for polling. The maximum link width and negotiated link width of the peripheral that can be read under each bandwidth allocation granularity are recorded, including: determining the target root port of this polling based on the current bandwidth allocation granularity.

[0055] The number of target root ports is the ratio between the server motherboard's rated bandwidth and the current bandwidth allocation granularity.

[0056] Specifically, in step 101, the PCIe bandwidth allocation device set in the BIOS performs the following operation in each poll: first, it calculates the ratio between the rated bandwidth of the server motherboard and the current bandwidth allocation granularity, and uses this ratio as the number n of root ports detected in this poll, and determines the target root port accordingly.

[0057] If it is determined that device identification information of a downstream peripheral is read from any of the target root ports, the maximum link width of the downstream peripheral is read.

[0058] Specifically, the PCIe bandwidth allocation device set in the BOIS reads the device identification information of the downstream devices sequentially for n target root ports. For any target root port, if the device identification information can be read, it means that the device is in place, and then the maximum link width corresponding to it is read from the link capability register of the downstream device.

[0059] However, if the device identification information can be read, it means the device is not present. Therefore, the device identification information is then read and determined for the next target root port.

[0060] The device identification information is used to uniquely distinguish this device from other devices. The device identification information can be set as a device ID and a vendor ID.

[0061] The negotiated link width of the downstream peripheral is determined based on the maximum link width of the target root port and the maximum link width of the downstream peripheral.

[0062] The maximum link width of the target root port is the current bandwidth allocation granularity.

[0063] It should be noted that since the number of target root ports is determined by the bandwidth allocation granularity, the maximum link width of the target root port corresponding to a certain bandwidth allocation granularity is the bandwidth value of that bandwidth allocation granularity.

[0064] Therefore, the larger the bandwidth allocation granularity, the larger the maximum link width of the target root port, and the fewer the number of target root ports.

[0065] Specifically, after the PCIe bandwidth allocation device set in the BOIS reads the maximum link width of the downstream peripheral in place at any target root port, it negotiates with the maximum link width of the target root port and stores the negotiated link width in the Link Status Register for it to read and call.

[0066] The polling results for this round are obtained by integrating the names of all target root ports, the names of downstream peripherals read from each target root port, and the maximum link width and negotiated link width of each downstream peripheral.

[0067] Specifically, the PCIe bandwidth allocation device in the BIOS, upon successfully reading the maximum link width and negotiated link width of each downstream peripheral present under a target root port, sequentially stores them under the name of the corresponding target root port, with each name corresponding one-to-one with the name of the downstream peripheral present under that target root port. This process continues until all target root ports have been polled, ultimately forming the polling result for this polling session.

[0068] The polling results record at least the names of the downstream peripherals in place (i.e., device ID and vendor ID), the name of the target root port (Root Port ID), the maximum link width, and the negotiated link width. These can be stored using tables, pointers, or other storage formats; this embodiment of the invention does not impose specific limitations on this.

[0069] For example, taking the example of connecting an unknown configuration PCIe peripheral to several slots in an x16 slot array on a server motherboard, a specific implementation of a polling method is given:

[0070] The BIOS first divides each slot using the smallest granularity supported by the platform, typically 8 x 2. It then reads the device ID and vendor ID of the downstream device from each of the 8 root ports. If found, the device is present; otherwise, it is absent. If the device is present, it reads the maximum link width from the device's Link Capabilities Register and the negotiated link width (bandwidth after training) from the Link Status Register. It records the corresponding RootPort ID, device ID, vendor ID, Maximum Link Width, and Maximum Link Width for this device, and presents the polling results in Table 1 below.

[0071] Table 1. Suggested Results of the First Round of Polling

[0072]

[0073] Next, the bandwidth splitting granularity is increased to 4 x 4. Similarly, the BIOS reads the device ID and vendor ID of the downstream device for each of the four root ports. If they are found, the device is present; otherwise, the device is not present. If the device is present, the maximum link width in the Link Capabilities Register and the negotiated link width (bandwidth after training) in the Link Status Register of this device are read. The Root Port ID, device ID, vendor ID, Maximum Link Width, and Maximum Link Width corresponding to this device are recorded respectively, and the results of this polling are shown in Table 2 below.

[0074] Table 2. Schematic diagram of the second round of polling results

[0075]

[0076] The bandwidth splitting granularity is further increased to 2 x 8. Similarly, the BIOS reads the device ID and vendor ID of the downstream device from the two root ports respectively. If they are found, the device is present; otherwise, the device is not present. If the device is present, the maximum link width in the Link Capabilities Register and the negotiated link width (bandwidth after training) in the Link Status Register of this device are read. The Root Port ID, device ID, vendor ID, Maximum Link Width, and Maximum Link Width corresponding to this device are recorded respectively, and the results of this polling are shown in Table 3 below.

[0077] Table 3. Schematic diagram of the third round of polling results

[0078]

[0079]

[0080] The bandwidth splitting granularity is then increased by 1x16 for the final round-robin. Similarly, the BIOS reads the device ID and vendor ID of the downstream device from the root port of this x16. If they are found, the device is present; otherwise, the device is not present. If the device is present, the maximum link width in the Link Capabilities Register and the negotiated link width (bandwidth after training) in the Link Status Register of this device are read. The Root Port ID, device ID, vendor ID, Maximum Link Width, and Maximum Link Width corresponding to this device are recorded respectively, and the results of this round-robin are shown in Table 4 below.

[0081] Table 4. Schematic diagram of the fourth round of polling results

[0082]

[0083] In each polling iteration, this invention determines the target root port based on the current bandwidth allocation granularity, detects downstream peripherals connected to the target root port, and records the maximum link width of the detected devices and their corresponding root ports, as well as the negotiated link width negotiated using the maximum link width, in the polling result for subsequent comparison and judgment. By polling at varying bandwidth allocation granularities to identify relevant configurations under different conditions and using this as a reference to infer the optimal bandwidth allocation scheme, a large data foundation can be provided for the automation of bandwidth allocation.

[0084] Based on any of the above embodiments, when the bandwidth allocation granularity is increased to the rated bandwidth of the server motherboard and the last poll is performed, the hardware connection topology information of the PCIe peripheral to be allocated is determined by back-calculation and comparison based on the maximum link width and negotiated link width of the peripheral polled under each bandwidth allocation granularity, including: selecting the target polling result from all polling results according to the principle of reading the most downstream devices at the maximum bandwidth allocation granularity.

[0085] Specifically, in step 102, the PCIe bandwidth allocation device set in the BOIS will obtain multiple sets of polling results after completing all polling. Based on the principle of reading the largest number of downstream devices at the maximum bandwidth allocation granularity, the target polling result that best meets the criterion is selected from them.

[0086] Based on the maximum link width and negotiated link width of the downstream peripherals carried in the target polling results, the hardware connection topology information of the PCIe peripherals to be allocated is determined.

[0087] Specifically, the PCIe bandwidth allocation device set in the BIOS determines the connection status of peripherals on the slots and the bandwidth allocated to peripherals on each slot based on the information recorded in the target polling results, such as RootRort ID, Lane, device, maximum link width of the target root port, maximum link width of the device, and negotiated link width of the device, and integrates them into hardware connection topology information for storage.

[0088] This invention uses polling results that meet the selection criteria as the target polling results that are closest to the actual configuration of the PCIe peripheral. Based on the maximum link width and negotiated link width of the root port and its downstream devices recorded in the target polling results, the hardware connection topology information of the PCIe peripheral is determined. By polling at the level of sequentially opening bandwidth allocation granularity to obtain relevant configurations under various conditions, and using these as a reference to infer the optimal bandwidth allocation scheme, bandwidth allocation can be automated.

[0089] Based on any of the above embodiments, the hardware connection topology information of the PCIe peripheral to be allocated is determined by judging the maximum link width and negotiated link width of the downstream peripherals carried in the target polling result, including: if the sum of the maximum link widths of the downstream peripherals carried in the target polling result is greater than the rated bandwidth of the server motherboard, the first Riser card with the allocated bandwidth of the rated bandwidth of the server motherboard is designated as the first tier.

[0090] It should be noted that the connection information of each device within a PCIe peripheral is stored in its corresponding topology according to different levels.

[0091] The topology can be divided into two levels: the first level consists of the parallel connection of root nodes corresponding to Riser cards and / or independent PCIe devices, and the second level consists of the serial connection of root nodes corresponding to Riser cards and / or independent PCIe devices that are further extended from the root node corresponding to the Riser card.

[0092] Specifically, the PCIe bandwidth allocation device set in the BIOS reads the target polling results. If it is found that the sum of the maximum link widths of the downstream peripherals is greater than the rated bandwidth of the server motherboard, it means that the server motherboard needs to be expanded to support full configuration with the maximum link width. Then, the rated bandwidth of the server motherboard is allocated to the Riser card directly connected to the server motherboard, and stored as a separate first Riser card on the corresponding root node in the topology to form the first level.

[0093] If the target polling results contain both a downstream peripheral with a maximum link width greater than the negotiated link width and a downstream peripheral with a maximum link width equal to the negotiated link width, then the second Riser card and the first peripheral, which are extended based on the first level, are determined.

[0094] Specifically, the PCIe bandwidth allocation device set in the BIOS reads the target polling results. If it analyzes and finds that there are both downstream peripherals with a maximum link width greater than the negotiated link width and downstream peripherals with a maximum link width equal to the negotiated link width, it means that there are both independent PCIe devices and Riser cards that can be further expanded with peripherals directly connected to the first-level Riser card. Then, the downstream peripheral with a maximum link width equal to the negotiated link width is determined as an independent PCIe device and stored as the first peripheral on the child node closest to the root node in the topology. The downstream peripheral with a maximum link width greater than the negotiated link width is determined as a Riser card and stored as the second Riser card on the child node closest to the root node in the topology.

[0095] Other Riser cards besides the second Riser card are used as third Riser cards, and other downstream peripherals besides the first peripheral are used as second peripherals to extend the second Riser card, until no more Riser cards can be extended, thus forming a cascaded second level.

[0096] Specifically, the PCIe bandwidth allocation device set in the BIOS continues to identify downstream peripherals other than the second Riser card that have a maximum link width greater than the negotiated link width as Riser cards and store them as third Riser cards on the child nodes of the second Riser card in the topology. It also identifies downstream peripherals other than the first peripheral that have a maximum link width equal to the negotiated link width as independent PCIe devices and stores them as second peripherals on the child nodes of the first peripheral in the topology. This process continues until the child nodes of the second Riser card are independent PCIe devices, at which point the identification ends, forming the second layer of internal cascading.

[0097] The bandwidth of at least the first Riser card, the second Riser card, the third Riser card, the first peripheral and the second peripheral, as well as their slot information, are integrated into the hardware connection topology information according to the hierarchical topology structure.

[0098] Specifically, the PCIe bandwidth allocation device set in the BIOS allocates bandwidth according to the maximum link width of the first Riser card, second Riser card, third Riser card, first peripheral and second peripheral included in the first and second tiers respectively. It also forms a corresponding topology according to the parallel connection relationship and serial connection relationship between the above devices to form the final hardware connection topology information, thereby indicating which slots on which device it is connected to, with the bandwidth allocated to each slot matching the bandwidth of the device it is connected to.

[0099] This invention, through determining the maximum link width and negotiated link width of downstream peripherals carried in the target polling results, parses the hardware connection topology of all Riser cards and PCIe devices, as well as the presence of PCIe devices connected to each slot on each Riser card, and allocates appropriate bandwidth to the corresponding ports based on the bandwidth supported by the devices and the final negotiated bandwidth.

[0100] Based on any of the above embodiments, the hardware connection topology information of the PCIe peripheral to be allocated is determined by judging the maximum link width and negotiated link width of the downstream peripherals carried in the target polling result, including: if the sum of the maximum link widths of the downstream peripherals carried in the target polling result is greater than the rated bandwidth of the server motherboard, the first Riser card with the allocated bandwidth of the rated bandwidth of the server motherboard is designated as the first tier.

[0101] Specifically, the PCIe bandwidth allocation device set in the BIOS reads the target polling results. If it is found that the sum of the maximum link widths of the downstream peripherals is greater than the rated bandwidth of the server motherboard, it means that the server motherboard needs to be expanded to support full configuration with the maximum link width. Then, the rated bandwidth of the server motherboard is allocated to the Riser card directly connected to the server motherboard, and stored as a separate first Riser card on the corresponding root node in the topology to form the first level.

[0102] If the maximum link width of all downstream peripherals is greater than the negotiated link width, determine the second Riser card to be extended based on the first level.

[0103] Specifically, the PCIe bandwidth allocation device set in the BOIS reads the target polling results. If it is found that the maximum link width of all downstream peripherals is greater than the negotiated link width, it means that only the independent Riser card is directly connected to the first-level Riser card. Then, the downstream peripheral with the maximum link width greater than the negotiated link width is identified as the Riser card and stored as the second Riser card on the child node closest to the root node in the topology.

[0104] Based on the names of all target root ports carried by the target polling results, a second level is obtained, formed by the third peripherals extended on each second Riser card.

[0105] Specifically, the PCIe bandwidth allocation device set in the BOIS combines the names of all target root ports carried by the target polling results, allocates bandwidth to the PCIe devices connected to the second Riser card according to the maximum link width of the records corresponding to each target root port, and stores the PCIe devices as third peripherals on the child nodes of the second Riser card in the topology, forming a second layer with only two layers.

[0106] The bandwidth of the first Riser card, the second Riser card, and the third peripheral, as well as their slot information, are integrated into the hardware connection topology information according to the hierarchical topology structure.

[0107] Specifically, the PCIe bandwidth allocation device set in the BIOS allocates bandwidth according to the maximum link width of the first Riser card, the second Riser card and the third peripheral included in the first and second tiers respectively, and forms a corresponding topology according to the parallel connection relationship and serial connection relationship between the above devices to form the final hardware connection topology information, thereby indicating which slots on which device it is connected to, with the bandwidth allocated to each slot matching the bandwidth of the device it is connected to.

[0108] This invention, through determining the maximum link width and negotiated link width of downstream peripherals carried in the target polling results, parses out all Riser cards, the hardware connection topology of PCIe devices connected to the Riser cards, and the presence status of PCIe devices connected to each slot on each Riser card. Based on the bandwidth supported by the devices and the final negotiated bandwidth, it allocates appropriate bandwidth to the corresponding ports.

[0109] Based on any of the above embodiments, the hardware connection topology information of the PCIe peripherals to be allocated is determined by judging the maximum link width and negotiated link width of the downstream peripherals carried in the target polling result. This includes: if the sum of the maximum link widths of the downstream peripherals carried in the target polling result is equal to the rated bandwidth of the server motherboard, and the maximum link width and negotiated link width of all downstream peripherals are equal, all downstream peripherals are connected in parallel in the first level of the topology, and the bandwidth of each downstream peripheral in the first level and its slot information are integrated into the hardware connection topology information.

[0110] Specifically, the PCIe bandwidth allocation device set in the BIOS reads the target polling results. If the analysis shows that the sum of the maximum link widths of the downstream peripherals is equal to the rated bandwidth of the server motherboard, and the maximum link widths of all downstream peripherals are equal to the negotiated link widths, it means that only independent PCIe devices are directly connected to the server motherboard slots. In this case, the downstream peripherals with maximum link widths equal to the negotiated link widths are determined as independent PCIe devices, and the bandwidth is allocated according to the maximum link widths of each downstream device. The bandwidth is then stored on the corresponding root node in the topology according to the parallel connection relationship between the devices, forming a topology that exists only at the first level, thus forming the final hardware connection topology information.

[0111] Figure 2 This is the second flowchart illustrating the PCIe bandwidth allocation method provided by this invention. For example... Figure 2 As shown, based on the polling results corresponding to Tables 1-4, a specific implementation method for inferring hardware connection topology information from the polling results is given:

[0112] The BIOS uses x2, x4, x8, and x16, which are supported by the platform, as bandwidth splitting granularities to split the bandwidth, resulting in the four-tenant round-robin results recorded in Tables 1-4. It can be seen that the round-robin results in Table 2 read four devices at the x4 granularity, which conforms to the principle of reading the maximum number of downstream devices at the maximum bandwidth allocation granularity. Therefore, the round-robin result with a bandwidth splitting granularity of x2 is taken as the target round-robin result.

[0113] Since the maximum link width and negotiated link width of device 1, device 2 and device 3 recorded in the polling results corresponding to Table 2 are equal, while the maximum link width of device 4 is greater than the negotiated link width, it can be known that the first level of the topology of the PCIe peripherals to be allocated includes both the Riser card and independent PCIe devices.

[0114] Then, proceeding in reverse order, firstly, the sum of the maximum link widths of devices 1-4, x18, is slightly greater than the rated bandwidth of the server motherboard, which is x16. Therefore, a first Riser card (i.e., Riser Card 1) with a bandwidth of x16 needs to be added to the server motherboard as the sole root node of the first level.

[0115] Secondly, considering the relationship between the maximum link width and the negotiated link width, devices 1, 2, and 3 should all be child nodes corresponding to PCIe devices under the root node. However, the total bandwidth of the PCIe devices is x10, while the rated bandwidth of the server motherboard is x16. The remaining x6 cannot meet the maximum link width of device 4. Therefore, device 3 is replaced with the child node closest to the root node in the second level with a node corresponding to a second Riser card (i.e., Riser card 2). Then, devices 3 and 4 are extended based on Riser card 2. The corresponding hardware connection topology information is shown in Table 5.

[0116] Table 5. Hardware Connection Topology Information Diagram

[0117]

[0118]

[0119] This invention, through determining the maximum link width and negotiated link width of downstream peripherals carried in the target polling results, resolves the hardware connection topology of all PCIe devices when the root node only includes independent PCIe devices, and allocates appropriate bandwidth to the corresponding ports based on the bandwidth supported by the devices and the final negotiated bandwidth.

[0120] Figure 3 This is a schematic diagram of the server motherboard provided by the present invention. Based on any of the above embodiments, such as... Figure 3 As shown, the server motherboard includes slots on the server motherboard and an input / output system chip for performing the PCIe bandwidth allocation method as described in any of the preceding claims.

[0121] Specifically, the BMC chip 310 in the server motherboard can transmit the information of each Riser card in the PCIe peripherals connected to the slots on the server motherboard, the bandwidth configuration information of the PCIe devices plugged into the Riser card slots, and the card slot information to the BIOS chip 320.

[0122] Upon receiving data from the BMC chip 310 regarding the connection status of PCIe peripherals to the slots on the server motherboard, BIOS chip 2 polls each port that might be connected to the Riser card. It begins by polling and detecting connected devices using the minimum bandwidth allocation granularity supported by the platform. For each detected device and its corresponding root port, it reads the Maximum Link Width and Negotiated Link Width, recording this information for later comparison. The bandwidth allocation granularity is gradually increased for device detection and reading, with relevant information recorded for each round of comparison. After polling is complete, BIOS chip 320 uses the recorded information to determine the hardware connection topology of the Riser card and the detailed device connection status, correctly allocating the optimal bandwidth to the ports.

[0123] This invention, based on the platform's minimum supported bandwidth allocation granularity, polls and detects PCIe peripherals connected to the slot. As the bandwidth allocation granularity gradually increases, it compares the maximum detected link width with the negotiated link width to determine the hardware connection topology and detailed device connection status of the PCIe peripherals connected to the slot. This achieves automated bandwidth allocation, whether for initial allocation or secondary allocation after replacing the Riser card and its devices, without requiring prior BIOS and BMC adaptation or additional customer operations. This improves bandwidth allocation efficiency and significantly shortens project development cycles.

[0124] Figure 4 This is a schematic diagram of the server provided by the present invention. Based on any of the above embodiments, such as… Figure 4 As shown, the server includes a Riser card 410 and a PCIe device 420 connected to the Riser card 410, and also includes a server motherboard 430 as described above.

[0125] Specifically, the server can use the BMC chip 431 in the server motherboard 430 to transmit the information 410 of each Riser card in the PCIe peripherals connected to the slots on the server motherboard 430, the bandwidth configuration information of the PCIe device 420 plugged into the card slot of the Riser card 410, and the card slot information to the BIOS chip 432.

[0126] Upon receiving data from the BMC chip 431 regarding the connection status of PCIe peripherals to be allocated and slots on the server motherboard 430, the BIOS chip 432 polls each port that might be connected to the Riser card 410. It begins by polling and detecting connected devices using the minimum bandwidth allocation granularity supported by the platform. For each detected device and its corresponding root port, it reads the Maximum LinkWidth and Negotiated Link Width, recording this information for later comparison. The bandwidth allocation granularity is gradually increased for device detection and reading, with relevant information recorded for each round of comparison. After polling is complete, the BIOS chip 432 determines the hardware connection topology and detailed device connection status of the Riser card based on the recorded information, and correctly allocates the optimal bandwidth to the ports.

[0127] This invention, based on the platform's minimum supported bandwidth allocation granularity, polls and detects PCIe peripherals connected to the slot. As the bandwidth allocation granularity gradually increases, it compares the maximum detected link width with the negotiated link width to determine the hardware connection topology and detailed device connection status of the PCIe peripherals connected to the slot. This achieves automated bandwidth allocation, whether for initial allocation or secondary allocation after replacing the Riser card and its devices, without requiring prior BIOS and BMC adaptation or additional customer operations. This improves bandwidth allocation efficiency and significantly shortens project development cycles.

[0128] Based on any of the above embodiments, the PCIe device 420 is a smart network card or a RAID card.

[0129] Specifically, PCIe device 420 is a smart network card or a RAID card.

[0130] Of course, the PCIe device 420 here can also be other types of PCIe devices, and this application does not make any special limitation here.

[0131] This invention improves server scalability through various types of PCIe devices. Even if users replace the Riser card and the PCIe devices on it at any time, bandwidth allocation can be automatically performed through polling, thus improving bandwidth allocation efficiency.

[0132] Furthermore, when the aforementioned logical instructions can be implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, essentially, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0133] On the other hand, the present invention also provides a computer program product, which includes a computer program that can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer can execute the PCIe bandwidth allocation method provided by the above methods. The method includes: when it is determined that the PCIe peripheral to be allocated is successfully connected to the slot on the server motherboard, polling by gradually increasing the bandwidth allocation granularity from the minimum value, and recording the maximum link width and negotiated link width of the peripheral that can be read at each bandwidth allocation granularity; when the bandwidth allocation granularity is increased to the rated bandwidth of the server motherboard, performing a final poll, and back-calculating and comparing the maximum link width and negotiated link width of the peripheral polled at each bandwidth allocation granularity to determine the hardware connection topology information of the PCIe peripheral to be allocated; wherein the PCIe peripheral to be allocated includes a PCIe Riser card and / or a PCIe device; the hardware connection topology information includes the optimal bandwidth allocated to the PCIe Riser card and / or the PCIe device at the correct port, and the connection structure of the PCIe Riser card and / or the PCIe device.

[0134] In another aspect, the present invention also provides a non-transitory computer-readable storage medium storing a computer program thereon. When executed by a processor, the computer program implements the PCIe bandwidth allocation method provided by the above methods. The method includes: when it is determined that the PCIe peripheral to be allocated is successfully connected to a slot on a server motherboard, polling by gradually increasing the bandwidth allocation granularity from the minimum value, and recording the maximum link width and negotiated link width of the peripheral that can be read at each bandwidth allocation granularity; when the bandwidth allocation granularity is increased to the rated bandwidth of the server motherboard, performing a final poll, and back-calculating and comparing the maximum link width and negotiated link width of the peripheral polled at each bandwidth allocation granularity to determine the hardware connection topology information of the PCIe peripheral to be allocated; wherein the PCIe peripheral to be allocated includes a PCIe Riser card and / or a PCIe device; the hardware connection topology information includes the optimal bandwidth allocated to the PCIe Riser card and / or the PCIe device at the correct port, and the connection structure of the PCIe Riser card and / or the PCIe device.

[0135] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0136] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0137] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A PCIe bandwidth allocation method, characterized in that, include: Once it is confirmed that the PCIe peripheral to be allocated has successfully connected to the slot on the server motherboard, the bandwidth allocation granularity is gradually increased from the minimum value and polled to record the maximum link width and negotiated link width of the peripheral that can be read at each bandwidth allocation granularity. When the bandwidth allocation granularity is increased to the rated bandwidth of the server motherboard, the last polling is performed. Based on the maximum link width and negotiated link width of the peripherals polled under each bandwidth allocation granularity, the hardware connection topology information of the PCIe peripherals to be allocated is determined by back-calculation and comparison. The PCIe peripherals to be allocated include PCIe Riser cards and / or PCIe devices; the hardware connection topology information includes the optimal bandwidth allocated to the PCIe Riser cards and / or PCIe devices in the correct ports, and the connection structure of the PCIe Riser cards and / or PCIe devices. When the bandwidth allocation granularity is increased to the rated bandwidth of the server motherboard, a final poll is performed. Based on the maximum link width and negotiated link width of the peripherals polled at each bandwidth allocation granularity, a reverse calculation and comparison are performed to determine the hardware connection topology information of the PCIe peripherals to be allocated, including: The target polling result is selected from all polling results based on the principle of reading the maximum number of downstream devices at the maximum bandwidth allocation granularity. Based on the maximum link width and negotiated link width of the downstream peripherals carried in the target polling results, the hardware connection topology information of the PCIe peripherals to be allocated is determined.

2. The PCIe bandwidth allocation method according to claim 1, characterized in that, Once it is confirmed that the PCIe peripheral to be allocated has successfully connected to the slot on the server motherboard, the bandwidth allocation granularity is gradually increased from the minimum value during polling. The maximum link width and negotiated link width of the peripheral that can be read at each bandwidth allocation granularity are recorded, including: Based on the current bandwidth allocation granularity, determine the target root port for this polling; If it is determined that device identification information of a downstream peripheral is read from any of the target root ports, the maximum link width of the downstream peripheral is read. Based on the maximum link width of the target root port and the maximum link width of the downstream peripheral, the negotiated link width of the downstream peripheral is determined; The polling results of this round are integrated with the names of all target root ports, the names of downstream peripherals read from each target root port, and the maximum link width and negotiated link width of each downstream peripheral. The number of target root ports is the ratio between the rated bandwidth of the server motherboard and the current bandwidth allocation granularity; the maximum link width of the target root ports is the current bandwidth allocation granularity.

3. The PCIe bandwidth allocation method according to claim 1, characterized in that, The determination of the hardware connection topology information of the PCIe peripheral to be allocated, based on the maximum link width and negotiated link width of the downstream peripherals carried in the target polling results, includes: If the sum of the maximum link widths of the downstream peripherals carried in the target polling results is greater than the rated bandwidth of the server motherboard, the first Riser card with a bandwidth allocated to the rated bandwidth of the server motherboard will be designated as the first tier. If the target polling results contain both downstream peripherals with a maximum link width greater than the negotiated link width and downstream peripherals with a maximum link width equal to the negotiated link width, then determine the second Riser card and the first peripheral to be extended based on the first level. Other Riser cards besides the second Riser card are used as third Riser cards, and other downstream peripherals besides the first peripheral are used as second peripherals to extend the second Riser card until no more Riser cards can be extended, thus forming a cascaded second level. The bandwidth of at least the first Riser card, the second Riser card, the third Riser card, the first peripheral and the second peripheral, as well as their slot information, are integrated into the hardware connection topology information according to the hierarchical topology structure.

4. The PCIe bandwidth allocation method according to claim 1, characterized in that, The determination of the hardware connection topology information of the PCIe peripheral to be allocated, based on the maximum link width and negotiated link width of the downstream peripherals carried in the target polling results, includes: If the sum of the maximum link widths of the downstream peripherals carried in the target polling results is greater than the rated bandwidth of the server motherboard, the first Riser card with a bandwidth allocated to the rated bandwidth of the server motherboard will be designated as the first tier. If the maximum link width of all downstream peripherals is greater than the negotiated link width, determine the second Riser card to be extended based on the first level. Based on the names of all target root ports carried in the target polling results, the second level formed by the third peripherals extended on each second Riser card is obtained; The bandwidth of the first Riser card, the second Riser card, and the third peripheral, as well as their slot information, are integrated into the hardware connection topology information according to the hierarchical topology structure.

5. The PCIe bandwidth allocation method according to claim 1, characterized in that, The determination of the hardware connection topology information of the PCIe peripheral to be allocated, based on the maximum link width and negotiated link width of the downstream peripherals carried in the target polling results, includes: If the sum of the maximum link widths of the downstream peripherals carried in the target polling result is equal to the rated bandwidth of the server motherboard, and the maximum link widths and negotiated link widths of all downstream peripherals are equal, then all downstream peripherals are connected in parallel in the first layer of the topology, and the bandwidths of each downstream peripheral in the first layer and their slot information are integrated into the hardware connection topology information.

6. A server motherboard, comprising a slot on the server motherboard, characterized in that, It also includes an input / output system chip for performing the PCIe bandwidth allocation method as described in any one of claims 1 to 5.

7. A server comprising a Riser card and a PCIe device connected to the Riser card, characterized in that, It also includes the server motherboard as described in claim 6.

8. The server as described in claim 7, characterized in that, The PCIe device is a smart network card or a RAID card.

9. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the PCIe bandwidth allocation method as described in any one of claims 1 to 5.

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